FIN12AMLX - Fairchild Semiconductor Corporation

Preliminary

April 2005

Revised April 2005

FIN12A PSerDes¥ Low Voltage 12-Bit Bi-Directional Serialize r/Deserializer with Multiple Frequency Ranges

(Preliminary)

FIN12A

PSerDes¥

Low Voltage 12-Bit Bi-Directional Serializer/Deserializer

with Multiple Frequency Ranges (Preliminary)

General Descript ion

The FIN1 2A is a 12-bit seri alizer capable of running a par-

allel frequency range between 5MHz and 56MHz. The fre-

quency rang e i s select ed by the S1 and S2 cont rol sign als.

The bi-directional data flow is controlled through use of a

direction (DIRI ) control pin. Th e device s can be c onfig ured

to operate in a unidirectional mo de only by hardwiring the

DIRI pin. An internal PLL generates the required bit clock

frequency for transfer across the serial link. Options exist

for dual or single PLL operation dependent upon system

operati ona l par ame ter s. The device h as been designed f or

low power operation and utilizes Fairchild Low Power

LVDS interface. The device also supports an ultra low

power Power-Down mode f or conserving power in battery

operated app l ic atio ns.

Features

■Low power consu mp ti on

■Low power LVDS differential interface

■LVCMOS parallel I/O interface

• 2 mA source/sink current

• Over-voltage tolerant control signals

■I/O power supply range between 1.65V and 3.6V

■Analog Power Supply range of 2.775V

■Multi-Mode operation allows for a single device to

operate as Serializer or Deserializer

■Internal PLL with no external components

■Standby Power-Down mode support

■Small footprint 32-terminal MLP packaging

■Built in differential termination

■Supports external CKREF frequencies between

5MHz and 56MHz

■Serialized data rate up to 784Mb/s

Ordering Code:

Pb-Free package per JEDEC J-STD-020B.

BGA and M LP packages ava ilable in Tape an d R eel only.

SerDes

is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

FIN12AGFX

(Preliminary) BGA42A Pb-Free 42-Ball Ultra Sm all Sca l e Ball Grid Array (USS-BGA), JEDEC MO-195,

3.5mm Wide

FIN12AMLX MLP032A Pb-Free 32-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm

Square

Preliminary

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FIN12A

Functional Block Diagram

Connection Diagram

Terminal Assignments for MLP

(Top View)

Preliminary

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FIN12A

Pin Description

Note 1: Th e D SO/DS I serial port t erm inals hav e been arrange d s uc h that when one de v ic e is rota t ed 180 deg r ees with res pect to th e ot her device the serial

connect ions will properly align with out the nee d f or any trac es or cable si gnals to cros s . Ot her layout orientat ions may require that t rac es or cables cross .

Control Logic Circuitry

The FIN12A has the ability to be used as a 12-bit Serializer

or a 12-bit Deserializer . Terminals S1 and S2 must be set to

accommodate the clock reference input frequency range of

the serializer. The table below shows the terminal program-

ming of the se options base d on the S1 and S2 control te r-

minals. The DIRI terminal controls whether the device is

the serializer or a deserializer. When DIRI is asserted

LOW, the de vice is confi gured as a deserial izer. When t he

DIRI terminal is asserted HIGH, the device will be config-

ured as a serialize r. Chang ing the state on the DIRI si gnal

will reverse the direction of the I/O signals and generate

the opposi te state signal on DIRO. For unidirectional oper-

ation the DIRI terminal should be hardwired to the HIGH or

LOW state and the DIRO terminal should be left floating.

For bi-directional operation the DIRI of the master device

will be driven by the system and the DIRO signal of the

master will be used to drive the DIRI of the slave device.

Turn-Around Functionality

The dev ice passes and inverts the D IRI signal th rough the

device asynchronously to the DIRO signal. Care must be

taken by the system designer to insure that no cont ention

occurs between the deserializer outputs and the other

devices on this port. Optimally the peripheral device driving

the serializer should be put into a HIGH Impedance state

prior to the DIRI sig nal bein g asser ted .

When a device with dedicated data outputs turns from a

deserializer to a serializer the dedicated outputs will remain

at the last logical value asserted. This value will only

change if the device is once again turned around into a

deserializer and the values are overwritten.

TABLE 1. Control Logic Circuitry

Pin Name I/O Type Number

of Pins Description of Signals

DP[1:12] I/O 12 LVCMOS Parallel I/O. Direction controlled by DIRI terminal.

CKREF IN 1 LVCMOS Clock Input and PLL Reference

STROBE IN 1 LVCMOS Strobe Signal for Latching Data into the Serializer

CKP OUT 1 LVCMOS Word Clock Output

DSO



/ DSI



DSO



/ DSI



DIFF-I/O 2 LpLVDS Differential Serial I/O Data Signals (Note 1)

DSO: Refers to output signal pair

DSI: Refers to input signal pair

DSO(I)



: Positive signal of DSO(I) pair

DSO(I)



: Negative signal of DSO(I) pair

CKSI



, SKSI



DIFF-IN 2 LpLVDS Differential Deserializer Input Bit Clock

CKSI: Refers to signal pair

CKSI



: Positive signal of CKSI pair

CKSI



: Negative signal of CKSI pair

CKSO



, CKSO



DIFF-OUT 2 LpLVDS Differential Serializer Output Bit Clock

CKSO: Refers to signal pair

CKSO



: Positive signal of CKSO pair

CKSO



: Negative signal of CKSO pair

S1 IN 1 LVCMOS Mode Selection terminals used to define

S2 IN 1 frequency range for the RefClock, CKREF

DIRI IN 1 LVCMOS Control Input

Used to control direction of Data Flow:

DIRI

“1” Serializer,

DIRI

“0” Deserializer

DIRO OUT 1 LVCMOS Control Output

Inversion of DIRI

VDDP Supply 1 Power Supply for Parallel I/O and Translation Circuitry

VDDS Supply 1 Power Supply for Core and Serial I/O

VDDA Supply 1 Power Supply for Analog PPL Circuitry

GND Supply 0 Use Bottom Ground Plane for Ground Signals

Mode

Number S2 S1 DIRI Description

0 0 0 X Power-Down Mode

1 0 1 1 12-Bit Serializer,

20MHz to 56MHz CKREF

0 1 0 12-Bit Deserializer

2 1 0 1 12-Bit Serializer,

5MHz to 15MHz CKREF

1 0 0 12-Bit Deserializer

3 1 1 1 12-Bit Serializer,

10MHz to 30MHz CKREF

1 1 0 12-Bit Deserializer

Preliminary

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FIN12A

Power-D own Mode

Mode 0 is used for powering down and resetting the

device. When both of the mode signals are driven to a

LOW state the PLL and references will be disabled, differ-

ential input buffers will be shut of f, diff erential output buf fers

will be placed into a HIGH Imp edance state, LVCMOS out-

puts will be placed into a HIGH Impedance state, and LVC-

MOS inputs will be driven to a valid level internally.

Additionally all internal circuitry will be reset. The loss of

CKREF state is also enabled to insure that the PLL will only

power-up if there is a valid CKREF signal.

In a typical application mode signals o f the device will not

change other than between the desired frequency range

and the power-down mode. This allows for system level

power-down functionality to be implemented via a single

wire for a SerDes pair. The S1 and S2 selection signals

that have their op erating mo de drive n to a “logic 0” shou ld

be hardwired to GND. The S1 and S2 signals that have

their operating mode driven to a “logic 1” should be con-

nected to a system level power-down signal.

Serializer Operation Mode

The serializer configurations are described in the following

sections. T he basic serialization circuitr y w orks essentially

identical in these modes but the actual data and clock

streams will differ dependent on if CKREF is the same as

the ST ROB E sign al o r no t. W h en it is stated tha t CK RE F

STROBE this means that the CKREF and STROBE signals

have an identical frequency of operation but may or may

not be pha se aligned. When it is stated that CKREF does

not equal STROBE then each signal is distinct and CKREF

must be r unning at a frequency high enough to a void any

loss of data condition. CKREF must never be a lower fre-

quency than STROBE.

Serializer Operation: (Figure 1)

Modes 1, 2, or 3

DIRI equals 1

CKREF equals STROBE

The PLL must receive a stable CKREF signal in order to

achieve lock prior to any valid data being sent. The CKREF

signal can be used as the data STROBE signal provided

that data can be ignored during the PLL lock phase.

Once the P LL is stable a nd locked the devi ce can b egin to

capture and serialize data. Data will be captured on the ris-

ing edge of the STROBE signal and then serialized. The

serialized data stream is synchronized and sent source

synchronously with a bit clock with an embedded word

boundar y. Wh en ope rat i ng in thi s m ode the i nte rna l dese ri -

alizer circuitry is disabled including the DS input buffer . The

CKSI serial inputs remain a ctive to allow th e pass through

of the CKSI signal to the CKP output. For more on this

mode pl ease see the se ction on Pa ssing a Word Cloc k. If

this mode is not needed then the CKSI inputs can either be

driven to valid l evels or left to float. Fo r lowest pow er oper-

ation let the CKSI inputs float.

Serializer Operation: (Figure 2)

DIRI equals 1

CKREF does not equal STOBE

If the same signal is not used for CKREF and STROBE,

then the C KREF signal m ust be run at a hig her frequency

than the STROBE rate in order to serialize the data cor-

rectly. The actual serial transfer rate will remain at 14 times

the CKREF frequency. A data value of zero will be sent

when no valid data is present in the serial bit stream. The

operation of the serializer will otherwise remain the same.

The exact frequenc y that th e reference clock nee ds to run

at will be dependent upon the stability of the CKREF and

STROBE signal. If th e source of t he CKREF signal imple-

ments sprea d spectrum te chnology then the minimum fre-

quency of this spread spectrum clock should be used in

calculating the ratio of STROBE frequency to the CKREF

frequency. Similarly if the STROBE signal has significant

cycle-to-cycle variation then the maximum cycle-to-cycle

time n eeds to be fa ctored i nto the sele ction of th e CKREF

frequency.

Serializer Operation: (Figure 3)

DIRI equals 1

No CKREF

A third method of serial ization can be done b y providi ng a

free running bit clock on the CKSI signal. This mode is

enabled by grounding the CKREF signal and driving the

DIRI signal HIGH.

At power- up the device is confi gured to acce pt a seriali za-

tion clock from CKSI. If a CKREF is received then this

device will enable the CKREF serialization mode. The

device will remain in this mode even if CKREF is stopped.

To r e-enable th is mode the de vice must be powered d own

and then powered back up with “logic 0” on CKREF.

Preliminary

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FIN12A

Serializer Operation Mode (Continued)

FIGURE 1. Serializer Timing Diagram (CKREF equals STROBE)

FIGURE 2. Serializer Timing Diagram (CKREF does not equal STROBE)

FIGURE 3. Serializer Timing Diagram Using Provided Bit Clock (No CKREF)

Preliminary

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FIN12A

Deserializer Operation Mode

The operation of the deserializer is only dependent upon

the data received on th e DS I da ta signal pair and t he CK SI

clock signal pair. The following two sections describe the

operation of the deserializer under two distinct serializer

source conditions. References to the CKREF and STROBE

signals refer to the signals associated with the serializer

device us ed in gene rating the serial data and clock si gnals

that are inputs to the deserializer.

When ope rat ing i n th is mo de th e i nte rn al ser i aliz er circu it ry

is disab led includi ng the parallel data input buffers . If ther e

is a CKREF signal provided then the CKSO serial clock will

continue to transmit bit clocks.

Deseria lize r Operatio n :

DIRI equals 0

(Serializer Source: CKREF equals STROBE)

When the DIRI signal is asserted LOW the device will be

configured as a deserializer. Data will be captured on the

serial port and deserialized through use of the bit clock

sent with the data. The word boundary is defined in the

actual clock and data signal. Parallel data will be generated

at the time the word boundary is detected. The falling edge

of CKP will occur coincident with the data transition. The

rising edge of CKP will be generated approximately 7 bit

times later. When no embedded word boundary occurs

then no pulse on CKP will be generated and CKP will

remain HIGH.

Deserializer Operation:

PwrDwn equals 1

DIRI equals 0

(Serializer Source: CKREF does not equal STROBE)

The log ical operat ion of the de serializer remains the same

regardless of if the CKREF is equal in frequency to the

STROBE or a t a higher frequen cy t han the STROBE. T he

actual serial data stream presented to the deserializer will

however be different because it will have non-valid data

bits sent between words. The duty cycle of CKP will vary

based on th e ra ti o o f the fre que ncy o f the C KR EF sign al to

the STROBE signal. The frequency of the CKP signal will

be equal to the STROBE frequency. The falling edge of

CKP will coincident with data transition. The LOW time of

the CKP signal will be equal to ½ (7 bit times) of the

CKREF period. The CKP HIGH time will be equal to

STROBE period



½ of the CKREF period. Figu re 5 is rep-

resentative of a waveform that could be seen when CKREF

is not equal to STROBE. I f CKREF was sig nificantly faster

than additional non-valid data bits would occur between

data words.

FIGURE 4. Deserializer Timing Diagram

(Serializer Source: CKREF equals STROBE)

FIGURE 5. Deserializer Timing Diagram

(Serializer Source: CKREF does not equal STROBE)

Preliminary

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FIN12A

Embedded Word Clock Operation

The FIN12A sends and receives serial data source syn-

chronously with a bit clock. The bit clock has been modified

to create a word boundary at the end of each data word.

The word boundary has been implemented by skipping a

low clock pulse. This app ears in the serial clock stream as

3 consecutive bit times where signal CKSO remains HIGH.

In order to implement this sort of scheme two extra data

bits are required. During the word boundary phase the data

will toggle either HIGH-then-LOW or LOW-then-HIGH

dependent upon the last bit of the actual data word. Table 2

prov i d es s o me e xam pl e s s h owi n g t h e ac t u al d a t a wor d an d

the data word with the word boundary bits added. Note that

a 12-bit word will be extended to 14 bits during serial trans-

mission. Bit 13 and Bit 14 are defined with-respect-to Bit

12. Bit 13 will always be the inversion of Bit 12 and Bit 14

will always be the same as Bit 12. This insures that a “0”

“1” and a “1”

“0” transition will always occur during the

embedded word phase where CKSO is HIGH.

The serializer generates the word boundary data bits and

the boundary clock condition and embeds them into the

serial data stream. The deserializer looks for the end of the

word boundary condition to capture and transfer the data to

the parallel po rt. The deser ializer only uses the embed ded

word boundary information to find and capture the data.

These boundary bits are then stripped prior to the word

being sent out of the parallel port.

TABL E 2. Word Boundary Data Bits

LVCMOS Data I/O

The LVCMOS input bu ffers have a no minal threshold value

equal t o ½ of VDDP. The input buffers are only o peratio nal

when the device is operating as a serializer. When the

device is operating as a deserializer the inputs are gated

off to conserve power.

The LVCMOS 3-STATE output buffers are rated for a

source/sink current of 2 mAs at 1.8V. The outputs are

active when the DIRI signal is asserted LOW. When the

DIRI signal is asserted HIGH the bi-di rectional LVCM OS I/

Os will be in HIGH-Z state. Under purely capacitive load

conditions the output will swing between GND and VDDP.

The LVCMOS I/O buffers in corporate b ushold fun ctionality

to allow for pins to maintain state when they are not driven.

The bushold circuitry only consumes power during signal

transitions.

FIGURE 6. LVCMOS I/O

Differe n ti a l I/O Circ u itry

The differential I/O circuitry is a low power variant of LVDS.

The differential outputs operate in the same fashion as

LVDS by sou rcing and sin king a balanced current thro ugh

the output pair. Like LVDS an input source termination

resistor is required to develop a voltage at the differential

input pair. The FIN12A de vice incor porates an internal t er-

minatio n re sistor on th e CK SI recei ver and a gate d inte rna l

termination resistor on the DS input receiver . The gated ter-

mination resistor insures proper termination regardless of

direction of data flow.

FIGURE 7. Bi-directional Differential I/O Circuitry

12 Bit Data Words 12 Bit Data Word with Word Boundary

HexBinaryHexBinary

FFFh 1111 1111 1111b 2FFFh 10 1111 1111 1111b

555h 0101 01010 0101b 1555h 01 0101 0101 0101b

xxxh 0xxx xxxx xxxxb 1xxxh 01 0xxx xxxx xxxxb

xxxh 1xxx xxxx xxxxb 2xxxh 10 1xxx xxxx xxxxb

Preliminary

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FIN12A

PLL Circuitry

The CK REF input signal is u sed to p rovide a re ference to

the PLL. The PLL will generate internal timing signals

capable of transferring data at 14 times the incoming

CKREF signal. The output of th e PLL is a Bi t Clock that is

used to ser i aliz e the da ta. T he bit clock is also sen t s our ce

synchronously with the serial data stream.

There are two ways to disable the PLL. The PLL can be

disab led by entering the Mo de 0 state. (S 1

0). The

PLL will disable immediately upon detecting a LOW on

both the S1 and S2 signals. When any of the other modes

are en ter ed by a sser ti ng eith er S 1 o r S2 H IGH a nd by pro -

viding a CKREF signal the PLL will power-up and goes

throug h a lock sequen ce. You m ust wait specif ied number

of clock cycles prior to capturing valid data into the parallel

port.

An alternate way of powering down the PLL is by stopping

the CKREF signal either HIGH or LOW. Internal circuitry

detects the la ck o f t ran sitions a nd shuts the PL L a nd se rial

I/O down. Inter nal references will not how ever be disabled

allowing for the PLL to power-up and re-lock in a lesser

number of clock cycles tha n when exiting Mod e 0. When a

transition is seen on the CKREF signal the PLL will once

again be reactivated.

Passing a Word Clock

For some applications it is desirable to pass a word clock

through th e deserializer to th e serializer an d output it as a

reference clock for another device. (See Figure 11) This

can be done under the following conditions:

1. The application mode is unidirectional only.

2. The maste r word clock is g enerated on t he same side

of the cable as the deserializer.

To implement pass through functionality on the deserial-

izer:

1. DIRI

LOW

2. CKREF

LOW

3. Word clock should be connected to the STROBE.

4. This will pass the STROBE signal out the CKSO port.

To implement pass through functionality on the serializer:

1. Connect CKSO of the deserializer to CKSI of the serial-

izer

2. CKSI passes the signal to CKP

3. CKP must be connected to CKREF

If the word clock bein g passed through the ser ializer stops

then the serializer must be placed in the reset mode

(MODE 0) and restarted before the CKSI signa l will again

pass through to CKP.

If CKREF o f the deserializer is running then a high speed

bit clock will be passed across the flip instea d of STROBE.

This bit clock will be used as the clock source by the serial-

izer provided that no CKREF signal exists on the serializer.

Preliminary

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FIN12A

Application Mode Diagrams

Modes 1, 2, 3: Unidirectional Data Transfer

FIGURE 8. Simplified Block Diagram for Unidirectional Serializer and Deserializer

Figure 8 show s the b asi c op era tion diagram w hen a pair of

SerDes is configured in an unidirectional operation mode.

Master Operation: The device will...

(Please refer to Figure 8)

1. During power-up the device will be configured as a

serializer based on the value of the DIRI signal.

2. Accept CKRE F_M word clock an d generate a bit clock

with embedded word boundary. This bit clock will be

sent to the slave device through the CKSO port.

3. Receive parallel data on the rising edge of

STROBE_M.

4. Generate and transmit serialized data on the DS sig-

nals which is source synchronous with CKSO.

5. Generate an embedded word clock for each strobe sig-

nal.

Slave Operation: The device will...

1. Be configured as a deserializer at po wer-up based on

the value of the DIRI signal.

2. Accept an embedded word boundary bit clock on CKSI.

3. Deserialize the DS Data stream using the CKSI input

clock.

4. Write parallel data onto the DP_S port and generate

the CKP_S. CKP_S will only be generated when a valid

data word occurs.

FIGURE 9. Unidirectional Serializer and Deserializer

Preliminary

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FIN12A

Application Mode Diagrams (Continued)

FIGURE 10. Multiple Units, Unidirectional Signals in Each Direction

FIGURE 11. 8-Bit Camera Interface (10MHz to 30MHz Parallel Operation)

Figure 10 shows an 8-bit LCD Interface with VSYNC/

HSYNC capability. This interface is a very straightforward

in im plementing the

SerDes de vices. Note th at two addi-

tional data bits are still available for implementing addi-

tional data bits or control signals.

Figure 11 shows an applicatio n for a camera in ter face for a

flip ph one using the FIN12A . For this ap plicatio n the refer -

ence clock is generated on the baseband side of the flip

and pas sed across th e SerDes pai r differential ly. This sig-

nal is then re converted to a single end ed signal for use as

a reference clock by the imager. For some applications it

may be possible to connect the REFCK directly to the

CKREF signal of the FIN12A serializer.

Preliminary

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FIN12A

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Abs olut e maxi mum ratin gs ar e DC value s beyond whi ch t he devi ce

may be damaged or have its useful life impaired. The datasheet specifica-

tions should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading vari-

ables. F airchild does not recommend ope ration outside datasheet specifi-

cations.

DC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified.

Note 3: Typical Values are given for VDD

2.5V and TA

C. Positive current values refer tot the current flowing into device and negative values means

current flowing out of pins. Voltage are referenced to Ground unless otherwise specified (except

VOD and VOD).

Note 4: The definit ion o f sh ort-cir cuit incl ud es al l the p ossib le sit uat ions . For e xam ple, the shor t of differe ntia l pair s to Gr oun d, the sho rt of differen tial pai rs

(No Grou nding) and either line of differential pairs tie d t o Ground.

Supply Voltage (VDD)



0.5V to



4.6V

ALL Input/O utp ut Voltage



0.5V to



4.6V

LVDS Output Short Circuit Duration Continuous

Storage Temperature Range (TSTG)



C to



150

Maximum Junction Temperature (TJ)



150

Lead Temperature (TL)

(Soldering, 4 seconds)



260

ESD Rating

Human Body Model, 1.5K

, 100pF

2kV

Machine Model, 0

, 200pF

200V

Supply Voltage (VDDA, VDDS) 2.775V

5.0%V

Supply Voltage (VDDP) 1.65V to 3.6V

Operating Temperature (TA) (Not e 2)



C to



Supply Noise Voltage (VDDA-PP) 100 mVP-P

Symbol Parameter Test Conditions Min Typ Max Unit

(Note 3)

LVCMOS I/O

VIH Input High Voltage 0.65 x VDDP VDDP

VIL Input Low Voltage GND 0.35 x VDDP V

VOH Output High Voltage IOH



2.0 mA VDDP

3.3

0.3 0.75 x VDDP VVDDP

2.5

0.2

VDDP

1.8

0.15

VOL Output Low Voltage VDDP

3.3

0.3 VIOL

2.0 mA VDDP

2.5

0.2 0.25 x VDDP

VDDP

1.8

0.15

IIN Input Current VIN

0V to 3.6V



5.0 5.0

IOFF Input/Output Power-Off VDDP

0V,

5.0

Leakage Current ALL LVCMOS Inputs/ Outputs 0V to 3.6V

DIFFERENTIAL I/ O

VOD Output Differential Voltage RL

100

, See Figure 12 150 225 350 mV

VOD VOD Magnitude Change from RL

100

, See Figure 12 15.0 mV

Differentia l LOW -to-HIGH

VOS Offset Voltage RL

100

, See Figure 12 VDD

2.775

5% 925 mV

VOS Offset Magnitude Change from 15.0 mV

Differentia l LOW -to-HIGH

IOS Short Circuit Output Current VOUT

0V Driver Enabled



2.5



5.0 mA

(Note 4) Driver Disabled

5.0

IOZ Disabled Output Leakage Current DP

0V to VDDP, DIRI

VDDP

1.0

10.0

VTH Differential Input Threshold HIGH See Figure 13 and Table 2 100 mV

VTL Differential Input Threshold LOW See Figure 13 and Table 2



100 mV

VICM Input Common Mode Range VDD

2.775

5% 300 925 1550 mV

RTRM0 CKSI Internal Receiver VID

225 mV, VIC

925 mV, DIRI

0 80.0 100 120

Termination Resistor |CKSI





CKSI



VID

DS I/O Termination Resistor VID

225 mV, VIC

925 mV, DIRI

0 80.0 100 120

|DS





DSI



VID

IIN Input Current VIN

VDD



0.3V or 0V

20.0

VDD

0V or VDD

Preliminary

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FIN12A

Power Supply Currents

Note 5: The worst case test pattern produces a maximum toggling of internal digital circuits, LpLVDS I/O and LVCMOS I/O with the PLL operating at th e ref-

erence frequency unless otherwise specified. Maximum power is measured at the maximum VDD values. Mini mu m va lue s ar e mea sur ed at th e mi nim um VDD

valu es . Typical v al ues are mea s ured at VDD

2.5V.

AC Specification: Serializer Timing Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified.

Symbol Parameter Test Conditions Min Typ Max Units

IDDA1 VDDA Serializer Static All DP and Control Inputs at 0V or VDD TBD TBD mA

Supply Current NOCKREF, S2

0, S1

1, DIR

IDDA2 VDDA Deserializer Static All DP and Control Inputs at 0V or VDD TBD TBD mA

Supply Current NOCKREF, S2

0, S1

1, DIR

IDDS1 VDDS Serializer Static All DP and Control Inputs at 0V or VDD TBD TBD mA

Supply Current NOCKREF, S2

0, S1

1, DIR

IDDS2 VDDS Deserializer Static All DP and Control Inputs at 0V or VDD TBD TBD mA

Supply Current NOCKREF, S2

0, S1

1, DIR

IDDS VDDA Static All DP and Control Inputs at 0V or VDD TBD TBD mA

Supply Current S1

IDD_PD VDD Power-Down Supply Current S1

0, 5.0 uA

IDD_PD

IDDA



IDDS



IDDP All Inputs at GND or VDD

IDD_SER1 14:1 Dynamic Serializer S2

H5 MHz TBD TBD

Power Supply Current CKREF

STROBE S1

L15 MHz TBD TBD

(Note 3) DIRI

HS2

H10 MHz TBD TBD

IDD_SER1

IDDA



IDDS



IDDP See Figure 14 S1

H30 MHz TBD TBD

L30 MHz TBD TBD

H56 MHz TBD TBD

IDD_DES1 14:1 Dynamic Deserializer S2

H5 MHz TBD TBD

Power Supply Current CKREF

STROBE S1

L15 MHz TBD TBD

(Note 5) DIRI

LS2

H10 MHz TBD TBD

IDD_DES1

IDDA



IDDS



IDDP See Figure 14 S1

H30 MHz TBD TBD

L30 MHz TBD TBD

H56 MHz TBD TBD

IDD_SER2 14 :1 Dynamic Serializer NOCKREF 5 MHz TBD TBD

Power Supply Current STROBE

Active 15 MHz TBD TBD

(Note 5) CKSI

8X STROBE 10 MHz TBD TBD

IDD_SER2

IDDA



IDDS



IDDP DIRI

H30 MHzTBDTBD

See Figure 14 56 MHz TBD TBD

Symbol Parameter Test Conditions Min Typ Max Units

tTCP CKREF Clock Period See Figure 18 S2

1S1

0 66.0 T166 ns(5 MHz - 56MHz) CKREF

STRO BE S2

1S1

1 33.0 100

0S1

1 17.8 33.0

fREF CKREF Frequency Relative CKREF S2

1S1

0 1.1 *fST

15.0 MHzto Strobe Frequency Does Not Equal S2

1S1

130.0

STROBE S2

0S1

156.0

tTCH CKREF Clock High Time TBD 0.5 TBD T

tTCL CKREF Clock Low Time TBD 0.5 TBD T

tCLKT LVCMOS Input Transition Time Figure 18 TBD ns

tTCH STROBE Pulse Width HIGH Figure 18 5.0 ns

tTCL STROBE Pulse Width LOW Figure 18 5.0 ns

fMAX Maximum S2

0S1

1 70.0 210 Mb/sSerial Data Rate REFCK x 14 S2

1S1

0 140 420

1S1

1 420 784

Preliminary

13 www.fairchildsemi.com

FIN12A

Serializer AC Electrical Characteristics

Serializer Timing Characteristics

Note 6: Skew is m easured f rom eit her the ris ing or falling ed ge of the bit cloc k (C KSO) r elative to the r is ing or falling edg e of the data bit (DSO). CKSO and

DSO have been designed to be edge aligne d.

PLL Sp ecifications

Note 7: This jitter specification is based on the assumption that PLL has a Ref Clock with cycle-to-cycle input jitter less than 2ns.

Note 8: The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the state of the S1/S2 mode pins. Th e

specific numbe r of c loc k c y cl es required for th e PLL to be dis abled w ill v ary dependent upon the operating mode of t he device .

Deserializer AC Electrical Characteristics

Note 9: Sign als a re tr a nsmitted from the serializer sou rce s ynch r onousl y. Note th at in some cases data is tr ansmi tte d when th e c lock r e mains at a high state.

Skew sh ould on ly be m easu red w hen da ta and cloc k are transit ionin g at t he sa me tim e. Total me asur ed input skew woul d be a c omb ination of output skew

from the serializer, load variations and ISI and jitter effects.

Note 10: Rising edge of CKP will appear approximately 7-bit times after the falling edge of the CKP output. Data will appear coincident with this falling edge.

Variation with respect to the CKP signal is due to internal propagation delays of the device. Note that if CKREF is not equal to STROBE fo r t he s erializer t he

CKP signal will not m aintain a 50% D ut y C y c le. T he low tim e of C KP will rem ain in 7 bit times.

Symbol Parameter Test Conditions Min Typ Max Units

tTLH Differential Output Rise Time (20% to 80%) See Figure 15 0.6 0.9 ns

tTHL Differential Output Fall Time (80% to 20%) 0.6 0.9 ns

tSTC DP[n] Setup to STROBE DIRI

12.5 ns

tHTC DP[n] Hold to STROBE See Figure 17 (f

10 MHz) 0 ns

tTCCD Transmitter Clock Input to See Figure 21, DIRI

1, TBD TBD TBD ns

Clock Output Delay CKREF

STROBE

tSK(P-P) CKSO Position Relative to DS See Figure 24, (Note 6) TBD TBD TBD ps

CKREF Serial izati on Mode

See Figure 24, (Note 6) TBD TBD TBD

No CKREF Serialization Mode

Symbol Parameter Test Conditions Min Typ Max Units

tJCC CKSO Clock Out Jitter (Cycle-to-Cycle) (Note 7) TBD ns

tTPLLS0 Serializer Phase Lock Loop Stabilization Time See Figure 20 1000 Cycles

tTPLLD0 PLL Disable Time Loss of Clock See Figure 25, (Note 8) 3.0 10.0 us

tTPLLD1 PLL Power-Down Time See Figure 26 20.0 ns

Symbol Parameter Test Conditions Min Typ Max Units

tS_DS Serial Port Setup Time DS to CKSI See Figure 23, (Note 9) 500 ps

tH_DS Serial Port Hold Time DS to CKSI See Figure 23, (Note 9)



500 ps

tRCOP Deserializer Clock Output (CKP OUT) Period See Figure 19 17.8 T 200 ns

tRCOL CKP OUT Low Time See Figure 19 (Rising Edge Strobe)

Seri al i z er Source STROBE

CKREF

Where a

(1/f)/14 (Note 10)



37a



3ns

tRCOH CKP OUT High Time 7a



37a



3ns

tPDV Data Valid to CKP HIGH See Figure 19 (Rising Edge Strobe)

Where a

(1/f)/14 (Note 10) 7a



37a7a



3ns

tROLH Output Rise Time (20% to 80%) CL

8pF 3.5 7.0 ns

tROHL Output Fall Time (80% to 20%) See Figure 16 3.5 7.0 ns

Preliminary

www.fairchildsemi.com 14

FIN12A

Control Logic Timing Controls

Capacitance

Symbol Parameter Test C onditions Min Typ Max Units

tPHL_DIR, Propagation Delay DIRI LOW-to-HIGH or HIGH-to-LOW TBD TBD 10.0 ns

tPLH_DIR DIRI-to-DIRO

tPLZ, Propagation Delay DIRI LOW-to-HIGH 7.0 ns

tPHZ DIRI-to-DP

tPZL, Propagation Delay DIRI HIGH-to-LOW 10.0 ns

tPZH DIRI-to-DP

tPLZ, Deserializer Disable Time: DIRI

0, S1(2)

0 and S2(1)

LOW-to-HIGH 7.0 ns

tPHZ S0 or S1 to DP Figure 27

tPZL, Deserializer Enable Time: DIRI

0, S1(2)

0 and S2(1)

LOW-to-HIGH 10.0 ns

tPZH S0 or S1 to DP Figure 27

tPLZ, Serializer Disable Time: DIRI

1, S1(2) and S2(1)

High-to-LOW 7.0 ns

tPHZ S0 or S1 to CKSO, DS Figure 26

tPZL, Serializer Enable Time: DIRI

1, S1(2) and S2(1)

LOW-to-HIGH 10.0 ns

tPZH S0 or S1 to CKSO, DS Figure 26

Symbol Parameter Test Conditions Min Typ Max Units

CIN Capacitance of Input Only Signals, DIRI

“1”, S1

0, TBD pF

CKREF, STROBE, S1, S2, DIRI VDD

2.5V

CIO Capacitance of Parallel Port Pins DIRI

“1”, S1

0, TBD pF

DP[1:12] VDD

2.5V

CIO-DIFF Capacitance of Differential I/O Signals DIRI

“0”, PwnDwn

0; TBD pF

0, VDD

2.5V

Preliminary

15 www.fairchildsemi.com

FIN12A

AC Loading and Waveforms

FIGURE 12. Differential LpLVDS Output DC Test Circuit

Note A: For All input pulses, tR or tF



1 ns

FIGURE 13. Differential Receiver Voltage Definitions

FIGURE 14. “Worst Case” Serialize r Test Patte rn

FIGURE 15. LpLVDS Output Load

and Transition Times FIGURE 16. LVCMOS Output Load

and Transition Times

Preliminary

www.fairchildsemi.com 16

FIN12A

AC Loading and Waveforms (Continu ed)

Setu p: M ode0

“0” or “1”m MODE1

“1”, SER/DES

“1”

FIGURE 17. Serial Setup and Hold Time FIGURE 18. LVCMOS Clock Parameters

Setup: DIRI

“0”, CKSI an d D S are Val id Signals

FIGURE 19. Deserializer Data Valid Window Time

and Cl ock Output Parameters

Note: CKREF Signal is free running.

FIGURE 20. Serializer PLL Lock Time

Note: STROBE

CKREF

FIGURE 21. Serializer Clock Propagation Delay FIGURE 22. Deserializer Clock Propagation Delay

Preliminary

17 www.fairchildsemi.com

FIN12A

AC Loading and Waveforms (Continued)

FIGURE 23. Differential Input Setup and Hold Times FIGURE 24. Differential Output Signal Skew

Note: CKREF S ignal can be stoppe d eit her HIGH or LOW

FIGURE 25. PLL Loss of Clock Disable Time FIGURE 26. PLL Power-Down Time

Note: CKREF must be active and PLL must be stable

FIGURE 27. Serializer Enable and Disable Time Note: If S1(2 ) tra ns it ioning then S2(1 ) m us t

0 for test to be valid.

FIGURE 28. Deserializer Enable and Disable Times

Preliminary

www.fairchildsemi.com 18

FIN12A

Tape and Reel Specification

TAPE FORMAT for USS-BGA

Dimensions are in millimeters

Note: A0, B0, an d K0 dimensions are determ ined wit h res pect to th e EI A/JEDEC R S-481 ro tational and lat eral movement requirements

(see sketche s A, B, and C).

Dimensions are in millimeters

Package A0B0DD1EF

K0P1P0P2TTCWWC

0.10

0.05 min

0.1

0.1 TYP TYP

0/05 TYP

0.005

0.3 TYP

3.5 x 4.5 TBD TBD 1.55 1.5 1.75 5.5 1.1 8.0 4.0 2.0 0.3 0.07 12.0 9.3

Tape Width Dia A Dim B Dia C Dia D Dim N Dim W1 Dim W2 Dim W3

max min



0.5/



0.2 min min



2.0/



0max(LSL - USL)

8 330 1.5 13.0 20.2 178 8.4 14.4 7.9

10.4

12 330 1.5 13.0 20.2 178 12.4 18.4 11.9

15.4

16 330 1.5 13.0 20.2 178 16.4 22.4 15.9

19.4

Preliminary

19 www.fairchildsemi.com

FIN12A

Tape and Reel Specification (Continued)

TAPE FORMAT for MLP

MLP Embos sed Tape Dimension

Packa ge Tape Number Cavity Cove r Tape

Designator Section Cavities Status Status

Leader (Start End) 125 (typ) Empty Sealed

MLX Carrier 2500/3000 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

Preliminary

www.fairchildsemi.com 20

FIN12A

Physical Dimensions inches (millimeters) unless otherwise noted

Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide

Packag e Num b er BGA4 2A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Preliminary

21 www.fairchildsemi.com

FIN12A PSerDes¥ Low Voltage 12-Bit Bi-Directional Serialize r/Deserializer with Multiple Frequency Ranges

(Preliminary)

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 32-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square

Package Num ber MLP032A

Fairchild does not assum e any responsibility for use of any circuitry des cribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use provided in the l abe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A criti cal com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.