January 2008 Rev 2 1/185
1
ST10F271Z1
16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM
Features
■16-bit CPU with DSP functions
– 31.25 ns instruction cycle time at 64MHz
max CPU clock
– Multiply/accumulate unit (MAC) 16 x 16-bit
multiplication, 40-bit accumulator
– Enhanced boolean bit manipulations
– Single-cycle context switching support
■On-chip memories
– 128 Kbyte Flash memory (32-bit fetch)
– Single voltage Flash memories with
erase/program controller and 100K
erasing/programming cycles.
– Up to 16 Mbyte linear address space for
code and data (5 Mbytes with CAN or I2C)
– 2 Kbyte internal RAM (IRAM)
– 10 Kbyte extension RAM (XRAM)
– Programmable external bus configuration &
characteristics for different address ranges
– Five programmable chip-select signals
– Hold-acknowledge bus arbitration support
■Interrupt
– 8-channel peripheral event controller for
single cycle interrupt driven data transfer
– 16-priority-level interrupt system with 56
sources, sampling rate down to 15.6ns
■Timers
– Two multi-functional general purpose timer
units with 5 timers
■Two 16-channel capture / compare units
■4-channel PWM unit + 4-channel XPWM
■A/D converter
– 24-channel 10-bit
–3µs minimum conversion time
■Serial channels
– Two synch. / asynch. serial channels
– Two high-speed synchronous channels
–One I
2C standard interface
■2 CAN 2.0B interfaces operating on 1 or 2 CAN
busses (64 or 2x32 message, C-CAN version)
■Fail-safe protection
– Programmable watchdog timer
– Oscillator watchdog
■On-chip bootstrap loader
■Clock generation
– On-chip PLL with 4 to 8 MHz oscillator
– Direct or prescaled clock input
■Real-time clock and 32 kHz on-chip oscillator
■Up to 111 general purpose I/O lines
– Individually programmable as input, output
or special function
– Programmable threshold (hysteresis)
■Idle, power-down and stand-by modes
■Single voltage supply: 5V ±10%
Order Codes
PQFP144 (28 x 28 x 3.4mm)
(Plastic Quad Flat Package)
LQFP144 (20 x 20 x 1.4mm)
(Low Profile Quad Flat Package)
Order code Package
Max CPU
frequency
(MHz)
Flash RAM Temperature
range (°C)
ST10F271Z1Q3 PQFP144 64 128 KB 12 KB -40/+125
ST10F271Z1T3 LQFP144 40 128 KB 12 KB -40/+125
www.st.com
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.2 Module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.1 Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.2 Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4.3 Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.4 Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4.5 Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4.6 Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4.7 Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4.8 Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4.9 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.10 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.11 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5 Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.5.1 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.5.2 Flash non-volatile write protection I register . . . . . . . . . . . . . . . . . . . . . 35
5.5.3 Flash non-volatile access protection register 0 . . . . . . . . . . . . . . . . . . . 35
5.5.4 Flash non-volatile access protection register 1 low . . . . . . . . . . . . . . . . 36
5.5.5 Flash non-volatile access protection register 1 high . . . . . . . . . . . . . . . 36
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5.5.6 XBus Flash volatile temporary access unprotection register
(XFVTAUR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5.7 Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5.8 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.5.9 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1 Selection among user-code, standard or selective bootstrap . . . . . . . . . . 43
6.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3 Alternate and selective boot mode (ABM and SBM) . . . . . . . . . . . . . . . . 44
6.3.1 Activation of the ABM and SBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.2 User mode signature integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.3 Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1 Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.3 MAC co-processor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8 External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.1 X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2 Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10 Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11 General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12 PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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13.2 I/O’s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13.2.1 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13.2.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
13.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
15 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
15.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 67
15.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
15.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 69
16 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
17 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17.1 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
17.2 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
18 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
19 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
20 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
20.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
20.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
20.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
21 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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21.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
21.2.1 Protected power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
21.2.2 Interruptible power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
21.3 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
21.3.1 Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
21.3.2 Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
21.3.3 Real-time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
21.3.4 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
22 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 107
23 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
23.1 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
23.2 XBus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
23.3 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
23.4 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
24 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
24.1 Injected conversion stalling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
24.2 Concurrent transmission requests in DAR-mode (C-CAN module) . . . . 127
24.3 Transmission request disabled (C-CAN module) . . . . . . . . . . . . . . . . . . 128
24.4 Spurious BREQ pulse in slave mode during external bus
arbitration phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
24.5 Flash wake-up from idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
24.6 Executing PWRDN instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
24.7 Flash wake-up from power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . 131
24.8 Behavior of CAPCOM outputs in compare mode 3 . . . . . . . . . . . . . . . . 131
25 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
25.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
25.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
25.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
25.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
25.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
25.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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25.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
25.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
25.7.2 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
25.7.3 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
25.7.4 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
25.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
25.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
25.8.2 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
25.8.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
25.8.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
25.8.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
25.8.6 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
25.8.7 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
25.8.8 Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
25.8.9 PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
25.8.10 PLL lock / unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
25.8.11 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
25.8.12 32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
25.8.13 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
25.8.14 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
25.8.15 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
25.8.16 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
25.8.17 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
25.8.18 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
25.8.19 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
25.8.20 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 178
26 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
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List of tables
Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2. Summary of IFlash address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3. Address space reserved to the Flash module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. Flash module sectorization (read operations). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. Flash modules sectorization
(write operations or with ROMS1=’1’ or bootstrap mode). . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12. Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14. Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15. Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 18. Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 19. Flash non-volatile write protection I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 20. Flash non-volatile access protection register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 21. Flash non-volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 22. Flash non-volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 23. XBus Flash volatile temporary access unprotection register . . . . . . . . . . . . . . . . . . . . . . . 37
Table 24. Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 25. ST10F271Z1 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 26. Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 27. MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 28. Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 29. X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 30. Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 31. Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 32. CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 57
Table 33. CAPCOM timer input frequencies, resolutions and periods at 64 MHz . . . . . . . . . . . . . . . 57
Table 34. GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 58
Table 35. GPT1 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 59
Table 36. GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 60
Table 37. GPT2 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 60
Table 38. PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 61
Table 39. PWM unit frequencies and resolutions at 64 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 61
Table 40. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . 67
Table 41. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . 68
Table 42. ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . . 68
Table 43. ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . . 69
Table 44. SSC synchronous baud rate and reload values (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . 70
Table 45. SSC synchronous baud rate and reload values (fCPU = 64 MHz) . . . . . . . . . . . . . . . . . . . 70
Table 46. WDTREL reload value (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 47. WDTREL reload value (fCPU = 64 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 48. Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Obsolete Product(s) - Obsolete Product(s)
List of tables ST10F271Z1
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Table 49. Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 50. PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 100
Table 51. Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 52. List of special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 53. List of XBus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 54. List of Flash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 55. IDMANUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 56. IDCHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 57. IDMEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 58. IDPROG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 59. List of limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 62. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 63. Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 64. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 68. A/D converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 69. On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 70. Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 71. PLL characteristics (VDD = 5 V ± 10%, VSS = 0 V, TA = –40 to +125 °C). . . . . . . . . . . . . 158
Table 72. Main oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 73. Main oscillator negative resistance (module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 74. 32kHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 75. Minimum values of negative resistance (module) for 32 kHz oscillator . . . . . . . . . . . . . . 160
Table 76. External clock drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 77. Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 79. Demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 81. External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 82. SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 84. PQFP144 - 144-pin plastic quad flatpack 28 x 28 mm, 0.65 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 85. LQFP144 - 144 pin low profile quad flat package 20x20mm, 0.5 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 86. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 List of figures
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List of figures
Figure 1. Logic symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4. ST10F271Z1 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - reset value) . . . 23
Figure 5. Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 7. CPU block diagram (MAC unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 8. MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 9. X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 10. Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 11. Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 12. Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 13. Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . . 73
Figure 14. Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . . 73
Figure 15. Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . . 74
Figure 16. Connection to one CAN bus with internal parallel mode enabled. . . . . . . . . . . . . . . . . . . . 74
Figure 17. Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 18. Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 19. Asynchronous hardware reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 20. Asynchronous hardware reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 21. Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 22. Synchronous short / long hardware reset (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 23. Synchronous long hardware reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 24. Synchronous long hardware reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 25. SW / WDT unidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 26. SW / WDT unidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 27. SW / WDT bidirectional RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 28. SW / WDT bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 29. SW / WDT bidirectional reset (EA=0) followed by a HW RESET . . . . . . . . . . . . . . . . . . . . 94
Figure 30. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 31. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 32. Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 33. Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . 97
Figure 34. Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . 98
Figure 35. PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 36. External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 37. ADC injection theoretical operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 38. ADC injection actual operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 39. ST10 in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 40. Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 41. Supply current versus the operating frequency (run and idle modes) . . . . . . . . . . . . . . . 139
Figure 42. A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 43. A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 44. Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 45. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 46. Input / output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 47. Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 48. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Obsolete Product(s) - Obsolete Product(s)
List of figures ST10F271Z1
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Figure 49. ST10F271Z1 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 50. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 51. 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 52. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 53. External memory cycle: multiplexed bus, with/without read/write delay, normal ALE. . . . 164
Figure 54. External memory cycle: multiplexed bus, with/without read/write delay, extended ALE. . 165
Figure 55. External memory cycle: multiplexed bus, with/without r/w delay, normal ALE, r/w CS. . . 166
Figure 56. External memory cycle: multiplexed bus, with/without r/w delay, extended ALE,
r/w CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 57. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 170
Figure 58. Exteral memory cycle: demultiplexed bus, with/without r/w delay, extended ALE . . . . . . 171
Figure 59. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE,
r/w CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 60. External memory cycle: demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 173
Figure 61. CLKOUT and READY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 62. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 63. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 64. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 65. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 66. PQFP144 - 144-pin plastic quad flatpack 28 x 28 mm, 0.65 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 67. LQFP144 - 144 pin low profile quad flat package 20x20 mm, 0.5 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Introduction
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1 Introduction
The ST10F271Z1 device is a derivative of the STMicroelectronics ST10 family of 16-bit
single-chip CMOS microcontrollers.
The ST10F271Z1 combines high CPU performance (up to 32 million instructions per
second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-
chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock
generation via PLL.
The ST10F271Z1 is processed in 0.18 µm CMOS technology. The MCU core and the logic
is supplied with a 5V to 1.8 V on-chip voltage regulator. The part is supplied with a single 5V
supply and I/Os work at 5 V.
The ST10F271Z1 devices are based on the ST10F272 silicon, and 100% compatible, with
the difference that only a reduced portion of the on-chip Flash and RAM memories are
usable. The available memories will be detailled in the Chapter 4: Memory organization.
Figure 1. Logic symbol
XTAL1
RSTIN
XTAL2
RSTOUT
NMI
EA / V
STBY
READY
ALE
RD
WR / WRL
Port 5
16-bit
Port 6
8-bit
Port 4
8-bit
Port 3
15-bit
Port 2
16-bit
Port 1
16-bit
Port 0
16-bit
V
DD
V
SS
Port 7
8-bit
Port 8
8-bit
V
AREF
V
AGND
ST10F271Z1
V
18
XTAL3
XTAL4
RPD
Obsolete Product(s) - Obsolete Product(s)
Pin data ST10F271Z1
12/185
2 Pin data
Figure 2. Pin configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P6.0 / CS0
P6.1 / CS1
P6.2 / CS2
P6.3 / CS3
P6.4 / CS4
P6.5 / HOLD / SCLK1
P6.6 / HLDA / MTSR1
P6.7 / BREQ / MRST1
P8.0 / XPOUT0 / CC16IO
P8.1 / XPOUT1 / CC17IO
P8.2 / XPOUT2 / CC18IO
P8.3 / XPOUT3 / CC19IO
P8.4 / CC20IO
P8.5 / CC21IO
P8.6 / RxD1 / CC22IO
P8.7 / TxD1 / CC23IO
VDD
VSS
P7.0 / POUT0
P7.1 / POUT1
P7.2 / POUT2
P7.3 / POUT3
P7.4 / CC28IO
P7.5 / CC29IO
P7.6 / CC30IO
P7.7 / CC31IO
P5.0 / AN0
P5.1 / AN1
P5.2 / AN2
P5.3 / AN3
P5.4 / AN4
P5.5 / AN5
P5.6 / AN6
P5.7 / AN7
P5.8 / AN8
P5.9 / AN9
P0H.0 / AD8
P0L.7 / AD7
P0L.6 / AD6
P0L.5 / AD5
P0L.4 / AD4
P0L.3 / AD3
P0L.2 / AD2
P0L.1 / AD1
P0L.0 / AD0
EA / VSTBY
ALE
READY
WR/WRL
RD
VSS
VDD
P4.7 / A23 / CAN2_TxD / SDA
P4.6 / A22 / CAN1_TxD / CAN2_TxD
P4.5 / A21 / CAN1_RxD / CAN2_RxD
P4.4 / A20 / CAN2_RxD / SCL
P4.3 / A19
P4.2 / A18
P4.1 / A17
P4.0 / A16
RPD
VSS
VDD
P3.15 / CLKOUT
P3.13 / SCLK0
P3.12 / BHE / WRH
P3.11 / RxD0
P3.10 / TxD0
P3.9 / MTSR0
P3.8 / MRST0
P3.7 / T2IN
P3.6 / T3IN
VAREF
VAGND
P5.10 / AN10 / T6EUD
P5.11 / AN11 / T5EUD
P5.12 / AN12 / T6IN
P5.13 / AN13 / T5IN
P5.14 / AN14 / T4EUD
P5.15 / AN15 / T2EUD
VSS
VDD
P2.0 / CC0IO
P2.1 / CC1IO
P2.2 / CC2IO
P2.3 / CC3IO
P2.4 / CC4IO
P2.5 / CC5IO
P2.6 / CC6IO
P2.7 / CC7IO
VSS
V18
P2.8 / CC8IO / EX0IN
P2.9 / CC9IO / EX1IN
P2.10 / CC10IO / EX2IN
P2.11 / CC11IO / EX3IN
P2.12 / CC12IO / EX4IN
P2.13 / CC13IO / EX5IN
P2.14 / CC14IO / EX6IN
P2.15 / CC15IO / EX7IN / T7IN
P3.0 / T0IN
P3.1 / T6OUT
P3.2 / CAPIN
P3.3 / T3OUT
P3.4 / T3EUD
P3.5 / T4IN
VSS
VDD
XTAL4
XTAL3
NMI
RSTOUT
RSTIN
VSS
XTAL1
XTAL2
VDD
P1H.7 / A15 / CC27I
P1H.6 / A14 / CC26I
P1H.5 / A13 / CC25I
P1H.4 / A12 / CC24I
P1H.3 / A11
P1H.2 / A10
P1H.1 / A9
P1H.0 / A8
VSS
VDD
P1L.7 / A7 / AN23
P1L.6 / A6 / AN22
P1L.5 / A5 / AN21
P1L.4 / A4 / AN20
P1L.3 / A3 / AN19
P1L.2 / A2 / AN18
P1L.1 / A1 / AN17
P1L.0 / A0 / AN16
P0H.7 / AD15
P0H.6 / AD14
P0H.5 / AD13
P0H.4 / AD12
P0H.3 / AD11
P0H.2 / AD10
P0H.1 / AD9
VSS
VDD
ST10F271Z1
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Pin data
13/185
Table 1. Pin description
Symbol Pin Type Function
P6.0 - P6.7
1 - 8 I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 6 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The
following Port 6 pins have alternate functions:
1OP6.0CS0 Chip select 0 output
... ... ... ... ...
5OP6.4CS4 Chip select 4 output
6IP6.5 HOLD External master hold request input
I/O SCLK1 SSC1: master clock output / slave clock input
7O P6.6 HLDA Hold acknowledge output
I/O MTSR1 SSC1: master-transmitter / slave-receiver O/I
8OP6.7 BREQ Bus request output
I/O MRST1 SSC1: master-receiver / slave-transmitter I/O
P8.0 - P8.7
9-16 I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 8 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS).
The following Port 8 pins have alternate functions:
9I/O P8.0 CC16IO CAPCOM2: CC16 capture input / compare output
O XPWM0 PWM1: channel 0 output
... ... ... ... ...
12 I/O P8.3 CC19IO CAPCOM2: CC19 capture input / compare output
O XPWM0 PWM1: channel 3 output
13 I/O P8.4 CC20IO CAPCOM2: CC20 capture input / compare output
14 I/O P8.5 CC21IO CAPCOM2: CC21 capture input / compare output
15 I/O P8.6 CC22IO CAPCOM2: CC22 capture input / compare output
I/O RxD1 ASC1: Data input (Asynchronous) or I/O (Synchronous)
16
I/O P8.7 CC23IO CAPCOM2: CC23 capture input / compare output
O TxD1 ASC1: Clock / Data output
(Asynchronous/Synchronous)
Obsolete Product(s) - Obsolete Product(s)
Pin data ST10F271Z1
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P7.0 - P7.7
19-26 I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction
bit. Programming an I/O pin as input forces the corresponding output driver to
high impedance state. Port 7 outputs can be configured as push-pull or open
drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS).
The following Port 7 pins have alternate functions:
19 O P7.0 POUT0 PWM0: channel 0 output
... ... ... ... ...
22 O P7.3 POUT3 PWM0: channel 3 output
23 I/O P7.4 CC28IO CAPCOM2: CC28 capture input / compare output
... ... ... ... ...
26 I/O P7.7 CC31IO CAPCOM2: CC31 capture input / compare output
P5.0 - P5.9
P5.10 - P5.15
27-36
39-44
I
I
16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can
be the analog input channels (up to 16) for the A/D converter, where P5.x equals
ANx (Analog input channel x), or they are timer inputs. The input threshold of
Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate
functions:
39 I P5.10 T6EUD GPT2: timer T6 external up/down control input
40 I P5.11 T5EUD GPT2: timer T5 external up/down control input
41 I P5.12 T6IN GPT2: timer T6 count input
42 I P5.13 T5IN GPT2: timer T5 count input
43 I P5.14 T4EUD GPT1: timer T4 external up/down control input
44 I P5.15 T2EUD GPT1: timer T2 external up/down control input
P2.0 - P2.7
P2.8 - P2.15
47-54
57-64 I/O
16-bit bidirectional I/O port, bit-wise programmable for input or output via
direction bit. Programming an I/O pin as input forces the corresponding output
driver to high impedance state. Port 2 outputs can be configured as push-pull or
open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS).
The following Port 2 pins have alternate functions:
47 I/O P2.0 CC0IO CAPCOM: CC0 capture input/compare output
... ... ... ... ...
54 I/O P2.7 CC7IO CAPCOM: CC7 capture input/compare output
57 I/O P2.8 CC8IO CAPCOM: CC8 capture input/compare output
I EX0IN Fast external interrupt 0 input
... ... ... ... ...
64
I/O P2.15 CC15IO CAPCOM: CC15 capture input/compare output
I EX7IN Fast external interrupt 7 input
I T7IN CAPCOM2: timer T7 count input
Table 1. Pin description (continued)
Symbol Pin Type Function
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Pin data
15/185
P3.0 - P3.5
P3.6 - P3.13,
P3.15
65-70,
73-80,
81
I/O
I/O
I/O
15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. Port 3 outputs can be configured as push-
pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or
CMOS). The following Port 3 pins have alternate functions:
65 I P3.0 T0IN CAPCOM1: timer T0 count input
66 O P3.1 T6OUT GPT2: timer T6 toggle latch output
67 I P3.2 CAPIN GPT2: register CAPREL capture input
68 O P3.3 T3OUT GPT1: timer T3 toggle latch output
69 I P3.4 T3EUD GPT1: timer T3 external up/down control input
70 I P3.5 T4IN GPT1; timer T4 input for count/gate/reload/capture
73 I P3.6 T3IN GPT1: timer T3 count/gate input
74 I P3.7 T2IN GPT1: timer T2 input for count/gate/reload / capture
75 I/O P3.8 MRST0 SSC0: master-receiver/slave-transmitter I/O
76 I/O P3.9 MTSR0 SSC0: master-transmitter/slave-receiver O/I
77 O P3.10 TxD0 ASC0: clock / data output (asynchronous/synchronous)
78 I/O P3.11 RxD0 ASC0: data input (asynchronous) or I/O (synchronous)
79 O P3.12 BHE External memory high byte enable signal
WRH External memory high byte write strobe
80 I/O P3.13 SCLK0 SSC0: master clock output / slave clock input
81 O P3.15 CLKOUT System clock output (programmable divider on CPU
clock)
Table 1. Pin description (continued)
Symbol Pin Type Function
Obsolete Product(s) - Obsolete Product(s)
Pin data ST10F271Z1
16/185
P4.0 –P4.7
85-92 I/O
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. The input threshold is selectable (TTL or
CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured as push-pull or open
drain drivers.
In case of an external bus configuration, Port 4 can be used to output the
segment address lines:
85 O P4.0 A16 Segment address line
86 O P4.1 A17 Segment address line
87 O P4.2 A18 Segment address line
88 O P4.3 A19 Segment address line
89
O
P4.4
A20 Segment address line
I CAN2_RxD CAN2: receive data input
I/O SCL I2C Interface: serial clock
90
O
P4.5
A21 Segment address line
I CAN1_RxD CAN1: receive data input
I CAN2_RxD CAN2: receive data input
91
O
P4.6
A22 Segment address line
O CAN1_TxD CAN1: transmit data output
O CAN2_TxD CAN2: transmit data output
92
O
P4.7
A23 Most significant segment address line
O CAN2_TxD CAN2: transmit data output
I/O SDA I2C Interface: serial data
RD 95 O External memory read strobe. RD is activated for every external instruction or
data read access.
WR/WRL 96 O
External memory write strobe. In WR-mode this pin is activated for every external
data write access. In WRL mode this pin is activated for low byte data write
accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See
WRCFG in the SYSCON register for mode selection.
READY/
READY 97 I
Ready input. The active level is programmable. When the ready function is
enabled, the selected inactive level at this pin, during an external memory
access, will force the insertion of waitstate cycles until the pin returns to the
selected active level.
ALE 98 O Address latch enable output. In case of use of external addressing or of
multiplexed mode, this signal is the latch command of the address lines.
Table 1. Pin description (continued)
Symbol Pin Type Function
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Pin data
17/185
EA / VSTBY 99 I
External access enable pin.
A low level applied to this pin during and after Reset forces the ST10F271Z1 to
start the program from the external memory space. A high level forces
ST10F271Z1 to start in the internal memory space. This pin is also used (when
Stand-by mode is entered, that is ST10F271Z1 under reset and main VDD turned
off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference
voltage for the low-power embedded voltage regulator which generates the
internal 1.8 V supply for the RTC module (when not disabled) and to retain data
inside the Stand-by portion of the XRAM (16 Kbyte).
It can range from 4.5 to 5.5 V (6 V for a reduced amount of time during the device
life, 4.0 V when RTC and 32 kHz on-chip oscillator amplifier are turned off). In
running mode, this pin can be tied low during reset without affecting 32 kHz
oscillator, RTC and XRAM activities, since the presence of a stable VDD
guarantees the proper biasing of all those modules.
P0L.0 -P0L.7,
P0H.0
P0H.1 -
P0H.7
100-107,
108,
111-117
I/O
Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. The input threshold of Port 0 is selectable
(TTL or CMOS).
In case of an external bus configuration, PORT0 serves as the address (A) and
as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus
in demultiplexed bus modes.
Demultiplexed bus modes
Multiplexed bus modes
P1L.0 - P1L.7
P1H.0 -
P1H.7
118-125
128-135 I/O
Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. PORT1 is used as the 16-bit address bus
(A) in demultiplexed bus modes: if at least BUSCONx is configured such the
demultiplexed mode is selected, the pis of PORT1 are not available for general
purpose I/O function. The input threshold of Port 1 is selectable (TTL or CMOS).
The pins of P1L also serve as the additional (up to 8) analog input channels for
the A/D converter, where P1L.x equals ANy (Analog input channel y,
where y = x + 16). This additional function have higher priority on demultiplexed
bus function.
The following PORT1 pins have alternate functions:
132 I P1H.4 CC24IO CAPCOM2: CC24 capture input
133 I P1H.5 CC25IO CAPCOM2: CC25 capture input
134 I P1H.6 CC26IO CAPCOM2: CC26 capture input
135 I P1H.7 CC27IO CAPCOM2: CC27 capture input
Table 1. Pin description (continued)
Symbol Pin Type Function
Data path width 8-bit 16-bi
P0L.0 – P0L.7: D0 – D7 D0 - D7
P0H.0 – P0H.7: I/O D8 - D15
Data path width 8-bit 16-bi
P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7: A8 – A15 AD8 - AD15
Obsolete Product(s) - Obsolete Product(s)
Pin data ST10F271Z1
18/185
XTAL1 138 I XTAL1 Main oscillator amplifier circuit and/or external clock input.
XTAL2 137 O XTAL2 Main oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in
the AC Characteristics must be observed.
XTAL3 143 I XTAL3 32 kHz oscillator amplifier circuit input
XTAL4 144 O XTAL4 32 kHz oscillator amplifier circuit output
When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,
XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32
in RTCCON register shall be set. 32 kHz oscillator can only be driven by an
external crystal, and not by a different clock source.
RSTIN 140 I
Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for
a specified duration while the oscillator is running resets the ST10F271Z1. An
internal pull-up resistor permits power-on reset using only a capacitor connected
to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON
register), the RSTIN line is pulled low for the duration of the internal reset
sequence.
RSTOUT 141 O
Internal Reset Indication Output. This pin is driven to a low level during hardware,
software or watchdog timer reset.
RSTOUT
remains low until the EINIT (end of
initialization) instruction is executed.
NMI 142 I
Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU
to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when
the PWRDN (power-down) instruction is executed, the NMI pin must be low in
order to force the ST10F271Z1 to go into power-down mode. If NMI is high and
PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal
mode.
If not used, pin NMI should be pulled high externally.
VAREF 37 - A/D converter reference voltage and analog supply
VAGND 38 - A/D converter reference and analog ground
RPD 84 - Timing pin for the return from interruptible power-down mode and synchronous /
asynchronous reset selection.
VDD
17, 46,
72,82,93
, 109,
126, 136
-
Digital supply voltage = + 5 V during normal operation, idle and power-down
modes.
It can be turned off when Stand-by RAM mode is selected.
VSS
18,45,
55,71,
83,94,
110,
127, 139
- Digital ground
V18 56 - 1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF)
must be connected between this pin and nearest VSS pin.
Table 1. Pin description (continued)
Symbol Pin Type Function
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Functional description
19/185
3 Functional description
The architecture of the ST10F271Z1 combines advantages of both RISC and CISC
processors and an advanced peripheral subsystem. The block diagram gives an overview of
the different on-chip components and the high bandwidth internal bus structure of the
ST10F271Z1.
Figure 3. Block diagram
4-8 MHz
External Bus
Controller
10-bit ADC
GPT1 / GPT2
ASC0
BRG BRG
SSC0
PWM
CAPCOM2
CAPCOM1
Port 0Port 1Port 4
Port 6 Port 5
CPU-Core and MAC Unit
XCAN2
XSSC
XASC
XCAN1
XI2C
XRAM
2K
XRAM
8K
(STBY)
(PEC)
IFlash
128K
32
16
16
16
16 16
16 16
16
PEC
Interrupt Controller
Port 3 Port 7 Port 8
16
Watchdog
IRAM
2K
16
XRTC PLL
5V-1.8V
Voltage
Regulator
Port 2
16
16
8
81615 8 8
16
16
32kHz
Oscillator
XPWM
16
16
Oscillator
Obsolete Product(s) - Obsolete Product(s)
Memory organization ST10F271Z1
20/185
4 Memory organization
The memory space of the ST10F271Z1 is configured in a unified memory architecture.
Code memory, data memory, registers and I/O ports are organized within the same linear
address space of 16 Mbytes. The entire memory space can be accessed Byte wise or Word
wise. Particular portions of the on-chip memory have additionally been made directly bit
addressable.
IFlash: 128 Kbytes of on-chip Flash memory. It is divided in 6 blocks (B0F0...B0F5) that
constitute the Bank 0. When Bootstrap mode is selected, the Test-Flash Block B0TF
(8 Kbyte) appears at address 00’0000h: refer to Chapter 5: Internal Flash memory on
page 24 for more details on memory mapping in boot mode. The summary of address range
for IFlash is the following:
(1) This area must be reserved by the application mapping.
IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data,
system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0
to R15) and / or Bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group.
XRAM: 8K+2 Kbytes of on-chip extension RAM (single port XRAM) is provided as a storage
for data, user stack and code.
The XRAM is divided into 2 areas, the first 2 Kbytes named XRAM1 and the second
8 Kbytes named XRAM2, connected to the internal XBUS and are accessed like an external
memory in 16-bit demultiplexed bus-mode without wait state or read/write delay (31.25ns
access at 64MHz CPU clock). Byte and Word accesses are allowed.
The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register),
and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then
any access in the address range 00’E000h - 00’E7FFh will be directed to external memory
interface, using the BUSCONx register corresponding to address matching ADDRSELx
register.
The XRAM2 address range is the one selected programming XADRS3 register, if XPEN (bit
2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is
cleared, then any access in the address range programmed for XRAM2 will be directed to
Table 2. Summary of IFlash address range
Blocks User mode Size
B0TF Not visible 8K
B0F0 00’0000h - 00’1FFFh 8K
B0F1 00’2000h - 00’3FFFh 8K
B0F2 00’4000h - 00’5FFFh 8K
B0F3 00’6000h - 00’7FFFh 8K
B0F4 01’8000h - 01’FFFFh 32K
B0F5 02’0000h - 02’FFFFh 64K
Reserved (1) 03’0000h - 03’FFFFh / RESERVED 64K
Reserved (1) 04’0000h - 04’FFFFh / RESERVED 64K
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Memory organization
21/185
external memory interface, using the BUSCONx register corresponding to address
matching ADDRSELx register.
After reset the XRAM2 is mapped from address 09’0000h.
XRAM2 represents also the Stand-by RAM, which can be maintained biased through EA /
VSTBY pin when main supply VDD is turned off.
As the XRAM appears like external memory, it cannot be used as system stack or as
register banks. The XRAM is not provided for single bit storage and therefore is not bit
addressable.
ST10F271 XRAM: 8 K + 2 Kbytes of XRAM
The XRAM1 (2 Kbytes) address range is 00’E000h - 00’E7FFh if enabled.
The XRAM2 (8 Kbytes) address range is after reset 09’0000h - 09’1FFFh and is mirrored
every 16 Kbyte boundary.
SFR/ESFR: 1024 Bytes (2 x 512 Bytes) of address space is reserved for the special
function register areas. SFRs are Wordwide registers which are used to control and to
monitor the function of the different on-chip units.
CAN1: Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 Module access. The
CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit
0 of the XPERCON register. Accesses to the CAN Module use demultiplexed addresses
and a 16-bit data bus (only word accesses are possible). Two wait states give an access
time of 62.5ns at 64MHz CPU clock. No tri-state wait states are used.
CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access. The
CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit
1 of the new XPERCON register. Accesses to the CAN Module use demultiplexed
addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an
access time of 62.5ns at 64MHz CPU clock. No tri-state wait states are used.
Note: If one or the two CAN modules are used, Port 4 cannot be programmed to output all 8
segment address lines. Thus, only 4 segment address lines can be used, reducing the
external memory space to 5 Mbytes (1 Mbyte per CS line).
RTC: Address range 00’ED00h - 00’EDFFh is reserved for the RTC Module access. The
RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON
register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz
CPU clock. No tristate waitstate is used.
PWM1: Address range 00’EC00h - 00’ECFFh is reserved for the PWM1 Module access.
The PWM1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the
XPERCON register. Accesses to the PWM1 Module use demultiplexed addresses and a 16-
bit data bus (only word accesses are possible). Two waitstates give an access time of
62.5ns at 64MHz CPU clock. No tristate waitstate is used. Only word access is allowed.
ASC1: Address range 00’E900h - 00’E9FFh is reserved for the ASC1 Module access. The
ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON
register. Accesses to the ASC1 Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64 MHz
CPU clock. No tristate waitstate is used.
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SSC1: Address range 00’E800h - 00’E8FFh is reserved for the SSC1 Module access. The
SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON
register. Accesses to the SSC1 Module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64 MHz
CPU clock. No tristate waitstate is used.
I2C: Address range 00’EA00h - 00’EAFFh is reserved for the I2C Module access. The I2C is
enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register.
Accesses to the I2C Module use demultiplexed addresses and a 16-bit data bus (only word
accesses are possible). Two waitstates give an access time of 62.5 ns at 64 MHz CPU
clock. No tristate waitstate is used.
X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set
of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON
register and bit 10 of the XPERCON register. Accesses to this additional features use
demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two
waitstates give an access time of 62.5 ns at 64 MHz CPU clock. No tristate waitstate is
used. The following set of features are provided:
●CLKOUT programmable divider
●XBUS interrupt management registers
●ADC multiplexing on P1L register
●Port1L digital disable register for extra ADC channels
●CAN2 multiplexing on P4.5/P4.6
●CAN1-2 main clock prescaler
●Main Voltage Regulator disable for power-down mode
●TTL / CMOS threshold selection for Port0, Port1, and Port5.
In order to meet the needs of designs where more memory is required than is provided on
chip, up to 16 Mbytes of external memory can be connected to the microcontroller.
Visibility of XBUS peripherals
In order to keep the ST10F271Z1 compatible with the ST10F168 / ST10F269, the XBUS
peripherals can be selected to be visible on the external address / data bus. Different bits for
X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the
global enabling with XPEN bit in SYSCON register, the corresponding address space, port
pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and
not available. Refer to Chapter 23: Register set on page 108.
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Figure 4. ST10F271Z1 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - reset value)
FF FFFF
00 0000
16 MB
255
0
Code Data
Page
1023
0
Data
Page
1
3
5
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
07 FFFF
06 0000
05 FFFF
04 0000
03 FFFF
02 0000
01 FFFF
00 0000
Flash
Flash
Reserved
00 C000
00 FFFF
XCAN1
ESFR
SFR
IRAM
Reserved
00 DFFF
00 E000
00 E7FF
00 E800
00 FDFF
00 FE00
00 F1FF
00 F200
00 F5FF
00 F600
8K
256
512
1K
2K
512
Data Page 3 (Segment 0) - 16 Kbyte
256
XCAN2
9
20
21
22
23
0A 0000
09 FFFF
08 0000
11
24
25
26
27
0C 0000
0B FFFF
13
28
29
30
31
0E 0000
0D FFFF
15
32
33
34
35
0F FFFF
00 F000
SFR
00 FFFF
01 0000
00 FDFF
00 FE00
512
512
00 EFFF
00 F000
XRAM1 2K
14
0F 0000
0E FFFF
12
0D 0000
0C FFFF
10
0B 0000
0A FFFF
8
6
4
05 0000
04 FFFF
07 0000
06 FFFF
09 0000
08 FFFF
2
03 0000
02 FFFF
0
0
Flash
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Reserved
Reserved
Reserved
01 0000
00 FFFF
Code
Segment
64
65
66
67
64
65
66
67
16
17
10 0000
10 FFFF
11 0000
11 FFFF
Flash + XRAM - 1 Mbyte
IRAM
00 EFFF
XSSC
XASC
XI2C
256
256
256
XRTC
1K
00 F1FF
00 F200
00 F5FF
00 F600
256
Reserved
XPWM 256
256
2K
XMiscellaneous
RAM / SFR (4 Kbyte)
Segment
ESFR
Reserved
Bit-addressable Memory
XADRS3 = 800Bh (512K)
Ext. Memory
Ext. Memory
Ext. Memory
Ext. Memory
Ext. Memory
* The first 32K of Flash may be remapped from segment 0 to segment 1 by setting SYSCON-ROMS1 (before EINIT).
Absolute Memory Address are hexadecimal values, while Data Page Number are decimal values.
Reserved
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
XRAM2
Address Area, where XRAM2
is mirrored every 16 Kbytes
boundary after reset
XRAM2
XRAM2
XRAM2
XRAM2
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5 Internal Flash memory
5.1 Overview
The on-chip Flash is composed by one matrix module, 128 Kbytes wide.
This module is on ST10 Internal bus, so it is called IFlash
Figure 5. Flash structure
The programming operations of the Flash are managed by an embedded Flash
Program/Erase Controller (FPEC). The High Voltages needed for Program/Erase operations
are internally generated.
The Data bus is 32-bit wide for fetch accesses to IFlash, while it is 16 bit wide for read
accesses to IFlash. Read/write accesses to IFlash Control Registers area are 16 bit wide.
5.2 Functional description
5.2.1 Structure
The following table shows the Address space reserved to the Flash module.
Note: 1 The ST10F271Z1 being based on the same silicon as the ST10F272, 256 Kbyte of Flash
are implemented on the device. The range 03’0000h - 04’FFFFh is not physically disabled
even if not available for use. Therefore this address range MUST be reserved by the
Flash Control
Bank 0: 128 Kbyte
Program Memory
HV and Ref.
Generator
Program/Erase
Controller
I-BUS Interface
+
8 Kbyte Test-Flash
IFlash Control Section
Registers
Table 3. Address space reserved to the Flash module
Description Addresses Size
IFlash sectors 0x00 0000 to 0x02 FFFF 128 Kbytes
IFlash reserved sector 1) 0x03 0000 to 0x04 FFFF 128 Kbytes
Reserved IBUS area 2) 0x05 0000 to 0x07 FFFF 192 Kbytes
Registers and Flash internal reserved area 0x08 0000 to 0x08 FFFF 64 Kbytes
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application mapping. Accesses to this address range will send back the content of the Flash
cell (by default FFFFh, blank value when the device is delivered)
2 Accesses to the area will send back the value 009Bh.
5.2.2 Module structure
The IFlash module is composed by a bank (Bank 0) of 128 Kbyte of Program Memory
divided in 6 sectors (B0F0...B0F5). Bank 0 contains also a reserved sector named Test-
Flash. The Addresses from 0x08 0000 to 0x08 FFFF are reserved for the Control Register
Interface and other internal service memory space used by the Flash Program/Erase
controller.
The following tables show the memory mapping of the Flash when it is accessed in read
mode (Table 4: Flash module sectorization (read operations)), and when accessed in write
or erase mode (Table 5: Flash modules sectorization (write operations or with ROMS1=’1’ or
bootstrap mode)): note that with this second mapping, the first four banks are remapped into
code segment 1 (same as obtained setting bit ROMS1 in SYSCON register).
Table 4. Flash module sectorization (read operations)
Bank Description Addresses Size ST10 Bus size
B0
Bank 0 Flash 0 (B0F0) 0x0000 0000 - 0x0000 1FFF 8 KB
32-bit (I-BUS)
Bank 0 Flash 1 (B0F1) 0x0000 2000 - 0x0000 3FFF 8 KB
Bank 0 Flash 2 (B0F2) 0x0000 4000 - 0x0000 5FFF 8 KB
Bank 0 Flash 3 (B0F3) 0x0000 6000 - 0x0000 7FFF 8 KB
Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB
Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB
Reserved (1)
1. This area must be reserved by the application mapping.
0x0003 0000 - 0x0003 FFFF 64 KB
Reserved (1) 0x0004 0000 - 0x0004 FFFF 64 KB
Table 5. Flash modules sectorization
(write operations or with ROMS1=’1’ or bootstrap mode)
Bank Description Addresses Size ST10 bus size
B0
Bank 0 Test-Flash (B0TF) 0x0000 0000 - 0x0000 1FFF 8 KB
32-bit (I-BUS)
Bank 0 Flash 0 (B0F0) 0x0001 0000 - 0x0001 1FFF 8 KB
Bank 0 Flash 1 (B0F1) 0x0001 2000 - 0x0001 3FFF 8 KB
Bank 0 Flash 2 (B0F2) 0x0001 4000 - 0x0001 5FFF 8 KB
Bank 0 Flash 3 (B0F3) 0x0001 6000 - 0x0001 7FFF 8 KB
Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB
Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB
Reserved (1)
1. This area must be reserved by the application mapping.
0x0003 0000 - 0x0003 FFFF 64 KB
Reserved (1) 0x0004 0000 - 0x0004 FFFF 64 KB
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The table above refers to the configuration when bit ROMS1 of SYSCON register is set.
When Bootstrap mode is entered:
●Test-Flash is seen and available for code fetches (address 00’0000h)
●User I-Flash is only available for read and write accesses
●Write accesses must be made with addresses starting in segment 1 from 01'0000h,
whatever ROMS1 bit in SYSCON value
●Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.
In Bootstrap mode, by default ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in
segment 0.
Example:
In default configuration, to program address 0, user must put the value 01'0000h in the
FARL and FARH registers, but to verify the content of the address 0 a read to 00'0000h must
be performed.
Next Table 6: Control register interface shows the Control Register interface composition:
this set of registers can be addressed by the CPU.
5.2.3 Low power mode
The Flash module is automatically switched off executing PWRDN instruction. The
consumption is drastically reduced, but exiting this state can require a long time (tPD).
Recovery time from power-down mode for the Flash modules is anyway shorter than the
main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash,
it is important to size properly the external circuit on RPD pin.
Note: PWRDN instruction must not be executed while a Flash program/erase operation is in
progress.
Table 6. Control register interface
Name Description Addresses Size Bus
size
FCR1-0 Flash control registers 1-0 0x0008 0000 - 0x0008 0007 8 byte
16-bit
FDR1-0 Flash data registers 1-0 0x0008 0008 - 0x0008 000F 8 byte
FAR Flash address registers 0x0008 0010 - 0x0008 0013 4 byte
FER Flash error register 0x0008 0014 - 0x0008 0015 2 byte
FNVWPIR Flash non volatile protection I Register 0x0008 DFB0 - 0x0008
DFB1 2 byte
FNVAPR0 Flash non-volatile access protection
Register 0
0x0008 DFB8 - 0x0008
DFB9 2 byte
FNVAPR1 Flash non-volatile access protection
Register 1
0x0008 DFBC - 0x0008
DFBF 4 byte
XFVTAUR0 XBus Flash volatile temporary access
unprotection register 0 0x0000 EB50 - 0x0000 EB51 2 byte
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5.3 Write operation
The Flash module have one single register interface mapped in the memory space of the
IBUS (0x08 0000 to 0x08 0015). All the operations are enabled through four 16-bit control
registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit
registers are used to store Flash Address and Data for Program operations (FARH/L and
FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible
with 8 and 16-bit instructions (since operates in 16-bit mode when in read/ write).
Before accessing the IFlash module (and consequently also the Flash register to be used for
program/erasing operations), bit ROMEN in SYSCON register shall be set.
During a Flash write operation any attempt to read the Flash itself, that is under
modification, will output invalid data (software trap 009Bh). This means that the Flash is not
fetchable when a programming operation is active: the write operation commands must be
executed from another memory (internal RAM or external memory), as in ST10F269 device.
In fact, due to IBUS characteristics, it is not possible to perform a write operation on IFlash,
when fetching code from IFlash.
Direct addressing is not allowed for write accesses to IFlash Control Registers.
During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the
Flash Control Registers.
Power supply drop
If during a write operation the internal low voltage supply drops below a certain internal
voltage threshold, any write operation running is suddenly interrupted and the module is
reset to Read mode. At following Power-on, the interrupted Flash write operation must be
repeated.
5.4 Register description
5.4.1 Flash control register 0 low
The Flash Control Register 0 Low (FCR0L) together with the Flash Control Register 0 High
(FCR0H) is used to enable and to monitor all the write operations on the IFlash. The user
has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by
the user in Bootstrap Mode only.
FCR0L (0x08 0000) FCR Reset Value: 0000h
1514131211109876543210
reserved LOCK res. res. BSY0 res.
RR
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5.4.2 Flash control register 0 high
The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low
(FCR0L) is used to enable and to monitor all the write operations on the IFlash. The user
has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by
the user in Bootstrap Mode only.
Table 7. Flash control register 0 low
Bit Function
BSY0
Bank 0 Busy (IFlash)
This bit indicates that a write operation is running on Bank 0 (IFlash). It is
automatically set when bit WMS is set. Setting Protection operation sets bit BSY0
(since protection registers are in this Block). When this bit is set, every read
access to Bank 0 will output invalid data (software trap 009Bh), while every write
access to the Bank will be ignored. At the end of the write operation or during a
Program or Erase Suspend this bit is automatically reset and the Bank returns to
read mode. After a Program or Erase Resume this bit is automatically set again.
LOCK
Flash Registers Access Locked
When this bit is set, it means that the access to the Flash Control Registers
FCR0H/-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC:
any read access to the registers will output invalid data (software trap 009Bh) and
any write access will be ineffective. LOCK bit is automatically set when the Flash
bit WMS is set.
This is the only bit the user can always access to detect the status of the Flash:
once it is found low, the rest of FCR0L and all the other Flash registers are
accessible by the user as well.
Note that FER content can be read when LOCK is low, but its content is updated
only when also BSY0 bit is reset.
FCR0H (0x08 0002) FCR Reset value: 0000h
1514131211109876543210
WMS SUSP WPG DWPG SER reserved SPR reserved
RW RW RW RW RW RW
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Table 8. Flash control register 0 high
Bit Function
SPR
Set Protection
This bit must be set to select the Set Protection operation. The Set Protection
operation allows to program 0s in place of 1s in the Flash non-volatile protection
registers. The Flash address in which to program must be written in the FARH/L
registers, while the Flash Data to be programmed must be written in the FDR0H/L
before starting the execution by setting bit WMS. A sequence error is flagged by bit
SEQER of FER if the address written in FARH/L is not in the range 0x0E8FB0-
0x08DFBF. SPR bit is automatically reset at the end of the Set Protection
operation.
SER
Sector Erase
This bit must be set to select the Sector Erase operation in the Flash modules. The
Sector Erase operation allows to erase all the Flash locations to value 0xFF. From
1 to all the sectors of the same Bank (excluded Test-Flash for Bank B0) can be
selected to be erased through bits BxFy of FCR1H/L registers before starting the
execution by setting bit WMS. It is not necessary to pre-program the sectors to
0x00, because this is done automatically. SER bit is automatically reset at the end
of the Sector Erase operation.
DWPG
Double Word Program
This bit must be set to select the Double Word (64 bits) Program operation in the
Flash module. The Double Word Program operation allows to program 0s in place
of 1s. The Flash Address in which to program (aligned with even words) must be
written in the FARH/L registers, while the 2 Flash Data to be programmed must be
written in the FDR0H/L registers (even word) and FDR1H/L registers (odd word)
before starting the execution by setting bit WMS. DWPG bit is automatically reset
at the end of the Double Word Program operation.
WPG
Word Program
This bit must be set to select the Word (32 bits) Program operation in the Flash
module. The Word Program operation allows to program 0s in place of 1s. The
Flash Address to be programmed must be written in the FARH/L registers, while
the Flash Data to be programmed must be written in the FDR0H/L registers before
starting the execution by setting bit WMS. WPG bit is automatically reset at the
end of the Word Program operation.
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5.4.3 Flash control register 1 low
The Flash Control Register 1 Low (FCR1L), together with Flash Control Register 1 High
(FCR1H), is used to select the Sectors to Erase, or during any write operation to monitor the
status of each Sector and Bank.
SUSP
Suspend
This bit must be set to suspend the current Program (Word or Double Word) or
Sector Erase operation in order to read data in one of the Sectors of the Bank
under modification or to program data in another Bank. The Suspend operation
resets the Flash Bank to normal read mode (automatically resetting bit BSY0).
When in Program Suspend, the Flash module accepts only the following
operations: Read and Program Resume. When in Erase Suspend the module
accepts only the following operations: Read, Erase Resume and Program (Word
or Double Word; Program operations cannot be suspended during Erase
Suspend). To resume a suspended operation, the WMS bit must be set again,
together with the selection bit corresponding to the operation to resume (WPG,
DWPG, SER).
Note: It is forbidden to start a new Write operation with bit SUSP already set.
WMS
Write Mode Start
This bit must be set to start every write operation in the Flash module. At the end
of the write operation or during a Suspend, this bit is automatically reset. To
resume a suspended operation, this bit must be set again. It is forbidden to set this
bit if bit ERR of FER is high (the operation is not accepted). It is also forbidden to
start a new write (program or erase) operation (by setting WMS high) when bit
SUSP of FCR0 is high. Resetting this bit by software has no effect.
Table 8. Flash control register 0 high (continued)
Bit Function
FCR1L (0x08 0004) FCR Reset value: 0000h
1514131211109876543210
reserved B0F5 B0F4 B0F3 B0F2 B0F1 B0F0
RS RS RS RS RS RS
Table 9. Flash control register 1 low
Bit Function
B0F(5:0)
Bank 0 IFlash Sector 5:0 Status
These bits must be set during a Sector Erase operation to select the sectors to
erase in Bank 0. Besides, during any erase operation, these bits are automatically
set and give the status of the 6 sectors of Bank 0 (B0F5-B0F0). The meaning of
B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end
of a Write operation if no errors are detected.
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5.4.4 Flash control register 1 high
The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low
(FCR1L), is used to select the Sectors to Erase, or during any write operation to monitor the
status of each Sector and Bank.
During any erase operation, this bit is automatically set and gives the status of the Bank 0.
The meaning of B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end of an
erase operation if no errors are detected.
5.4.5 Flash data register 0 low
The Flash Address Registers (FARH/L) and the Flash Data Registers (FDR1H/L-FDR0H/L)
are used during the program operations to store Flash Address in which to program and
Data to program.
FCR1H (0x08 0006) FCR Reset value: 0000h
1514131211109876543210
reserved B0S reserved
RS
Table 10. Flash control register 1 high
Bit Function
B0S
Bank 0 Status (IFlash)
During any erase operation, this bit is automatically modified and gives the status
of the Bank 0. The meaning of B0S bit is given in the next Table 4 Banks (BxS) and
Sectors (BxFy) Status bits meaning. This bit is automatically reset at the end of a
erase operation if no errors are detected.
Table 11. Banks (BxS) and sectors (BxFy) status bits meaning
ERR SUSP B0S = 1 meaning B0Fy = 1 meaning
1 - Erase error in Bank 0 Erase error in sector y of Bank 0
0 1 Erase suspended in Bank 0 Erase suspended in sector y of Bank 0
0 0 Don’t care Don’t care
FDR0L (0x08 0008) FCR Reset value: FFFFh
1514131211109876543210
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
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5.4.6 Flash data register 0 high
5.4.7 Flash data register 1 low
5.4.8 Flash data register 1 high
Table 12. Flash data register 0 low
Bit Function
DIN(15:0)
Data Input 15:0
These bits must be written with the Data to program the Flash with the following
operations: Word Program (32-bit), Double Word Program (64-bit) and Set
Protection.
FDR0H (0x08 000A) FCR Reset value: FFFFh
1514131211109876543210
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 13. Flash data register 0 high
Bit Function
DIN(31:16)
Data Input 31:16
These bits must be written with the Data to program the Flash with the following
operations: word program (32-bit), double word program (64-bit) and set
protection.
FDR1L (0x08 000C) FCR Reset value: FFFFh
1514131211109876543210
DIN15 DIN14 DIN13 DIN12 DIN11 DIN10
DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 14. Flash data register 1 low
Bit Function
DIN(15:0)
Data Input 15:0
These bits must be written with the data to program the Flash with the following
operations: word program (32-bit), double word program (64-bit) and set
protection.
FDR1H (0x08 000E) FCR Reset value: FFFFh
1514131211109876543210
DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
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5.4.9 Flash address register low
5.4.10 Flash address register high
Table 15. Flash data register 1 high
Bit Function
DIN(
31:16
)
Data input 31:16
These bits must be written with the data to program the Flash with the following
operations: word program (32-bit), double word program (64-bit) and set
protection.
FARL (0x08 0010) FCR Reset value: 0000h
1514131211109876543210
ADD15ADD14ADD13ADD12ADD11ADD10
ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2
reserved
RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 16. Flash address register low
Bit Function
ADD(15:2)
Address 15:2
These bits must be written with the address of the Flash location to program in the
following operations: word program (32-bit) and double word program (64-bit). in
double word program bit ADD2 must be written to ‘0’.
FARH (0x08 0012) FCR Reset value: 0000h
1514131211109876543210
reserved ADD20 ADD19 ADD18 ADD17 ADD16
RW RW RW RW RW
Table 17. Flash address register high
Bit Function
ADD(20:16)
Address 20:16
These bits must be written with the address of the Flash location to program in the
following operations: word program and double word program.
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5.4.11 Flash error register
Flash error register, as well as all the other Flash registers, can be properly read only once
LOCK bit of register FCR0L is low. Nevertheless, its content is updated when also BSY0 bit
is reset as well; for this reason, it is definitively meaningful reading FER register content only
when LOCK bit and BSY0 bit are cleared.
FER (0x8 0014h) FCR Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WPF RESER SEQER reserved 10ER PGER ERER ERR
RC RC RC RC RC RC RC
Table 18. Flash error register
Bit Function
ERR
Write error
This bit is automatically set when an error occurs during a Flash write operation or
when a bad write operation setup is done. Once the error has been discovered
and understood, ERR bit must be software reset.
ERER
Erase error
This bit is automatically set when an erase error occurs during a Flash write
operation. This error is due to a real failure of a Flash cell, that can no more be
erased. This kind of error is fatal and the sector where it occurred must be
discarded. This bit has to be software reset.
PGER
Program error
This bit is automatically set when a program error occurs during a Flash write
operation. This error is due to a real failure of a Flash cell, that can no more be
programmed. The word where this error occurred must be discarded. This bit has
to be software reset.
10ER
1 over 0 error
This bit is automatically set when trying to program at 1 bits previously set at 0
(this does not happen when programming the protection bits). This error is not due
to a failure of the Flash cell, but only flags that the desired data has not been
written. This bit has to be software reset.
SEQER
Sequence error
This bit is automatically set when the control registers (FCR1H/L-FCR0H/L,
FARH/L, FDR1H/L-FDR0H/L) are not correctly filled to execute a valid write
operation. In this case no write operation is executed. This bit has to be software
reset.
RESER
Resume error
This bit is automatically set when a suspended program or erase operation is not
resumed correctly due to a protocol error. In this case the suspended operation is
aborted. This bit has to be software reset.
WPF
Write Protection Flag
This bit is automatically set when trying to program or erase in a sector write
protected. In case of multiple sector erase, the not protected sectors are erased,
while the protected sectors are not erased and bit WPF is set. This bit has to be
software reset.
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5.5 Protection strategy
The protection bits are stored in non-volatile Flash cells inside IFlash module, that are read
once at reset and stored in 4 Volatile registers. Before they are read from the non-volatile
cells, all the available protections are forced active during reset.
The protections can be programmed using the set protection operation (see Flash control
registers paragraph), that can be executed from all the internal or external memories except
from the Flash itself.
Two kind of protections are available: write protections to avoid unwanted writings and
access protections to avoid piracy. In next paragraphs all different level of protections are
shown, and architecture limitations are highlighted as well.
5.5.1 Protection registers
The 4 non-volatile protection registers are one time programmable for the user.
One register (FNVWPIR) is used to store the write protection fuses respectively for each
sector IFlash module. The other three registers (FNVAPR0 and FNVAPR1L/H) are used to
store the access protection fuses.
5.5.2 Flash non-volatile write protection I register
5.5.3 Flash non-volatile access protection register 0
FNVWPIR (0x08 DFB0) NVR Reset value: FFFFh
1514131211109876543210
reserved W0P7W0P6W0P5W0P4W0P3W0P2W0P1W0P0
RW RW RW RW RW RW RW RW
Table 19. Flash non-volatile write protection I register
Bit Function
W0P(9:0)
Write protection bank 0 / sectors 9-0 (IFlash)
These bits, if programmed at 0, disable any write access to the sectors of bank 0
(IFlash)
FNVAPR0 (0x08 DFB8) NVR Reset value: ACFFh
1514131211109876543210
reserved DBGP ACCP
RW RW
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5.5.4 Flash non-volatile access protection register 1 low
5.5.5 Flash non-volatile access protection register 1 high
Table 20. Flash non-volatile access protection register 0
Bit Function
ACCP
Access protection
This bit, if programmed at 0, disables any access (read/write) to data mapped
inside IFlash module address space, unless the current instruction is fetched from
IFlash.
DBGP
Debug protection
This bit, if erased at 1, allows to by-pass all the protections using the debug
features through the Test Interface. If programmed at 0, on the contrary, all the
debug features, the Test Interface and all the Flash test modes are disabled. Even
STMicroelectronics will not be able to access the device to run any eventual failure
analysis.
FNVAPR1L (0x08 DFBC) NVR Delivery value: FFFFh
1514131211109876543210
PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 21. Flash non-volatile access protection register 1 low
Bit Function
PDS(15:0)
Protections Disable 15-0
If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP
is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP
have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit
PENx-1 has already been programmed at 0.
FNVAPR1H (0x08 DFBE) NVR Delivery value: FFFFh
1514131211109876543210
PEN15PEN14PEN13PEN12PEN11PEN10
PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Table 22. Flash non-volatile access protection register 1 high
Bit Function
PEN15-0
Protections enable 15-0
If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit
ACCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has
already been programmed at 0.
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5.5.6 XBus Flash volatile temporary access unprotection register
(XFVTAUR0)
5.5.7 Access protection
The I-Flash module has one level of access protection (access to data both in Reading and
Writing): if bit ACCP of FNVAPR0 is programmed at 0 and bit TAUB in XFVTAUR0 is set at
0, the I-Flash module becomes access protected: data in the I-Flash module can be read
only if the current execution is from the I-Flash module itself.
To enable Access Protection, the following sequence of operations is recommended:
●execution from external memory or internal Rams
●program TAUB bit at 1 in XFVTAUR0 register
●program ACCP bit in FNVAPR0 to 0 using Set Protection operation
●program TAUB bit at 0 in XFVTAUR0 register
●Access Protection is active when both ACCP bit and TAUB bit are set to 0.
Protection can be permanently disabled by programming bit PDS0 of FNVAPR1H, in order
to analyze rejects. Protection can be permanently enabled again by programming bit PEN0
of FNVAPR1L. The action to disable and enable again Access Protections in a permanent
way can be executed a maximum of 16 times. To execute the above described operations,
the Flash has to be temporary unprotected (See Section 5.5.9: Temporary unprotection)
Trying to write into the access protected Flash from internal RAM or external memories will
be unsuccessful. Trying to read into the access protected Flash from internal RAM or
external memories will output a dummy data (software trap 0x009Bh).
When the Flash module is protected in access, also the data access through PEC of a
peripheral is forbidden. To read/write data in PEC mode from/to a protected bank, first it is
necessary to temporary unprotect the Flash module.
In the following table a summary of all levels of possible access protection is reported: in
particular, supposing to enable all possible access protections, when fetching from a
memory as listed in the first column, what is possible and what is not possible to do (see
column headers) is shown in the table.
XFVTAUR0 (0x00 EB50) NVR Reset value: 0000h
1514131211109876543210
TAU B
reserved RW
Table 23. XBus Flash volatile temporary access unprotection register
Bit Function
TAU B
Temporary access unprotection bit
If this bit is set to 1, the access protection is temporary disabled.
This bit can be written only executing from IFlash.This fact guarantees that only a
code executed in IFlash, can unprotect the IFlash, when it is Access Protected.
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When the Access Protection is enabled, Flash registers can not be written, so no
program/erase operation can be run on I-Flash. To enable the access to registers again, the
Temporary Access Unprotection procedure has to be followed (see Section 5.5.9).
5.5.8 Write protection
The Flash modules have one level of write protections: each sector of each bank of each
Flash module can be software write protected by programming at 0 the related bit W0Px in
FNVWPIRL register.
5.5.9 Temporary unprotection
Bits W0Px of FNVWPIRL can be temporary unprotected by executing the set protection
operation and by writing 1 into these bits.
To restore the write protection bits it is necessary to reset the microcontroller or to execute a
set protection operation and write 0 into the desired bits.
In reality, when a temporary write unprotection operation is executed, the corresponding
volatile register is written to 1, while the non-volatile registers bits previously written to 0 (for
a protection set operation), will continue to maintain the 0. For this reason, the user software
must be in charge to track the current write protection status (for instance using a specific
RAM area), it is not possible to deduce it by reading the non-volatile register content (a
temporary unprotection cannot be detected).
To temporary unprotect the Flash when the access protection is active, it is necessary to set
at 1 the bit TAUB in XFVTAUR0. This bit can be write at 1, only executing from Flash: in this
way only an instruction executed from Flash can unprotect the Flash itself.
To restore the access protection, it is necessary to reset the microcontroller or to write at 0
the bit TAUB in XFVTAUR0.
5.6 Write operation examples
In the following, examples for each kind of Flash write operation are presented.
Figure 6. Summary of access protection level
Read IFlash /
jump to IFlash
Read XRAMS or
ext mem / jump to
XRAM or ext mem
Read Flash
registers
Write Flash
registers
Fetching from IFlash Yes / Yes Yes / Yes Yes No
Fetching from IRAM No / Yes Yes / Yes Yes No
Fetching from XRAM No / Yes Yes / Yes Yes No
Fetching from external
memory N o / Ye s Ye s / Ye s Ye s N o
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Note: The write operation commands must be executed from another memory (internal RAM or
external memory), as in ST10F269 device. In fact, due to IBus characteristics, it is not
possible to perform write operation in Flash while fetching code from Flash.
Moreover, direct addressing is not allowed for write accesses to IFlash control registers.
This means that both address and data for a writing operation must be loaded in one of
ST10 GPR register (R0...R15).
Write operation on IBus registers is 16 bit wide.
Example of indirect addressing mode
MOV RWm, #ADDRESS; /*Load Add in RWm*/
MOV RWn, #DATA; /*Load Data in RWn*/
MOV [RWm], RWn; /*Indirect addressing*/
Word program
Example: 32-bit word program of data 0xAAAAAAAA at address 0x025554
FCR0H|= 0x2000; /*Set WPG in FCR0H*/
FARL = 0x5554; /*Load Add in FARL*/
FARH = 0x0002; /*Load Add in FARH*/
FDR0L = 0xAAAA; /*Load Data in FDR0L*/
FDR0H = 0xAAAA; /*Load Data in FDR0H*/
FCR0H|= 0x8000; /*Operation start*/
Double word program
Example: double word program (64-bit) of data 0x55AA55AA at address 0x035558 and data
0xAA55AA55 at address 0x03555C in IFlash Module.
FCR0H |= 0x1000; /*Set DWPG/
FARL = 0x5558; /*Load Add in FARL*/
FARH = 0x0003; /*Load Add in FARH*/
FDR0L = 0x55AA; /*Load Data in FDR0L*/
FDR0H = 0x55AA; /*Load Data in FDR0H*/
FDR1L = 0xAA55; /*Load Data in FDR1L*/
FDR1H = 0xAA55; /*Load Data in FDR1H*/
FCR0H |= 0x8000; /*Operation start*/
Double word program is always performed on the double word aligned on a even word: bit
ADD2 of FARL is ignored.
Sector erase
Example: sector erase of sectors B0F1 and B0F0 of bank 0 in IFlash module.
FCR0H |= 0x0800; /*Set SER in FCR0H*/
FCR1L |= 0x0003; /*Set B0F1, B0F0*/
FCR0H |= 0x8000; /*Operation start*/
Suspend and resume
Word program, double word program, and sector erase operations can be suspended in the
following way:
FCR0H |= 0x4000; /*Set SUSP in FCR0H*/
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Then the operation can be resumed in the following way:
FCR0H |= 0x0800; /*Set SER in FCR0H*/
FCR0H |= 0x8000; /*Operation resume*/
Before resuming a suspended erase, FCR1H/FCR1L must be read to check if the erase is
already completed (FCR1H = FCR1L = 0x0000 if erase is complete). Original setup of select
operation bits in FCR0H/L must be restored before the operation resume, otherwise the
operation is aborted and bit RESER of FER is set.
Erase suspend, program and resume
A sector erase operation can be suspended in order to program (word or double word)
another sector.
Example: sector erase of sector B0F1 of IFlash module.
FCR0H |= 0x0800; /*Set SER in FCR0H*/
FCR1L |= 0x0002; /*Set B0F1*/
FCR0H |= 0x8000; /*Operation start*/
Example: sector erase suspend.
FCR0H |= 0x4000; /*Set SUSP in FCR0H*/
do /*Loop to wait for LOCK=0 and WMS=0*/
{tmp1 = FCR0L;
tmp2 = FCR0H;
} while ((tmp1 && 0x0010) || (tmp2 && 0x8000));
Example: word program of data 0x5555AAAA at address 0x045554 in IFlash module.
FCR0H &= 0xBFFF; /*Rst SUSP in FCR0H*/
FCR0H|= 0x2000;/*Set WPG in FCR0H*/
FARL = 0x5554; /*Load Add in FARL*/
FARH = 0x0004; /*Load Add in FARH*/
FDR0L = 0xAAAA; /*Load Data in FDR0L*/
FDR0H = 0x5555; /*Load Data in FDR0H*/
FCR0H |= 0x8000; /*Operation start*/
Once the program operation is finished, the erase operation can be resumed in the following
way:
FCR0H|= 0x0800;/*Set SER in FCR0H*/
FCR0H|= 0x8000;/*Operation resume*/
Notice that during the program operation in erase suspend, bits SER and SUSP are low. A
word or double word program during erase suspend cannot be suspended.
In summary:
A sector erase can be suspended by setting SUSP bit.
●To perform a word program operation during erase suspend, firstly bits SUSP and SER
must be reset, then bit WPG and WMS can be set.
●To resume the sector erase operation bit SER must be set again.
●In any case it is forbidden to start any write operation with SUSP bit already set.
Set protection
Example 1: Enable write protection of sectors B0F3-0 of bank 0 in IFlash module.
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FCR0H |= 0x0100; /*Set SPR in FCR0H*/
FARL = 0xDFB4; /*Load Add of register FNVWPIR in FARL*/
FARH = 0x0008; /*Load Add of register FNVWPIR in FARH*/
FDR0L = 0xFFF0; /*Load Data in FDR0L*/
FDR0H = 0xFFFF; /*Load Data in FDR0H*/
FCR0H |= 0x8000; /*Operation start*/
Example 2: Enable access and debug protection.
FCR0H |= 0x0100; /*Set SPR in FCR0H*/
FARL = 0xDFB8; /*Load Add of register FNVAPR0 in FARL*/
FARH = 0x0008; /*Load Add of register FNVAPR0 in FARH*/
FDR0L = 0xFFFC; /*Load Data in FDR0L*/
FCR0H |= 0x8000; /*Operation start*/
Example 3: Disable in a permanent way access and debug protection.
XFVTAUR0 = 0x0001; /*Set TAUB in XFVTAUR0*/
FCR0H |= 0x0100; /*Set SPR in FCR0H*/
FARL = 0xDFBC; /*Load Add of register FNVAPR1L in FARL*/
FARH = 0x0008; /*Load Add of register FNVAPR1L in FARH*/
FDR0L = 0xFFFE; /*Load Data in FDR0L for clearing PDS0*/
FCR0H |= 0x8000; /*Operation start*/
Example 4: Enable again in a permanent way access and debug protection, after having
disabled them.
XFVTAUR0 = 0x0001; /*Set TAUB in XFVTAUR0*/
FCR0H |= 0x0100; /*Set SPR in FCR0H*/
FARL = 0xDFBC; /*Load Add register FNVAPR1H in FARL*/
FARH = 0x0008; /*Load Add register FNVAPR1H in FARH*/
FDR0H = 0xFFFE; /*Load Data in FDR0H for clearing
PEN0*/
FCR0H |= 0x8000; /*Operation start*/
XFVTAUR0 = 0x0000; /*Reset TAUB in XFVTAUR0*/
Disable and re-enable of access and debug protection in a permanent way (as shown by
examples 3 and 4) can be done for a maximum of 16 times.
5.7 Write operation summary
In general, each write operation is started through a sequence of 3 steps:
1. The first instruction is used to select the desired operation by setting its corresponding
selection bit in the Flash control register 0.
2. The second step is the definition of the address and data for programming or the
sectors or banks to erase.
3. The last instruction is used to start the write operation, by setting the start bit WMS in
the FCR0.
Once selected, but not yet started, one operation can be canceled by resetting the operation
selection bit.
A summary of the available Flash module write operations are shown in the following
Table 24: Flash write operations.
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Table 24. Flash write operations
Operation Select bit Address and data Start bit
Word program (32-bit) WPG FARL/FARH
FDR0L/FDR0H WMS
Double word program (64-bit) DWPG
FARL/FARH
FDR0L/FDR0H
FDR1L/FDR1H
WMS
Sector erase SER FCR1L/FCR1H WMS
Set protection SPR FDR0L/FDR0H WMS
Program/erase suspend SUSP None None
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6 Bootstrap loader
ST10F271Z1 implements boot capabilities in order to:
●Support bootstrap via UART or bootstrap via CAN for the standard bootstrap.
●Support a selective bootstrap loader, to manage the bootstrap sequence in a different
way.
6.1 Selection among user-code, standard or selective bootstrap
The boot modes are triggered with a special combination set on Port0L[5...4]. Those
signals, as other configuration signals, are latched on the rising edge of RSTIN pin.
●Decoding of reset configuration (P0L.5 = 1, P0L.4 = 1) will select the normal mode
(also called User Mode) and select the user Flash to be mapped from address
00’0000h.
●Decoding of reset configuration (P0L.5 = 1, P0L.4 = 0) will select ST10 standard
bootstrap mode (Test-Flash is active and overlaps user Flash for code fetches from
address 00'0000h; user Flash is active and available for read accesses).
●Decoding of reset configuration (P0L.5 = 0, P0L.4 = 1) will activate new verifications to
select which bootstrap software to execute:
– if the User mode signature in the User Flash is programmed correctly, then a
software reset sequence is selected and the User code is executed;
– if the User mode signature is not programmed correctly in the user Flash, then the
User key location is read again. Its value will determine which communication
channel will be enabled for bootstraping
.
6.2 Standard bootstrap loader
After entering the standard BSL mode and the respective initialization, the ST10F271Z1
scans the RxD0 line and the CAN1_RxD line to receive either a valid dominant bit from CAN
interface, or a start condition from UART line.
Start condition on UART RxD: ST10F271Z1 starts standard bootstrap loader. This
bootstrap loader is identical to other ST10 devices (example: ST10F269, ST10F168).
Valid dominant bit on CAN1 RxD: ST10F271Z1 start bootstrapping via CAN1.
Table 25. ST10F271Z1 boot mode selection
P0.5 P0.4 ST10 decoding
11User mode: user Flash mapped at 00’0000h
10
Standard bootstrap loader: User Flash mapped from 00’0000h, code fetches
redirected to Test-Flash at 00’0000h
01
Selective boot mode: User Flash mapped from 00’0000h, code fetches
redirected to Test-Flash at 00’0000h (different sequence execution in respect of
Standard Bootstrap Loader)
00Reserved
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6.3 Alternate and selective boot mode (ABM and SBM)
6.3.1 Activation of the ABM and SBM
Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of
RSTIN.
6.3.2 User mode signature integrity check
The behavior of the selective boot mode is based on the computing of a signature between
the content of 2 memory locations and a comparison with a reference signature. This
requires that users who use selective boot have reserved and programmed the Flash
memory locations.
6.3.3 Selective boot mode
When the user signature is not correct, instead of executing the standard bootstrap loader
(triggered by P0L.4 low at reset), additional check is made.
Depending on the value at the user key location, following behavior will occur:
●A jump is performed to the standard bootstrap loader
●Only UART is enabled for bootstraping
●Only CAN1 is enabled for bootstraping
●The device enters an infinite loop.
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7 Central processing unit (CPU)
The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and
dedicated SFRs. Additional hardware has been added for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Most of the ST10F271Z1’s instructions can be executed in one instruction cycle which
requires 31.25 ns at 64 MHz CPU clock. For example, shift and rotate instructions are
processed in one instruction cycle independent of the number of bits to be shifted.
Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x
16-bit multiplication in 5 cycles and a 32/16-bit division in 10 cycles.
The jump cache reduces the execution time of repeatedly performed jumps in a loop, from
2 cycles to 1 cycle.
The CPU uses a bank of 16 word registers to run the current context. This bank of General
Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area.
A Context Pointer (CP) register determines the base address of the active register bank to
be accessed by the CPU.
The number of register banks is only restricted by the available Internal RAM space. For
easy parameter passing, a register bank may overlap others.
A system stack of up to 2048 bytes is provided as a storage for temporary data. The system
stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack
pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer
value upon each stack access for the detection of a stack overflow or underflow.
Figure 7. CPU block diagram (MAC unit not included)
32
Internal
RAM
2 Kbyte
General
Purpose
Registers
R0
R15
MDH
MDL
Barrel-Shift
Mul./Div.-HW
Bit-Mask Gen.
ALU
16-Bit
CP
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Pg. Ptrs Code Seg. Ptr.
CPU
128 Kbyte
Flash
memory
16
16
Bank
n
Bank
i
Bank
0
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7.1 Multiplier-accumulator unit (MAC)
The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order
to improve the performances of the ST10 Family in signal processing algorithms.
The standard ST10 CPU has been modified to include new addressing capabilities which
enable the CPU to supply the new co-processor with up to 2 operands per instruction cycle.
This new co-processor (so-called MAC) contains a fast multiply-accumulate unit and a
repeat unit.
The co-processor instructions extend the ST10 CPU instruction set with multiply, multiply-
accumulate, 32-bit signed arithmetic operations.
Figure 8. MAC unit architecture
7.2 Instruction set summary
The Ta bl e 26 lists the instructions of the ST10F271Z1. The detailed description of each
instruction can be found in the “ST10 Family Programming Manual”.
Operand 2Operand 1
Control Unit
Repeat Unit
ST10 CPU
Interrupt
Controller
MSW
MRW
MAH MAL
MCW
Flags MAE
Mux
8-bit Left/Right
Shifter
Mux
Mux
Sign Extend
16 x 16
Concatenation
signed/unsigned
Multiplier
40-bit Signed Arithmetic Unit
0h 0h08000h
40
16
40 40
32 32
16
40
40
40
40
40
Scaler
AB
40
GPR Pointers *
IDX0 Pointer
IDX1 Pointer
QR0 GPR Offset Register
QR1 GPR Offset Register
QX0 IDX Offset Register
QX1 IDX Offset Register
* Shared with standard ALU
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Table 26. Standard instruction set summary
Mnemonic Description Bytes
ADD(B) Add word (byte) operands 2 / 4
ADDC(B) Add word (byte) operands with Carry 2 / 4
SUB(B) Subtract word (byte) operands 2 / 4
SUBC(B) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bit-wise AND, (word/byte operands) 2 / 4
OR(B) Bit-wise OR, (word/byte operands) 2 / 4
XOR(B) Bit-wise XOR, (word/byte operands) 2 / 4
BCLR Clear direct bit 2
BSET Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bit 4
BFLDH/L Bit-wise modify masked high/low byte of bit-addressable direct word
memory with immediate data 4
CMP(B) Compare word (byte) operands 2 / 4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct word GPR and
store result in direct word GPR 2
SHL / SHR Shift left/right direct word GPR 2
ROL / ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2
MOV(B) Move word (byte) data 2 / 4
MOVBS Move byte operand to word operand with sign extension 2 / 4
MOVBZ Move byte operand to word operand with zero extension 2 / 4
JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
J(N)B Jump relative if direct bit is (not) set 4
JBC Jump relative and clear bit if direct bit is set 4
JNBS Jump relative and set bit if direct bit is not set 4
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7.3 MAC co-processor specific instructions
The Ta bl e 27 lists the MAC instructions of the ST10F271Z1. The detailed description of
each instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC
instructions are encoded on 4 Bytes.
CALLA, CALLI,
CALLR Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call absolute
subroutine 4
TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack and update register
with word operand 4
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
RETP Return from intra-segment subroutine and pop direct word register
from system stack 2
RETI Return from interrupt service subroutine 2
SRST Software reset 4
IDLE Enter Idle mode 4
PWRDN Enter power-down mode (supposes NMI-pin being low) 4
SRVWDT Service watchdog timer 4
DISWDT Disable watchdog timer 4
EINIT Signify end-of-initialization on RSTOUT-pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended register sequence 2
EXTP(R) Begin EXTended page (and register) sequence 2 / 4
EXTS(R) Begin EXTended segment (and register) sequence 2 / 4
NOP Null operation 2
Table 26. Standard instruction set summary (continued)
Mnemonic Description Bytes
Table 27. MAC instruction set summary
Mnemonic Description
CoABS Absolute value of the accumulator
CoADD(2) Addition
CoASHR(rnd) Accumulator arithmetic shift right & optional round
CoCMP Compare accumulator with operands
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CoLOAD(-,2) Load accumulator with operands
CoMAC(R,u,s,-,rnd) (Un)Signed/(un)signed multiply-accumulate & optional round
CoMACM(R)(u,s,-,rnd) (Un)Signed/(un)Signed multiply-accumulate with parallel data move
& optional round
CoMAX / CoMIN Maximum / minimum of operands and accumulator
CoMOV Memory to memory move
CoMUL(u,s,-,rnd) (Un)Signed/(un)signed multiply & optional round
CoNEG(rnd) Negate accumulator & optional round
CoNOP No-operation
CoRND Round accumulator
CoSHL / CoSHR Accumulator logical shift left / right
CoSTORE Store a MAC unit register
CoSUB(2,R) Substraction
Table 27. MAC instruction set summary (continued)
Mnemonic Description
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8 External bus controller
All of the external memory accesses are performed by the on-chip external bus controller.
The EBC can be programmed to single chip mode when no external memory is required, or
to one of four different external memory access modes:
●16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed
●16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed
●16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed
●16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed
In demultiplexed bus modes addresses are output on PORT1 and data is input / output on
PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use
PORT0 for input / output.
Timing characteristics of the external bus interface (memory cycle time, memory tri-state
time, length of ALE and read / write delay) are programmable giving the choice of a wide
range of memories and external peripherals.
Up to four independent address windows may be defined (using register pairs ADDRSELx /
BUSCONx) to access different resources and bus characteristics.
These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3
and BUSCON2 overrides BUSCON1.
All accesses to locations not covered by these four address windows are controlled by
BUSCON0. Up to five external CS signals (four windows plus default) can be generated in
order to save external glue logic. Access to very slow memories is supported by a ‘Ready’
function.
A HOLD / HLDA protocol is available for bus arbitration which shares external resources
with other bus masters.
The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN
once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In
master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to’1’ the
slave mode is selected where pin HLDA is switched to input. This directly connects the slave
controller to another master controller without glue logic.
For applications which require less external memory space, the address space can be
restricted to 1 Mbyte, 256 Kbytes or to 64 Kbytes. Port 4 outputs all eight address lines if an
address space of 16 Mbytes is used, otherwise four, two or no address lines.
Chip select timing can be made programmable. By default (after reset), the CSx lines
change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the
SYSCON register the CSx lines change with the rising edge of ALE.
The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers.
When the READY function is enabled for a specific address window, each bus cycle within
the window must be terminated with the active level defined by bit RDYPOL in the
associated BUSCON register.
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9 Interrupt system
The interrupt response time for internal program execution is from 78 ns to 187.5 ns at
64 MHz CPU clock.
The ST10F271Z1 architecture supports several mechanisms for fast and flexible response
to service requests that can be generated from various sources (internal or external) to the
microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or
by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’
from the current CPU activity to perform a PEC service. A PEC service implies a single Byte
or Word data transfer between any two memory locations with an additional increment of
either the PEC source or destination pointer. An individual PEC transfer counter is implicitly
decremented for each PEC service except when performing in the continuous transfer
mode. When this counter reaches zero, a standard interrupt is performed to the
corresponding source related vector location. PEC services are very well suited to perform
the transmission or the reception of blocks of data. The ST10F271Z1 has 8 PEC channels,
each of them offers such fast interrupt-driven data transfer capabilities.
An interrupt control register which contains an interrupt request flag, an interrupt enable flag
and an interrupt priority bit-field is dedicated to each existing interrupt source. Thanks to its
related register, each source can be programmed to one of sixteen interrupt priority levels.
Once starting to be processed by the CPU, an interrupt service can only be interrupted by a
higher prioritized service request. For the standard interrupt processing, each of the
possible interrupt sources has a dedicated vector location.
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge,
falling edge or both edges).
Fast external interrupts may also have interrupt sources selected from other peripherals; for
example the CANx controller receive signals (CANx_RxD) and I2C serial clock signal can be
used to interrupt the system.
Ta bl e 2 8 shows all the available ST10F271Z1 interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
Table 28. Interrupt sources
Source of interrupt or
PEC service request
Request
flag
Enable
flag
Interrupt
vector
Vector
location
Trap
number
CAPCOM register 0 CC0IR CC0IE CC0INT 00’0040h 10h
CAPCOM register 1 CC1IR CC1IE CC1INT 00’0044h 11h
CAPCOM register 2 CC2IR CC2IE CC2INT 00’0048h 12h
CAPCOM register 3 CC3IR CC3IE CC3INT 00’004Ch 13h
CAPCOM register 4 CC4IR CC4IE CC4INT 00’0050h 14h
CAPCOM register 5 CC5IR CC5IE CC5INT 00’0054h 15h
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CAPCOM register 6 CC6IR CC6IE CC6INT 00’0058h 16h
CAPCOM register 7 CC7IR CC7IE CC7INT 00’005Ch 17h
CAPCOM register 8 CC8IR CC8IE CC8INT 00’0060h 18h
CAPCOM register 9 CC9IR CC9IE CC9INT 00’0064h 19h
CAPCOM register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah
CAPCOM register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh
CAPCOM register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch
CAPCOM register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh
CAPCOM register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh
CAPCOM register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh
CAPCOM register 16 CC16IR CC16IE CC16INT 00’00C0h 30h
CAPCOM register 17 CC17IR CC17IE CC17INT 00’00C4h 31h
CAPCOM register 18 CC18IR CC18IE CC18INT 00’00C8h 32h
CAPCOM register 19 CC19IR CC19IE CC19INT 00’00CCh 33h
CAPCOM register 20 CC20IR CC20IE CC20INT 00’00D0h 34h
CAPCOM register 21 CC21IR CC21IE CC21INT 00’00D4h 35h
CAPCOM register 22 CC22IR CC22IE CC22INT 00’00D8h 36h
CAPCOM register 23 CC23IR CC23IE CC23INT 00’00DCh 37h
CAPCOM register 24 CC24IR CC24IE CC24INT 00’00E0h 38h
CAPCOM register 25 CC25IR CC25IE CC25INT 00’00E4h 39h
CAPCOM register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah
CAPCOM register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh
CAPCOM register 28 CC28IR CC28IE CC28INT 00’00F0h 3Ch
CAPCOM register 29 CC29IR CC29IE CC29INT 00’0110h 44h
CAPCOM register 30 CC30IR CC30IE CC30INT 00’0114h 45h
CAPCOM register 31 CC31IR CC31IE CC31INT 00’0118h 46h
CAPCOM timer 0 T0IR T0IE T0INT 00’0080h 20h
CAPCOM timer 1 T1IR T1IE T1INT 00’0084h 21h
CAPCOM timer 7 T7IR T7IE T7INT 00’00F4h 3Dh
CAPCOM timer 8 T8IR T8IE T8INT 00’00F8h 3Eh
GPT1 timer 2 T2IR T2IE T2INT 00’0088h 22h
GPT1 timer 3 T3IR T3IE T3INT 00’008Ch 23h
GPT1 timer 4 T4IR T4IE T4INT 00’0090h 24h
GPT2 timer 5 T5IR T5IE T5INT 00’0094h 25h
Table 28. Interrupt sources (continued)
Source of interrupt or
PEC service request
Request
flag
Enable
flag
Interrupt
vector
Vector
location
Trap
number
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Hardware traps are exceptions or error conditions that arise during run-time. They cause
immediate non-maskable system reaction similar to a standard interrupt service (branching
to a dedicated vector table location).
The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any other program execution. Hardware trap services cannot not
be interrupted by standard interrupt or by PEC interrupts.
9.1 X-Peripheral interrupt
The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some
constraints on the implementation of the new functionality. In particular, the additional X-
Peripherals SSC1, ASC1, I2C, PWM1 and RTC need some resources to implement interrupt
and PEC transfer capabilities. For this reason, a multiplexed structure for the interrupt
management is proposed. In the next Figure 9, the principle is explained through a simple
diagram, which shows the basic structure replicated for each of the four X-interrupt available
vectors (XP0INT, XP1INT, XP2INT and XP3INT).
It is based on a set of 16-bit registers XIRxSEL (x=0,1,2,3), divided in two portions each:
●Byte High XIRxSEL[15:8] Interrupt enable bits
●Byte Low XIRxSEL[7:0] Interrupt flag bits
When different sources submit an interrupt request, the enable bits (byte high of XIRxSEL
register) define a mask which controls which sources will be associated with the unique
GPT2 timer 6 T6IR T6IE T6INT 00’0098h 26h
GPT2 CAPREL register CRIR CRIE CRINT 00’009Ch 27h
A/D conversion complete ADCIR ADCIE ADCINT 00’00A0h 28h
A/D overrun error ADEIR ADEIE ADEINT 00’00A4h 29h
ASC0 transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah
ASC0 transmit buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h
ASC0 receive S0RIR S0RIE S0RINT 00’00ACh 2Bh
ASC0 error S0EIR S0EIE S0EINT 00’00B0h 2Ch
SSC transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh
SSC receive SCRIR SCRIE SCRINT 00’00B8h 2Eh
SSC error SCEIR SCEIE SCEINT 00’00BCh 2Fh
PWM channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh
See paragraph 9.1 XP0IR XP0IE XP0INT 00’0100h 40h
See paragraph 9.1 XP1IR XP1IE XP1INT 00’0104h 41h
See paragraph 9.1 XP2IR XP2IE XP2INT 00’0108h 42h
See paragraph 9.1 XP3IR XP3IE XP3INT 00’010Ch 43h
Table 28. Interrupt sources (continued)
Source of interrupt or
PEC service request
Request
flag
Enable
flag
Interrupt
vector
Vector
location
Trap
number
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available vector. If more than one source is enabled to issue the request, the service routine
will have to take care to identify the real event to be serviced. This can easily be done by
checking the flag bits (byte low of XIRxSEL register). Note that the flag bits can also provide
information about events which are not currently serviced by the interrupt controller (since
masked through the enable bits), allowing an effective software management also in
absence of the possibility to serve the related interrupt request: a periodic polling of the flag
bits may be implemented inside the user application.
Figure 9. X-Interrupt basic structure
The Ta bl e 29 summarizes the mapping of the different interrupt sources which shares the
four X-interrupt vectors.
Table 29. X-Interrupt detailed mapping
XP0INT XP1INT XP2INT XP3INT
CAN1 interrupt xx
CAN2 interrupt xx
I2C receive xxx
I2C transmit xxx
I2C error x
SSC1 receive xxx
SSC1 transmit xxx
SSC1 error x
ASC1 receive xxx
ASC1 transmit xxx
ASC1 transmit buffer xxx
XIRxSEL[7:0] (x = 0, 1, 2, 3)
XIRxSEL[15:8] (x = 0, 1, 2, 3)
XPxIC.XPxIR (x = 0, 1, 2, 3)
70
15 8
IT Source 7
IT Source 6
IT Source 5
IT Source 4
IT Source 3
IT Source 2
IT Source 1
IT Source 0
Enable[7:0]
Flag[7:0]
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9.2 Exception and error traps list
Ta bl e 3 0 shows all of the possible exceptions or error conditions that can arise during run-
time.
Note: * - All the class B traps have the same trap number (and vector) and the same lower priority
compare to the class A traps and to the resets.
- Each class A traps has a dedicated trap number (and vector). They are prioritized in the
second priority level.
- The resets have the highest priority level and the same trap number.
- The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are
serviced.
ASC1 error x
PLL unlock / OWD x
PWM1 channel 3...0 xx
Table 29. X-Interrupt detailed mapping (continued)
XP0INT XP1INT XP2INT XP3INT
Table 30. Trap priorities
Exception condition Trap
flag
Trap
vector
Vector
location
Trap
number
Trap*
priority
Reset functions:
Hardware reset
Software reset
Watchdog timer overflow
RESET
RESET
RESET
00’0000h
00’0000h
00’0000h
00h
00h
00h
III
III
III
Class A hardware traps:
Non-maskable interrupt
Stack overflow
Stack underflow
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008h
00’0010h
00’0018h
02h
04h
06h
II
II
II
Class B hardware traps:
Undefined opcode
MAC interruption
Protected instruction fault
Illegal word operand access
Illegal instruction access
Illegal external bus access
UNDOPC
MACTRP
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
I
I
I
I
I
I
Reserved [002Ch - 003Ch] [0Bh - 0Fh]
Software traps
TRAP instruction
Any
0000h – 01FCh
in steps of 4h
Any
[00h - 7Fh]
Current
CPU
Priority
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10 Capture / compare (CAPCOM) units
The ST10F271Z1 has two 16-channel CAPCOM units which support generation and control
of timing sequences on up to 32 channels with a maximum resolution of 125 ns at 64 MHz
CPU clock.
The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and
waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion,
software timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases
for the capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows precise
adjustments to application specific requirements. In addition, external count inputs for
CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers
relative to external events.
Each of the two capture/compare register arrays contain 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7
or T8, respectively), and programmed for capture or compare functions. Each of the 32
registers has one associated port pin which serves as an input pin for triggering the capture
function, or as an output pin to indicate the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current contents
of the allocated timer will be latched (captured) into the capture/compare register in
response to an external event at the port pin which is associated with this register. In
addition, a specific interrupt request for this capture/compare register is generated.
Either a positive, a negative, or both a positive and a negative external signal transition at
the pin can be selected as the triggering event. The contents of all registers which have
been selected for one of the five compare modes are continuously compared with the
contents of the allocated timers.
When a match occurs between the timer value and the value in a capture / compare
register, specific actions will be taken based on the selected compare mode.
The input frequencies fTx, for the timer input selector Tx, are determined as a function of the
CPU clocks. The timer input frequencies, resolution and periods which result from the
selected prescaler option in TxI when using a 40 MHz and 64 MHz CPU clock are listed in
the Ta b l e 3 2 and Ta bl e 3 3 respectively.
The numbers for the timer periods are based on a reload value of 0000h. Note that some
numbers may be rounded to 3 significant figures.
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Table 31. Compare modes
Compare
modes Function
Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are
possible
Mode 1 Pin toggles on each compare match; several compare events per timer period are
possible
Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is
generated
Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare
event per timer period is generated
Double register
mode
Two registers operate on one pin; pin toggles on each compare match; several
compare events per timer period are possible.
Table 32. CAPCOM timer input frequencies, resolutions and periods at 40 MHz
fCPU = 40 MHz
Timer input selection TxI
000b 001b 010b 011b 100b 101b 110b 111b
Prescaler for
fCPU
8 16 32 64 128 256 512 1024
Input frequency 5 MHz 2.5 MHz 1.25
MHz 625 kHz 312.5
kHz
156.25
kHz
78.125
kHz
39.1
kHz
Resolution 200 ns 400 ns 0.8 µs 1.6 µs 3.2 µs 6.4 µs 12.8 µs 25.6 µs
Period 13.1 ms 26.2 ms 52.4 ms 104.8
ms 209.7 ms 419.4 ms 838.9 ms 1.678 s
Table 33. CAPCOM timer input frequencies, resolutions and periods at 64 MHz
fCPU = 64 MHz
Timer input selection TxI
000b 001b 010b 011b 100b 101b 110b 111b
Prescaler for fCPU 8 16 32 64 128 256 512 1024
Input frequency 8 MHz 4 MHz 2 MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz
Resolution 125 ns 250 ns 0.5 µs 1.0 µs 2.0 µs 4.0 µs 8.0 µs 16.0 µs
Period 8.2 ms 16.4
ms 32.8 ms 65.5 ms 131.1
ms 262.1 ms 524.3 ms 1.049 s
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11 General purpose timer unit
The GPT unit is a flexible multifunctional timer/counter structure which is used for time
related tasks such as event timing and counting, pulse width and duty cycle measurements,
pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized
into two separate modules GPT1 and GPT2. Each timer in each module may operate
independently in several different modes, or may be concatenated with another timer of the
same module.
11.1 GPT1
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for
one of four basic modes of operation: timer, gated timer, counter mode and incremental
interface mode.
In timer mode, the input clock for a timer is derived from the CPU clock, divided by a
programmable prescaler.
In counter mode, the timer is clocked in reference to external events.
Pulse width or duty cycle measurement is supported in gated timer mode where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input.
Ta bl e 3 4 and Ta b l e 3 5 list the timer input frequencies, resolution and periods for each
prescaler option at 40 MHz and 64 MHz CPU clock respectively.
In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to
the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.
Direction and count signals are internally derived from these two input signals so that the
contents of the respective timer Tx corresponds to the sensor position. The third position
sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow /
underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring
of external hardware components, or may be used internally to clock timers T2 and T4 for
high resolution of long duration measurements.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or
capture registers for timer T3.
Table 34. GPT1 timer input frequencies, resolutions and periods at 40 MHz
fCPU = 40 MHz
Timer input selection T2I / T3I / T4I
000b 001b 010b 011b 100b 101b 110b 111b
Prescaler factor 8 16 32 64 128 256 512 1024
Input frequency 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.1 kHz
Resolution 200 ns 400 ns 0.8 µs 1.6 µs 3.2 µs 6.4 µs 12.8 µs 25.6 µs
Period maximum 13.1 ms 26.2 ms 52.4 ms 104.8 ms 209.7 ms 419.4 ms 838.9 ms 1.678 s
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Figure 10. Block diagram of GPT1
11.2 GPT2
The GPT2 module provides precise event control and time measurement. It includes two
timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an
input clock which is derived from the CPU clock via a programmable prescaler or with
external signals. The count direction (up/down) for each timer is programmable by software
or may additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, or it may be output on a port pin
(T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the
CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL
register may capture the contents of timer T5 based on an external signal transition on the
corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture
procedure. This allows absolute time differences to be measured or pulse multiplication to
be performed without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1
timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental
Interface Mode.
Table 35. GPT1 timer input frequencies, resolutions and periods at 64 MHz
fCPU = 64 MHz
Timer input selection T2I / T3I / T4I
000b 001b 010b 011b 100b 101b 110b 111b
Prescaler factor 8 16 32 64 128 256 512 1024
Input freq 8 MHz 4 MHz 2 MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz
Resolution 125 ns 250 ns 0.5 µs 1.0 µs 2.0 µs 4.0 µs 8.0 µs 16.0 µs
Period maximum 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 1.049 s
2n n=3...10
2n n=3...10
2n n=3...10
T2EUD
T2IN
CPU clock
CPU clock
CPU clock
T3IN
T4IN
T3EUD
T4EUD
GPT1 Timer T2
GPT1 Timer T3
GPT1 Timer T4
T3OTL
Reload
Capture
U/D
U/D
Reload
Capture
Interrupt
Request
Interrupt
Request
Interrupt
Request
T3OUT
U/D
T2
Mode
Control
T3
Mode
Control
T4
Mode
Control
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Ta bl e 3 6 and Ta b l e 3 7 list the timer input frequencies, resolution and periods for each
prescaler option at 40MHz and 64MHz CPU clock respectively.
Figure 11. Block diagram of GPT2
Table 36. GPT2 timer input frequencies, resolutions and periods at 40 MHz
fCPU = 40 MHz
Timer input selection T5I / T6I
000b 001b 010b 011b 100b 101b 110b 111b
Prescaler factor 4 8 16 32 64 128 256 512
Input freq 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz
Resolution 100 ns 200 ns 400 ns 0.8µs 1.6 µs 3.2 µs 6.4 µs 12.8 µs
Period maximum 6.55 ms 13.1ms 26.2 ms 52.4 ms 104.8 ms 209.7ms 419.4 ms 838.9 ms
Table 37. GPT2 timer input frequencies, resolutions and periods at 64 MHz
fCPU = 64 MHz
Timer input selection T5I / T6I
000b 001b 010b 011b 100b 101b 110b 111b
Prescaler factor 4 8 16 32 64 128 256 512
Input freq 16 MHz 8 MHz 4 MHz 2 MHz 1 kHz 500 kHz 250 kHz 128 kHz
Resolution 62.5 ns 125 ns 250 ns 0.5 µs 1.0 µs 2.0 µs 4.0 µs 8.0 µs
Period maximum 4.1 ms 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms
2n n=2...9
2n n=2...9
T5EUD
T5IN
CPU clock
CPU clock
T6IN
T6EUD
GPT2 Timer T5
GPT2 Timer T6
U/D
Interrupt
Request
U/D
GPT2 CAPREL
T60TL
Toggle FF
T6OUT
CAPIN
Reload Interrupt
Request
to CAPCOM
Timers
Capture
Clear
Interrupt
Request
T5
Mode
Control
T6
Mode
Control
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12 PWM modules
Two pulse width modulation modules are available on ST10F271Z1: standard PWM0 and
XBus PWM1. They can generate up to four PWM output signals each, using edge-aligned or
centre-aligned PWM. In addition, the PWM modules can generate PWM burst signals and
single shot outputs. The Ta b l e 3 8 and Ta b l e 3 9 show the PWM frequencies for different
resolutions. The level of the output signals is selectable and the PWM modules can
generate interrupt requests.
Figure 12. Block diagram of PWM module
Table 38. PWM unit frequencies and resolutions at 40 MHz CPU clock
Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU clock/1 25 ns 156.25 kHz 39.1 kHz 9.77 kHz 2.44 Hz 610 Hz
CPU
clock/64 1.6 µs 2.44 kHz 610 Hz 152.6 Hz 38.15 Hz 9.54 Hz
Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU clock/1 25 ns 78.12 kHz 19.53 kHz 4.88 kHz 1.22 kHz 305.2 Hz
CPU
clock/64 1.6 µs 1.22 kHz 305.17 Hz 76.29 Hz 19.07 Hz 4.77 Hz
Table 39. PWM unit frequencies and resolutions at 64 MHz CPU clock
Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU clock/1 15.6 ns 250 kHz 62.5 kHz 15.63 kHz 3.91 Hz 977 Hz
CPU
clock/64 1.0 µs 3.91 kHz 976.6 Hz 244.1 Hz 61.01 Hz 15.26 Hz
Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU clock/1 15.6 ns 125 kHz 31.25 kHz 7.81 kHz 1.95 kHz 488.3 Hz
CPU
clock/64 1.0 µs 1.95 kHz 488.28 Hz 122.07 Hz 30.52 Hz 7.63 Hz
PPx Period Register
Comparator
PTx
16-bit Up/Down Counter
Shadow Register
PWx Pulse Width Register
Input
Run
Control
Clock 1
Clock 2
Comparator
*
*
*
Up/Down/
Clear Control
Match
Output Control
Match
Write Control
*User readable / writeable register
Enable
POUTx
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13 Parallel ports
13.1 Introduction
The ST10F271Z1 MCU provides up to 111 I/O lines with programmable features. These
capabilities bring very flexible adaptation of this MCU to wide range of applications.
ST10F271Z1 has nine groups of I/O lines gathered as follows:
●Port 0 is a two time 8-bit port named P0L (Low as less significant byte) and P0H (high
as most significant byte)
●Port 1 is a two time 8-bit port named P1L and P1H
●Port 2 is a 16-bit port
●Port 3 is a 15-bit port (P3.14 line is not implemented)
●Port 4 is a 8-bit port
●Port 5 is a 16-bit port input only
●Port 6, Port 7 and Port 8 are 8-bit ports
These ports may be used as general purpose bidirectional input or output, software
controlled with dedicated registers.
For example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bit-
wise) for push-pull or open drain operation using ODPx registers.
The input threshold levels are programmable (TTL/CMOS) for all the ports. The logic level of
a pin is clocked into the input latch once per state time, regardless whether the port is
configured for input or output. The threshold is selected with PICON and XPICON registers
control bits.
A write operation to a port pin configured as an input causes the value to be written into the
port output latch, while a read operation returns the latched state of the pin itself. A read-
modify-write operation reads the value of the pin, modifies it, and writes it back to the output
latch.
Writing to a pin configured as an output (DPx.y=‘1’) causes the output latch and the pin to
have the written value, since the output buffer is enabled. Reading this pin returns the value
of the output latch. A read-modify-write operation reads the value of the output latch,
modifies it, and writes it back to the output latch, thus also modifying the level at the pin.
I/O lines support an alternate function which is detailed in the following description of each
port.
13.2 I/O’s special features
13.2.1 Open drain mode
Some of the I/O ports of ST10F271Z1 support the open drain capability. This programmable
feature may be used with an external pull-up resistor, in order to get an AND wired logical
function.
This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections),
and is controlled through the respective Open Drain Control Registers ODPx.
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13.2.2 Input threshold control
The standard inputs of the ST10F271Z1 determine the status of input signals according to
TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be
selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds
are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs
from toggling while the respective input signal level is near the thresholds.
The Port Input Control registers PICON and XPICON are used to select these thresholds for
each Byte of the indicated ports, this means the 8-bit ports P0L, P0H, P1L, P1H, P4, P7 and
P8 are controlled by one bit each while ports P2, P3 and P5 are controlled by two bits each.
All options for individual direction and output mode control are available for each pin,
independent of the selected input threshold.
13.3 Alternate port functions
Each port line has one associated programmable alternate input or output function.
●PORT0 and PORT1 may be used as address and data lines when accessing external
memory. Besides, PORT1 provides also:
– Input capture lines
– 8 additional analog input channels to the A/D converter
●Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of
the CAPCOM units and/or with the outputs of the PWM0 module, of the PWM1 module
and of the ASC1.
Port 2 is also used for fast external interrupt inputs and for timer 7 input.
●Port 3 includes the alternate functions of timers, serial interfaces, the optional bus
control signal BHE and the system clock output (CLKOUT).
●Port 4 outputs the additional segment address bit A23...A16 in systems where more
than 64 Kbytes of memory are to be access directly. In addition, CAN1, CAN2 and I2C
lines are provided.
●Port 5 is used as analog input channels of the A/D converter or as timer control signals.
●Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select
signals and the SSC1 lines.
If the alternate output function of a pin is to be used, the direction of this pin must be
programmed for output (DPx.y=‘1’), except for some signals that are used directly after reset
and are configured automatically. Otherwise the pin remains in the high-impedance state
and is not effected by the alternate output function. The respective port latch should hold a
‘1’, because its output is ANDed with the alternate output data (except for PWM output
signals).
If the alternate input function of a pin is used, the direction of the pin must be programmed
for input (DPx.y=‘0’) if an external device is driving the pin. The input direction is the default
after reset. If no external device is connected to the pin, however, one can also set the
direction for this pin to output. In this case, the pin reflects the state of the port output latch.
Thus, the alternate input function reads the value stored in the port output latch. This can be
used for testing purposes to allow a software trigger of an alternate input function by writing
to the port output latch.
On most of the port lines, the user software is responsible for setting the proper direction
when using an alternate input or output function of a pin.
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This is done by setting or clearing the direction control bit DPx.y of the pin before enabling
the alternate function.
There are port lines, however, where the direction of the port line is switched automatically.
For instance, in the multiplexed external bus modes of PORT0, the direction must be
switched several times for an instruction fetch in order to output the addresses and to input
the data.
Obviously, this cannot be done through instructions. In these cases, the direction of the port
line is switched automatically by hardware if the alternate function of such a pin is enabled.
To determine the appropriate level of the port output latches check how the alternate data
output is combined with the respective port latch output.
There is one basic structure for all port lines with only an alternate input function. Port lines
with only an alternate output function, however, have different structures due to the way the
direction of the pin is switched and depending on whether the pin is accessible by the user
software or not in the alternate function mode.
All port lines that are not used for these alternate functions may be used as general purpose
I/O lines.
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14 A/D converter
A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is
integrated on-chip. An automatic self-calibration adjusts the A/D converter module to
process parameter variations at each reset event. The sample time (for loading the
capacitors) and the conversion time is programmable and can be adjusted to the external
circuitry.
The ST10F271 has 16+8 multiplexed input channels on Port 5 and Port 1. The selection
between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the User Manual for
a detailed description.
A different accuracy is guaranteed (Total Unadjusted Error) on Port 5 and Port 1 analog
channels (with higher restrictions when overload conditions occur); in particular, Port 5
channels are more accurate than the Port 1 ones. Refer to Chapter 25: Electrical
characteristics for details.
The A/D converter input bandwidth is limited by the achievable accuracy: supposing a
maximum error of 0.5LSB (2mV) impacting the global TUE (TUE depends also on other
causes), in worst case of temperature and process, the maximum frequency for a sine wave
analog signal is around 7.5 kHz. Of course, to reduce the effect of the input signal variation
on the accuracy down to 0.05LSB, the maximum input frequency of the sine wave shall be
reduced to 800 Hz.
If static signal is applied during sampling phase, series resistance shall not be greater than
20 kΩ (this taking into account eventual input leakage). It is suggested to not connect any
capacitance on analog input pins, in order to reduce the effect of charge partitioning (and
consequent voltage drop error) between the external and the internal capacitance: in case
an RC filter is necessary the external capacitance must be greater than 10 nF to minimize
the accuracy impact.
Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt
request is generated when the result of a previous conversion has not been read from the
result register at the time the next conversion is complete, or the next conversion is
suspended until the previous result has been read. For applications which require less than
16+8 analog input channels, the remaining channel inputs can be used as digital input port
pins.
The A/D converter of the ST10F271Z1 supports different conversion modes:
●Single channel single conversion: The analog level of the selected channel is
sampled once and converted. The result of the conversion is stored in the ADDAT
register.
●Single channel continuous conversion: The analog level of the selected channel is
repeatedly sampled and converted. The result of the conversion is stored in the ADDAT
register.
●Auto scan single conversion: The analog level of the selected channels are sampled
once and converted. After each conversion the result is stored in the ADDAT register.
The data can be transferred to the RAM by interrupt software management or using the
powerful Peripheral Event Controller (PEC) data transfer.
●Auto scan continuous conversion: The analog level of the selected channels are
repeatedly sampled and converted. The result of the conversion is stored in the ADDAT
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register. The data can be transferred to the RAM by interrupt software management or
using the PEC data transfer.
●Wait for ADDAT read mode: When using continuous modes, in order to avoid to
overwrite the result of the current conversion by the next one, the ADWR bit of ADCON
control register must be activated. Then, until the ADDAT register is read, the new
result is stored in a temporary buffer and the conversion is on hold.
●Channel injection mode: When using continuous modes, a selected channel can be
converted in between without changing the current operating mode. The 10-bit data of
the conversion are stored in ADRES field of ADDAT2. The current continuous mode
remains active after the single conversion is completed.
A full calibration sequence is performed after a reset. This full calibration lasts up to 40.630
CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It
compensates the capacitance mismatch, so the calibration procedure does not need any
update during normal operation.
No conversion can be performed during this time: the bit ADBSY shall be polled to verify
when the calibration is over, and the module is able to start a convertion.
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15 Serial channels
Serial communication with other microcontrollers, microprocessors, terminals or external
peripheral components is provided by up to four serial interfaces: two asynchronous /
synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial
channel (SSC0 and SSC1). Dedicated Baud rate generators set up all standard Baud rates
without the requirement of oscillator tuning. For transmission, reception and erroneous
reception, separate interrupt vectors are provided for ASC0 and SSC0 serial channel. A
more complex mechanism of interrupt sources multiplexing is implemented for ASC1 and
SSC1 (XBus mapped).
15.1 Asynchronous / synchronous serial interfaces
The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial
communication between the ST10F271Z1 and other microcontrollers, microprocessors or
external peripherals.
15.2 ASCx in asynchronous mode
In asynchronous mode, 8- or 9-bit data transfer, parity generation and the number of stop
bits can be selected. Parity framing and overrun error detection is provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. Full-
duplex communication up to 2M Bauds (at 64 MHz of fCPU) is supported in this mode.
Table 40. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz)
S0BRS = ‘0’, fCPU = 40 MHz S0BRS = ‘1’, fCPU = 40 MHz
Baud rate (baud) Deviation
error
Reload value
(hex) Baud rate (baud) Deviation
error
Reload value
(hex)
1 250 000 0.0% / 0.0% 0000 / 0000 833 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% / -7.0% 000A / 000B 112 000 +6.3% / -7.0% 0006 / 0007
56 000 +1.5% / -3.0% 0015 / 0016 56 000 +6.3% / -0.8% 000D / 000E
38 400 +1.7% / -1.4% 001F / 0020 38 400 +3.3% / -1.4% 0014 / 0015
19 200 +0.2% / -1.4% 0040 / 0041 19 200 +0.9% / -1.4% 002A / 002B
9 600 +0.2% / -0.6% 0081 / 0082 9 600 +0.9% / -0.2% 0055 / 0056
4 800 +0.2% / -0.2% 0103 / 0104 4 800 +0.4% / -0.2% 00AC / 00AD
2 400 +0.2% / 0.0% 0207 / 0208 2 400 +0.1% / -0.2% 015A / 015B
1 200 0.1% / 0.0% 0410 / 0411 1 200 +0.1% / -0.1% 02B5 / 02B6
600 0.0% / 0.0% 0822 / 0823 600 +0.1% / 0.0% 056B / 056C
300 0.0% / 0.0% 1045 / 1046 300 0.0% / 0.0% 0AD8 / 0AD9
153 0.0% / 0.0% 1FE8 / 1FE9 102 0.0% / 0.0% 1FE8 / 1FE9
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Note: The deviation errors given in the Ta bl e 4 0 and Ta b l e 4 1 are rounded. To avoid deviation
errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency).
15.3 ASCx in synchronous mode
In synchronous mode, data is transmitted or received synchronously to a shift clock which is
generated by the ST10F271Z1. Half-duplex communication up to 8 Mbaud (at 40 MHz of
fCPU) is possible in this mode.
Table 41. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz)
S0BRS = ‘0’, fCPU = 64 MHz S0BRS = ‘1’, fCPU = 64 MHz
Baud rate (baud) Deviation error Reload value
(hex) Baud rate (baud) Deviation error Reload value
(hex)
2 000 000 0.0% / 0.0% 0000 / 0000 1 333 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% / -7.0% 0010 / 0011 112 000 +6.3% / -7.0% 000A / 000B
56 000 +1.5% / -3.0% 0022 / 0023 56 000 +6.3% / -0.8% 0016 / 0017
38 400 +1.7% / -1.4% 0033 / 0034 38 400 +3.3% / -1.4% 0021 / 0022
19 200 +0.2% / -1.4% 0067 / 0068 19 200 +0.9% / -1.4% 0044 / 0045
9 600 +0.2% / -0.6% 00CF / 00D0 9 600 +0.9% / -0.2% 0089 / 008A
4 800 +0.2% / -0.2% 019F / 01A0 4 800 +0.4% / -0.2% 0114 / 0115
2 400 +0.2% / 0.0% 0340 / 0341 2 400 +0.1% / -0.2% 022A / 015B
1 200 0.1% / 0.0% 0681 / 0682 1 200 +0.1% / -0.1% 0456 / 0457
600 0.0% / 0.0% 0D04 / 0D05 600 +0.1% / 0.0% 08AD / 08AE
300 0.0% / 0.0% 1A09 / 1A0A 300 0.0% / 0.0% 115B / 115C
245 0.0% / 0.0% 1FE2 / 1FE3 163 0.0% / 0.0% 1FF2 / 1FF3
Table 42. ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz)
S0BRS = ‘0’, fCPU = 40 MHz S0BRS = ‘1’, fCPU = 40 MHz
Baud rate (baud) Deviation
error
Reload value
(hex) Baud rate (baud) Deviation
error
Reload value
(hex)
5 000 000 0.0% / 0.0% 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% / -0.8% 002B / 002C 112 000 +2.6% / -0.8% 001C / 001D
56 000 +0.3% / -0.8% 0058 / 0059 56 000 +0.9% / -0.8% 003A / 003B
38 400 +0.2% / -0.6% 0081 / 0082 38 400 +0.9% / -0.2% 0055 / 0056
19 200 +0.2% / -0.2% 0103 / 0104 19 200 +0.4% / -0.2% 00AC / 00AD
9 600 +0.2% / 0.0% 0207 / 0208 9 600 +0.1% / -0.2% 015A / 015B
4 800 +0.1% / 0.0% 0410 / 0411 4 800 +0.1% / -0.1% 02B5 / 02B6
2 400 0.0% / 0.0% 0822 / 0823 2 400 +0.1% / 0.0% 056B / 056C
1 200 0.0% / 0.0% 1045 / 1046 1 200 0.0% / 0.0% 0AD8 / 0AD9
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Note: The deviation errors given in the Ta bl e 4 2 and Ta b le 4 3 are rounded. To avoid deviation
errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency)
15.4 High speed synchronous serial interfaces
The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible high-
speed serial communication between the ST10F271Z1 and other microcontrollers,
microprocessors or external peripherals.
The SSCx supports full-duplex and half-duplex synchronous communication. The serial
clock signal can be generated by the SSCx itself (master mode) or be received from an
external master (slave mode). Data width, shift direction, clock polarity and phase are
programmable.
This allows communication with SPI-compatible devices. Transmission and reception of data
is double-buffered. A 16-bit Baud rate generator provides the SSCx with a separate serial
clock signal. The serial channel SSCx has its own dedicated 16-bit Baud rate generator with
16-bit reload capability, allowing Baud rate generation independent from the timers.
900 0.0% / 0.0% 15B2 / 15B3 600 0.0% / 0.0% 15B2 / 15B3
612 0.0% / 0.0% 1FE8 / 1FE9 407 0.0% / 0.0% 1FFD / 1FFE
Table 42. ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz)
S0BRS = ‘0’, fCPU = 40 MHz S0BRS = ‘1’, fCPU = 40 MHz
Baud rate (baud) Deviation
error
Reload value
(hex) Baud rate (baud) Deviation
error
Reload value
(hex)
Table 43. ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz)
S0BRS = ‘0’, fCPU = 64 MHz S0BRS = ‘1’, fCPU = 64 MHz
Baud rate (baud) Deviation
error
Reload value
(hex) Baud rate (baud) Deviation
error
Reload value
(hex)
8 000 000 0.0% / 0.0% 0000 / 0000 5 333 333 0.0% / 0.0% 0000 / 0000
112 000 +0.6% / -0.8% 0046 / 0047 112 000 +1.3% / -0.8% 002E / 002F
56 000 +0.6% / -0.1% 008D / 008E 56 000 +0.3% / -0.8% 005E / 005F
38 400 +0.2% / -0.3% 00CF / 00D0 38 400 +0.6% / -0.1% 0089 / 008A
19 200 +0.2% / -0.1% 019F / 01A0 19 200 +0.3% / -0.1% 0114 / 0115
9 600 +0.0% / -0.1% 0340 / 0341 9 600 +0.1% / -0.1% 022A / 022B
4 800 0.0% / 0.0% 0681 / 0682 4 800 0.0% / -0.1% 0456 / 0457
2 400 0.0% / 0.0% 0D04 / 0D05 2 400 0.0% / 0.0% 08AD / 08AE
1 200 0.0% / 0.0% 1A09 / 1A0A 1 200 0.0% / 0.0% 115B / 115C
977 0.0% / 0.0% 1FFB / 1FFC 900 0.0% / 0.0% 1724 / 1725
652 0.0% / 0.0% 1FF2 / 1FF3
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Ta bl e 4 4 and Ta b l e 4 5 list some possible Baud rates against the required reload values and
the resulting bit times for 40 MHz and 64 MHz CPU clock respectively. The maximum is
anyway limited to 8 Mbaud.
Table 44. SSC synchronous baud rate and reload values (fCPU = 40 MHz)
Baud rate Bit time Reload value
Reserved --- 0000h
Can be used only with fCPU = 32 MHz (or
lower) --- 0001h
6.6 Mbaud 150 ns 0002h
5 Mbaud 200 ns 0003h
2.5 Mbaud 400 ns 0007h
1 Mbaud 1 µs 0013h
100 Kbaud 10 µs 00C7h
10 Kbaud 100 µs07CFh
1 Kbaud 1 ms 4E1Fh
306 baud 3.26 ms FF4Eh
Table 45. SSC synchronous baud rate and reload values (fCPU = 64 MHz)
Baud rate Bit time Reload value
Reserved --- 0000h
Can be used only with fCPU = 32 MHz (or
lower) --- 0001h
Can be used only with fCPU = 48 MHz (or
lower) --- 0002h
8 Mbaud 125 ns 0003h
4 Mbaud 250 ns 0007h
1 Mbaud 1 µs 001Fh
100 Kbaud 10 µs 013Fh
10 Kbaud 100 µs0C7Fh
1 Kbaud 1 ms 7CFFh
489 baud 2.04 ms FF9Eh
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16 I2C interface
The integrated I2C Bus Module handles the transmission and reception of frames over the
two-line SDA/SCL in accordance with the I2C Bus specification. The I2C Module can
operate in slave mode, in master mode or in multi-master mode. It can receive and transmit
data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s
(both Standard and Fast I2C bus modes are supported).
The module can generate three different types of interrupt:
●Requests related to bus events, like start or stop events, arbitration lost, etc.
●Requests related to data transmission
●Requests related to data reception
These requests are issued to the interrupt controller by three different lines, and identified as
Error, Transmit, and Receive interrupt lines.
When the I2C module is enabled by setting bit XI2CEN in XPERCON register, pins P4.4 and
P4.7 (where SCL and SDA are respectively mapped as alternate functions) are
automatically configured as bidirectional open-drain: the value of the external pull-up
resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin
configuration.
When the I2C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O
controlled by P4, DP4 and ODP4.
The speed of the I2C interface may be selected between Standard mode (0 to 100 kHz) and
Fast I2C mode (100 to 400 kHz).
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17 CAN modules
The two integrated CAN modules (CAN1 and CAN2) are identical and handle the
completely autonomous transmission and reception of CAN frames according to the CAN
specification V2.0 part B (active). It is based on the C-CAN specification.
Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers
as well as extended frames with 29-bit identifiers.
Because of duplication of the CAN controllers, the following adjustments are to be
considered:
●Same internal register addresses of both CAN controllers, but with base addresses
differing in address bit A8; separate chip select for each CAN module. Refer to
Chapter 4: Memory organization on page 20.
●The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and
the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin.
●The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and
the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin.
●Interrupt request lines of the CAN1 and CAN2 modules are connected to the XBUS
interrupt lines together with other X-Peripherals sharing the four vectors.
●The CAN modules must be selected with corresponding CANxEN bit of XPERCON
register before the bit XPEN of SYSCON register is set.
●The reset default configuration is: CAN1 enabled, CAN2 disabled.
Note: If one or both CAN modules is used, Port 4 cannot be programmed to output all 8 segment
address lines. Thus, only four segment address lines can be used, reducing the external
memory space to 5 Mbytes (1 Mbyte per CS line).
17.1 Configuration support
It is possible that both CAN controllers are working on the same CAN bus, supporting
together up to 64 message objects. In this configuration, both receive signals and both
transmit signals are linked together when using the same CAN transceiver. This
configuration is especially supported by providing open drain outputs for the CAN1_Txd and
CAN2_TxD signals. The open drain function is controlled with the ODP4 register for port P4:
in this way it is possible to connect together P4.4 with P4.5 (receive lines) and P4.6 with
P4.7 (transmit lines configured to be configured as Open-Drain).
The user is also allowed to map internally both CAN modules on the same pins P4.5 and
P4.6. In this way, P4.4 and P4.7 may be used either as general purpose I/O lines, or used
for I2C interface. This is possible by setting bit CANPAR of XMISC register. To access this
register it is necessary to set bit XMISCEN of XPERCON register and bit XPEN of SYSCON
register.
17.2 CAN bus configurations
Depending on application, CAN bus configuration may be one single bus with a single or
multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F271Z1 is
able to support these two cases.
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Single CAN bus
The single CAN Bus multiple interfaces configuration may be implemented using two CAN
transceivers as shown in Figure 13.
Figure 13. Connection to single CAN bus via separate CAN transceivers
The ST10F271Z1 also supports single CAN Bus multiple (dual) interfaces using the open
drain option of the CANx_TxD output as shown in Figure 14. Thanks to the OR-Wired
Connection, only one transceiver is required. In this case the design of the application must
take in account the wire length and the noise environment.
Figure 14. Connection to single CAN bus via common CAN transceivers
Multiple CAN bus
The ST10F271Z1 provides two CAN interfaces to support such kind of bus configuration as
shown in Figure 15.
CAN1
RX TX
CAN_H
CAN_L CAN bus
CAN2
RX TX
XMISC.CANPAR = 0
CAN CAN
TransceiverTransceiver
P4.4 P4.7P4.5 P4.6
OD = Open Drain output
+5V
CAN
CAN_H
CAN_L CAN bus
2.7kW OD
Transceiver
XMISC.CANPAR = 0
CAN1
RX TX
CAN2
RX TX
P4.4 P4.7P4.5 P4.6 OD
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Figure 15. Connection to two different CAN buses (e.g. for gateway application)
Parallel Mode
In addition to previous configurations, a parallel mode is supported. This is shown in
Figure 16.
Figure 16. Connection to one CAN bus with internal parallel mode enabled
CAN_H
CAN_L CAN bus 1
CAN_H
CAN_L
CAN bus 2
XMISC.CANPAR = 0
CAN1
RX TX
CAN2
RX TX
CAN CAN
TransceiverTransceiver
P4.4 P4.7P4.5 P4.6
XMISC.CANPAR = 1
CAN2
RX TX
P4.4 P4.7P4.5 P4.6
CAN
CAN_H
CAN_L CAN bus
Transceiver
CAN1
RX TX
(Both CAN enabled)
1. P4.4 and P4.7 when not used as CAN functions can be used as general purpose I/O
while they cannot be used as external bus address lines.
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18 Real-time clock
The Real-Time Clock is an independent timer, in which the clock is derived directly from the
clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator)
so that it can be kept on running even in Idle or power-down mode (if enabled to). Registers
access is implemented onto the XBUS. This module is designed with the following
characteristics:
●Generation of the current time and date for the system
●Cyclic time based interrupt, on Port2 external interrupts every ’RTC basic clock tick’
and after n’RTC basic clock ticks’ (n is programmable) if enabled
●58-bit timer for long term measurement
●Capability to exit the ST10 chip from power-down mode (if PWDCFG of SYSCON set)
after a programmed delay
The real-time clock is based on two main blocks of counters. The first block is a prescaler
which generates a basic reference clock (for example a 1 second period). This basic
reference clock is coming out of a 20-bit DIVIDER. This 20-bit counter is driven by an input
clock derived from the on-chip CPU clock, pre-divided by a 1/64 fixed counter. This 20-bit
counter is loaded at each basic reference clock period with the value of the 20-bit
PRESCALER register. The value of the 20-bit RTCP register determines the period of the
basic reference clock.
A timed interrupt request (RTCSI) may be sent on each basic reference clock period. The
second block of the RTC is a 32-bit counter that may be initialized with the current system
time. This counter is driven with the basic reference clock signal. In order to provide an
alarm function the contents of the counter is compared with a 32-bit alarm register. The
alarm register may be loaded with a reference date. An alarm interrupt request (RTCAI),
may be generated when the value of the counter matches the alarm register.
The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external
interrupt via EXISEL register of port 2 and wake-up the ST10 chip when running power-
down mode. Using the RTCOFF bit of RTCCON register, the user may switch off the clock
oscillator when entering the power-down mode.
The last function implemented in the RTC is to switch off the main on-chip oscillator and the
32 kHz on chip oscillator if the ST10 enters the power-down mode, so that the chip can be
fully switched off (if RTC is disabled).
At power on, and after Reset phase, if the presence of a 32 kHz oscillation on XTAL3 /
XTAL4 pins is detected, then the RTC counter is driven by this low frequency reference
clock: when power-down mode is entered, the RTC can either be stopped or left running,
and in both the cases the main oscillator is turned off, reducing the power consumption of
the device to the minimum required to keep on running the RTC counter and relative
reference oscillator. This is valid also if Stand-by mode is entered (switching off the main
supply VDD), since both the RTC and the low power oscillator (32 kHz) are biased by the
VSTBY
. Vice versa, when at power on and after Reset, the 32 kHz is not present, the main
oscillator drives the RTC counter, and since it is powered by the main power supply, it
cannot be maintained running in Stand-by mode, while in power-down mode the main
oscillator is maintained running to provide the reference to the RTC module (if not disabled).
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19 Watchdog timer
The Watchdog timer is a fail-safe mechanism which prevents the microcontroller from
malfunctioning for long periods of time.
The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in
the time interval until the EINIT (end of initialization) instruction has been executed.
Therefore, the chip start-up procedure is always monitored. The software must be designed
to service the watchdog timer before it overflows. If, due to hardware or software related
failures, the software fails to do so, the watchdog timer overflows and generates an internal
hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components
to be reset.
Each of the different reset sources is indicated in the WDTCON register:
●Watchdog timer reset in case of an overflow
●Software reset in case of execution of the SRST instruction
●Short, long and Power-On Reset in case of hardware reset (and depending of reset
pulse duration and RPD pin configuration)
The indicated bits are cleared with the EINIT instruction. The source of the reset can be
identified during the initialization phase.
The Watchdog timer is 16-bit, clocked with the system clock divided by 2 or 128. The high
Byte of the watchdog timer register can be set to a pre-specified reload value (stored in
WDTREL).
Each time it is serviced by the application software, the high byte of the watchdog timer is
reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced
The Ta bl e 4 6 and Ta b le 4 7 show the watchdog time range for 40 MHz and 64 MHz CPU
clock respectively.
Table 46. WDTREL reload value (fCPU = 40 MHz)
Reload value in WDTREL
Prescaler for fCPU = 40 MHz
2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)
FFh 12.8 µs 819.2 µs
00h 3.277 ms 209.7 ms
Table 47. WDTREL reload value (fCPU = 64 MHz)
Reload value in WDTREL
Prescaler for fCPU = 64 MHz
2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)
FFh 8 µs 512 µs
00h 2.048 ms 131.1 ms
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20 System reset
System reset initializes the MCU in a predefined state. There are six ways to activate a reset
state. The system start-up configuration is different for each case as shown in Ta bl e 4 8 .
1) RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0.
2) See next Section 20.1 for more details on minimum reset pulse duration.
3) The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD
low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to
Sections 20.4, 20.5 and 20.6).
20.1 Input filter
On RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all the spikes
shorter than 50 ns. On the other side, a valid pulse shall be longer than 500 ns to grant that
ST10 recognizes a reset command. In between 50 ns and 500 ns a pulse can either be
filtered or recognized as valid, depending on the operating conditions and process
variations.
For this reason all minimum durations mentioned in this Chapter for the different kind of
reset events shall be carefully evaluated taking into account of the above requirements.
In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input
reset pulse duration, the operating frequency is a key factor. Examples:
●For a CPU clock of 64 MHz, 4 TCL is 31.25 ns, so it would be filtered. In this case the
minimum becomes the one imposed by the filter (that is 500 ns).
●For a CPU clock of 4 MHz, 4 TCL is 500 ns. In this case the minimum from the formula
is coherent with the limit imposed by the filter.
20.2 Asynchronous reset
An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low
level. Then the ST10F271Z1 is immediately (after the input filter delay) forced in reset
default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts
Table 48. Reset event definition
Reset source Flag RPD
status Conditions
Power-on reset PONR Low Power-on
Asynchronous hardware reset
LHWR
Low tRSTIN > 1)
Synchronous long hardware
reset High tRSTIN > (1032 + 12) TCL + max(4 TCL,
500 ns)
Synchronous short hardware
reset SHWR High
tRSTIN > max(4 TCL, 500 ns)
tRSTIN ≤ (1032 + 12) TCL + max(4 TCL,
500 ns)
Watchdog timer reset WDTR 3) WDT overflow
Software reset SWR 3) SRST instruction execution
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all internal/external bus cycles, it switches buses (data, address and control signals) and I/O
pin drivers to high-impedance, it pulls high Port0 pins.
Note: If an asynchronous reset occurs during a read or write phase in internal memories, the
content of the memory itself could be corrupted: to avoid this, synchronous reset usage is
strongly recommended.
Power-on reset
The asynchronous reset must be used during the power-on of the device. Depending
on crystal or resonator frequency, the on-chip oscillator needs about 1ms to 10ms to
stabilize (Refer to Electrical Characteristics Section), with an already stable VDD. The logic
of the ST10F271Z1 does not need a stabilized clock signal to detect an asynchronous reset,
so it is suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin
and the RPD pin must be held at low level until the device clock signal is stabilized and the
system configuration value on Port0 is settled.
At Power-on it is important to respect some additional constraints introduced by the start-up
phase of the different embedded modules.
In particular the on-chip voltage regulator needs at least 1ms to stabilize the internal 1.8V
for the core logic: this time is computed from when the external reference (VDD) becomes
stable (inside specification range, that is at least 4.5 V). This is a constraint for the
application hardware (external voltage regulator): the RSTIN pin assertion shall be extended
to guarantee the voltage regulator stabilization.
A second constraint is imposed by the embedded Flash. When booting from internal
memory, starting from RSTIN releasing, it needs a maximum of 1 ms for its initialization:
before that, the internal reset (RST signal) is not released, so the CPU does not start code
execution in internal memory.
Note: This is not true if external memory is used (pin EA held low during reset phase). In this case,
once RSTIN pin is released, and after few CPU clock (Filter delay plus 3...8 TCL), the
internal reset signal RST is released as well, so the code execution can start immediately
after. Obviously, an eventual access to the data in internal Flash is forbidden before its
initialization phase is completed: an eventual access during starting phase will return FFFFh
(just at the beginning), while later 009Bh (an illegal opcode trap can be generated).
At Power-on, the RSTIN pin shall be tied low for a minimum time that includes also the start-
up time of the main oscillator (tSTUP = 1ms for resonator, 10 ms for crystal) and PLL
synchronization time (tPSUP = 200 µs): this means that if the internal Flash is used, the
RSTIN pin could be released before the main oscillator and PLL are stable to recover some
time in the start-up phase (Flash initialization only needs stable V18, but does not need
stable system clock since an internal dedicated oscillator is used).
Warning: It is recommended to provide the external hardware with a
current limitation circuitry. This is necessary to avoid
permanent damages of the device during the power-on
transient, when the capacitance on V18 pin is charged. For
the on-chip voltage regulator functionality 10nF are
sufficient: anyway, a maximum of 100 nF on V18 pin should
not generate problems of over-current (higher value is
allowed if current is limited by the external hardware).
External current limitation is anyway recommended also to
avoid risks of damage in case of temporary short between
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V18 and ground: the internal 1.8V drivers are sized to drive
currents of several tens of Ampere, so the current shall be
limited by the external hardware. The limit of current is
imposed by power dissipation considerations (Refer to
Electrical Characteristics Section).
In next Figures 17 and 18 Asynchronous Power-on timing diagrams are reported,
respectively with boot from internal or external memory, highlighting the reset phase
extension introduced by the embedded Flash module when selected.
Note: Never power the device without keeping RSTIN pin grounded: the device could enter in
unpredictable states, risking also permanent damages.
Figure 17. Asynchronous power-on RESET (EA = 1)
RSTF
P0[15:13]
P0[12:2]
transparent
transparent
P0[1:0] not t.
not transparent
FLARST
V18
XTAL1 ...
≤
2 TCL
RST
≤ 1 ms
Latching point of Port0 for
system start-up configuration
VDD
≥ 1 ms (for on-chip VREG stabilization)
RPD
IBUS-CS
≤ 1.2 ms (for resonator oscillation + PLL stabilization)
≤ 10.2 ms (for crystal oscillation + PLL stabilization)
RSTIN
(After Filter)
≤ 500 ns
≥ 50 ns
7 TCL
3..4 TCL
(Internal)
not t.
not t.
not t.
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Figure 18. Asynchronous power-on RESET (EA = 0)
Hardware reset
The asynchronous reset must be used to recover from catastrophic situations of the
application. It may be triggered by the hardware of the application. Internal hardware logic
and application circuitry are described in Reset circuitry chapter and Figures 30, 31 and 32.
It occurs when RSTIN is low and RPD is detected (or becomes) low as well.
RSTIN
P0[15:13]
P0[12:2]
not t.
transparent
not t.
P0[1:0] not t.
not transparent
V18
XTAL1 ...
3..8 TCL1)
RST
Latching point of Port0 for
system start-up configuration
VDD
≥ 1 ms (for on-chip VREG stabilization)
RPD
ALE
≥ 1.2 ms (for resonator oscillation + PLL stabilization)
≥ 10.2 ms (for crystal oscillation + PLL stabilization)
Note 1. 3 to 8 TCL depending on clock source selection.
RSTF
≤ 500 ns
(After Filter)
≥ 50 ns
8 TCL
transparent
3..4 TCL
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Figure 19. Asynchronous hardware reset (EA = 1)
RSTF
P0[15:13]
P0[12:2]
transparent
transparent
not t.
P0[1:0] not t.
not transparent
FLARST
≤
2 TCL
RST
≤ 1 ms
Latching point of Port0 for
system start-up configuration
RPD
IBUS-CS
1)
not transparent
not transparent
Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed)
Longer than 500 ns to take into account of Input Filter on RSTIN pin
(After Filter)
RSTIN
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
7 TCL
(internal)
3..4 TCL
not t. not t.
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Figure 20. Asynchronous hardware reset (EA = 0)
Exit from asynchronous reset state
When the
RSTIN
pin is pulled high, the device restarts: as already mentioned, if internal
Flash is used, the restarting occurs after the embedded Flash initialization routine is
completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are
driven to their inactive level. The ST10F271Z1 starts program execution from memory
location 00'0000h in code segment 0. This starting location will typically point to the general
initialization routine. Timing of asynchronous Hardware Reset sequence are summarized in
Figure 19 and Figure 20.
20.3 Synchronous reset (warm reset)
A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high
level. In order to properly activate the internal reset logic of the device, the RSTIN pin must
be held low, at least, during 4 TCL (2 periods of CPU clock): refer also to Section 20.1 for
details on minimum reset pulse duration. The I/O pins are set to high impedance and
RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of
12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are
cancelled and the current internal access cycle if any is completed. External bus cycle is
aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON
register was previously set by software. Note that this bit is always cleared on power-on or
after a reset sequence.
RSTF
P0[15:13]
P0[12:2]
transparent not t.
transparent not t.
P0[1:0] not t.
not transparent
3..8 TCL2)
RST
Latching point of Port0 for
system start-up configuration
RPD
ALE
1)
Note 2. 3 to 8 TCL depending on clock source selection.
not transparent
not transparent
Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed)
Longer than 500ns to take into account of Input Filter on RSTIN pin
(After Filter)
RSTIN
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
8 TCL
3..4 TCL
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Short and long synchronous reset
Once the first maximum 16 TCL are elapsed (4+12 TCL), the internal reset sequence starts.
It is 1024 TCL cycles long: at the end of it, and after other 8 TCL the level of RSTIN is
sampled (after the filter, see RSTF in the drawings): if it is already at high level, only Short
Reset is flagged (Refer to Chapter 19: Watchdog timer for details on reset flags); if it is
recognized still low, the Long reset is flagged as well. The major difference between Long
and Short reset is that during the Long reset, also P0(15:13) become transparent, so it is
possible to change the clock options.
Warning: In case of a short pulse on RSTIN pin, and when Bidirectional
reset is enabled, the RSTIN pin is held low by the internal
circuitry. At the end of the 1024 TCL cycles, the RTSIN pin is
released, but due to the presence of the input analog filter the
internal input reset signal (RSTF in the drawings) is released
later (from 50 to 500 ns). This delay is in parallel with the
additional 8 TCL, at the end of which the internal input reset
line (RSTF) is sampled, to decide if the reset event is Short or
Long. In particular:
●If 8 TCL > 500 ns (FCPU < 8 MHz), the reset event is always recognized as Short
●If 8 TCL < 500 ns (FCPU > 8 MHz), the reset event could be recognized either as Short
or Long, depending on the real filter delay (between 50 and 500 ns) and the CPU
frequency (RSTF sampled High means Short reset, RSTF sampled Low means Long
reset). Note that in case a Long Reset is recognized, once the 8 TCL are elapsed, the
P0(15:13) pins becomes transparent, so the system clock can be re-configured. The
port returns not transparent 3-4 TCL after the internal RSTF signal becomes high.
The same behavior just described, occurs also when unidirectional reset is selected and
RSTIN pin is held low till the end of the internal sequence (exactly 1024 TCL + max 16 TCL)
and released exactly at that time.
Note: When running with CPU frequency lower than 40 MHz, the minimum valid reset pulse to be
recognized by the CPU (4 TCL) could be longer than the minimum analog filter delay (50ns);
so it might happen that a short reset pulse is not filtered by the analog input filter, but on the
other hand it is not long enough to trigger a CPU reset (shorter than 4 TCL): this would
generate a Flash reset but not a system reset. In this condition, the Flash answers always
with FFFFh, which leads to an illegal opcode and consequently a trap event is generated.
Exit from synchronous reset state
The reset sequence is extended until RSTIN level becomes high. Besides, it is internally
prolonged by the Flash initialization when EA=1 (internal memory selected). Then, the code
execution restarts. The system configuration is latched from Port0, and ALE, RD and
WR/WRL pins are driven to their inactive level. The ST10F271Z1 starts program execution
from memory location 00'0000h in code segment 0. This starting location will typically point
to the general initialization routine. Timing of synchronous reset sequence are summarized
in Figures 21 and 22 where a Short Reset event is shown, with particular highlighting on the
fact that it can degenerate into Long Reset: the two figures show the behavior when booting
from internal or external memory respectively. Figures 23 and 24 reports the timing of a
typical synchronous Long Reset, again when booting from internal or external memory.
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Synchronous reset and RPD pin
Whenever the RSTIN pin is pulled low (by external hardware or as a consequence of a
Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance
(if any) on RPD pin is slowly discharged through the internal weak pull-down. If the voltage
level on RPD pin reaches the input low threshold (around 2.5 V), the reset event becomes
immediately asynchronous. In case of hardware reset (short or long) the situation goes
immediately to the one illustrated in Figure 19. There is no effect if RPD comes again above
the input threshold: the asynchronous reset is completed coherently. To grant the normal
completion of a synchronous reset, the value of the capacitance shall be big enough to
maintain the voltage on RPD pin sufficient high along the duration of the internal reset
sequence.
For a software or watchdog reset events, an active synchronous reset is completed
regardless of the RPD status.
It is important to highlight that the signal that makes RPD status transparent under reset is
the internal RSTF (after the noise filter).
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Figure 21. Synchronous short / long hardware RESET (EA = 1)
P0[15:13] not transparent
RSTF
P0[12:2] transparent not t.
P0[1:0] not t.
not transparent
FLARST
RST
≤ 1 ms
1024 TCL
≤ 2 TCL
2) VRPD > 2.5V Asynchronous Reset not entered
200
µ
A Discharge
RPD
RSTOUT
At this time RSTF is sampled HIGH or LOW
so it is SHORT or LONG reset
(After Filter)
RSTIN
< 1032 TCL≤4 TCL4)
3)
≤12 TCL
1)
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
IBUS-CS
7 TCL
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.
2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation),
the asynchronous reset is then immediately entered.
3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software.
Bit BDRSTEN is cleared after reset.
4. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the
internal filter (refer to Section 21.1).
Notes:
(Internal)
8 TCL
not t.
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Figure 22. Synchronous short / long hardware reset (EA = 0)
P0[15:13] not transparent
RSTF
P0[12:2] transparent not t.
P0[1:0] not t.
not transparent
RST
1024 TCL
3..8 TCL3)
2) VRPD > 2.5V Asynchronous Reset not entered
200mA Discharge
RPD
RSTOUT
At this time RSTF is sampled HIGH or LOW
so it is SHORT or LONG reset
(After Filter)
RSTIN
< 1032 TCL≤4 TCL5)
4)
≤12 TCL
1)
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
ALE
8 TCL
1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration.
2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation
)
the asynchronous reset is then immediately entered.
4. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software.
Bit BDRSTEN is cleared after reset.
5. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the
internal filter (refer to Section 21.1).
Notes:
3. 3 to 8 TCL depending on clock source selection.
8 TCL
not t.
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Figure 23. Synchronous long hardware reset (EA = 1)
P0[15:13] not transparent
RSTF
P0[12:2] transparent not t.
P0[1:0] not t.
not transparent
FLARST
RST
≤ 1 ms
1024+8 TCL
≤
2 TCL
1) VRPD > 2.5V Asynchronous Reset not entered
200
µ
A Discharge
RPD
RSTOUT
At this time RSTF is sampled LOW
so it is definitely LONG reset
(After Filter)
RSTIN
1024+8 TCL≤4 TCL2) ≤12 TCL
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
IBUS-CS
7 TCL
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation),
the asynchronous reset is then immediately entered. Even if RPD returns above the threshold,
2. Minimum RSTIN low pulse duration shall also be longer than 500 ns to guarantee the pulse is not masked by the
internal filter (refer to Section 21.1).
Notes:
not t.
transparent
not t.
3..4 TCL
(Internal)
the reset is defnitively taken as asynchronous.
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Figure 24. Synchronous long hardware reset (EA = 0)
20.4 Software reset
A software reset sequence can be triggered at any time by the protected SRST (software
reset) instruction. This instruction can be deliberately executed within a program, e.g. to
leave bootstrap loader mode, or on a hardware trap that reveals system failure.
On execution of the SRST instruction, the internal reset sequence is started. The
microcontroller behavior is the same as for a synchronous short reset, except that only bits
P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits
P0.7...P0.2 are cleared (that is written at ‘1’).
A Software reset is always taken as synchronous: there is no influence on Software Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.
P0[15:13] not transparent
RSTF
P0[12:2] transparent not t.
P0[1:0] not t.
not transparent
RST
1024+8 TCL
3..8 TCL3)
1) VRPD > 2.5V Asynchronous Reset not entered
200
µ
A Discharge
RPD
RSTOUT
At this time RSTF is sampled LOW
so it is LONG reset
(After Filter)
RSTIN
1024+8 TCL4 TCL2) 12 TCL
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
ALE
8 TCL
1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5 V for 5 V operation),
the asynchronous reset is then immediately entered.
2. Minimum RSTIN low pulse duration shall also be longer than 500 ns to guarantee the pulse is not masked by the
internal filter (refer to Section 21.1).
Notes:
not t.
transparent
3. 3 to 8 TCL depending on clock source selection.
3..4 TCL
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Refer to next Figures 25 and 26 for unidirectional SW reset timing, and to Figures 27, 28 and
29 for bidirectional.
20.5 Watchdog timer reset
When the watchdog timer is not disabled during the initialization, or serviced regularly
during program execution, it will overflow and trigger the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus
cycle if this bus cycle either does not use READY
, or if READY is sampled active (low) after
the programmed wait states.
When READY is sampled inactive (high) after the programmed wait states the running
external bus cycle is aborted. Then the internal reset sequence is started.
Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared
(that is written at ‘1’).
A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.
Refer to next Figures 25 and 26 for unidirectional SW reset timing, and to Figures 27, 28 and
29 for bidirectional.
Figure 25. SW / WDT unidirectional reset (EA = 1)
P0[7:2] not transparent
P0[12:8] transparent not t.
P0[1:0] not t.
not transparent
RST
1024 TCL
RSTOUT
RSTIN
IBUS-CS
7 TCL
P0[15:13] not transparent
FLARST
≤ 1 ms
(Internal)
≤ 2 TCL
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Figure 26. SW / WDT unidirectional reset (EA = 0)
20.6 Bidirectional reset
As shown in the previous sections, the RSTOUT pin is driven active (low level) at the
beginning of any reset sequence (synchronous/asynchronous hardware, software and
watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization
routine, until the protected EINIT instruction (End of Initialization) is completed.
The Bidirectional Reset function is useful when external devices require a reset signal but
cannot be connected to RSTOUT pin, because RSTOUT signal lasts during initialization. It
is, for instance, the case of external memory running initialization routine before the
execution of EINIT instruction.
Bidirectional reset function is enabled by setting bit 3 (BDRSTEN) in SYSCON register. It
only can be enabled during the initialization routine, before EINIT instruction is completed.
When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal,
for the duration of the internal reset sequence (synchronous/asynchronous hardware,
synchronous software and synchronous watchdog timer resets). At the end of the internal
reset sequence the pull down is released and:
●After a Short Synchronous Bidirectional Hardware Reset, if RSTF is sampled low
8 TCL periods after the internal reset sequence completion (refer to Figure 21 and
Figure 22), the Short Reset becomes a Long Reset. On the contrary, if RSTF is
sampled high the device simply exits reset state.
●After a Software or Watchdog Bidirectional Reset, the device exits from reset. If RSTF
remains still low for at least 4 TCL periods (minimum time to recognize a Short
Hardware reset) after the reset exiting (refer to Figure 27 and Figure 28), the Software
or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains
low for less than 4 TCL, the device simply exits reset state.
P0[7:2] not transparent
P0[12:8] transparent not t.
P0[1:0] not t.
not transparent
RST
1024 TCL
RSTOUT
RSTIN
ALE
8 TCL
P0[15:13] not transparent
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The Bidirectional reset is not effective in case RPD is held low, when a Software or
Watchdog reset event occurs. On the contrary, if a Software or Watchdog Bidirectional reset
event is active and RPD becomes low, the RSTIN pin is immediately released, while the
internal reset sequence is completed regardless of RPD status change (1024 TCL).
Note: The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of
SYSCON is cleared). To be activated again it must be enabled during the initialization
routine.
WDTCON flags
Similarly to what already highlighted in the previous section when discussing about Short
reset and the degeneration into Long reset, similar situations may occur when Bidirectional
reset is enabled. The presence of the internal filter on RSTIN pin introduces a delay: when
RSTIN is released, the internal signal after the filter (see RSTF in the drawings) is delayed,
so it remains still active (low) for a while. It means that depending on the internal clock
speed, a short reset may be recognized as a long reset: the WDTCON flags are set
accordingly.
Besides, when either Software or Watchdog bidirectional reset events occur, again when the
RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal
(after the filter) remains low for a while, and depending on the clock frequency it is
recognized high or low: 8TCL after the completion of the internal sequence, the level of
RSTF signal is sampled, and if recognized still low a hardware reset sequence starts, and
WDTCON will flag this last event, masking the previous one (Software or Watchdog reset).
Typically, a short hardware reset is recognized, unless the RSTIN pin (and consequently
internal signal RSTF) is sufficiently held low by the external hardware to inject a long
hardware reset. After this occurrence, the initialization routine is not able to recognize a
software or watchdog bidirectional reset event, since a different source is flagged inside
WDTCON register. This phenomenon does not occur when internal Flash is selected during
reset (EA = 1), since the initialization of the Flash itself extend the internal reset duration
well beyond the filter delay.
Next Figures 27, 28 and 29 summarize the timing for software and watchdog timer
bidirectional reset events: In particular Figure 29 shows the degeneration into hardware
reset.
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Figure 27. SW / WDT bidirectional RESET (EA=1)
P0[15:13] not transparent
RSTF
P0[12:8] transparent not t.
P0[1:0] not t.
not transparent
RST
1024 TCL
RSTOUT
(After Filter)
RSTIN
≤
500 ns
≥
50 ns
≤
500 ns
≥
50 ns
IBUS-CS
7 TCL
FLARST
≤
1 ms
≤
2 TCL
(Internal)
P0[7:2] not transparent
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Figure 28. SW / WDT bidirectional reset (EA = 0)
P0[15:13] not transparent
RSTF
P0[12:8] transparent not t.
P0[1:0] not t.
not transparent
RST
1024 TCL
RSTOUT
At this time RSTF is sampled HIGH
so SW or WDT Reset is flagged in WDTCON
(After Filter)
RSTIN
≤ 500 ns
≥ 50 ns
≤ 500 ns
≥ 50 ns
ALE
8 TCL
P0[7:2] not transparent
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Figure 29. SW / WDT bidirectional reset (EA=0) followed by a HW RESET
20.7 Reset circuitry
Internal reset circuitry is described in Figure 32. The
RSTIN
pin provides an internal pull-up
resistor of 50 kΩ to 250 kΩ (The minimum reset time must be calculated using the lowest
value).
It also provides a programmable (BDRSTEN bit of SYSCON register) pull-down to output
internal reset state signal (synchronous reset, watchdog timer reset or software reset).
This bidirectional reset function is useful in applications where external devices require a
reset signal but cannot be connected to
RSTOUT
pin.
This is the case of an external memory running codes before EINIT (end of initialization)
instruction is executed.
RSTOUT
pin is pulled high only when EINIT is executed.
The RPD pin provides an internal weak pull-down resistor which discharges external
capacitor at a typical rate of 200 µA. If bit PWDCFG of SYSCON register is set, an internal
pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any
capacitor connected on RPD pin.
The simplest way to reset the ST10F271Z1 is to insert a capacitor C1 between
RSTIN
pin
and VSS, and a capacitor between RPD pin and VSS (C0) with a pull-up resistor R0 between
RPD pin and VDD. The input
RSTIN
provides an internal pull-up device equalling a resistor of
50 kΩ to 250 kΩ (the minimum reset time must be determined by the lowest value). Select
C1 that produce a sufficient discharge time to permit the internal or external oscillator and /
or internal PLL and the on-chip voltage regulator to stabilize.
P0[15:13] not transparent
RSTF
P0[12:8] transparent not t.
P0[1:0] not t.
not transparent
RST
1024 TCL
RSTOUT
At this time RSTF is sampled LOW
so HW Reset is entered
(After Filter)
RSTIN
≤ 500 ns
≥ 50 ns
ALE
8 TCL
≤ 500 ns
≥ 50 ns
P0[7:2] not transparent
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To ensure correct power-up reset with controlled supply current consumption, specially if
clock signal requires a long period of time to stabilize, an asynchronous hardware reset is
required during power-up. For this reason, it is recommended to connect the external R0-C0
circuit shown in Figure 30 to the RPD pin. On power-up, the logical low level on RPD pin
forces an asynchronous hardware reset when
RSTIN
is asserted low. The external pull-up
R0 will then charge the capacitor C0. Note that an internal pull-down device on RPD pin is
turned on when
RSTIN
pin is low, and causes the external capacitor (C0) to begin
discharging at a typical rate of 100-200µA. With this mechanism, after power-up reset, short
low pulses applied on
RSTIN
produce synchronous hardware reset. If
RSTIN
is asserted
longer than the time needed for C0 to be discharged by the internal pull-down device, then
the device is forced in an asynchronous reset. This mechanism insures recovery from very
catastrophic failure.
Figure 30. Minimum external reset circuitry
The minimum reset circuit of Figure 30 is not adequate when the
RSTIN
pin is driven from
the ST10F271Z1 itself during software or watchdog triggered resets, because of the
capacitor C1 that will keep the voltage on
RSTIN
pin above VIL after the end of the internal
reset sequence, and thus will trigger an asynchronous reset sequence.
Figure 31 shows an example of a reset circuit. In this example, R1-C1 external circuit is only
used to generate power-up or manual reset, and R0-C0 circuit on RPD is used for power-up
reset and to exit from power-down mode. Diode D1 creates a wired-OR gate connection to
the reset pin and may be replaced by open-collector Schmitt trigger buffer. Diode D2
provides a faster cycle time for repetitive power-on resets.
R2 is an optional pull-up for faster recovery and correct biasing of TTL open collector
drivers.
RSTOUT
RPD
RSTIN
C1 a) Hardware
VCC
+
C0
R0 b) For Power-up
(and Interruptible
Power-down
External Hardware
Reset
mode)
Reset
+
ST10F271Z1
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Figure 31. System reset circuit
Figure 32. Internal (simplified) reset circuitry
RPD
RSTIN
VDD
+
C0
R0
External Hardware
VDD
R2
+
C1
R1
D2
D1
o.d. External
Reset Source
Open Drain Inverter
VDD
ST10F271Z1
RSTOUT
EINIT Instruction
Trigger
Clr
Clock
Reset State
Machine
Internal
Reset
Signal
Reset Sequence
(512 CPU clock cycles)
SRST instruction
watchdog overflow RSTIN
VDD
BDRSTEN
VDD
RPD
Weak Pulldown
(~200µA)
From/to Exit
Powerdown
Circuit
Asynchronous
Reset
Clr
Q
Set
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20.8 Reset application examples
Next two timing diagrams (Figure 33 and Figure 34) provides additional examples of
bidirectional internal reset events (software and watchdog) including in particular the
external capacitances charge and discharge transients (refer also to Figure 31 for the
external circuit scheme).
Figure 33. Example of software or watchdog bidirectional reset (EA = 1)
VIL
VIH
RSTOUT
RSTIN
RSTF
ideal
Tfilter RST
< 500 ns
1024 TCL (12.8 us) 1 ms (C1 charge)
Tfilter RST
< 500 ns
RPD
VIL
RST
WDTCON
[5:0]
EINIT
04h 1Ch 00h
P0[15:13]
< 4 TCL
P0[12:8]
P0[7:2]
P0[1:0]
Latching point
Latching point
Latching point
Latching point
not transparent not transparent
not transparent
not transparent
not transparent
not transparent
not transparent
not transparent
transparent
transparent
transparent
4 TCL
3..8 TCL
0Ch
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Figure 34. Example of software or watchdog bidirectional reset (EA = 0)
VIL
VIH
RSTOUT
RSTIN
RSTF
ideal
Tfilter RST
< 500 ns
1024 TCL (12.8 us) 1 ms (C1 charge)
Tfilter RST
< 500 ns
RPD
VIL
RST
WDTCON
[5:0]
EINIT
04h 1Ch 00h
P0[15:13]
< 4 TCL
P0[12:8]
P0[7:2]
P0[1:0]
Latching point
Latching point
Latching point
Latching point
not transparent not transparent
not transparent
not transparent
not transparent
not transparent
not transparent
not transparent
transparent
transparent
transparent
4 TCL
3..8 TCL
0Ch
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20.9 Reset summary
A summary of the different reset events is reported in the table below.
Table 49. Reset event
Event
RPD
EA
Bidir
Synch.
asynch.
RSTIN WDTCON flags
min max
PONR
LHWR
SHWR
SWR
WDTR
Power-on reset
0 0 N Asynch.
1 ms (VREG)
1.2 ms
(Reson. + PLL)
10.2 ms
(Crystal + PLL)
- 11110
0 1 N Asynch. 1 ms (VREG) - 1 1 1 1 0
1 x x FORBIDDEN
x x Y NOT APPLICABLE
Hardware reset
(asynchronous)
0 0 N Asynch. 500 ns - 0 1 1 1 0
0 1 N Asynch. 500 ns - 0 1 1 1 0
0 0 Y Asynch. 500 ns - 0 1 1 1 0
0 1 Y Asynch. 500 ns - 0 1 1 1 0
Short hardware
reset
(synchronous) (1)
1 0 N Synch. max (4 TCL, 500 ns) 1032 + 12 TCL +
max(4 TCL, 500ns) 00110
1 1 N Synch. max (4 TCL, 500 ns) 1032 + 12 TCL +
max(4 TCL, 500ns) 00110
1 0 Y Synch. max (4 TCL, 500 ns) 1032 + 12 TCL +
max(4 TCL, 500ns) 00110
Activated by internal logic for 1024 TCL
1 1 Y Synch. max (4 TCL, 500 ns) 1032 + 12 TCL +
max(4 TCL, 500ns) 00110
Activated by internal logic for 1024 TCL
Long hardware
reset
(synchronous)
1 0 N Synch. 1032 + 12 TCL +
max(4 TCL, 500ns) - 01110
1 1 N Synch. 1032 + 12 TCL +
max(4 TCL, 500ns) - 01110
1 0 Y Synch.
1032 + 12 TCL +
max(4 TCL, 500 ns) -01110
Activated by internal logic only for 1024 TCL
1 1 Y Synch.
1032 + 12 TCL +
max(4 TCL, 500 ns) -01110
Activated by internal logic only for 1024 TCL
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The start-up configurations and some system features are selected on reset sequences as
described in Ta bl e 5 0 and Figure 35.
Ta bl e 5 0 describes what is the system configuration latched on PORT0 in the six different
reset modes. Figure 35 summarizes the state of bits of PORT0 latched in RP0H, SYSCON,
BUSCON0 registers.
Software reset (2)
x 0 N Synch. Not activated 0 0 0 1 0
x 0 N Synch. Not activated 0 0 0 1 0
0 1 Y Synch. Not activated 0 0 0 1 0
1 1 Y Synch. Activated by internal logic for 1024 TCL 0 0 0 1 0
Watchdog reset (2)
x 0 N Synch. Not activated 0 0 0 1 1
x 0 N Synch. Not activated 0 0 0 1 1
0 1 Y Synch. Not activated 0 0 0 1 1
1 1 Y Synch. Activated by internal logic for 1024 TCL 0 0 0 1 1
1. It can degenerate into a Long Hardware Reset and consequently differently flagged (see Section 20.3 for details).
2. When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently
flagged (see Section 20.6 for details).
Table 49. Reset event (continued)
Event
RPD
EA
Bidir
Synch.
asynch.
RSTIN WDTCON flags
min max
PONR
LHWR
SHWR
SWR
WDTR
Table 50. PORT0 latched configuration for the different reset events
X: Pin is sampled
-: Pin is not sampled
PORT0
Clock options
Segm. addr. lines
Chip selects
WR config.
Bus type
Reserved
BSL
Reserved
Reserved
Adapt mode
Emu mode
Sample event
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
Software reset - - - XXXXXXX - - - - - -
Watchdog reset - - - XXXXXXX - - - - - -
Synchronous short hardware reset - - - XXXXXXXXXXXXX
Synchronous long hardware reset XXXXXXXXXXXXXXXX
Asynchronous hardware reset XXXXXXXXXXXXXXXX
Asynchronous power-on reset XXXXXXXXXXXXXXXX
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Figure 35. PORT0 bits latched into the different registers after reset
L.5 L.4 L.3 L.2 L.1 L.0H.3 H.2 H.1 H.0 L.7 L.6H.7 H.6 H.5 H.4
EMUADPWRCCSSELSALSEL BUSTYP
RP0H
Clock
Port 4
Logic Port 6
Logic
SYSCON BUSCON0
Internal Control Logic
CLKCFG
76
2
P0L.7
P0L.7
9
BYTDIS
WRCFG
PORT0
Bootstrap Loader
Generator
CLKCFG SALSEL CSSEL WRC
BTYP
BSL Res.
10 9
ALE
CTL0
BUS
ACT0
EA / VSTBY
ROMEN
10 8
7
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21 Power reduction modes
Three different power reduction modes with different levels of power reduction have been
implemented in the ST10F271Z1. In Idle mode only CPU is stopped, while peripheral still
operate. In power-down mode both CPU and peripherals are stopped. In Stand-by mode the
main power supply (VDD) can be turned off while a portion of the internal RAM remains
powered via VSTBY dedicated power pin.
Idle and power-down modes are software activated by a protected instruction and are
terminated in different ways as described in the following sections.
Stand-by mode is entered simply removing VDD, holding the MCU under reset state.
Note: All external bus actions are completed before Idle or power-down mode is entered.
However, Idle or power-down mode is not entered if READY is enabled, but has not been
activated (driven low for negative polarity, or driven high for positive polarity) during the last
bus access.
21.1 Idle mode
Idle mode is entered by running IDLE protected instruction. The CPU operation is stopped
and the peripherals still run.
Idle mode is terminate by any interrupt request. Whatever the interrupt is serviced or not,
the instruction following the IDLE instruction will be executed after return from interrupt
(RETI) instruction, then the CPU resumes the normal program.
21.2 Power-down mode
Power-down mode starts by running PWRDN protected instruction. Internal clock is
stopped, all MCU parts are on hold including the watchdog timer. The only exception could
be the Real-Time Clock if opportunely programmed and one of the two oscillator circuits as
a consequence (either the main or the 32 kHz on-chip oscillator).
When Real-Time Clock module is used, when the device is in power-down mode a
reference clock is needed. In this case, two possible configurations may be selected by the
user application according to the desired level of power reduction:
●A 32 kHz crystal is connected to the on-chip low-power oscillator (pins XTAL3 / XTAL4)
and running. In this case the main oscillator is stopped when power-down mode is
entered, while the Real-Time Clock continue counting using 32 kHz clock signal as
reference. The presence of a running low-power oscillator is detected after the Power-
on: this clock is immediately assumed (if present, or as soon as it is detected) as
reference for the Real-Time Clock counter and it will be maintained forever (unless
specifically disabled via software).
●Only the main oscillator is running (XTAL1 / XTAL2 pins). In this case the main
oscillator is not stopped when power-down is entered, and the Real-Time Clock
continue counting using the main oscillator clock signal as reference.
There are two different operating power-down modes: protected mode and interruptible
mode.
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Before entering power-down mode (by executing the instruction PWRDN), bit VREGOFF in
XMISC register must be set.
Note: Leaving the main voltage regulator active during power-down may lead to unexpected
behavior (ex: CPU wake-up) and power consumption higher than what specified.
21.2.1 Protected power-down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is cleared. The protected
power-down mode is only activated if the NMI pin is pulled low when executing PWRDN
instruction (this means that the PWRD instruction belongs to the NMI software routine). This
mode is only deactivated with an external hardware reset on RSTIN pin.
21.2.2 Interruptible power-down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is set.
The Interruptible power-down mode is only activated if all the enabled Fast External
Interrupt pins are in their inactive level.
This mode is deactivated with an external reset applied to RSTIN pin or with an interrupt
request applied to one of the Fast External Interrupt pins, or with an interrupt generated by
the Real-Time Clock, or with an interrupt generated by the activity on CAN’s and I2C module
interfaces. To allow the internal PLL and clock to stabilize, the RSTIN pin must be held low
according the recommendations described in Chapter 20: System reset on page 77.
An external RC circuit must be connected to RPD pin, as shown in the Figure 36.
Figure 36. External RC circuitry on RPD pin
To exit power-down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be
asserted for at least 40 ns.
21.3 Stand-by mode
In Stand-by mode, it is possible to turn off the main VDD provided that VSTBY is available
through the dedicated pin of the ST10F271Z1.
To enter Stand-by mode it is mandatory to held the device under reset: once the device is
under reset, the RAM is disabled (see XRAM2EN bit of XPERCON register), and its digital
interface is frozen in order to avoid any kind of data corruption.
A dedicated embedded low-power voltage regulator is implemented to generate the internal
low voltage supply (about 1.65 V in Stand-by mode) to bias all those circuits that shall
remain active: the portion of XRAM (8 Kbytes), the RTC counters and 32 kHz on-chip
oscillator amplifier.
RPD
VDD
C0
R0
220kΩ minimum
1 µF Typical
ST10F271Z1
+
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In normal running mode (that is when main VDD is on) the VSTBY pin can be tied to VSS
during reset to exercise the EA functionality associated with the same pin: the voltage
supply for the circuitries which are usually biased with VSTBY (see in particular the 32 kHz
oscillator used in conjunction with Real-Time Clock module), is granted by the active main
VDD.
It must be noted that Stand-by Mode can generate problems associated with the usage of
different power supplies in CMOS systems; particular attention must be paid when the
ST10F271Z1 I/O lines are interfaced with other external CMOS integrated circuits: if VDD of
ST10F271Z1 becomes (for example in Stand-by Mode) lower than the output level forced by
the I/O lines of these external integrated circuits, the ST10F271Z1 could be directly powered
through the inherent diode existing on ST10F271Z1 output driver circuitry. The same is valid
for ST10F271Z1 interfaced to active/inactive communication buses during Stand-by mode:
current injection can be generated through the inherent diode.
Furthermore, the sequence of turning on/off of the different voltage could be critical for the
system (not only for the ST10F271Z1 device). The device Stand-by mode current (ISTBY)
may vary while VDD to VSTBY (and vice versa) transition occurs: some current flows between
VDD and VSTBY pins. System noise on both VDD and VSTBY can contribute to increase this
phenomenon.
21.3.1 Entering stand-by mode
As already said, to enter Stand-by Mode XRAM2EN bit in the XPERCON Register must be
cleared: this allows to freeze immediately the RAM interface, avoiding any data corruption.
As a consequence of a RESET event, the RAM Power Supply is switched to the internal
low-voltage supply V18SB (derived from VSTBY through the low-power voltage regulator).
The RAM interface will remain frozen until the bit XRAM2EN is set again by software
initialization routine (at next exit from main VDD power-on reset sequence).
Since V18 is falling down (as a consequence of VDD turning off), it can happen that the
XRAM2EN bit is no longer able to guarantee its content (logic “0”), being the XPERCON
Register powered by internal V18. This does not generate any problem, because the Stand-
by Mode switching dedicated circuit continues to confirm the RAM interface freezing,
irrespective the XRAM2EN bit content; XRAM2EN bit status is considered again when
internal V18 comes back over internal stand-by reference V18SB.
If internal V18 becomes lower than internal stand-by reference (V18SB) of about 0.3 to 0.45 V
with bit XRAM2EN set, the RAM Supply switching circuit is not active: in case of a
temporary drop on internal V18 voltage versus internal V18SB during normal code execution,
no spurious Stand-by Mode switching can occur (the RAM is not frozen and can still be
accessed).
The ST10F271Z1 Core module, generating the RAM control signals, is powered by internal
V18 supply; during turning off transient these control signals follow the V18, while RAM is
switched to V18SB internal reference. It could happen that a high level of RAM write strobe
from ST10F271Z1 Core (active low signal) is low enough to be recognized as a logic “0” by
the RAM interface (due to V18 lower than V18SB): The bus status could contain a valid
address for the RAM and an unwanted data corruption could occur. For this reason, an extra
interface, powered by the switched supply, is used to prevent the RAM from this kind of
potential corruption mechanism.
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Warning: During power-off phase, it is important that the external
hardware maintains a stable ground level on RSTIN pin,
without any glitch, in order to avoid spurious exiting from
reset status with unstable power supply.
21.3.2 Exiting stand-by mode
After the system has entered the Stand-by Mode, the procedure to exit this mode consists of
a standard Power-on sequence, with the only difference that the RAM is already powered
through V18SB internal reference (derived from VSTBY pin external voltage).
It is recommended to held the device under RESET (RSTIN pin forced low) until external
VDD voltage pin is stable. Even though, at the very beginning of the power-on phase, the
device is maintained under reset by the internal low voltage detector circuit (implemented
inside the main voltage regulator) till the internal V18 becomes higher than about 1.0 V,
there is no warranty that the device stays under reset status if RSTIN is at high level
during power ramp up. So, it is important the external hardware is able to guarantee a
stable ground level on RSTIN along the power-on phase, without any temporary
glitch.
The external hardware shall be responsible to drive low the RSTIN pin until the VDD is
stable, even though the internal LVD is active.
Once the internal Reset signal goes low, the RAM (still frozen) power supply is switched to
the main V18.
At this time, everything becomes stable, and the execution of the initialization routines can
start: XRAM2EN bit can be set, enabling the RAM.
21.3.3 Real-time clock and stand-by mode
When Stand-by mode is entered (turning off the main supply VDD), the Real-Time Clock
counting can be maintained running in case the on-chip 32 kHz oscillator is used to provide
the reference to the counter. This is not possible if the main oscillator is used as reference
for the counter: being the main oscillator powered by VDD, once ths is switched off, the
oscillator is stopped.
21.3.4 Power reduction modes summary
In the following Table 51: Power reduction modes summary, a summary of the different
Power reduction modes is reported.
Obsolete Product(s) - Obsolete Product(s)
Power reduction modes ST10F271Z1
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Table 51. Power reduction modes summary
Mode
VDD
VSTBY
CPU
Peripherals
RTC
Main OSC
32 kHz OSC
STBY XRAM
XRAM
Idle on on off on off run off biased biased
on on off on on run on biased biased
Power-down
on on off off off off off biased biased
on on off off on on off biased biased
on on off off on off on biased biased
Stand-by off on off off off off off biased off
off on off off on off on biased off
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Programmable output clock divider
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22 Programmable output clock divider
A specific register mapped on the XBUS allows to choose the division factor on the
CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address
range.
When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the
CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of
register SYSCON, it is possible to program the clock prescaling factor: in this way on P3.15
a prescaled value of the CPU clock can be output.
When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15
does not output any clock signal, even though XCLKOUTDIV register is programmed.
Obsolete Product(s) - Obsolete Product(s)
Register set ST10F271Z1
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23 Register set
This section summarizes all registers implemented in the ST10F271Z1, ordered by name.
23.1 Special function registers
The following table lists all SFRs which are implemented in the ST10F271Z1 in alphabetical
order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”.
SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column
“Physical Address”.
Table 52. List of special function registers
Name Physical
address
8-bit
address Description Reset
value
ADCIC bFF98h CCh A/D converter end of conversion interrupt control
register - - 00h
ADCON bFFA0h D0h A/D converter control register 0000h
ADDAT FEA0h 50h A/D converter result register 0000h
ADDAT2 F0A0h E50h A/D converter 2 result register 0000h
ADDRSEL1 FE18h 0Ch Address select register 1 0000h
ADDRSEL2 FE1Ah 0Dh Address select register 2 0000h
ADDRSEL3 FE1Ch 0Eh Address select register 3 0000h
ADDRSEL4 FE1Eh 0Fh Address select register 4 0000h
ADEIC bFF9Ah CDh A/D converter overrun error interrupt control register - - 00h
BUSCON0 bFF0Ch 86h Bus configuration register 0 0xx0h
BUSCON1 bFF14h 8Ah Bus configuration register 1 0000h
BUSCON2 bFF16h 8Bh Bus configuration register 2 0000h
BUSCON3 bFF18h 8Ch Bus configuration register 3 0000h
BUSCON4 bFF1Ah 8Dh Bus configuration register 4 0000h
CAPREL FE4Ah 25h GPT2 capture/reload register 0000h
CC0 FE80h 40h CAPCOM register 0 0000h
CC0IC bFF78h BCh CAPCOM register 0 interrupt control register - - 00h
CC1 FE82h 41h CAPCOM register 1 0000h
CC1IC bFF7Ah BDh CAPCOM register 1 interrupt control register - - 00h
CC2 FE84h 42h CAPCOM register 2 0000h
CC2IC bFF7Ch BEh CAPCOM register 2 interrupt control register - - 00h
CC3 FE86h 43h CAPCOM register 3 0000h
CC3IC bFF7Eh BFh CAPCOM register 3 interrupt control register - - 00h
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Register set
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CC4 FE88h 44h CAPCOM register 4 0000h
CC4IC bFF80h C0h CAPCOM register 4 interrupt control register - - 00h
CC5 FE8Ah 45h CAPCOM register 5 0000h
CC5IC bFF82h C1h CAPCOM register 5 interrupt control register - - 00h
CC6 FE8Ch 46h CAPCOM register 6 0000h
CC6IC bFF84h C2h CAPCOM register 6 interrupt control register - - 00h
CC7 FE8Eh 47h CAPCOM register 7 0000h
CC7IC bFF86h C3h CAPCOM register 7 interrupt control register - - 00h
CC8 FE90h 48h CAPCOM register 8 0000h
CC8IC bFF88h C4h CAPCOM register 8 interrupt control register - - 00h
CC9 FE92h 49h CAPCOM register 9 0000h
CC9IC bFF8Ah C5h CAPCOM register 9 interrupt control register - - 00h
CC10 FE94h 4Ah CAPCOM register 10 0000h
CC10IC bFF8Ch C6h CAPCOM register 10 interrupt control register - - 00h
CC11 FE96h 4Bh CAPCOM register 11 0000h
CC11IC bFF8Eh C7h CAPCOM register 11 interrupt control register - - 00h
CC12 FE98h 4Ch CAPCOM register 12 0000h
CC12IC bFF90h C8h CAPCOM register 12 interrupt control register - - 00h
CC13 FE9Ah 4Dh CAPCOM register 13 0000h
CC13IC bFF92h C9h CAPCOM register 13 interrupt control register - - 00h
CC14 FE9Ch 4Eh CAPCOM register 14 0000h
CC14IC bFF94h CAh CAPCOM register 14 interrupt control register - - 00h
CC15 FE9Eh 4Fh CAPCOM register 15 0000h
CC15IC bFF96h CBh CAPCOM register 15 interrupt control register - - 00h
CC16 FE60h 30h CAPCOM register 16 0000h
CC16IC bF160h EB0h CAPCOM register 16 interrupt control register - - 00h
CC17 FE62h 31h CAPCOM register 17 0000h
CC17IC bF162h EB1h CAPCOM register 17 interrupt control register - - 00h
CC18 FE64h 32h CAPCOM register 18 0000h
CC18IC bF164h EB2h CAPCOM register 18 interrupt control register - - 00h
CC19 FE66h 33h CAPCOM register 19 0000h
CC19IC bF166h EB3h CAPCOM register 19 interrupt control register - - 00h
CC20 FE68h 34h CAPCOM register 20 0000h
CC20IC bF168h EB4h CAPCOM register 20 interrupt control register - - 00h
Table 52. List of special function registers (continued)
Name Physical
address
8-bit
address Description Reset
value
Obsolete Product(s) - Obsolete Product(s)
Register set ST10F271Z1
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CC21 FE6Ah 35h CAPCOM register 21 0000h
CC21IC bF16Ah EB5h CAPCOM register 21 interrupt control register - - 00h
CC22 FE6Ch 36h CAPCOM register 22 0000h
CC22IC bF16Ch EB6h CAPCOM register 22 interrupt control register - - 00h
CC23 FE6Eh 37h CAPCOM register 23 0000h
CC23IC bF16Eh EB7h CAPCOM register 23 interrupt control register - - 00h
CC24 FE70h 38h CAPCOM register 24 0000h
CC24IC bF170h EB8h CAPCOM register 24 interrupt control register - - 00h
CC25 FE72h 39h CAPCOM register 25 0000h
CC25IC bF172h EB9h CAPCOM register 25 interrupt control register - - 00h
CC26 FE74h 3Ah CAPCOM register 26 0000h
CC26IC bF174h EBAh CAPCOM register 26 interrupt control register - - 00h
CC27 FE76h 3Bh CAPCOM register 27 0000h
CC27IC bF176h EBBh CAPCOM register 27 interrupt control register - - 00h
CC28 FE78h 3Ch CAPCOM register 28 0000h
CC28IC bF178h EBCh CAPCOM register 28 interrupt control register - - 00h
CC29 FE7Ah 3Dh CAPCOM register 29 0000h
CC29IC bF184h EC2h CAPCOM register 29 interrupt control register - - 00h
CC30 FE7Ch 3Eh CAPCOM register 30 0000h
CC30IC bF18Ch EC6h CAPCOM register 30 interrupt control register - - 00h
CC31 FE7Eh 3Fh CAPCOM register 31 0000h
CC31IC bF194h ECAh CAPCOM register 31 interrupt control register - - 00h
CCM0 bFF52h A9h CAPCOM Mode Control register 0 0000h
CCM1 bFF54h AAh CAPCOM Mode Control register 1 0000h
CCM2 bFF56h ABh CAPCOM Mode Control register 2 0000h
CCM3 bFF58h ACh CAPCOM mode Control register 3 0000h
CCM4 bFF22h 91h CAPCOM Mode Control register 4 0000h
CCM5 bFF24h 92h CAPCOM Mode Control register 5 0000h
CCM6 bFF26h 93h CAPCOM Mode Control register 6 0000h
CCM7 bFF28h 94h CAPCOM Mode Control register 7 0000h
CP FE10h 08h CPU Context Pointer register FC00h
CRIC bFF6Ah B5h GPT2 CAPREL interrupt control register - - 00h
CSP FE08h 04h CPU Code Segment Pointer register (read only) 0000h
DP0L bF100h E80h P0L direction control register - - 00h
Table 52. List of special function registers (continued)
Name Physical
address
8-bit
address Description Reset
value
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Register set
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DP0H bF102h E81h P0h direction control register - - 00h
DP1L bF104h E82h P1L direction control register - - 00h
DP1H bF106h E83h P1h direction control register - - 00h
DP2 bFFC2h E1h Port 2 direction control register 0000h
DP3 bFFC6h E3h Port 3 direction control register 0000h
DP4 bFFCAh E5h Port 4 direction control register - - 00h
DP6 bFFCEh E7h Port 6 direction control register - - 00h
DP7 bFFD2h E9h Port 7 direction control register - - 00h
DP8 bFFD6h EBh Port 8 direction control register - - 00h
DPP0 FE00h 00h CPU data page pointer 0 register (10-bit) 0000h
DPP1 FE02h 01h CPU data page pointer 1 register (10-bit) 0001h
DPP2 FE04h 02h CPU data page pointer 2 register (10-bit) 0002h
DPP3 FE06h 03h CPU data page pointer 3 register (10-bit) 0003h
EMUCON FE0Ah 05h Emulation control register - - XXh
EXICON bF1C0h EE0h External interrupt control register 0000h
EXISEL bF1DAh EEDh External interrupt source selection register 0000h
IDCHIP F07Ch E3Eh Device identifier register (n is the device revision) 110nh
IDMANUF F07Eh E3Fh Manufacturer identifier register 0403h
IDMEM F07Ah E3Dh On-chip memory identifier register 3040h
IDPROG F078h E3Ch Programming voltage identifier register 0040h
IDX0 bFF08h 84h MAC unit address pointer 0 0000h
IDX1 bFF0Ah 85h MAC unit address pointer 1 0000h
MAH FE5Eh 2Fh MAC unit accumulator - high word 0000h
MAL FE5Ch 2Eh MAC unit accumulator - low word 0000h
MCW bFFDCh EEh MAC unit control word 0000h
MDC bFF0Eh 87h CPU multiply divide control register 0000h
MDH FE0Ch 06h CPU multiply divide register – high word 0000h
MDL FE0Eh 07h CPU multiply divide register – low word 0000h
MRW bFFDAh EDh MAC unit repeat word 0000h
MSW bFFDEh EFh MAC unit status word 0200h
ODP2 bF1C2h EE1h Port 2 open drain control register 0000h
ODP3 bF1C6h EE3h Port 3 open drain control register 0000h
ODP4 bF1CAh EE5h Port 4 open drain control register - - 00h
ODP6 bF1CEh EE7h Port 6 open drain control register - - 00h
Table 52. List of special function registers (continued)
Name Physical
address
8-bit
address Description Reset
value
Obsolete Product(s) - Obsolete Product(s)
Register set ST10F271Z1
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ODP7 bF1D2h EE9h Port 7 open drain control register - - 00h
ODP8 bF1D6h EEBh Port 8 open drain control register - - 00h
ONES bFF1Eh 8Fh Constant value 1’s register (read only) FFFFh
P0L bFF00h 80h PORT0 low register (lower half of PORT0) - - 00h
P0H bFF02h 81h PORT0 high register (upper half of PORT0) - - 00h
P1L bFF04h 82h PORT1 low register (lower half of PORT1) - - 00h
P1H bFF06h 83h PORT1 high register (upper half of PORT1) - - 00h
P2 bFFC0h E0h Port 2 register 0000h
P3 bFFC4h E2h Port 3 register 0000h
P4 bFFC8h E4h Port 4 register (8-bit) - - 00h
P5 bFFA2h D1h Port 5 register (read only) XXXXh
P6 bFFCCh E6h Port 6 register (8-bit) - - 00h
P7 bFFD0h E8h Port 7 register (8-bit) - - 00h
P8 bFFD4h EAh Port 8 register (8-bit) - - 00h
P5DIDIS bFFA4h D2h Port 5 digital disable register 0000h
PECC0 FEC0h 60h PEC channel 0 control register 0000h
PECC1 FEC2h 61h PEC channel 1 control register 0000h
PECC2 FEC4h 62h PEC channel 2 control register 0000h
PECC3 FEC6h 63h PEC channel 3 control register 0000h
PECC4 FEC8h 64h PEC channel 4 control register 0000h
PECC5 FECAh 65h PEC channel 5 control register 0000h
PECC6 FECCh 66h PEC channel 6 control register 0000h
PECC7 FECEh 67h PEC channel 7 control register 0000h
PICON bF1C4h EE2h Port input threshold control register - - 00h
PP0 F038h E1Ch PWM module period register 0 0000h
PP1 F03Ah E1Dh PWM module period register 1 0000h
PP2 F03Ch E1Eh PWM module period register 2 0000h
PP3 F03Eh E1Fh PWM module period register 3 0000h
PSW bFF10h 88h CPU program status word 0000h
PT0 F030h E18h PWM module up/down counter 0 0000h
PT1 F032h E19h PWM module up/down counter 1 0000h
PT2 F034h E1Ah PWM module up/down counter 2 0000h
PT3 F036h E1Bh PWM module up/down counter 3 0000h
PW0 FE30h 18h PWM module pulse width register 0 0000h
Table 52. List of special function registers (continued)
Name Physical
address
8-bit
address Description Reset
value
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Register set
113/185
PW1 FE32h 19h PWM module pulse width register 1 0000h
PW2 FE34h 1Ah PWM module pulse width register 2 0000h
PW3 FE36h 1Bh PWM module pulse width register 3 0000h
PWMCON0 bFF30h 98h PWM module control register 0 0000h
PWMCON1 bFF32h 99h PWM module control register 1 0000h
PWMIC bF17Eh EBFh PWM module interrupt control register - - 00h
QR0 F004h E02h MAC unit offset register r0 0000h
QR1 F006h E03h MAC unit offset register R1 0000h
QX0 F000h E00h MAC unit offset register X0 0000h
QX1 F002h E01h MAC unit offset register X1 0000h
RP0H bF108h E84h System start-up configuration register (read only) - - XXh
S0BG FEB4h 5Ah Serial channel 0 baud rate generator reload register 0000h
S0CON bFFB0h D8h Serial channel 0 control register 0000h
S0EIC bFF70h B8h Serial channel 0 error interrupt control register - - 00h
S0RBUF FEB2h 59h Serial channel 0 receive buffer register (read only) - - XXh
S0RIC bFF6Eh B7h Serial channel 0 receive interrupt control register - - 00h
S0TBIC bF19Ch ECEh Serial channel 0 transmit buffer interrupt control reg. - - 00h
S0TBUF FEB0h 58h Serial channel 0 transmit buffer register (write only) 0000h
S0TIC bFF6Ch B6h Serial channel 0 transmit interrupt control register - - 00h
SP FE12h 09h CPU system stack pointer register FC00h
SSCBR F0B4h E5Ah SSC Baud rate register 0000h
SSCCON bFFB2h D9h SSC control register 0000h
SSCEIC bFF76h BBh SSC error interrupt control register - - 00h
SSCRB F0B2h E59h SSC receive buffer (read only) XXXXh
SSCRIC bFF74h BAh SSC receive interrupt control register - - 00h
SSCTB F0B0h E58h SSC transmit buffer (write only) 0000h
SSCTIC bFF72h B9h SSC transmit interrupt control register - - 00h
STKOV FE14h 0Ah CPU stack overflow pointer register FA00h
STKUN FE16h 0Bh CPU stack underflow pointer register FC00h
SYSCON bFF12h 89h CPU system configuration register 0xx0h 1)
T0 FE50h 28h CAPCOM timer 0 register 0000h
T01CON bFF50h A8h CAPCOM timer 0 and timer 1 control register 0000h
T0IC bFF9Ch CEh CAPCOM timer 0 interrupt control register - - 00h
T0REL FE54h 2Ah CAPCOM timer 0 reload register 0000h
Table 52. List of special function registers (continued)
Name Physical
address
8-bit
address Description Reset
value
Obsolete Product(s) - Obsolete Product(s)
Register set ST10F271Z1
114/185
T1 FE52h 29h CAPCOM timer 1 register 0000h
T1IC bFF9Eh CFh CAPCOM timer 1 interrupt control register - - 00h
T1REL FE56h 2Bh CAPCOM timer 1 reload register 0000h
T2 FE40h 20h GPT1 timer 2 register 0000h
T2CON bFF40h A0h GPT1 timer 2 control register 0000h
T2IC bFF60h B0h GPT1 timer 2 interrupt control register - - 00h
T3 FE42h 21h GPT1 timer 3 register 0000h
T3CON bFF42h A1h GPT1 timer 3 control register 0000h
T3IC bFF62h B1h GPT1 timer 3 interrupt control register - - 00h
T4 FE44h 22h GPT1 timer 4 register 0000h
T4CON bFF44h A2h GPT1 timer 4 control register 0000h
T4IC bFF64h B2h GPT1 timer 4 interrupt control register - - 00h
T5 FE46h 23h GPT2 timer 5 register 0000h
T5CON bFF46h A3h GPT2 timer 5 control register 0000h
T5IC bFF66h B3h GPT2 timer 5 interrupt control register - - 00h
T6 FE48h 24h GPT2 timer 6 register 0000h
T6CON bFF48h A4h GPT2 timer 6 control register 0000h
T6IC bFF68h B4h GPT2 timer 6 interrupt control register - - 00h
T7 F050h E28h CAPCOM timer 7 register 0000h
T78CON bFF20h 90h CAPCOM timer 7 and 8 control register 0000h
T7IC bF17Ah EBDh CAPCOM timer 7 interrupt control register - - 00h
T7REL F054h E2Ah CAPCOM timer 7 reload register 0000h
T8 F052h E29h CAPCOM timer 8 register 0000h
T8IC bF17Ch EBEh CAPCOM timer 8 interrupt control register - - 00h
T8REL F056h E2Bh CAPCOM timer 8 reload register 0000h
TFR bFFACh D6h Trap Flag register 0000h
WDT FEAEh 57h Watchdog timer register (read only) 0000h
WDTCON bFFAEh D7h Watchdog timer control register 00xxh 2)
XADRS3 F01Ch E0Eh XPER address select register 3 800Bh
XP0IC bF186h EC3h See Section 9.1 - - 00h 3)
XP1IC bF18Eh EC7h See Section 9.1 - - 00h 3)
XP2IC bF196h ECBh See Section 9.1 - - 00h 3)
XP3IC bF19Eh ECFh See Section 9.1 - - 00h 3)
Table 52. List of special function registers (continued)
Name Physical
address
8-bit
address Description Reset
value
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Register set
115/185
Note: 1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0
x000 0000b.
2. Reset Value depends on different triggered reset event.
3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus
peripherals. Some software controlled interrupt requests may be generated by setting the
XPnIR bits (of XPnIC register) of the unused X-Peripheral nodes.
23.2 XBus registers
The following table lists all XBus registers which are implemented in the ST10F271Z1
ordered by their name.
Note: The XBus registers are not bit-addressable.
XPERCON bF024h E12h XPER configuration register - - 05h
ZEROS bFF1Ch 8Eh Constant value 0’s register (read only) 0000h
Table 52. List of special function registers (continued)
Name Physical
address
8-bit
address Description Reset
value
Table 53. List of XBus registers
Name Physical
address Description Reset
value
CAN1BRPER EF0Ch CAN1: BRP extension register 0000h
CAN1BTR EF06h CAN1: Bit timing register 2301h
CAN1CR EF00h CAN1: CAN control register 0001h
CAN1EC EF04h CAN1: error counter 0000h
CAN1IF1A1 EF18h CAN1: IF1 arbitration 1 0000h
CAN1IF1A2 EF1Ah CAN1: IF1 arbitration 2 0000h
CAN1IF1CM EF12h CAN1: IF1 command mask 0000h
CAN1IF1CR EF10h CAN1: IF1 command request 0001h
CAN1IF1DA1 EF1Eh CAN1: IF1 data A 1 0000h
CAN1IF1DA2 EF20h CAN1: IF1 data A 2 0000h
CAN1IF1DB1 EF22h CAN1: IF1 data B 1 0000h
CAN1IF1DB2 EF24h CAN1: IF1 data B 2 0000h
CAN1IF1M1 EF14h CAN1: IF1 mask 1 FFFFh
CAN1IF1M2 EF16h CAN1: IF1 mask 2 FFFFh
CAN1IF1MC EF1Ch CAN1: IF1 message control 0000h
CAN1IF2A1 EF48h CAN1: IF2 arbitration 1 0000h
CAN1IF2A2 EF4Ah CAN1: IF2 arbitration 2 0000h
CAN1IF2CM EF42h CAN1: IF2 command mask 0000h
Obsolete Product(s) - Obsolete Product(s)
Register set ST10F271Z1
116/185
CAN1IF2CR EF40h CAN1: IF2 command request 0001h
CAN1IF2DA1 EF4Eh CAN1: IF2 data A 1 0000h
CAN1IF2DA2 EF50h CAN1: IF2 data A 2 0000h
CAN1IF2DB1 EF52h CAN1: IF2 data B 1 0000h
CAN1IF2DB2 EF54h CAN1: IF2 data B 2 0000h
CAN1IF2M1 EF44h CAN1: IF2 Mask 1 FFFFh
CAN1IF2M2 EF46h CAN1: IF2 mask 2 FFFFh
CAN1IF2MC EF4Ch CAN1: IF2 message control 0000h
CAN1IP1 EFA0h CAN1: interrupt pending 1 0000h
CAN1IP2 EFA2h CAN1: interrupt pending 2 0000h
CAN1IR EF08h CAN1: interrupt register 0000h
CAN1MV1 EFB0h CAN1: message valid 1 0000h
CAN1MV2 EFB2h CAN1: message valid 2 0000h
CAN1ND1 EF90h CAN1: new data 1 0000h
CAN1ND2 EF92h CAN1: new data 2 0000h
CAN1SR EF02h CAN1: status register 0000h
CAN1TR EF0Ah CAN1: test register 00x0h
CAN1TR1 EF80h CAN1: transmission request 1 0000h
CAN1TR2 EF82h CAN1: transmission request 2 0000h
CAN2BRPER EE0Ch CAN2: BRP extension register 0000h
CAN2BTR EE06h CAN2: bit timing register 2301h
CAN2CR EE00h CAN2: CAN control register 0001h
CAN2EC EE04h CAN2: error counter 0000h
CAN2IF1A1 EE18h CAN2: IF1 arbitration 1 0000h
CAN2IF1A2 EE1Ah CAN2: IF1 arbitration 2 0000h
CAN2IF1CM EE12h CAN2: IF1 command mask 0000h
CAN2IF1CR EE10h CAN2: IF1 command request 0001h
CAN2IF1DA1 EE1Eh CAN2: IF1 data A 1 0000h
CAN2IF1DA2 EE20h CAN2: IF1 data A 2 0000h
CAN2IF1DB1 EE22h CAN2: IF1 data B 1 0000h
CAN2IF1DB2 EE24h CAN2: IF1 data B 2 0000h
CAN2IF1M1 EE14h CAN2: IF1 mask 1 FFFFh
CAN2IF1M2 EE16h CAN2: IF1 mask 2 FFFFh
CAN2IF1MC EE1Ch CAN2: IF1 message control 0000h
Table 53. List of XBus registers (continued)
Name Physical
address Description Reset
value
Obsolete Product(s) - Obsolete Product(s)
ST10F271Z1 Register set
117/185
CAN2IF2A1 EE48h CAN2: IF2 arbitration 1 0000h
CAN2IF2A2 EE4Ah CAN2: IF2 arbitration 2 0000h
CAN2IF2CM EE42h CAN2: IF2 command mask 0000h
CAN2IF2CR EE40h CAN2: IF2 command request 0001h
CAN2IF2DA1 EE4Eh CAN2: IF2 data A 1 0000h
CAN2IF2DA2 EE50h CAN2: IF2 data A 2 0000h
CAN2IF2DB1 EE52h CAN2: IF2 data B 1 0000h
CAN2IF2DB2 EE54h CAN2: IF2 data B 2 0000h
CAN2IF2M1 EE44h CAN2: IF2 mask 1 FFFFh
CAN2IF2M2 EE46h CAN2: IF2 mask 2 FFFFh
CAN2IF2MC EE4Ch CAN2: IF2 message control 0000h
CAN2IP1 EEA0h CAN2: interrupt pending 1 0000h
CAN2IP2 EEA2h CAN2: interrupt pending 2 0000h
CAN2IR EE08h CAN2: interrupt register 0000h
CAN2MV1 EEB0h CAN2: message valid 1 0000h
CAN2MV2 EEB2h CAN2: message valid 2 0000h
CAN2ND1 EE90h CAN2: new data 1 0000h
CAN2ND2 EE92h CAN2: new data 2 0000h
CAN2SR EE02h CAN2: status register 0000h
CAN2TR EE0Ah CAN2: test register 00x0h
CAN2TR1 EE80h CAN2: transmission request 1 0000h
CAN2TR2 EE82h CAN2: Transmission request 2 0000h
I2CCCR1 EA06h I2C clock control register 1 0000h
I2CCCR2 EA0Eh I2C clock control register 2 0000h
I2CCR EA00h I2C control register 0000h
I2CDR EA0Ch I2C data register 0000h
I2COAR1 EA08h I2C own address register 1 0000h
I2COAR2 EA0Ah I2C own address register 2 0000h
I2CSR1 EA02h I2C status register 1 0000h
I2CSR2 EA04h I2C status register 2 0000h
RTCAH ED14h RTC alarm register high byte XXXXh
RTCAL ED12h RTC alarm register low byte XXXXh
RTCCON ED00H RTC control register 000Xh
RTCDH ED0Ch RTC divider counter high byte XXXXh
Table 53. List of XBus registers (continued)
Name Physical
address Description Reset
value
Obsolete Product(s) - Obsolete Product(s)
Register set ST10F271Z1
118/185
RTCDL ED0Ah RTC divider counter low byte XXXXh
RTCH ED10h RTC programmable counter high byte XXXXh
RTCL ED0Eh RTC programmable counter low byte XXXXh
RTCPH ED08h RTC prescaler register high byte XXXXh
RTCPL ED06h RTC prescaler register low byte XXXXh
XCLKOUTDIV EB02h CLKOUT divider control register - - 00h
XEMU0 EB76h XBUS emulation register 0 (write only) XXXXh
XEMU1 EB78h XBUS emulation register 1 (write only) XXXXh
XEMU2 EB7Ah XBUS emulation register 2 (write only) XXXXh
XEMU3 EB7Ch XBUS emulation register 3 (write only) XXXXh
XIR0CLR EB14h X-Interrupt 0 clear register (write only) 0000h
XIR0SEL EB10h X-Interrupt 0 selection register 0000h
XIR0SET EB12h X-Interrupt 0 set register (write only) 0000h
XIR1CLR EB24h X-Interrupt 1 clear register (write only) 0000h
XIR1SEL EB20h X-Interrupt 1 selection register 0000h
XIR1SET EB22h X-Interrupt 1 set register (write only) 0000h
XIR2CLR EB34h X-Interrupt 2 clear register (write only) 0000h
XIR2SEL EB30h X-Interrupt 2 selection register 0000h
XIR2SET EB32h X-Interrupt 2 set register (write only) 0000h
XIR3CLR EB44h X-Interrupt 3 clear selection register (write only) 0000h
XIR3SEL EB40h X-Interrupt 3 selection register 0000h
XIR3SET EB42h X-Interrupt 3 set selection register (write only) 0000h
XMISC EB46h XBUS miscellaneous features register 0000h
XP1DIDIS EB36h Port 1 digital disable register 0000h
XPEREMU EB7Eh XPERCON copy for emulation (write only) XXXXh
XPICON EB26h Extended port input threshold control register - - 00h
XPOLAR EC04h XPWM module channel polarity register 0000h
XPP0 EC20h XPWM module period register 0 0000h
XPP1 EC22h XPWM module period register 1 0000h
XPP2 EC24h XPWM module period register 2 0000h
XPP3 EC26h XPWM module period register 3 0000h
XPT0 EC10h XPWM module up/down counter 0 0000h
XPT1 EC12h XPWM module up/down counter 1 0000h
XPT2 EC14h XPWM module up/down counter 2 0000h
Table 53. List of XBus registers (continued)
Name Physical
address Description Reset
value
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23.3 Flash registers ordered by name
The following table lists all Flash Control Registers which are implemented in the
ST10F271Z1 ordered by their name. These registers are physically mapped on the IBus,
except for XFVTAUR0, which is mapped on XBus.
Note: These registers are not bit-addressable.
XPT3 EC16h XPWM module up/down counter 3 0000h
XPW0 EC30h XPWM module pulse width register 0 0000h
XPW1 EC32h XPWM module pulse width register 1 0000h
XPW2 EC34h XPWM module pulse width register 2 0000h
XPW3 EC36h XPWM module pulse width register 3 0000h
XPWMCON0 EC00h XPWM module control register 0 0000h
XPWMCON0CLR EC08h XPWM module clear control reg. 0 (write only) 0000h
XPWMCON0SET EC06h XPWM module set control register 0 (write only) 0000h
XPWMCON1 EC02h XPWM module control register 1 0000h
XPWMCON1CLR EC0Ch XPWM module clear control reg. 0 (write only) 0000h
XPWMCON1SET EC0Ah XPWM module set control register 0 (write only) 0000h
XPWMPORT EC80h XPWM module port control register 0000h
XS1BG E906h XASC Baud rate generator reload register 0000h
XS1CON E900h XASC control register 0000h
XS1CONCLR E904h XASC clear control register (write only) 0000h
XS1CONSET E902h XASC set control register (write only) 0000h
XS1PORT E980h XASC port control register 0000h
XS1RBUF E90Ah XASC receive buffer register 0000h
XS1TBUF E908h XASC transmit buffer register 0000h
XSSCBR E80Ah XSSC Baud rate register 0000h
XSSCCON E800h XSSC control register 0000h
XSSCCONCLR E804h XSSC clear control register (write only) 0000h
XSSCCONSET E802h XSSC set control register (write only) 0000h
XSSCPORT E880h XSSC port control register 0000h
XSSCRB E808h XSSC receive buffer XXXXh
XSSCTB E806h XSSC transmit buffer 0000h
Table 53. List of XBus registers (continued)
Name Physical
address Description Reset
value
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23.4 Identification registers
The ST10F271Z1 has four Identification registers, mapped in ESFR space. These registers
contain:
●A manufacturer identifier
●A chip identifier with its revision
●A internal Flash and size identifier
●Programming voltage description
Note: As the ST10F271Z1 device is supported with the silicon of the ST10F272 (commercial
version of the same product), the identification registers provide the values corresponding to
the ST10F272 device.
IDMANUF (F07Eh / 3Fh) ESFR Reset Value: 0403h
Table 54. List of Flash registers
Name Physical
address Description Reset value
FARH 0x0008 0012 Flash address register - high 0000h
FARL 0x0008 0010 Flash address register - low 0000h
FCR0H 0x0008 0002 Flash control register 0 - high 0000h
FCR0L 0x0008 0000 Flash control register 0 - low 0000h
FCR1H 0x0008 0006 Flash control register 1 - high 0000h
FCR1L 0x0008 0004 Flash control register 1 - low 0000h
FDR0H 0x0008 000A Flash data register 0 - high FFFFh
FDR0L 0x0008 0008 Flash data register 0 - low FFFFh
FDR1H 0x0008 000E Flash data register 1 - high FFFFh
FDR1L 0x0008 000C Flash data register 1 - low FFFFh
FER 0x0008 0014 Flash error register 0000h
FNVAPR0 0x0008 DFB8 Flash non-volatile access protection reg.0 ACFFh
FNVAPR1H 0x0008 DFBE Flash non-volatile access protection reg.1 - high FFFFh
FNVAPR1L 0x0008 DFBC Flash non-volatile access protection reg.1 - low FFFFh
FNVWPIR 0x000E DFB0 Flash non-volatile protection I register FFFFh
XFVTAUR0 0x0000 EB50 XBus Flash volatile temporary access
unprotection register 0 FFFFh
1514131211109876543210
MANUF 00011
RR
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IDCHIP (F07Ch / 3Eh) ESFR Reset Value: 110Xh
IDMEM (F07Ah / 3Dh) ESFR Reset Value: 3040h
Table 55. IDMANUF
Bit Function
MANUF Manufacturer identifier
020h: STMicroelectronics manufacturer (JTAG worldwide normalization).
1514131211109876543210
IDCHIP REVID
RR
Table 56. IDCHIP
Bit Function
IDCHIP Device identifier
110h: ST10F271Z1 identifier (272).
REVID Device revision identifier
Xh: According to revision number.
1514131211109876543210
MEMTYP MEMSIZE
RR
Table 57. IDMEM
Bit Function
MEMSIZE
Internal memory size
Internal memory size is 4 x (MEMSIZE) (in Kbyte)
040h for 256 Kbytes (ST10F272)
MEMTYP
Internal memory type
‘0h’: ROM-Less
‘1h’: (M) ROM memory
‘2h’: (S) Standard Flash memory
‘3h’: (H) High performance Flash memory (ST10F271Z1)
‘4h...Fh’: Reserved
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IDPROG (F078h / 3Ch) ESFR Reset Value: 0040h
Note: All identification words are read only registers.
The values written inside different Identification Register bits are valid only after the Flash
initialization phase is completed. When code execution is started from internal memory (pin
EA held high during reset), the Flash has certainly completed its initialization, so the bits of
identification registers are immediately ready to be read out. On the contrary, when code
execution is started from external memory (pin EA held low during reset), the Flash
initialization is not yet completed, so the bits of identification registers are not ready. The
user can poll bits 15 and 14 of IDMEM register: when both bits are read low, the Flash
initialization is complete, so all identification register bits are correct.
Before Flash initialization completion, the default setting of the different identification
registers are the following:
●IDMANUF 0403h
●IDCHIP 110xh (x = silicon revision)
●IDMEM F040h
●IDPROG 0040h
1514131211109876543210
PROGVPP PROGVDD
RR
Table 58. IDPROG
Bit Function
PROGVDD
Programming VDD voltage
VDD voltage when programming EPROM or Flash devices is calculated using the
following formula: VDD = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F271Z1 (5V).
PROGVPP Programming VPP voltage (no need of external VPP) - 00h
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24 Known limitations
This section describes all functional and electrical limitations identified on the silicon revision
A of the ST10F271Z1. They are listed in Table 59: List of limitations on page 123
The revision number of the device can be read in the IDCHIP register (@F07Ch) which is
set to 1102h for this device (refer to 23.4: Identification registers).
Table 59. List of limitations
Limitation
24.1: Injected conversion stalling the ADC
24.2: Concurrent transmission requests in DAR-mode (C-CAN module)
24.3: Transmission request disabled (C-CAN module)
24.4: Spurious BREQ pulse in slave mode during external bus arbitration phase
24.5: Flash wake-up from idle mode
24.6: Executing PWRDN instruction
24.7: Flash wake-up from power-down mode
24.8: Behavior of CAPCOM outputs in compare mode 3
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24.1 Injected conversion stalling the ADC
Description
Whenever a new injection request occurs before the ADDAT2 register has been read by the
CPU (that is, when the result of the previous injection request has not been read), the ADC
is stalled and no further conversions are performed.
Workaround
The following actions make it possible to unlock the ADC module:
1. Read the ADDAT2 register twice at the end of every injected conversion. This action
also prevents the ADC from being stalled).
2. Disable and then enable again the wait for read mode
Application conditions
This problem can occur if all the following conditions are fulfilled:
●Injection requests are hardware triggered (via CapCom CC31)
●The result of injected conversions is read via a PEC transfer. This prevents from
reading twice the ADDAT2 register by software)
●A high level task is disabling the PEC transfer for a long time (2 analog conversions +
time between 2 injection requests)
Therefore, to prevent the locking situation from occurring, it is important to make sure that,
at application level, no task can disable interrupts for a period of time during which 2
injection requests can occur before a read operation is performed.
Detailed analysis
Channel injection mode allows the conversion of a specific analog channel without changing
the current operating mode. It can also be used while the ADC is running in a continuous or
auto scan mode.
The following main points need to be highlighted:
●Wait for ADDAT read mode is needed in order for the ADC Channel Injection mode to
operate properly
●At the end of the injected conversion the data is available in the alternate result register
ADDAT2 and a Channel Injection Complete Interrupt request is generated (ADEIR
Flag)
●If the temporary data register used for ADDAT2 read mode is full, the next conversion
(standard or injected) is suspended. The temporary register then stores the content of
ADDAT (standard conversion) or ADDAT2 (from an injected conversion).
If the temporary data register used for ADDAT2 read mode is full and a new injection request
occurs then the new converted value is stored into a temporary data register until the
previous one is read from ADDAT2.
To ensure a correct operation as soon as ADDAT2 register is read, the last converted value
should be moved from temporary register to ADDAT2 and the ADEINT interrupt should be
requested. The last converted value can then be read by the CPU. See Figure 37.
In real circumstances, as soon as ADDAT2 register is read then the last converted value is
correctly moved from temporary register to ADDAT2 but the ADEINT interrupt request is not
received by the Interrupt Controller (see Figure 38). As a consequence, the CPU/PEC can
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not know that a new converted value is ready to be read in ADDAT2 register. Therefore at
the following injection request the ADC fills the temporary register again (without generating
any ADEINT interrupt request) and then the ADC is stalled for any further conversion. The
ADC stays in the “wait for read ADDAT2 register” condition forever.
Figure 37. ADC injection theoretical operation
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Figure 38. ADC injection actual operation
ADEINT Interrupt
not generated
ADDAT2 correctly updated
and can be read by software
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24.2 Concurrent transmission requests in DAR-mode (C-CAN
module)
Description
When the C-CAN module is configured to operate in DAR-mode (Disable Automatic
Retransmission) and the host requests the transmission of several messages at the same
time, only two of these messages are transmitted. For all other requested transmit
messages, the TxRqst bits are reset but no transmission starts, NewDat and IntPnd are kept
unchanged. For the two messages which are transmitted, the TxRqst and NewDat bits are
reset and IntPnd is set if it has been enabled by TxIE.
The normal operation mode (DAR = 0) is not affected by this phenomenon.
Workaround
The DAR-mode is intended to support time triggered operation (TTCAN level 1), accepting
the transmission of a message only in its dedicated time window. It is an error to request the
transmission of several messages at the same time. So no workaround is necessary for
TTCAN applications.
The progress of a requested transmission can be monitored by checking the message
object’s TxRqst and NewDat [optionally IntPnd] bits. In DAR-Mode, when a message
transmission has failed either because the transmission was disturbed or because it has not
started, it is necessary to request the message transmission again.
For details on DAR mode and message control registers, refer to user manual UM0409.
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24.3 Transmission request disabled (C-CAN module)
Description
The transmission request of a message object may remain disabled (even if the host
immediately enables it again) in the following situations:
1. if the host disables the pending transmission request of the lowest-priority message
object (number 32 by default) in the short time window during which the message
handler state machine prepares the transmission of the message
2. if the transmission has not started.
Reading the transmission request bit of this message object does not show that the
transmission request is disabled. This only happens when this message object is the only
one with a pending transmission request.
If the transmission request is blocked in the disabled state, it will be re-enabled by the first
activity detected on the CAN bus or by setting the transmission request of any other
message object.
The other message objects are not affected by this phenomenon.
Workaround
It is usually not necessary to disable the transmission request of a message object. If the
message object is to be used for another message, it is sufficient to prepare the new content
for this message object in the CPU interface register (Identifier, DLC, Data, with TxRqst and
NewDat [optionally TxIE] bits) and to transfer this content into the message object. The new
content is transmitted at the next opportunity. It is not altered by a possibly ongoing
transmission of the previous content of the same message object.
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24.4 Spurious BREQ pulse in slave mode during external bus
arbitration phase
Description
Sporadic bus errors may occur when external bus arbitration is used via the HOLD function
and the ST10F272Z2 is configured as a slave.
After the slave has been granted access to the bus, the slave disables the BREQ signal
sporadically for a short time, even though slave access to the bus has not been completed.
The master starts then its own bus access, generating a bus conflict between master and
slave.
Workaround
To avoid producing any spurious BREQ pulse during a slave external bus arbitration phase,
it is necessary to guarantee that the time between the HLDA assertion (Bus Acknowledge
from Master device) and the following HOLD falling edge (Bus Request from Master) is
longer than three clock cycles.
This can be implemented by delaying the HOLD signal with an RC circuit as shown in Figure
3.
Figure 39. ST10 in Slave mode
BREQ
HLDA
HOLD BREQ (P6.7)
HLDA (P6.6)
HOLD (P6.5)
Master ST10 in Slave mode
VSS
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24.5 Flash wake-up from idle mode
Description
When waking up from idle mode, the Flash response time is slower than in running mode.
This can lead to an incorrect data read or code fetch when the CPU frequency is higher than
55 MHz.
As a consequence, the use of IDLE instruction is not allowed for frequencies higher than
55 MHz.
Workaround
There is no workaround for frequencies higher than 55 MHz.
24.6 Executing PWRDN instruction
Description
The power-down mode is not entered and the PWRDN instruction is ignored in the following
cases:
●The PWRDN instruction is executed while NMI is high (PWDCFG bit of the SYSCON
register cleared)
●The PWRDN instruction is executed while at least one of the Port 2 pins used to exit
from power-down mode (PWDCFG bit of the SYSCON register is set) is at the active
level.
However, under the conditions described below, the PWRDN instruction is not ignored, and
no further instructions are fetched from external memory, that is, the CPU is in a quasi-idle
state.
This problem only occurs in the following situations:
1. The instructions following the PWRDN instruction are located in an external memory
and a multiplexed bus configuration with memory tristate waitstate (bit MTTCx = 0)
is used.
2. The instruction preceding the PWRDN instruction writes to external memory or an
XPeripheral (such as XRAM or CAN) and the instructions following the PWRDN
instruction are located in external memory. In this case, the problem occurs for any bus
configuration.
Note: The on-chip peripherals still work correctly, in particular the watchdog timer. if the watchdog
timer is not disabled, it resets the device upon an overflow. However, interrupts and PEC
transfers cannot be processed. If NMI is asserted low while the device is in this quasi-idle
state, power-down mode is entered.
No problem occurs if the NMI pin is low (if PWDCFG = 0) or if all Port 2 pins used to exit
from power-down mode are at inactive level (if PWDCFG = 1): the chip enters normally
power-down mode.
Workaround
Ensure that no instruction that writes to external memory or to an XPeripheral precedes the
PWRDN instruction. Otherwise, insert a NOP instruction in front of PWRDN. When a
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multiplexed bus with memory tristate wait state is used, the PWRDN instruction must be
executed from internal RAM or XRAM.
24.7 Flash wake-up from power-down mode
Description
When waking up from interruptible power-down mode, the Flash response time is slower
than in running mode. This can lead to an incorrect data read or code fetch when the CPU
frequency is higher than 55 MHz.
As a consequence, exiting from interruptible power-down mode with an external interrupt is
not supported for frequencies greater than 55 MHz.
Workaround
There is no workaround for frequencies greater than 55 MHz.
Exiting from interruptible power-down mode with an external reset is supported at all
frequencies.
24.8 Behavior of CAPCOM outputs in compare mode 3
Description
When a CAPCOM channel is configured in compare mode 3, then the related output level
switches to high when the allocated timer, Tx, matches the related CAPCOM register, CCy.
When an overflow occurs on the CAPCOM timer Tx, it is reloaded with TxREL content and
the output pin is cleared. The output pin level does not change if TxREL and CCy have the
same value.
The related CAPCOM output stays low when the CAPCOM channel is configured in
compare mode 3 and TxREL and Tx related timer registers are loaded with the same value
as CCy. This is obtained by executing the following instructions:
MOV TxREL, #CCy value x =0,1,7,8
MOV Tx, #CCy value x = 0,1,7,8
MOV TxxCON, #data or bfldl/bfldh TxxCON , #mask, #data i.e. an
access is made to the T01CON or T78CON register.
Workarounds
The following workarounds make the CAPCOM output toggle as expected:
1) Invert the TxREL and Tx configuration as follow:
MOV Tx, #CCy value
MOV TxREL, #CCy value
bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data
2) Insert a NOP instruction before the T01CON or T78CON configuration:
MOV Tx, #value
MOV TxREL, #value
NOP
bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data
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3) Load the Tx timer with the CCy register minus 1:
MOV TxREL, #value
MOV Tx, #( value-1)
bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data
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25 Electrical characteristics
25.1 Absolute maximum ratings
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS) the
voltage on pins with respect to ground (VSS) must not exceed the values defined by the
Absolute Maximum Ratings.
During Power-on and Power-off transients (including Standby entering/exiting phases), the
relationships between voltages applied to the device and the main VDD shall be always
respected. In particular power-on and power-off of VAREF shall be coherent with VDD
transient, in order to avoid undesired current injection through the on-chip protection diodes.
Table 60. Absolute maximum ratings
Symbol Parameter Values Unit
VDD Voltage on VDD pins with respect to ground (VSS) -0.5 to +6.5 V
VSTBY Voltage on VSTBY pin with respect to ground (VSS) -0.5 to +6.5 V
VAREF Voltage on VAREF pins with respect to ground (VSS) -0.3 to VDD V
VAGND Voltage on VAGND pins with respect to ground (VSS)V
SS V
VIO Voltage on any pin with respect to ground (VSS) -0.5 to VDD + 0.5 V
IOV Input current on any pin during overload condition ± 10 mA
ITOV Absolute sum of all input currents during overload condition | 75 | mA
TST Storage temperature -65 to +150 °C
ESD ESD Susceptibility (Human Body Model) 2000 V
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25.2 Recommended operating conditions
25.3 Power considerations
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the
following equation:
TJ = TA + (PD x ΘJA) (1)
Where:
TA is the Ambient Temperature in °C,
ΘJA is the Package Junction-to-Ambient Thermal Resistance, in °C/W,
PD is the sum of PINT and PI/O (PD = PINT + PI/O),
PINT is the product of IDD and VDD, expressed in Watt. This is the Chip Internal Power,
PI/O represents the Power Dissipation on Input and Output Pins; User Determined.
Most of the time for the applications PI/O< PINT and may be neglected. On the other hand,
PI/O may be significant if the device is configured to drive continuously external modules
and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273°C) (2)
Therefore (solving equations 1 and 2):
K = PD x (TA + 273°C) + ΘJA x PD2 (3)
Where:
K is a constant for the particular part, which may be determined from equation (3) by
measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ
may be obtained by solving equations (1) and (2) iteratively for any value of TA.
Table 61. Recommended operating conditions
Symbol Parameter
Value
Unit
min max
VDD Operating supply voltage 4.5 5.5 V
VSTBY Operationg stand-by supply voltage (1) 4.5 5.5 V
VAREF Operating analog reference voltage (2)
TAAmbient temperature under bias -40 +125 °C
TJJunction temperature under bias -40 +150 °C
1. The value of the VSTBY voltage is specified in the range 4.5 - 5.5 Volt. Nevertheless, it is acceptable to exceed the upper
limit (up to 6.0 Volt) for a maximum of 100 hours over the global 300000 hours, representing the lifetime of the device
(about 30 years). On the other hand, it is possible to exceed the lower limit (down to 4.0 Volt) whenever RTC and 32kHz
on-chip oscillator amplifier are turned off (only Stand-by RAM powered through VSTBY pin in Stand-by mode). When
VSTBY voltage is lower than main VDD, the input section of VSTBY/EA pin can generate a spurious static consumption on
VDD power supply (in the range of tenth of µA).
2. For details on operating conditions concerning the usage of A/D Converter refer to Section 25.7.
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Based on thermal characteristics of the package and with reference to the power
consumption figures provided in next tables and diagrams, the following product
classification can be proposed. Anyhow, the exact power consumption of the device inside
the application must be computed according to different working conditions, thermal profiles,
real thermal resistance of the system (including printed circuit board or other substrata), I/O
activity, and so on.
25.4 Parameter interpretation
The parameters listed in the following tables represent the characteristics of the
ST10F271Z1 and its demands on the system.
Where the ST10F271Z1 logic provides signals with their respective timing characteristics,
the symbol “CC” for Controller Characteristics, is included in the “Symbol” column. Where
the external system must provide signals with their respective timing characteristics to the
ST10F271Z1, the symbol “SR” for System Requirement, is included in the “Symbol” column.
25.5 DC characteristics
VDD = 5 V ± 10%, VSS = 0 V, TA = –40 to +125 °C
Table 62. Thermal characteristics
Symbol Description Value (typical) Unit
ΘJA
Thermal Resistance Junction-Ambient
PQFP 144 - 28 x 28 x 3.4 mm / 0.65 mm pitch
LQFP 144 - 20 x 20 mm / 0.5 mm pitch
LQFP 144 - 20 x 20 mm / 0.5 mm pitch on four layer
FR4 board (2 layers signals / 2 layers power)
30
40
35
°C/W
Table 63. Package characteristics
Package Ambient temperature range CPU frequency range
PQFP 144 –40 / +125 °C1 – 64 MHz
LQFP 144 –40 / +125 °C1 – 40 MHz
Table 64. DC characteristics
Parameter Symbol
Limit values
Unit Test condition
min. max.
Input low voltage (TTL mode)
(except RSTIN, EA, NMI, RPD, XTAL1,
READY)
VIL SR – 0.3 0.8 V –
Input low voltage (CMOS mode)
(except RSTIN, EA, NMI, RPD, XTAL1,
READY)
VILS SR – 0.3 0.3 VDD V–
Input low voltage RSTIN, EA, NMI, RPD VIL1 SR – 0.3 0.3 VDD V–
Input low voltage XTAL1 (CMOS only) VIL2 SR – 0.3 0.3 VDD V Direct Drive mode
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Input low voltage READY (TTL only) VIL3 SR – 0.3 0.8 V –
Input high voltage (TTL mode)
(except RSTIN, EA, NMI, RPD, XTAL1) VIH SR 2.0 VDD + 0.3 V –
Input high voltage (CMOS mode)
(except RSTIN, EA, NMI, RPD, XTAL1) VIHS SR 0.7 VDD VDD + 0.3 V –
Input high voltage RSTIN, EA, NMI, RPD VIH1 SR 0.7 VDD VDD + 0.3 V –
Input high voltage XTAL1 (CMOS only) VIH2 SR 0.7 VDD VDD + 0.3 V Direct Drive mode
Input high voltage READY (TTL only) VIH3 SR 2.0 VDD + 0.3 V –
Input Hysteresis (TTL mode)
(except RSTIN, EA, NMI, XTAL1, RPD) VHYS CC 400 700 mV (1)
Input Hysteresis (CMOS mode)
(except RSTIN, EA, NMI, XTAL1, RPD) VHYSSCC 750 1400 mV (1)
Input Hysteresis RSTIN, EA, NMI VHYS1CC 750 1400 mV (1)
Input Hysteresis XTAL1 VHYS2CC 050mV (1)
Input Hysteresis READY (TTL only) VHYS3CC 400 700 mV (1)
Input Hysteresis RPD VHYS4CC 500 1500 mV (1)
Output low voltage
(P6[7:0], ALE, RD, WR/WRL,
BHE/WRH, CLKOUT, RSTIN,
RSTOUT)
VOL CC –0.4
0.05 VIOL = 8 mA
IOL = 1 mA
Output low voltage
(P0[15:0], P1[15:0], P2[15:0],
P3[15,13:0], P4[7:0], P7[7:0],
P8[7:0])
VOL1 CC –0.4
0.05 VIOL1 = 4 mA
IOL1 = 0.5 mA
Output low voltage RPD VOL2 CC –
VDD
0.5 VDD
0.3 VDD
V
IOL2 = 85 µA
IOL2 = 80 µA
IOL2 = 60 µA
Output high voltage
(P6[7:0], ALE, RD, WR/WRL,
BHE/WRH, CLKOUT, RSTOUT)
VOH CC VDD – 0.8
VDD – 0.08 –V
IOH = – 8 mA
IOH = – 1 mA
Output high voltage (2)
(P0[15:0], P1[15:0], P2[15:0],
P3[15,13:0], P4[7:0], P7[7:0],
P8[7:0])
VOH1 CC VDD – 0.8
VDD – 0.08 –V
IOH1 = – 4 mA
IOH1 = – 0.5 mA
Output high voltage RPD VOH2 CC
0
0.3 VDD
0.5 VDD
–V
IOH2 = – 2 mA
IOH2 = – 750 µA
IOH2 = – 150 µA
Input leakage current (P5[15:0]) (3) |IOZ1 |CC –±0.2µA–
Input leakage current
(all except P5[15:0], P2[0], RPD, P3[12],
P3[15])
|IOZ2 |CC –±0.5µA–
Table 64. DC characteristics (continued)
Parameter Symbol
Limit values
Unit Test condition
min. max.
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Input leakage current (P2[0]) (4) |IOZ3 |CC –+1.0
–0.5 µA–
Input leakage current (RPD) |IOZ4 |CC –±3.0µA–
Input leakage current ( P3[12], P3[15]) |IOZ5 |CC –±1.0µA–
Overload current (all except P2[0]) |IOV1 |SR –±5mA (1) (5)
Overload current (P2[0]) (4) |IOV2 |SR –+5
–1 mA (1) (5)
RSTIN pull-up resistor RRST CC 50 250 kΩ100 kΩ nominal
Read/Write inactive current (6) (7) IRWH ––40µAV
OUT = 2.4 V
Read/Write active current (6) (8) IRWL –500 – µAV
OUT = 0.4 V
ALE inactive current (6) (7) IALEL 20 – µAV
OUT = 0.4 V
ALE active current (6) (8) IALEH –300µAV
OUT = 2.4 V
Port 6 inactive current (P6[4:0]) (6) (7) IP6H ––40µAV
OUT = 2.4 V
Port 6 active current (P6[4:0]) (6) (8) IP6L –500 – µAV
OUT = 0.4 V
PORT0 configuration current (6) IP0H 6) ––10µAV
IN = 2.0 V
IP0L 7) –100 – µAV
IN = 0.8 V
Pin Capacitance (Digital inputs / outputs) CIO CC –10pF (1) (6)
Run Mode Power supply current (9)
(Execution from Internal RAM) ICC1 –15 + 1.5
fCPU
mA –
Run Mode Power supply current (1) (10)
(Execution from Internal Flash) ICC2 –15 + 1.5
fCPU
mA –
Idle mode supply current (11) IID –15 + 0.6
fCPU
mA –
Power-down supply current (12)
(RTC off, Oscillators off,
Main Voltage Regulator off)
IPD1 –200µAT
A = 25 °C
Power-down supply current (12)
(RTC on, Main Oscillator on,
Main Voltage Regulator off)
IPD2 –
400
Ty p ic al
Value
µAT
A = 25 °C
Power-down supply current (12)
(RTC on, 32kHz Oscillator on,
Main Voltage Regulator off)
IPD3 –200µAT
A = 25 °C
Stand-by supply current (12)
(RTC off, Oscillators off, VDD off, VSTBY
on)
ISB1
–120µAVSTBY = 5.5 V
TA = TJ = 25 °C
–500µAVSTBY = 5.5 V
TA = TJ = 125 °C
Table 64. DC characteristics (continued)
Parameter Symbol
Limit values
Unit Test condition
min. max.
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Stand-by supply current (12)
(RTC on, 32 kHz Oscillator on,
main VDD off, VSTBY on)
ISB2
–120µAVSTBY = 5.5 V
TA = TJ = 125 °C
–500µAVSTBY = 5.5 V
TA = TJ = 125 °C
Stand-by supply current (1) (12)
(VDD transient condition) ISB3 –2.5mA –
1. Not 100% tested, guaranteed by design characterization.
2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
and the voltage is imposed by the external circuitry.
3. Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default,
after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.
4. The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)
implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:
failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 40: Port2 test mode structure for a
scheme of the input circuitry.
5. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the
specified range (i.e. VOV > VDD + 0.3 V or VOV < –0.3 V). The absolute sum of input overload currents on all port pins may
not exceed 50mA. The supply voltage must remain within the specified limits.
6. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used
for CS output and the open drain function is not enabled.
7. The maximum current may be drawn while the respective signal line remains inactive.
8. The minimum current must be drawn in order to drive the respective signal line active.
9. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 41 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs
disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is
doing the following:
Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules
Watchdog Timer is enabled and regularly serviced
RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
10. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 38 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs
disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is
doing the following:
- Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM
- Watchdog Timer is enabled and regularly serviced
- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles
- Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling
- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)
- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5
- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced
11. The Idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is
illustrated in the Figure 37 below. These parameters are tested and at maximum CPU clock with all outputs disconnected
and all inputs at VIL or VIH, RSTIN pin at VIH1min.
12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD
– 0.1 V to VDD, VAREF = 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage
Regulator is assumed off: in case it is not, additional 1mA shall be assumed.
Table 64. DC characteristics (continued)
Parameter Symbol
Limit values
Unit Test condition
min. max.
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Figure 40. Port2 test mode structure
Figure 41. Supply current versus the operating frequency (run and idle modes)
Input
latch
Clock
P2.0
CC0IO
Output
buffer
Test mode
Alternate data input
Fast external interrupt input
Flash sense amplifier
and column decoder
I [mA]
fCPU [MHz]
10 20
150
100
50
4030 50 60 70
0
0
IID
ICC1 = ICC2
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25.6 Flash characteristics
VDD = 5 V ± 10%, VSS = 0 V
Table 65. Flash characteristics
Parameter
Typical Maximum
Unit NotesTA = 25 °C TA = 125 °C
0 cycles(1) 0 cycles(1) 100k cycles
Word program (32-bit) (2) 35 80 290 µs–
Double word program (64-bit)(2)) 60 150 570 µs–
Bank 0 program (128K)
(double word program) 1.6 2.0 3.9 s –
Sector erase (8K) 0.6
0.5
0.9
0.8
1.0
0.9 snot preprogrammed
preprogrammed
Sector erase (32K) 1.1
0.8
2.0
1.8
2.7
2.5 snot preprogrammed
preprogrammed
Sector erase (64K) 1.7
1.3
3.7
3.3
5.1
4.7 snot preprogrammed
preprogrammed
Bank 0 erase (128K) (3) 5.6
4.0
13.6
11.9
19.2
17.5 snot preprogrammed
preprogrammed
Recovery from power-down (tPD)– 40 40 µs(4)
Program suspend latency (4) –1010µs
Erase suspend latency (4) –3030µs
Erase suspend request rate (4) 20 20 20 ms Min delay between 2
requests
Set protection (4) 40 90 300 µs
1. The figures are given after about 100 cycles due to testing routines (0 cycles at the final customer).
2. Word and Double Word Programming times are provided as average values derived from a full sector programming time:
absolute value of a Word or Double Word Programming time could be longer than the average value.
3. Bank Erase is obtained through a multiple Sector Erase operation (setting bits related to all sectors of the Bank). As
ST10F271Z1 implements only one bank, the Bank Erase operation is equivalent to Module and Chip Erase operations.
4. Not 100% tested, guaranteed by Design Characterization.
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25.7 A/D converter characteristics
VDD = 5 V ± 10%, VSS = 0 V, TA = –40 to +125 °C, 4.5 V ≤ VAREF ≤ VDD,
VSS ≤ VAGND ≤ VSS + 0.2 V
Table 66. Flash data retention characteristics
Number of program / erase cycles
(-40 °C ≤ TA ≤ 125 °C)
Data retention time
(average ambient temperature 60°C)
128 Kbyte (code store) 64 Kbyte (EEPROM emulation) (1)
0 - 100 > 20 years > 20 years
1,000 - > 20 years
10,000 - 10 years
100,000 - 1 year
1. Two 64 Kbyte Flash Sectors may be typically used to emulate up to 4, 8 or 16 Kbyte of EEPROM. Therefore, in case of an
emulation of a 16 Kbyte EEPROM, 100,000 Flash Program / Erase cycles are equivalent to 800,000 EEPROM
Program/Erase cycles. For an efficient use of the EEPROM Emulation please refer to dedicated Application Note document
(AN2061 - “EEPROM Emulation with ST10F2xx”). Contact your local field service, local sales person or STMicroelectronics
representative to get copy of such a guideline document.
Table 67. A/D converter characteristics
Parameter Symbol
Limit values
Unit Test condition
min. max.
Analog reference voltage 1) VAREF SR 4.5 VDD V
Analog ground voltage VAGND SR VSS VSS + 0.2 V
Analog input voltage 2) VAIN SR VAGND VAREF V
Reference supply current IAREF CC –
–
5
1
mA
µA
Running mode 3)
Power-down mode
Sample time tSCC 1–µs4)
Conversion time tCCC 3–µs5)
Differential non linearity 6) DNL CC –1 +1 LSB No overload
Integral non linearity 6) INL CC –1.5 +1.5 LSB No overload
Offset error 6) OFS CC –1.5 +1.5 LSB No overload
Total unadjusted error 6) TUE CC
–2.0
–5.0
–7.0
+2.0
+5.0
+7.0
LSB
Port5
Port1 - No overload 3)
Port1 - Overload 3)
Coupling factor between inputs 3) 7) K CC –10
–6 – On both Port5 and Port1
Input pin capacitance 3) 8)
CP1 CC –3pF
CP2 CC –4
6pF Port5
Port1
Sampling capacitance 3) 8) CSCC –3.5pF
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1. VAREF can be tied to ground when A/D Converter is not in use: an extra consumption (around 200
µ
A) on
main VDD is added due to internal analogue circuitry not completely turned off: so, it is suggested to
maintain the VAREF at VDD level even when not in use, and eventually switch off the A/D Converter circuitry
setting bit ADOFF in ADCON register.
2. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be 0x000H or 0x3FFH, respectively.
3. Not 100% tested, guaranteed by design characterization.
4. During the sample time the input capacitance CAIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion
result.
Values for the sample clock tS depends on programming and can be taken from Table 68: A/D converter
programming.
5. This parameter includes the sample time tS, the time for determining the digital result and the time to load
the result register with the conversion result. Values for the conversion clock tCC depend on programming
and can be taken from next Table 68.
6. DNL, INL, OFS and TUE are tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 5.0 V. It is guaranteed by design
characterization for all other voltages within the defined voltage range.
‘LSB’ has a value of VAREF/1024.
For Port5 channels, the specified TUE (± 2LSB) is guaranteed also with an overload condition (see IOV
specification) occurring on maximum 2 not selected analog input pins of Port5 and the absolute sum of
input overload currents on all Port5 analog input pins does not exceed 10 mA.
For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins:
when an overload condition occurs on maximum 2 not selected analog input pins of Port1 and the input
positive overload current on all analog input pins does not exceed 10 mA (either dynamic or static
injection), the specified TUE is degraded (± 7LSB). To get the same accuracy, the negative injection
current on Port1 pins shall not exceed -1mA in case of both dynamic and static injection.
7. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not
selected channels with the overload current within the different specified ranges (for both positive and
negative injection current).
8. Refer to scheme reported in Figure 43: A/D converter input pins scheme.
25.7.1 Conversion timing control
When a conversion is started, first the capacitances of the converter are loaded via the
respective analog input pin to the current analog input voltage. The time to load the
capacitances is referred to as sample time. Next the sampled voltage is converted to a
digital value several successive steps, which correspond to the 10-bit resolution of the ADC.
During these steps the internal capacitances are repeatedly charged and discharged via the
VAREF pin.
The current that has to be drawn from the sources for sampling and changing charges
depends on the time that each respective step takes, because the capacitors must reach
their final voltage level within the given time, at least with a certain approximation. The
maximum current, however, that a source can deliver, depends on its internal resistance.
The time that the two different actions during conversion take (sampling, and converting)
can be programmed within a certain range in the ST10F271Z1 relative to the CPU clock.
The absolute time that is consumed by the different conversion steps therefore is
independent from the general speed of the controller. This allows adjusting the A/D
converter of the ST10F271Z1 to the properties of the system:
Analog switch resistance 3) 8) RSW CC –
–
600
1600 WPort5
Port1
RAD CC –1300W
Table 67. A/D converter characteristics
Parameter Symbol
Limit values
Unit Test condition
min. max.
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Fast conversion can be achieved by programming the respective times to their absolute
possible minimum. This is preferable for scanning high frequency signals. The internal
resistance of analog source and analog supply must be sufficiently low, however.
High internal resistance can be achieved by programming the respective times to a higher
value, or the possible maximum. This is preferable when using analog sources and supply
with a high internal resistance in order to keep the current as low as possible. The
conversion rate in this case may be considerably lower, however.
The conversion times are programmed via the upper four bits of register ADCON. Bit fields
ADCTC and ADSTC are used to define the basic conversion time and in particular the
partition between sample phase and comparison phases. The table below lists the possible
combinations. The timings refer to the unit TCL, where fCPU = 1/2TCL. A complete
conversion time includes the conversion itself, the sample time and the time required to
transfer the digital value to the result register.
Note: The total conversion time is compatible with the formula valid for ST10F269, while the
meaning of the bit fields ADCTC and ADSTC is no longer compatible: the minimum
conversion time is 388 TCL, which at 40 MHz CPU frequency corresponds to 4.85
µ
s (see
ST10F269).
25.7.2 A/D conversion accuracy
The A/D Converter compares the analog voltage sampled on the selected analog input
channel to its analog reference voltage (VAREF) and converts it into 10-bit digital data. The
absolute accuracy of the A/D conversion is the deviation between the input analog value and
the output digital value. It includes the following errors:
●Offset error (OFS)
●Gain Error (GE)
●Quantization error
●Non-Linearity Error (differential and integral)
Table 68. A/D converter programming
ADCTC ADSTC Sample Comparison Extra Total conversion
00 00 TCL * 120 TCL * 240 TCL * 28 TCL * 388
00 01 TCL * 140 TCL * 280 TCL * 16 TCL * 436
00 10 TCL * 200 TCL * 280 TCL * 52 TCL * 532
00 11 TCL * 400 TCL * 280 TCL * 44 TCL * 724
11 00 TCL * 240 TCL * 480 TCL * 52 TCL * 772
11 01 TCL * 280 TCL * 560 TCL * 28 TCL * 868
11 10 TCL * 400 TCL * 560 TCL * 100 TCL * 1060
11 11 TCL * 800 TCL * 560 TCL * 52 TCL * 1444
10 00 TCL * 480 TCL * 960 TCL * 100 TCL * 1540
10 01 TCL * 560 TCL * 1120 TCL * 52 TCL * 1732
10 10 TCL * 800 TCL * 1120 TCL * 196 TCL * 2116
10 11 TCL * 1600 TCL * 1120 TCL * 164 TCL * 2884
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These four error quantities are explained below using Figure 42: A/D conversion
characteristic.
Offset error
Offset error is the deviation between actual and ideal A/D conversion characteristics when
the digital output value changes from the minimum (zero voltage) 00 to 01 (Figure 42, see
OFS).
Gain error
Gain error is the deviation between the actual and ideal A/D conversion characteristics when
the digital output value changes from the 3FE to the maximum 3FF, once offset error is
subtracted. Gain error combined with offset error represents the so-called full-scale error
(Figure 42, OFS + GE).
Quantization error
Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB.
Non-linearity error
Non-Linearity error is the deviation between actual and the best-fitting A/D conversion
characteristics (see Figure 42):
●Differential Non-Linearity error is the actual step dimension versus the ideal one (1
LSBIDEAL).
●Integral Non-Linearity error is the distance between the center of the actual step and
the center of the bisector line, in the actual characteristics. Note that for Integral Non-
Linearity error, the effect of offset, gain and quantization errors is not included.
Note: Bisector characteristic is obtained drawing a line from 1/2 LSB before the first step of the
real characteristic, and 1/2 LSB after the last step again of the real characteristic.
25.7.3 Total unadjusted error
The Total Unadjusted Error specifies the maximum deviation from the ideal characteristic:
the number provided in the datasheet represents the maximum error with respect to the
entire characteristic. It is a combination of the Offset, Gain and Integral Linearity errors. The
different errors may compensate each other depending on the relative sign of the offset and
gain errors. Refer to Figure 42, see TUE.
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Figure 42. A/D conversion characteristic
25.7.4 Analog reference pins
The accuracy of the A/D converter depends on how accurate is its analog reference: a noise
in the reference results in at least that much error in a conversion. A low pass filter on the
A/D converter reference source (supplied through pins VAREF and VAGND), is recommended
in order to clean the signal, minimizing the noise. A simple capacitive bypassing may be
sufficient in most of the cases; in presence of high RF noise energy, inductors or ferrite
beads may be necessary.
In this architecture, VAREF and VAGND pins represents also the power supply of the analog
circuitry of the A/D converter: there is an effective DC current requirement from the
reference voltage by the internal resistor string in the R-C DAC array and by the rest of the
analog circuitry.
An external resistance on VAREF could introduce error under certain conditions: for this
reasons, series resistance are not advisable, and more in general any series devices in the
filter network should be designed to minimize the DC resistance.
Analog input pins
To improve the accuracy of the A/D converter, it is definitively necessary that analog input
pins have low AC impedance. Placing a capacitor with good high frequency characteristics
at the input pin of the device, can be effective: the capacitor should be as large as possible,
ideally infinite. This capacitor contributes to attenuating the noise present on the input pin;
(2)
(1)
(3)
(4)
(5)
Offset Error OFS
Offset Error OFS
Gain Error GE
1 LSB (ideal)
VAIN (LSBIDEAL)
[LSBIDEAL = VAREF / 1024]
Digital
Out
(HEX)
3FF
3FE
3FD
3FC
3FB
3FA
005
004
003
002
001
000
007
006
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential Non-Linearity Error (DNL)
(4) Integral Non-Linearity Error (INL)
(5) Center of a step of the actual transfer curve
(6) Quantization Error (1/2 LSB)
(7) Total Unadjusted Error (TUE)
1357 1024102210201018
246
(6)
(7)
Bisector Characteristic
Ideal Characteristic
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besides, it sources charge during the sampling phase, when the analog signal source is a
high-impedance source.
A real filter, can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC Filter). The RC filtering may be limited according to the value of source
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth).
Figure 43. A/D converter input pins scheme
Input leakage and external circuit
The series resistor utilized to limit the current to a pin (see RL in Figure 43), in combination
with a large source impedance can lead to a degradation of A/D converter accuracy when
input leakage is present.
Data about maximum input leakage current at each pin are provided in the Data Sheet
(Electrical Characteristics section). Input leakage is greatest at high operating temperatures,
and in general it decreases by one half for each 10 ° C decrease in temperature.
Considering that, for a 10-bit A/D converter one count is about 5mV (assuming VAREF =
5 V), an input leakage of 100 nA acting though an RL = 50 kΩ of external resistance leads to
an error of exactly one count (5 mV); if the resistance were 100 kΩ the error would become
two counts.
Eventual additional leakage due to external clamping diodes must also be taken into
account in computing the total leakage affecting the A/D converter measurements. Another
contribution to the total leakage is represented by the charge sharing effects with the
sampling capacitance: being CS substantially a switched capacitance, with a frequency
equal to the conversion rate of a single channel (maximum when fixed channel continuous
conversion mode is selected), it can be seen as a resistive path to ground. For instance,
assuming a conversion rate of 250 kHz, with CS equal to 4 pF, a resistance of 1 MΩ is
obtained (REQ = 1 / fCCS, where fC represents the conversion rate at the considered
channel). To minimize the error induced by the voltage partitioning between this resistance
(sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit
must be designed to respect the following relation:
RF
CF
RSRLRSW
CP2 CS
VDD
Sampling
Source Filter Current Limiter
External circuit Internal circuit scheme
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW Channel Selection Switch Impedance
RADSampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
CP1
RAD
Channel
Selection
VA
VA
RSRFRLRSW RAD
+++ +
REQ
------------------------------------------------------------------------------
⋅1
2
---LSB<
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The formula above provides a constraints for external network design, in particular on
resistive path.
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF
, CP1 and CP2 initially charged at the source voltage VA (refer to the
equivalent circuit reported in Figure 40), when the sampling phase is started (A/D switch
close), a charge sharing phenomena is installed.
Figure 44. Charge sharing timing diagram during sampling phase
In particular two different transient periods can be distinguished (see Figure 41):
●A first and quick charge transfer from the internal capacitance CP1 and CP2 to the
sampling capacitance CS occurs (CS is supposed initially completely discharged):
considering a worst case (since the time constant in reality would be faster) in which
CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitance CP and CS
are in series, and the time constant is:
This relation can again be simplified considering only CS as an additional worst
condition. In reality, the transient is faster, but the A/D Converter circuitry has been
designed to be robust also in the very worst case: the sampling time TS is always much
longer than the internal time constant:
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the
voltage VA1 on the capacitance according to the following equation:
●A second charge transfer involves also CF (that is typically bigger than the on-chip
capacitance) through the resistance RL: again considering the worst case in which CP2
and CS were in parallel to CP1 (since the time constant in reality would be faster), the
time constant is:
In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time TS, a constraints on
VA
VA1
VA2
t
TS
VCS Voltage Transient on CS
∆V < 0.5 LSB
12
τ1 < (RSW + RAD) CS << TS
τ2 = RL (CS + CP1 + CP2)
τ1RSW RAD
+()=
CPCS
⋅
CPCS
+
-----------------------
⋅
τ1RSW RAD
+()<CSTS
<<⋅
VA1 CSCP1 CP2
++()⋅VACP1 CP2
+()⋅=
τ2RL
<CSCP1 CP2
++()⋅
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RL sizing is obtained:
Of course, RL shall be sized also according to the current limitation constraints, in
combination with RS (source impedance) and RF (filter resistance). Being CF
definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the
charge transfer transient) will be much higher than VA1. The following equation must be
respected (charge balance assuming now CS already charged at VA1):
The two transients above are not influenced by the voltage source that, due to the presence
of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on
CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with
respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing (see
Figure 45).
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the anti-aliasing filter, fF), according to Nyquist theorem the conversion rate fC must be at
least 2f0; it means that the constant time of the filter is greater than or at least equal to twice
the conversion period (TC). Again the conversion period TC is longer than the sampling time
TS, which is just a portion of it, even when fixed channel continuous conversion mode is
selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter RFCF is definitively much higher than the sampling time TS, so the
charge level on CS cannot be modified by the analog signal source during the time in which
the sampling switch is closed.
Figure 45. Anti-aliasing filter and conversion rate
The considerations above lead to impose new constraints to the external circuit, to reduce
the accuracy error due to the voltage drop on CS; from the two charge balance equations
above, it is simple to derive the following relation between the ideal and real sampled
voltage on CS:
10 τ2
⋅10 R⋅L
=CSCP1 CP2
++()TS
≤⋅
VA2CSCP1 CP2 CF
+++()⋅VACF
⋅VA1
+CP1 CP2
+C
S
+()⋅=
f0f
Analog Source Bandwidth (VA)
f0f
Sampled Signal Spectrum (fC = conversion Rate)
fC
f
Anti-Aliasing Filter (fF = RC Filter pole)
fF
2 f0 ≤ fC (Nyquist)
fF = f0 (Anti-aliasing Filtering Condition)
TC ≤ 2 RFCF (Conversion Rate vs. Filter Pole)
Noise
VA
VA2
-----------
CP1 CP2
+C
F
+
CP1 CP2
+C
FCS
++
------------------------------------------------------------=
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From this formula, in the worst case (when VA is maximum, that is for instance 5 V),
assuming to accept a maximum error of half a count (~2.44 mV), it is immediately evident a
constraints on CF value:
In the next section an example of how to design the external network is provided, assuming
some reasonable values for the internal parameters and making hypothesis on the
characteristics of the analog signal to be sampled.
Example of external network sizing
The following hypothesis are formulated in order to proceed in designing the external
network on A/D Converter input pins:
●Analog signal source bandwidth (f0): 10 kHz
●Conversion rate (fC): 25 kHz
●Sampling time (TS): 1 µs
●Pin input capacitance (CP1): 5 pF
●Pin input routing capacitance (CP2): 1 pF
●Sampling capacitance (CS): 4 pF
●Maximum input current injection (IINJ): 3 mA
●Maximum analog source voltage (VAM):12 V
●Analog source impedance (RS): 100 Ω
●Channel switch resistance (RSW): 500 Ω
●Sampling switch resistance (RAD): 200 Ω
CF2048 CS
⋅>
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1. Supposing to design the filter with the pole exactly at the maximum frequency of the
signal, the time constant of the filter is:
2. Using the relation between CF and CS and taking some margin (4000 instead of 2048),
it is possible to define CF:
3. As a consequence of step 1 and 2, RC can be chosen:
4. Considering the current injection limitation and supposing that the source can go up to
12V, the total series resistance can be defined as:
from which is now simple to define the value of RL:
5. Now the three element of the external circuit RF
, CF and RL are defined. Some
conditions discussed in the previous paragraphs have been used to size the
component, the other must now be verified. The relation which allow to minimize the
accuracy error introduced by the switched capacitance equivalent resistance is in this
case:
So the error due to the voltage partitioning between the real resistive path and CS is
less then half a count (considering the worst case when VA = 5V):
The other conditions to be verified is the time constants of the transients are really and
significantly shorter than the sampling period duration TS:
For complete set of parameters characterizing the ST10F271Z1 A/D Converter equivalent
circuit, refer to Section 25.7: A/D converter characteristics on page 141.
RCCF
1
2πf0
------------ 15.9µs==
CF4000 CS
⋅16nF==
RF
1
2πf0CF
---------------------995Ω1kΩ≅==
RSRFRL
VAM
IINJ
------------- 4 k Ω==++
RL
VAM
IINJ
------------- R FRS2.9kΩ=––=
REQ
1
fCCS
---------------10MΩ==
VA
RSRFRLRSW RAD
+++ +
REQ
---------------------------------------------------------------------------2.35mV=⋅1
2
---LSB<
τ1RSW RAD
+()=CS2.8ns=⋅<< TS = 1µs
10 τ2
⋅10 R⋅L
=CSCP1 CP2
++()290ns=⋅< TS = 1µs
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25.8 AC characteristics
25.8.1 Test waveforms
Figure 46. Input / output waveforms
Figure 47. Float waveforms
25.8.2 Definition of internal timing
The internal operation of the ST10F271Z1 is controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (for example pipeline) or external (for example
bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock, called “TCL”.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate fCPU.
This influence must be regarded when calculating the timings for the ST10F271Z1.
The example for PLL operation shown in Figure 48 refers to a PLL factor of 4.
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).
2.4V
0.4V
Test Points
2.0V 2.0V
0.8V 0.8V
AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’.
Timing measurements are made at VIH min. for a logic ‘1’ and VIL max for a logic ‘0’.
Timing
Reference
Points
VLOAD + 0.1V
VLOAD - 0.1V
VOH - 0.1V
VOL + 0.1V
VLOAD
VOL
VOH
For timing purposes a port pin is no longer floating when VLOAD changes of ±100 mV.
It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA).
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Figure 48. Generation mechanisms for the CPU clock
25.8.3 Clock generation modes
Next Ta b l e 6 9 associates the combinations of these three bits with the respective clock
generation mode.
1. The external clock input range refers to a CPU clock range of 1...64 MHz. Besides, the PLL usage is limited
to 4-8 MHz. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the
internal oscillator amplifier (apart from Direct Drive): vice versa, the clock can be forced through an external
clock source only in Direct Drive mode (on-chip oscillator amplifier disabled, so no crystal or resonator can
be used).
2. The maximum depends on the duty cycle of the external clock signal: when 64 MHz is used, 50% duty
cycle shall be granted (low phase = high phase = 7.8 ns); when 32 MHz is selected a 25% duty cycle can
be accepted (minimum phase, high or low, again equal to 7.8 ns).
3. The limits on input frequency are 4-8 MHz since the usage of the internal oscillator amplifier is required.
Also when the PLL is not used and the CPU clock corresponds to FXTAL/2, an external crystal or resonator
shall be used: it is not possible to force any clock though an external clock source.
TCLTCL
TCLTCL
fCPU
fXTAL
fCPU
fXTAL
Phase Locked Loop operation
Direct clock drive
TCL TCL
fCPU
fXTAL
Prescaler operation
Table 69. On-chip clock generator selections
P0.15-13
(P0H.7-5)
CPU frequency
fCPU = fXTAL x F
External clock
input range 1) 3) Notes
111 F
XTAL x 4 4 to 8MHz Default configuration
110 F
XTAL x 3 5.3 to 8MHz See Ta bl e 7 0
101 F
XTAL x 8 4 to 8MHz
100 F
XTAL x 5 6.4 to 8MHz
011 F
XTAL x 1 1 to 64MHz Direct drive (oscillator bypassed)
2)
010 F
XTAL x 10 4 to 6.4MHz
001 F
XTAL / 2 4 to 8MHz CPU clock via prescaler 3)
000 F
XTAL x 16 4MHz
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25.8.4 Prescaler operation
When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the
internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock fXTAL.
The timings listed in the AC Characteristics that refer to TCL therefore can be calculated
using the period of fXTAL for any TCL.
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set,
then the PLL is switched off.
25.8.5 Direct drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is
disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by
the input clock signal on XTAL1 pin.
The frequency of CPU clock (fCPU) directly follows the frequency of fXTAL so the high and
low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the
input clock fXTAL.
Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value
can be calculated by the following formula:
For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated,
so the duration of 2TCL is always 1/fXTAL.
The minimum value TCLmin has to be used only once for timings that require an odd number
of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:
The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of
TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLmin.
Similarly to what happen for Prescaler Operation, if the bit OWDDIS in SYSCON register is
cleared, the PLL runs on its free-running frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
25.8.6 Oscillator watchdog (OWD)
An on-chip watchdog oscillator is implemented in the ST10F271Z1. This feature is used for
safety operation with external crystal oscillator (available only when using direct drive mode
with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the
frequency of the external crystal oscillator). This watchdog oscillator operates as following.
The reset default configuration enables the watchdog oscillator. It can be disabled by setting
the OWDDIS (bit 4) of SYSCON register.
When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the
watchdog counter. On each transition of external clock, the watchdog counter is cleared. If
TCLmin 1f⁄XTALlxlDCmin
=
DC duty cycle=
2TCL 1 fXTAL
⁄=
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an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock
cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator
watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external
clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or
bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct
clock input.
When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct
Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply
current.
25.8.7 Phase Locked Loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see Ta b l e 6 9 ). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (fCPU =
fXTAL x F). With every F’th transition of fXTAL the PLL circuit synchronizes the CPU clock to
the input clock. This synchronization is done smoothly, so the CPU clock frequency does not
change abruptly.
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is
locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of
individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to
keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to
one TCL period.
This is especially important for bus cycles using wait states and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower Baud rates, etc.) the deviation caused by the PLL jitter is
negligible. Refer to next Section 25.8.9: PLL Jitter for more details.
25.8.8 Voltage Controlled Oscillator
The ST10F271Z1 implements a PLL which combines different levels of frequency dividers
with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. In the following
table, a detailed summary of the internal settings and VCO frequency is reported.
Table 70. Internal PLL divider mechanism
P0.15-13
(P0H.7-5) XTAL frequency Input
prescaler
PLL Output
prescaler
CPU frequency
fCPU = fXTAL x F
Multiply by Divide by
111 4 to 8 MHz F
XTAL / 4 64 4 – FXTAL x 4
1 1 0 5.3 to 8 MHz 1) FXTAL / 4 48 4 – FXTAL x 3
101 4 to 8 MHz F
XTAL / 4 64 2 – FXTAL x 8
1 0 0 6.4 to 8 MHz 1) FXTAL / 4 40 2 – FXTAL x 5
0 1 1 1 to 64 MHz – PLL bypassed – FXTAL x 1
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The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is
64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 64 MHz.
Example 1
●fXTAL = 10 MHz
●P0(15:13) = ‘110’ (multiplication by 3)
●PLL input frequency = 2.5 MHz
●VCO frequency = 120 MHz
●PLL output frequency = 30 MHz
(VCO frequency divided by 4)
●fCPU = 30 MHz (no effect of output prescaler)
Example 2
●fXTAL = 8 MHz
●P0(15:13) = ‘100’ (multiplication by 5)
●PLL input frequency = 2 MHz
●VCO frequency = 80 MHz
●PLL output frequency = 40 MHz (VCO frequency divided by 2)
●fCPU = 40 MHz (no effect of Output Prescaler)
25.8.9 PLL Jitter
The following terminology is hereafter defined:
●Self referred single period jitter
Also called “period jitter”, it can be defined as the difference of the Tmax and Tmin,
where Tmax is maximum time period of the PLL output clock and Tmin is the minimum
time period of the PLL output clock.
●Self referred long term jitter
Also called “N period jitter”, it can be defined as the difference of Tmax and Tmin, where
Tmax is the maximum time difference between N+1 clock rising edges and Tmin is the
minimum time difference between N+1 clock rising edges. Here N should be kept
sufficiently large to have the long term jitter. For N=1, this becomes the single period
jitter.
Jitter at the PLL output can be due to the following reasons:
●Jitter in the input clock
●Noise in the PLL loop.
0 1 0 4 to 6.4MHz FXTAL / 2 40 2 – FXTAL x 10
001 4 to 8MHz 1) – PLL bypassed FPLL / 2 FXTAL / 2
000 4MHz F
XTAL / 2 64 2 – FXTAL x 16
Table 70. Internal PLL divider mechanism (continued)
P0.15-13
(P0H.7-5) XTAL frequency Input
prescaler
PLL Output
prescaler
CPU frequency
fCPU = fXTAL x F
Multiply by Divide by
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Jitter in the input clock
PLL acts like a low pass filter for any jitter in the input clock. Input clock jitter with the
frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency
jitter (frequency > PLL bandwidth) is attenuated @20 dB/decade.
Noise in the PLL loop
This contribution again can be caused by the following sources:
●Device noise of the circuit in the PLL
●Noise in supply and substrate.
Device noise of the circuit in the PLL
The long term jitter is inversely proportional to the bandwidth of the PLL: the wider is the
loop bandwidth, the lower is the jitter due to noise in the loop. Besides, the long term jitter is
practically independent on the multiplication factor.
The most noise sensitive circuit in the PLL circuit is definitively the VCO (Voltage Controlled
Oscillator). There are two main sources of noise: thermal (random noise, frequency
independent so practically white noise) and flicker (low frequency noise, 1/f). For the
frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a 1/f2
region in the output noise spectrum, while the flicker noise in a 1/f3. Assuming a noiseless
PLL input and supposing that the VCO is dominated by its 1/f2 noise, the R.M.S. value of the
accumulated jitter is proportional to the square root of N, where N is the number of clock
periods within the considered time interval.
On the contrary, assuming again a noiseless PLL input and supposing that the VCO is
dominated by its 1/f3 noise, the R.M.S. value of the accumulated jitter is proportional to N,
where N is the number of clock periods within the considered time interval.
The jitter in the PLL loop can be modelized as dominated by the i1/f2 noise for N smaller
than a certain value depending on the PLL output frequency and on the bandwidth
characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f3 noise
component. Lastly, for N greater than a second value of N, a saturation effect is evident, so
the jitter does not grow anymore when considering a longer time interval (jitter stable
increasing the number of clock periods N). The PLL loop acts as a high pass filter for any
noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation
value corresponds to what has been called self referred long term jitter of the PLL. In
Figure 49 the maximum jitter trend versus the number of clock periods N (for some typical
CPU frequencies) is reported: the curves represent the very worst case, computed taking
into account all corners of temperature, power supply and process variations: the real jitter
is always measured well below the given worst case values.
Noise in supply and substrate
Digital supply noise adds deterministic components to the PLL output jitter, independent on
multiplication factor. Its effects is strongly reduced thanks to particular care used in the
physical implementation and integration of the PLL module inside the device. Anyhow, the
contribution of the digital noise to the global jitter is widely taken into account in the curves
provided in Figure 49.
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Figure 49. ST10F271Z1 PLL jitter
25.8.10 PLL lock / unlock
During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the
CPU is generated, and the reference clock (oscillator) is automatically disconnected from
the PLL input: in this way, the PLL goes into free-running mode, providing the system with a
backup clock signal (free running frequency Ffree). This feature allows to recover from a
crystal failure occurrence without risking to go in an undefined configuration: the system is
provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe
mode.
The path between reference clock and PLL input can be restored only by a hardware reset,
or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.
Note: The external RC circuit on RSTIN pin shall be properly sized in order to extend the duration
of the low pulse to grant the PLL gets locked before the level at RSTIN pin is recognized
high: bidirectional reset internally drives RSTIN pin low for just 1024 TCL (definitively not
sufficient to get the PLL locked starting from free-running mode).
Jitter [ns]
N (CPU clock periods)
200
400
±5
±1
800600 1000 1200 1400
0
0
64MHz
±2
±3
±4
24MHz 40MHz32MHz16MHz
TJIT
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1. Not 100% tested, guaranteed by design characterization.
25.8.11 Main oscillator specifications
VDD = 5 V ± 10%, VSS = 0 V, TA = –40 to +125 °C
1. Not 100% tested, guaranteed by design characterization.
Figure 50. Crystal oscillator and resonator connection diagram
Table 71. PLL characteristics (VDD = 5 V ± 10%, VSS = 0 V, TA = –40 to +125 °C)
Symbol Parameter Conditions
Value
Unit
min. max.
TPSUP PLL Start-up time 1) Stable VDD and reference clock – 300 µs
TLOCK PLL Lock-in time Stable VDD and reference clock,
starting from free-running mode – 250 µs
TJIT
Single Period Jitter 1)
(cycle to cycle = 2 TCL)
6 sigma time period variation
(peak to peak) –500 +500 ps
Ffree PLL free running frequency Multiplication Factors: 3, 4
Multiplication Factors: 5, 8, 10, 16
250
500
2000
4000 kHz
Table 72. Main oscillator characteristics
Symbol Parameter Conditions
Value
Unit
min. typ. max.
gm
Oscillator
transconductance 1.4 2.6 4.2 mA/V
VOSC Oscillation amplitude 1) Peak to peak – 1.5 – V
VAV Oscillation voltage level 1) Sine wave middle – 0.8 – V
tSTUP Oscillator start-up time 1) Stable VDD - Crystal – 6 10 ms
Stable VDD - Resonator–12ms
CA
CA
crystal
XTAL1
XTAL2
Resonator
XTAL1
XTAL2
ST10F271Z1 ST10F271Z1
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The given values of CA do not include the stray capacitance of the package and of the
printed circuit board: the negative resistance values are calculated assuming additional 5pF
to the values in the table. The crystal shunt capacitance (C0) and the package capacitance
between XTAL1 and XTAL2 pins is globally assumed equal to 10 pF.
The external resistance between XTAL1 and XTAL2 is not necessary, since already present
on the silicon.
25.8.12 32 kHz oscillator specifications
VDD = 5 V ± 10%, VSS = 0 V, TA = –40 to +125 °C
1. At power-on a high current biasing is applied for faster oscillation start-up. Once the oscillation is started,
the current biasing is reduced to lower the power consumption of the system.
2. Not 100% tested, guaranteed by design characterization.
Figure 51. 32 kHz crystal oscillator connection diagram
Table 73. Main oscillator negative resistance (module)
CA = 15 pF CA = 25 pF CA = 35 pF
min. typ. max. min. typ. max. min. typ. max.
4 MHz 545 Ω1035 Ω– 550 Ω1050 Ω– 430 Ω850 Ω–
8 MHz 240 Ω450 Ω– 170 Ω350 Ω– 120 Ω250 Ω–
Table 74. 32kHz oscillator characteristics
Symbol Parameter Conditions
Value
Unit
min. typ. max.
gm32 Oscillator transconductance 1) Start-up 20 31 50 µA/V
Normal run 8 17 30 µA/V
VOSC32 Oscillation amplitude 2) Peak to peak 0.5 1.0 2.4 V
VAV32 Oscillation voltage level 2) Sine wave middle 0.7 0.9 1.2 V
tSTUP32 Oscillator start-up time 2) Stable VDD –15s
CA
CA
crystal
XTAL3
XTAL4
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The given values of CA do not include the stray capacitance of the package and of the
printed circuit board: the negative resistance values are calculated assuming additional 5pF
to the values in the table. The crystal shunt capacitance (C0) and the package capacitance
between XTAL3 and XTAL4 pins is globally assumed equal to 4 pF. The external resistance
between XTAL3 and XTAL4 is not necessary, since already present on the silicon.
Warning: Direct driving on XTAL3 pin is not supported. Always use a
32 kHz crystal oscillator.
25.8.13 External clock drive XTAL1
When Direct Drive configuration is selected during reset, it is possible to drive the CPU clock
directly from the XTAL1 pin, without particular restrictions on the maximum frequency, since
the on-chip oscillator amplifier is bypassed. The speed limit is imposed by internal logic that
targets a maximum CPU frequency of 64 MHz.
In all other clock configurations (Direct Drive with Prescaler or PLL usage) the on-chip
oscillator amplifier is not bypassed, so it determines the input clock speed limit. Then, when
the on-chip oscillator is enabled it is forbidden to use any external clock source different
from crystal or ceramic resonator.
1. The minimum value for the XTAL1 signal period shall be considered as the theoretical minimum. The real
minimum value depends on the duty cycle of the input clock signal.
2. 4-8 MHz is the input frequency range when using an external clock source. 64 MHz can be applied with an
external clock source only when Direct Drive mode is selected: in this case, the oscillator amplifier is
bypassed so it does not limit the input frequency.
3. The input clock signal must reach the defined levels VIL2 and VIH2.
Table 75. Minimum values of negative resistance (module) for 32 kHz oscillator
CA = 6 pF CA = 12 pF CA = 15 pF CA = 18 pF CA = 22 pF CA = 27 pF CA = 33 pF
32 kHz ----150 kΩ120 kΩ90 kW
Table 76. External clock drive
Parameter Symbol
Direct drive
fCPU = fXTAL
Direct drive with
prescaler
fCPU = fXTAL / 2
PLL usage
fCPU = fXTAL x F Unit
min. max. min. max. min. max.
XTAL1 period 1, 2 tOSC SR 15.625 – 83.3 250 83.3 250 ns
High time 3 t1SR 6 –3–6–ns
Low time 3 t2SR 6–3–6–ns
Rise time 3 t3SR –2–2–2ns
Fall time 3 t4SR –2–2–2ns
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Figure 52. External clock drive XTAL1
Note: When Direct Drive is selected, an external clock source can be used to drive XTAL1. The
maximum frequency of the external clock source depends on the duty cycle: when 64MHz is
used, 50% duty cycle shall be granted (low phase = high phase = 7.8 ns); when for instance
32 MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again
equal to 7.8ns).
25.8.14 Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.
25.8.15 External memory bus timing
The following sections include the External Memory Bus timings. The given values are
computed for a maximum CPU clock of 40MHz.
Obviously, when higher CPU clock frequency is used (up to 64MHz), some numbers in the
timing formulas become zero or negative which, in most cases is not acceptable or not
meaningless at all. In these cases, it is necessary to relax the speed of the bus setting
properly tA, tC and tF
.
Note: All External Memory Bus Timings and SSC Timings reported in the following tables are
granted by Design Characterization and not fully tested in production.
25.8.16 Multiplexed bus
VDD = 5 V ± 10%, VSS = 0V, TA = –40 to +125 °C, CL = 50 pF,
ALE cycle time = 6 TCL + 2tA + tC + tF (75 ns at 40 MHz CPU clock without wait states)
t1 t3 t4
VIL2
t2
tOSC
VIH2
Table 77. Memory cycle variables
Description Symbol Values
ALE extension tATCL x [ALECTL]
Memory cycle time wait states tC2TCL x (15 - [MCTC])
Memory tri-state time tF2TCL x (1 - [MTTC])
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Table 78. Multiplexed bus timings
Symbol Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU clock
1/2 TCL = 1 to 64MHz
Unit
min. max. min. max.
t5CC ALE high time 4 + tA– TCL – 8.5 + tA–ns
t6CC Address setup to ALE 1.5 + tA– TCL – 11 + tA–ns
t7CC Address hold after ALE 4 + tA– TCL – 8.5 + tA–ns
t8CC ALE falling edge to RD, WR
(with RW-delay) 4 + tA– TCL – 8.5 + tA–ns
t9CC ALE falling edge to RD, WR
(no RW-delay) – 8.5 + tA– – 8.5 + tA–ns
t10 CC Address float after RD, WR
(with RW-delay)1–6 – 6ns
t11 CC Address float after RD, WR
(no RW-delay)1– 18.5 – TCL + 6 ns
t12 CC RD, WR low time
(with RW-delay) 15.5 + tC– 2TCL – 9.5 + tC–ns
t13 CC RD, WR low time
(no RW-delay) 28 + tC– 3TCL – 9.5 + tC–ns
t14 SR RD to valid data in
(with RW-delay) –6 + t
C– 2TCL – 19 + tCns
t15 SR RD to valid data in
(no RW-delay) –18.5 + t
C– 3TCL – 19 + tCns
t16 SR ALE low to valid data in – 17.5 +
+ tA + tC
–3TCL – 20 +
+ tA + tC
ns
t17 SR Address/Unlatched CS to valid
data in –20 + 2tA +
+ tC
–4TCL – 30 +
+ 2tA + tC
ns
t18 SR Data hold after RD
rising edge 0– 0 –ns
t19 SR Data float after RD1– 16.5 + tF– 2TCL – 8.5 + tFns
t22 CC Data valid to WR 10 + tC– 2TCL – 15 + tC–ns
t23 CC Data hold after WR 4 + tF– 2TCL – 8.5 + tF–ns
t25 CC ALE rising edge after RD, WR 15 + tF– 2TCL – 10 + tF–ns
t27 CC Address/Unlatched CS hold
after RD, WR 10 + tF– 2TCL – 15 + tF–ns
t38 CC ALE falling edge to Latched CS – 4 – tA10 – tA– 4 – tA10 – tAns
t39 SR Latched CS low to Valid Data
In –16.5 + tC +
+ 2tA
–3TCL – 21 +
+ tC + 2tA
ns
t40 CC Latched CS hold after RD, WR 27 + tF– 3TCL – 10.5 + tF–ns
t42 CC ALE fall. edge to RdCS, WrCS
(with RW delay) 7 + tA– TCL – 5.5 + tA–ns
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t43 CC ALE fall. edge to RdCS, WrCS
(no RW delay) – 5.5 + tA– – 5.5 + tA–ns
t44 CC Address float after RdCS,
WrCS (with RW delay)1– 1.5 – 1.5 ns
t45 CC Address float after RdCS,
WrCS (no RW delay)1– 14 – TCL + 1.5 ns
t46 SR RdCS to Valid Data In
(with RW delay) –4 + t
C– 2TCL – 21 + tCns
t47 SR RdCS to Valid Data In
(no RW delay) –16.5 + t
C– 3TCL – 21 + tCns
t48 CC RdCS, WrCS Low Time
(with RW delay) 15.5 + tC– 2TCL – 9.5 + tC–ns
t49 CC RdCS, WrCS Low Time
(no RW delay) 28 + tC– 3TCL – 9.5 + tC–ns
t50 CC Data valid to WrCS 10 + tC– 2TCL – 15 + tC–ns
t51 SR Data hold after RdCS 0– 0 –ns
t52 SR Data float after RdCS1– 16.5 + tF– 2TCL – 8.5 + tFns
t54 CC Address hold after
RdCS, WrCS 6 + tF– 2TCL – 19 + tF–ns
t56 CC Data hold after WrCS 6 + tF– 2TCL – 19 + tF–ns
Table 78. Multiplexed bus timings (continued)
Symbol Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU clock
1/2 TCL = 1 to 64MHz
Unit
min. max. min. max.
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Figure 53. External memory cycle: multiplexed bus, with/without read/write delay, normal ALE
Data in
Data out
Address
Address
t38
t10
Read cycle
Write cycle
t5t16
t39
t40
t25
t27
t1
t14
t22
t23
t12
t8
t8
t6
t19
Address
t17
t6
t7
t9t1
t13
t15
t16
t12
t13
Address
t9
t17
t6
t27
ALE
CSx
A23-A16
(A15-A8)
Address/data
RD
WR
WRL
BHE
WRH
bus (P0)
Address/data
bus (P0)
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Figure 54. External memory cycle: multiplexed bus, with/without read/write delay, extended ALE
Data out
Address
Data in
Address
Address
t5t16
t6t7
t39
t40
t14
t8
t18
t23
t6
t27
t38
t10 t19
t25
t17
t9t11
t15
t12
t13
t8t10
t9t11
t12
t13
t22
t27
t17
t6
Read cycle
Write cycle
ALE
CSx
A23-A16
(A15-A8)
RD
WR
WRL
BHE
WRH
Address/data
bus (P0)
Address/Data
Bus (P0)
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Figure 55. External memory cycle: multiplexed bus, with/without r/w delay, normal ALE, r/w CS
Read cycle
Write cycle
CLKOUT
ALE
A23-A16
(A15-A8)
BHE
Data In
Data Out
Address
Address
Address
Address
RdCSx
WrCSx
Address/data
Bus (P0)
Address/data
bus (P0)
t25
t16
t5
t6t17 t27
t51
t16
t7
t6
t42 t44 t52
t46
t48
t49
t43 t45
t47 t55
t42 t50
t48
t49
t43
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Figure 56. External memory cycle: multiplexed bus, with/without r/w delay, extended ALE,
r/w CS
Data out
Address
Data in
Address
Address
t5t16
t6t7
t46
t42
t42
t50
t18
t56
t6
t54
t44
t19
t25
t17
t43 t45
t47
t48
t49
t49
t43
t48
t44
t45
Read cycle
Write cycle
CLKOUT
ALE
A23-A16
(A15-A8)
BHE
RdCSx
WrCSx
Address/data
bus (P0)
Address/data
bus (P0)
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25.8.17 Demultiplexed bus
VDD = 5 V ± 10%, VSS = 0V, TA = –40 to +125 °C, CL = 50 pF,
ALE cycle time = 4 TCL + 2tA + tC + tF (50 ns at 40 MHz CPU clock without wait states).
Table 79. Demultiplexed bus timings
Symbol Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU clock
1/2 TCL = 1 to 64 MHz
Unit
min. max. min. max.
t5CC ALE high time 4 + tA– TCL – 8.5 + tA–ns
t6CC Address setup to ALE 1.5 + tA– TCL – 11 + tA–ns
t80 CC
Address/Unlatched CS setup
to RD, WR
(with RW-delay)
12.5 + 2tA–2TCL – 12.5 +
+ 2tA
–ns
t81 CC
Address/Unlatched CS setup
to RD, WR
(no RW-delay)
0.5 + 2tA– TCL – 12 + 2tA–ns
t12 CC RD, WR low time
(with RW-delay) 15.5 + tC– 2TCL – 9.5 + tC–ns
t13 CC RD, WR low time
(no RW-delay) 28 + tC– 3TCL – 9.5 + tC–ns
t14 SR RD to valid data in
(with RW-delay) –6 + t
C– 2TCL – 19 + tCns
t15 SR RD to valid data in
(no RW-delay) –18.5 + t
C– 3TCL – 19 + tCns
t16 SR ALE low to valid data in – 17.5 + tA +
+ tC
–3TCL – 20 +
+ tA + tC
ns
t17 SR Address/Unlatched CS to
valid data in –20 + 2tA +
+ tC
–4TCL – 30 +
+ 2tA + tC
ns
t18 SR Data hold after RD
rising edge 0– 0 –ns
t20 SR Data float after RD rising
edge (with RW-delay)31 – 16.5 + tF–2TCL – 8.5 +
+ tF + 2tA
ns
t21 SR Data float after RD rising
edge (no RW-delay) 1 –4 + t
F–TCL – 8.5 +
+ tF + 2tA
ns
t22 CC Data valid to WR 10 + tC– 2TCL – 15 + tC–ns
t24 CC Data hold after WR 4 + tF– TCL – 8.5 + tF–ns
t26 CC ALE rising edge after RD,
WR –10 + tF––10 + t
F–ns
t28 CC Address/unlatched CS hold
after RD, WR 20 + tF–0 + t
F–ns
t28h CC Address/unlatched CS hold
after WRH – 5 + tF–– 5 + t
F–ns
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1. RW-delay and tA refer to the next following bus cycle.
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
t38 CC ALE falling edge to latched
CS – 4 – tA6 – tA– 4 – tA6 – tAns
t39 SR Latched CS low to valid data
In –16.5 +
+ tC + 2tA
–3TCL – 21 +
+ tC + 2tA
ns
t41 CC Latched CS hold after RD,
WR 2 + tF– TCL – 10.5 + tF–ns
t82 CC
Address setup to RdCS,
WrCS
(with RW-delay)
14 + 2tA– 2TCL – 11 + 2tA–ns
t83 CC
Address setup to RdCS,
WrCS
(no RW-delay)
2 + 2tA– TCL –10.5 + 2tA–ns
t46 SR RdCS to valid data in
(with RW-delay) –4 + t
C– 2TCL – 21 + tCns
t47 SR RdCS to valid data in
(no RW-delay) –16.5 + t
C– 3TCL – 21 + tCns
t48 CC RdCS, WrCS low time
(with RW-delay) 15.5 + tC– 2TCL – 9.5 + tC–ns
t49 CC RdCS, WrCS low time
(no RW-delay) 28 + tC– 3TCL – 9.5 + tC–ns
t50 CC Data valid to WrCS 10 + tC– 2TCL – 15 + tC–ns
t51 SR Data hold after RdCS 0– 0 –ns
t53 SR Data float after RdCS
(with RW-delay) 3– 16.5 + tF– 2TCL – 8.5 + tFns
t68 SR Data float after RdCS
(no RW-delay) 3–4 + t
F– TCL – 8.5 + tFns
t55 CC Address hold after
RdCS, WrCS – 8.5 + tF– – 8.5 + tF–ns
t57 CC Data hold after WrCS 2 + tF– TCL – 10.5 + tF–ns
Table 79. Demultiplexed bus timings (continued)
Symbol Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU clock
1/2 TCL = 1 to 64 MHz
Unit
min. max. min. max.
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Figure 57. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE
Write cycle
CLKOUT
ALE
A23-A16
A15-A0 (P1)
BHE
WR
WRL
WRH
Data in
Data out
t38
t5t9
t39
t41
t18
t14
t22
t12
Address
t17
t13
t15
t12
t13
t21
t20
t81
t80
t26
t24
t17
t6
t41u
t6
t80
t81
t28 (or t28h)
CSx
Read cycle
Data bus (P0)
RD
(D15-D8) D7-D0
Data bus (P0)
(D15-D8) D7-D0
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Figure 58. Exteral memory cycle: demultiplexed bus, with/without r/w delay, extended ALE
t5
Read cycle
Write cycle
CLKOUT
ALE
CSx
RD
WR
WRL
WRH
Data bus (P0)
(D15-D8) D7-D0
Data bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
t26
t16
t17
t39
t41
t28
t38
t6
t6t17 t28
Address
t18
Data in
t20
t14
t80
t81 t15 t21
t13
t12
Data out
t80
t81 t22 t24
t12
t13
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Figure 59. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE,
r/w CS
Read cycle
Write cycle
CLKOUT
ALE
Data in
Data out
t5t16
t5
t46
t50
t48
Address
t17
t49
t47
t48
t49
t68
t53
t83
t82
t26
t57
t55
t6
t82
t83
RdCSx
WrCSx
Data bus (P0)
(D15-D8) D7-D0
Data bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
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Figure 60. External memory cycle: demultiplexed bus, without r/w delay, extended ALE, r/w CS
Address
t5t16
t46
t57
t6
t53
t26
t17
t47
t48
t49
t48
t49
t50
Data in
t51
t68
t55
Data out
t82
t83
t82
t83
Read cycle
Write cycle
CLKOUT
ALE
RdCSx
WrCSx
Data bus (P0)
(D15-D8) D7-D0
Data bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
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25.8.18 CLKOUT and READY
VDD = 5 V ± 10%, VSS = 0 V, TA = -40 to + 125 °C, CL = 50 pF
1. These timings are given for characterization purposes only, in order to assure recognition at a specific
clock edge.
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values.
This adds even more time for deactivating READY. 2tA and tC refer to the next following bus cycle, tF refers
to the current bus cycle.
Table 80. CLKOUT and READY timings
Symbol Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU clock
1/2 TCL = 1 to 64 MHz
Unit
min. max. min. max.
t29 CC CLKOUT cycle time 25 25 2TCL 2TCL ns
t30 CC CLKOUT high time 9 – TCL – 3.5 – ns
t31 CC CLKOUT low time 10 – TCL – 2.5 – ns
t32 CC CLKOUT rise time – 4 – 4 ns
t33 CC CLKOUT fall time – 4 – 4 ns
t34 CC CLKOUT rising edge to
ALE falling edge – 2 + tA8 + tA– 2 + tA8 + tAns
t35 SR Synchronous READY
setup time to CLKOUT 17 – 17 – ns
t36 SR Synchronous READY
hold time after CLKOUT 2– 2 –ns
t37 SR Asynchronous READY
low time 35 – 2TCL + 10 – ns
t58 SR Asynchronous READY
setup time 117 – 17 – ns
t59 SR Asynchronous READY
hold time 12– 2 –ns
t60 SR
Async. READY hold time after
RD, WR high (Demultiplexed
Bus) 2
02t
A + tC + tF02t
A + tC + tF ns
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Figure 61. CLKOUT and READY
1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
LOW at this sampling point terminates the currently running bus cycle.
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is
guaranteed, if READY is removed in response to the command (see Note 4).
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state
may be inserted here.
For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus
without MTTC wait state this delay is zero.
7. The next external bus cycle may start here.
t30
t34
t35 t36 t35 t36
t58 t59 t58 t59
wait state
READY MUX / Tri-state 6)
t32 t33
t29
Running cycle 1)
t31
t37
3) 3)
5)
t60 4)
6)
2)
7)
3) 3)
CLKOUT
ALE
RD, WR
Synchronous
Asynchronous
READY
READY
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25.8.19 External bus arbitration
VDD = 5 V ± 10 %, VSS = 0 V, TA = -40 to +125 °C, CL = 50 pF
1. Partially tested, guaranteed by design characterization.
Figure 62. External bus arbitration (releasing the bus)
1. The ST10F271Z1 will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t64.
Table 81. External bus arbitration timings
Symbol Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU clock
1/2 TCL = 1 to 64 MHz
Unit
min. max. min. max.
t61 SR HOLD input setup time
to CLKOUT 18.5–18.5–ns
t62 CC CLKOUT to HLDA high
or BREQ low delay – 12.5 – 12.5 ns
t63 CC CLKOUT to HLDA low
or BREQ high delay – 12.5 – 12.5 ns
t64 CC CSx release 1) –20–20ns
t65 CC CSx drive – 415– 415ns
t66 CC Other signals release 1) –20–20ns
t67 CC Other signals drive – 4 15 – 4 15 ns
t61
t63
t66
1)
t64
1)
2)
t62
3)
CLKOUT
HOLD
HLDA
BREQ
Others
CSx
(P6.x)
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Figure 63. External bus arbitration (regaining the bus)
1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated
earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be
deactivated without the ST10F271Z1 requesting the bus.
2. The next ST10F271Z1 driven bus cycle may start here.
CLKOUT
HOLD
HLDA
Other
signals
t62
CSx
(On P6.x)
t67
t62
1)
2)
t65
t61
BREQ
t63
t62
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25.8.20 High-speed synchronous serial interface (SSC) timing
Master mode
VDD = 5 V ±10%, VSS = 0 V, TA = -40 to +125 °C, CL = 50 pF
Table 82. SSC master mode timings
Symbol Parameter
Max. baudrate 6.6 MBd
(1)@fCPU = 40 MHz
(<SSCBR> = 0002h)
Variable baudrate
(<SSCBR> = 0001h -
FFFFh) Unit
min. max. min. max.
t300 CC SSC clock cycle time(2)) 150 150 8TCL 262144 TCL ns
t301 CC SSC clock high time 63 – t300 / 2 – 12 – ns
t302 CC SSC clock low time 63 – t300 / 2 – 12 – ns
t303 CC SSC clock rise time – 10 – 10 ns
t304 CC SSC clock fall time – 10 – 10 ns
t305 CC Write data valid after shift edge – 15 – 15 ns
t306 CC Write data hold after shift edge(3) – 2 – – 2 – ns
t307p SR
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
37.5 – 2TCL + 12.5 – ns
t308p SR
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
50 – 4TCL – ns
t307 SR
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
25 – 2TCL – ns
t308 SR
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
0–0–ns
1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to ‘3h’, or with
48 MHz CPU clock and <SSCBR> set to ‘2h’. When 40 MHz CPU clock is used the maximum baudrate cannot be higher
than 6.6 Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> can be used only
with CPU clock equal to (or lower than) 32 MHz.
2. Formula for SSC clock cycle time: t300 = 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC
Baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t300 is 125 ns (corresponding to 8Mbaud).
3. Partially tested, guaranteed by design characterization.
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Figure 64. SSC master timing
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
Slave mode
VDD = 5V ±10%, VSS = 0 V, TA = -40 to +125 °C, CL = 50 pF
1st out bit Last out bit2nd out bit
1) 2)
2nd In bit
1st in bit Last in bit
SCLK
MTSR
MRST
t308
t307
t308
t307
t305 t305
t300 t301 t302
t304 t303
t306 t305
Table 83. SSC slave mode timings
Symbol Parameter
Max. baudrate
6.6 MBd (1))
@FCPU = 40 MHz
(<SSCBR> = 0002h)
Variable baudrate
(<SSCBR> = 0001h -
FFFFh) Unit
min. max. min. max.
t310 SR SSC clock cycle time(2) 150 150 8TCL 262144 TCL ns
t311 SR SSC clock high time 63 – t310 / 2 – 12 – ns
t312 SR SSC clock low time 63 – t310 / 2 – 12 – ns
t313 SR SSC clock rise time – 10 – 10 ns
t314 SR SSC clock fall time – 10 – 10 ns
t315 CC Write data valid after shift edge – 55 – 2TCL + 30 ns
t316 CC Write data hold after shift edge 0 – 0 – ns
t317p SR
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
62 – 4TCL + 12 – ns
t318p SR
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
87 – 6TCL + 12 – ns
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Figure 65. SSC slave timing
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
t317 SR
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
6– 6 –ns
t318 SR
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
31 – 2TCL + 6 – ns
1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to ‘3h’, or with
48 MHz CPU clock and <SSCBR> set to ‘2h’. When 40 MHz CPU clock is used the maximum baudrate cannot be higher
than 6.6 Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only
with CPU clock lower than 32 MHz (after checking that resulting timings are suitable for the master).
2. Formula for SSC clock cycle time: t310 = 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t310 is 125 ns (corresponding to 8Mbaud).
Table 83. SSC slave mode timings (continued)
Symbol Parameter
Max. baudrate
6.6 MBd (1))
@FCPU = 40 MHz
(<SSCBR> = 0002h)
Variable baudrate
(<SSCBR> = 0001h -
FFFFh) Unit
min. max. min. max.
1st out bit Last out bit2nd out bit
1) 2)
2nd in bit1st in bit Last in bit
SCLK
MRST
MTSR
t313
t314
t315
t316
t315
t317 t318
t317 t318
t315
t310 t311 t312
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26 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package information ST10F271Z1
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Figure 66. PQFP144 - 144-pin plastic quad flatpack 28 x 28 mm, 0.65 mm pitch,
package outline
Table 84. PQFP144 - 144-pin plastic quad flatpack 28 x 28 mm, 0.65 mm pitch,
package mechanical data
Symbol
mm inches(1)
1. Values in inches are converted from mm and rounded up to 4 decimal places.
Typ Min Max Typ Min Max
A 4.070 0.1602
A1 0.250 0.0098
A2 3.420 3.170 3.670 0.1346 0.1248 0.1445
b 0.220 0.380 0.0087 0.0150
C 0.130 0.230 0.0051 0.0091
D 31.200 30.950 31.450 1.2283 1.2185 1.2382
D1 28.000 27.900 28.100 1.1024 1.0984 1.1063
D3 22.750 0.8957
e 0.650 0.0256
E 31.200 30.950 31.450 1.2283 1.2185 1.2382
E1 28.000 27.900 28.100 1.1024 1.0984 1.1063
E3 22.750 0.8957
L 0.800 0.650 0.950 0.0315 0.0256 0.0374
L1 1.600 0.0630
K 0°7° 0°7°
ddd 0.101 0.0040
A
A2
A1
B
C
36
37
72
73
108
109
144
E3
D3
E1
E
D1
D
e
1
K
b
L
L1
7G_ME
ddd
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Figure 67. LQFP144 - 144 pin low profile quad flat package 20x20 mm, 0.5 mm pitch,
package outline
Table 85. LQFP144 - 144 pin low profile quad flat package 20x20mm, 0.5 mm pitch,
package mechanical data
Dim.
mm inches(1)
1. Values in inches are converted from mm and rounded up to 4 decimal places.
Min Typ Max Min Typ Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.057
b 0.17 0.22 0.27 0.007 0.011
c 0.09 0.20 0.004 0.008
D 21.80 22.00 22.20 0.858 0.867 0.874
D1 19.80 20.00 20.20 0.780 0.787 0.795
D3 17.50 0.689
E 21.80 22.00 22.20 0.858 0.867 0.874
E1 19.80 20.00 20.20 0.780 0.787 0.795
E3 17.50 0.689
e 0.50 0.020
K 0°3.5°7° 0°3.5°7°
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
A
A2
A1
b
c
36
37
72
73108
109
144
E1 E
D1
D
1
h
b
L
L1
Seating Plane
0.08 mm
.003 in.
e
E3
D3
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Revision history ST10F271Z1
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27 Revision history
Table 86. Document revision history
Date Revision Changes
30-Jun-2006 1Initial release.
18-Jan-2008 2
ST10F271 replaced by ST10F271Z1
Added Section 24: Known limitations on page 123
Modified example 1 in Section 25.8.8: Voltage Controlled Oscillator
on page 154
Section 26: Package information on page 181: added information on
ECOPACK specifications and modified figures and tables
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