ST10F271Z1 16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM Features 16-bit CPU with DSP functions - 31.25 ns instruction cycle time at 64MHz max CPU clock - Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator - Enhanced boolean bit manipulations - Single-cycle context switching support ) s ( ct u d o PQFP144 (28 x 28 x 3.4mm) LQFP144 (20 x 20 x 1.4mm) (Plastic Quad Flat Package) (Low Profile Quad Flat Package) On-chip memories - 128 Kbyte Flash memory (32-bit fetch) - Single voltage Flash memories with erase/program controller and 100K erasing/programming cycles. - Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I2C) - 2 Kbyte internal RAM (IRAM) - 10 Kbyte extension RAM (XRAM) - Programmable external bus configuration & characteristics for different address ranges - Five programmable chip-select signals - Hold-acknowledge bus arbitration support s ( t c u d o Pr Interrupt - 8-channel peripheral event controller for single cycle interrupt driven data transfer - 16-priority-level interrupt system with 56 sources, sampling rate down to 15.6ns e t e ol t e l o Serial channels - Two synch. / asynch. serial channels - Two high-speed synchronous channels - One I2C standard interface s b O )- r P e - 24-channel 10-bit - 3 s minimum conversion time s b O 2 CAN 2.0B interfaces operating on 1 or 2 CAN busses (64 or 2x32 message, C-CAN version) Fail-safe protection - Programmable watchdog timer - Oscillator watchdog On-chip bootstrap loader Clock generation - On-chip PLL with 4 to 8 MHz oscillator - Direct or prescaled clock input Real-time clock and 32 kHz on-chip oscillator Up to 111 general purpose I/O lines - Individually programmable as input, output or special function - Programmable threshold (hysteresis) Timers - Two multi-functional general purpose timer units with 5 timers Two 16-channel capture / compare units 4-channel PWM unit + 4-channel XPWM Idle, power-down and stand-by modes A/D converter Single voltage supply: 5V 10% Order Codes Order code Package Max CPU frequency Flash RAM Temperature range (C) (MHz) ST10F271Z1Q3 PQFP144 64 128 KB 12 KB -40/+125 ST10F271Z1T3 LQFP144 40 128 KB 12 KB -40/+125 January 2008 Rev 2 1/185 www.st.com 1 Contents ST10F271Z1 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ) s ( ct Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 r P e 5.2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.2 Module structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 t e l o s b O 5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4.2 Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4.3 Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 s b O 5.5 t c u od Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pr 5.4.6 Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4.7 Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4.8 Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4.9 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.10 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.11 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4.5 e t e ol ) (s 5.4.1 5.4.4 2/185 u d o 5.1 Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5.1 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5.2 Flash non-volatile write protection I register . . . . . . . . . . . . . . . . . . . . . 35 5.5.3 Flash non-volatile access protection register 0 . . . . . . . . . . . . . . . . . . . 35 5.5.4 Flash non-volatile access protection register 1 low . . . . . . . . . . . . . . . . 36 5.5.5 Flash non-volatile access protection register 1 high . . . . . . . . . . . . . . . 36 ST10F271Z1 6 Contents 5.5.6 XBus Flash volatile temporary access unprotection register (XFVTAUR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.5.7 Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.5.8 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.5.9 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 ) s ( ct 6.1 Selection among user-code, standard or selective bootstrap . . . . . . . . . . 43 6.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3 Alternate and selective boot mode (ABM and SBM) . . . . . . . . . . . . . . . . 44 u d o 6.3.1 Activation of the ABM and SBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.2 User mode signature integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.3 Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 r P e t e l o Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 s b O 7.1 Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.3 MAC co-processor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ) (s t c u 8 External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 d o r P e let o s b 9.1 X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2 Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10 Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11 General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 O 11.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12 PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3/185 Contents ST10F271Z1 13.2 13.3 I/O's special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.2.1 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.2.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 15 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 15.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 67 15.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 15.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 15.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 69 ) s ( ct u d o r P e 16 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 17 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 t e l o s b O 17.1 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 17.2 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ) (s 18 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 19 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 20 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 t c u d o r P e let o s b O 21 20.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 20.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 20.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 21.1 4/185 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ST10F271Z1 Contents 21.2 21.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 21.2.1 Protected power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 21.2.2 Interruptible power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 21.3.1 Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 21.3.2 Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 21.3.3 Real-time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 21.3.4 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 ) s ( ct 22 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 107 23 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 24 u d o 23.1 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 23.2 XBus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 23.3 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 23.4 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 r P e t e l o ) (s 24.1 Injected conversion stalling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 24.2 Concurrent transmission requests in DAR-mode (C-CAN module) . . . . 127 24.3 Transmission request disabled (C-CAN module) . . . . . . . . . . . . . . . . . . 128 24.4 Spurious BREQ pulse in slave mode during external bus arbitration phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 t c u d o r P e 24.5 Flash wake-up from idle mode 24.6 Executing PWRDN instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 24.7 Flash wake-up from power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . 131 24.8 Behavior of CAPCOM outputs in compare mode 3 . . . . . . . . . . . . . . . . 131 t e l o s b O 25 s b O Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 25.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 25.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 25.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 25.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 25.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 25.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5/185 Contents ST10F271Z1 25.7 25.8 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 25.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 25.7.2 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 25.7.3 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 25.7.4 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 25.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 25.8.2 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 25.8.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 25.8.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 25.8.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 25.8.6 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 25.8.7 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 25.8.8 Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 25.8.9 PLL Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 ) s ( ct u d o r P e t e l o 25.8.10 PLL lock / unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 s b O 25.8.11 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 25.8.12 32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 ) (s 25.8.13 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 25.8.14 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 t c u 25.8.15 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 25.8.16 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 d o r 25.8.17 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 P e 25.8.18 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 let o s b 25.8.19 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 25.8.20 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 178 26 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 O 6/185 ST10F271Z1 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Summary of IFlash address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Address space reserved to the Flash module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Flash module sectorization (read operations). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Flash modules sectorization (write operations or with ROMS1='1' or bootstrap mode). . . . . . . . . . . . . . . . . . . . . . . . . . 25 Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash non-volatile write protection I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash non-volatile access protection register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Flash non-volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Flash non-volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 XBus Flash volatile temporary access unprotection register . . . . . . . . . . . . . . . . . . . . . . . 37 Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ST10F271Z1 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 57 CAPCOM timer input frequencies, resolutions and periods at 64 MHz . . . . . . . . . . . . . . . 57 GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 58 GPT1 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 59 GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 60 GPT2 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 60 PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 61 PWM unit frequencies and resolutions at 64 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 61 ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . 67 ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . 68 ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . . 68 ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . . 69 SSC synchronous baud rate and reload values (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . 70 SSC synchronous baud rate and reload values (fCPU = 64 MHz) . . . . . . . . . . . . . . . . . . . 70 WDTREL reload value (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 WDTREL reload value (fCPU = 64 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e s b O t e l o 7/185 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 62. Table 63. Table 64. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 79. Table 81. Table 82. Table 84. Table 85. Table 86. ST10F271Z1 Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 100 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 List of special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 List of XBus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 List of Flash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 IDMANUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 IDCHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 IDMEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 IDPROG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 List of limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 A/D converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 PLL characteristics (VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C). . . . . . . . . . . . . 158 Main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Main oscillator negative resistance (module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 32kHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Minimum values of negative resistance (module) for 32 kHz oscillator . . . . . . . . . . . . . . 160 External clock drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 PQFP144 - 144-pin plastic quad flatpack 28 x 28 mm, 0.65 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 LQFP144 - 144 pin low profile quad flat package 20x20mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 ) s ( ct u d o r P e t e l o ) (s t c u P e d o r t e l o s b O 8/185 s b O ST10F271Z1 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ST10F271Z1 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - reset value) . . . 23 Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CPU block diagram (MAC unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . . 73 Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . . 73 Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . . 74 Connection to one CAN bus with internal parallel mode enabled. . . . . . . . . . . . . . . . . . . . 74 Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Asynchronous hardware reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Asynchronous hardware reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Synchronous short / long hardware reset (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Synchronous long hardware reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Synchronous long hardware reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SW / WDT unidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SW / WDT unidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SW / WDT bidirectional RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SW / WDT bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SW / WDT bidirectional reset (EA=0) followed by a HW RESET . . . . . . . . . . . . . . . . . . . . 94 Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . . 97 Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . . 98 PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 101 External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 ADC injection theoretical operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ADC injection actual operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 ST10 in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Supply current versus the operating frequency (run and idle modes) . . . . . . . . . . . . . . . 139 A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Input / output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e s b O t e l o 9/185 List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. ST10F271Z1 ST10F271Z1 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 External memory cycle: multiplexed bus, with/without read/write delay, normal ALE. . . . 164 External memory cycle: multiplexed bus, with/without read/write delay, extended ALE. . 165 External memory cycle: multiplexed bus, with/without r/w delay, normal ALE, r/w CS. . . 166 External memory cycle: multiplexed bus, with/without r/w delay, extended ALE, r/w CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 170 Exteral memory cycle: demultiplexed bus, with/without r/w delay, extended ALE . . . . . . 171 External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE, r/w CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 External memory cycle: demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 173 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 PQFP144 - 144-pin plastic quad flatpack 28 x 28 mm, 0.65 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 LQFP144 - 144 pin low profile quad flat package 20x20 mm, 0.5 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 10/185 s b O ST10F271Z1 1 Introduction Introduction The ST10F271Z1 device is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. The ST10F271Z1 combines high CPU performance (up to 32 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides onchip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL. The ST10F271Z1 is processed in 0.18 m CMOS technology. The MCU core and the logic is supplied with a 5V to 1.8 V on-chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5 V. ) s ( ct The ST10F271Z1 devices are based on the ST10F272 silicon, and 100% compatible, with the difference that only a reduced portion of the on-chip Flash and RAM memories are usable. The available memories will be detailled in the Chapter 4: Memory organization. u d o Figure 1. r P e Logic symbol t e l o s b O V18 VDD VSS XTAL1 XTAL2 XTAL3 XTAL4 ) (s od b O so let r P e Port 1 16-bit t c u RSTIN RSTOUT VAREF VAGND NMI EA / VSTBY READY ALE RD WR / WRL Port 5 16-bit Port 0 16-bit Port 2 16-bit Port 3 15-bit ST10F271Z1 Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit RPD 11/185 Pin data 2 ST10F271Z1 Pin data Pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 t e l o ) (s d o r P e t e l o s b O 12/185 VAREF VAGND P5.10 / AN10 / T6EUD P5.11 / AN11 / T5EUD P5.12 / AN12 / T6IN P5.13 / AN13 / T5IN P5.14 / AN14 / T4EUD P5.15 / AN15 / T2EUD VSS VDD P2.0 / CC0IO P2.1 / CC1IO P2.2 / CC2IO P2.3 / CC3IO P2.4 / CC4IO P2.5 / CC5IO P2.6 / CC6IO P2.7 / CC7IO VSS V18 P2.8 / CC8IO / EX0IN P2.9 / CC9IO / EX1IN P2.10 / CC10IO / EX2IN P2.11 / CC11IO / EX3IN P2.12 / CC12IO / EX4IN P2.13 / CC13IO / EX5IN P2.14 / CC14IO / EX6IN P2.15 / CC15IO / EX7IN / T7IN P3.0 / T0IN P3.1 / T6OUT P3.2 / CAPIN P3.3 / T3OUT P3.4 / T3EUD P3.5 / T4IN VSS VDD t c u P0H.0 / AD8 P0L.7 / AD7 P0L.6 / AD6 P0L.5 / AD5 P0L.4 / AD4 P0L.3 / AD3 P0L.2 / AD2 P0L.1 / AD1 P0L.0 / AD0 EA / VSTBY ALE READY WR/WRL RD VSS VDD P4.7 / A23 / CAN2_TxD / SDA P4.6 / A22 / CAN1_TxD / CAN2_TxD P4.5 / A21 / CAN1_RxD / CAN2_RxD P4.4 / A20 / CAN2_RxD / SCL P4.3 / A19 P4.2 / A18 P4.1 / A17 P4.0 / A16 RPD VSS VDD P3.15 / CLKOUT P3.13 / SCLK0 P3.12 / BHE / WRH P3.11 / RxD0 P3.10 / TxD0 P3.9 / MTSR0 P3.8 / MRST0 P3.7 / T2IN P3.6 / T3IN ) s ( ct u d o r P e ST10F271Z1 s b O 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 P6.0 / CS0 P6.1 / CS1 P6.2 / CS2 P6.3 / CS3 P6.4 / CS4 P6.5 / HOLD / SCLK1 P6.6 / HLDA / MTSR1 P6.7 / BREQ / MRST1 P8.0 / XPOUT0 / CC16IO P8.1 / XPOUT1 / CC17IO P8.2 / XPOUT2 / CC18IO P8.3 / XPOUT3 / CC19IO P8.4 / CC20IO P8.5 / CC21IO P8.6 / RxD1 / CC22IO P8.7 / TxD1 / CC23IO VDD VSS P7.0 / POUT0 P7.1 / POUT1 P7.2 / POUT2 P7.3 / POUT3 P7.4 / CC28IO P7.5 / CC29IO P7.6 / CC30IO P7.7 / CC31IO P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 XTAL4 XTAL3 NMI RSTOUT RSTIN VSS XTAL1 XTAL2 VDD P1H.7 / A15 / CC27I P1H.6 / A14 / CC26I P1H.5 / A13 / CC25I P1H.4 / A12 / CC24I P1H.3 / A11 P1H.2 / A10 P1H.1 / A9 P1H.0 / A8 VSS VDD P1L.7 / A7 / AN23 P1L.6 / A6 / AN22 P1L.5 / A5 / AN21 P1L.4 / A4 / AN20 P1L.3 / A3 / AN19 P1L.2 / A2 / AN18 P1L.1 / A1 / AN17 P1L.0 / A0 / AN16 P0H.7 / AD15 P0H.6 / AD14 P0H.5 / AD13 P0H.4 / AD12 P0H.3 / AD11 P0H.2 / AD10 P0H.1 / AD9 VSS VDD Figure 2. ST10F271Z1 Table 1. Pin data Pin description Symbol Pin 1-8 Type P6.0 - P6.7 Function I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The following Port 6 pins have alternate functions: 1 O P6.0 CS0 Chip select 0 output ... ... ... ... ... 5 O P6.4 CS4 Chip select 4 output I P6.5 HOLD External master hold request input SCLK1 SSC1: master clock output / slave clock input HLDA Hold acknowledge output MTSR1 SSC1: master-transmitter / slave-receiver O/I BREQ Bus request output MRST1 SSC1: master-receiver / slave-transmitter I/O ) s ( ct 6 I/O O P6.6 7 I/O O P6.7 r P e 8 I/O 9-16 I/O I/O P8.0 ct s b O CAPCOM2: CC16 capture input / compare output XPWM0 PWM1: channel 0 output ... ... CC19IO CAPCOM2: CC19 capture input / compare output XPWM0 PWM1: channel 3 output ... ... ro P8.3 12 13 I/O P8.4 CC20IO CAPCOM2: CC20 capture input / compare output 14 I/O P8.5 CC21IO CAPCOM2: CC21 capture input / compare output I/O P8.6 CC22IO CAPCOM2: CC22 capture input / compare output RxD1 ASC1: Data input (Asynchronous) or I/O (Synchronous) CC23IO CAPCOM2: CC23 capture input / compare output TxD1 ASC1: Clock / Data output (Asynchronous/Synchronous) I/O bs du P e ... ) (s CC16IO O t e l o t e l o 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 8 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS). The following Port 8 pins have alternate functions: 9 P8.0 - P8.7 u d o O 15 I/O O I/O P8.7 16 O 13/185 Pin data Table 1. ST10F271Z1 Pin description (continued) Symbol P7.0 - P7.7 P5.0 - P5.9 P5.10 - P5.15 Pin Type Function 19-26 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS). The following Port 7 pins have alternate functions: 19 O P7.0 POUT0 PWM0: channel 0 output ... ... ... ... ... 22 O P7.3 POUT3 PWM0: channel 3 output 23 I/O P7.4 CC28IO CAPCOM2: CC28 capture input / compare output ... ... ... ... ... 26 I/O P7.7 CC31IO CAPCOM2: CC31 capture input / compare output 27-36 39-44 I I 39 I P5.10 T6EUD 40 I P5.11 T5EUD 41 I P5.12 T6IN 42 I P5.13 T5IN 43 I P5.14 44 I P5.15 od s b O GPT2: timer T5 external up/down control input )- GPT2: timer T5 count input T4EUD GPT1: timer T4 external up/down control input T2EUD GPT1: timer T2 external up/down control input I/O 47 I/O P2.0 CC0IO CAPCOM: CC0 capture input/compare output ... ... ... ... ... 54 I/O P2.7 CC7IO CAPCOM: CC7 capture input/compare output I/O P2.8 CC8IO CAPCOM: CC8 capture input/compare output EX0IN Fast external interrupt 0 input Pr 57 I ... 64 14/185 t e l o GPT2: timer T6 external up/down control input GPT2: timer T6 count input t(s uc r P e 16-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS). The following Port 2 pins have alternate functions: e t e ol P2.0 - P2.7 P2.8 - P2.15 u d o 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be the analog input channels (up to 16) for the A/D converter, where P5.x equals ANx (Analog input channel x), or they are timer inputs. The input threshold of Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate functions: 47-54 57-64 s b O ) s ( ct ... ... ... ... I/O P2.15 CC15IO CAPCOM: CC15 capture input/compare output I EX7IN Fast external interrupt 7 input I T7IN CAPCOM2: timer T7 count input ST10F271Z1 Table 1. Pin data Pin description (continued) Symbol P3.0 - P3.5 P3.6 - P3.13, P3.15 Pin Type Function 65-70, 73-80, 81 I/O I/O I/O 15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 3 outputs can be configured as pushpull or open drain drivers. The input threshold of Port 3 is selectable (TTL or CMOS). The following Port 3 pins have alternate functions: 65 I P3.0 T0IN CAPCOM1: timer T0 count input 66 O P3.1 T6OUT GPT2: timer T6 toggle latch output 67 I P3.2 CAPIN GPT2: register CAPREL capture input 68 O P3.3 T3OUT GPT1: timer T3 toggle latch output 69 I P3.4 T3EUD GPT1: timer T3 external up/down control input 70 I P3.5 T4IN GPT1; timer T4 input for count/gate/reload/capture 73 I P3.6 T3IN GPT1: timer T3 count/gate input 74 I P3.7 T2IN GPT1: timer T2 input for count/gate/reload / capture 75 I/O P3.8 MRST0 SSC0: master-receiver/slave-transmitter I/O 76 I/O P3.9 MTSR0 SSC0: master-transmitter/slave-receiver O/I 77 O P3.10 TxD0 ASC0: clock / data output (asynchronous/synchronous) 78 I/O P3.11 RxD0 79 O P3.12 BHE ) (s WRH t c u ) s ( ct u d o r P e t e l o s b O ASC0: data input (asynchronous) or I/O (synchronous) External memory high byte enable signal External memory high byte write strobe 80 I/O P3.13 SCLK0 SSC0: master clock output / slave clock input 81 O P3.15 CLKOUT System clock output (programmable divider on CPU clock) d o r P e t e l o s b O 15/185 Pin data Table 1. Symbol ST10F271Z1 Pin description (continued) Pin Type Function 85-92 I/O Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold is selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured as push-pull or open drain drivers. In case of an external bus configuration, Port 4 can be used to output the segment address lines: 85 O P4.0 A16 Segment address line 86 O P4.1 A17 Segment address line 87 O P4.2 A18 Segment address line 88 O P4.3 A19 Segment address line A20 Segment address line CAN2_RxD CAN2: receive data input I/O SCL I2C Interface: serial clock O A21 Segment address line CAN1_RxD CAN1: receive data input O P4.0 -P4.7 89 90 91 I I P4.4 P4.5 I CAN2_RxD O A22 O P4.6 92 o r P I/O RD 95 e t e ol WR/WRL s b O 96 du O P4.7 )- r P e t e l o s b O CAN2: receive data input CAN1: transmit data output CAN2_TxD CAN2: transmit data output A23 Most significant segment address line s ( t c O u d o Segment address line CAN1_TxD O ) s ( ct CAN2_TxD CAN2: transmit data output SDA I2C Interface: serial data O External memory read strobe. RD is activated for every external instruction or data read access. O External memory write strobe. In WR-mode this pin is activated for every external data write access. In WRL mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection. READY/ READY 97 I Ready input. The active level is programmable. When the ready function is enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of waitstate cycles until the pin returns to the selected active level. ALE 98 O Address latch enable output. In case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines. 16/185 ST10F271Z1 Table 1. Pin data Pin description (continued) Symbol EA / VSTBY Pin Type Function I External access enable pin. A low level applied to this pin during and after Reset forces the ST10F271Z1 to start the program from the external memory space. A high level forces ST10F271Z1 to start in the internal memory space. This pin is also used (when Stand-by mode is entered, that is ST10F271Z1 under reset and main VDD turned off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8 V supply for the RTC module (when not disabled) and to retain data inside the Stand-by portion of the XRAM (16 Kbyte). It can range from 4.5 to 5.5 V (6 V for a reduced amount of time during the device life, 4.0 V when RTC and 32 kHz on-chip oscillator amplifier are turned off). In running mode, this pin can be tied low during reset without affecting 32 kHz oscillator, RTC and XRAM activities, since the presence of a stable VDD guarantees the proper biasing of all those modules. 99 ) s ( ct u d o Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold of Port 0 is selectable (TTL or CMOS). In case of an external bus configuration, PORT0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes r P e P0L.0 -P0L.7, 100-107, P0H.0 108, P0H.1 111-117 P0H.7 t e l o I/O s b O Data path width 8-bit 16-bi P0L.0 - P0L.7: D0 - D7 D0 - D7 I/O D8 - D15 )- s ( t c P0H.0 - P0H.7: Multiplexed bus modes u d o e t e ol s b O Pr Data path width 8-bit 16-bi P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15 Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes: if at least BUSCONx is configured such the demultiplexed mode is selected, the pis of PORT1 are not available for general purpose I/O function. The input threshold of Port 1 is selectable (TTL or CMOS). The pins of P1L also serve as the additional (up to 8) analog input channels for the A/D converter, where P1L.x equals ANy (Analog input channel y, where y = x + 16). This additional function have higher priority on demultiplexed bus function. The following PORT1 pins have alternate functions: 118-125 128-135 I/O 132 I P1H.4 CC24IO CAPCOM2: CC24 capture input 133 I P1H.5 CC25IO CAPCOM2: CC25 capture input 134 I P1H.6 CC26IO CAPCOM2: CC26 capture input 135 I P1H.7 CC27IO CAPCOM2: CC27 capture input P1L.0 - P1L.7 P1H.0 P1H.7 17/185 Pin data Table 1. ST10F271Z1 Pin description (continued) Symbol Pin Type Function XTAL1 138 I XTAL1 Main oscillator amplifier circuit and/or external clock input. XTAL2 137 O XTAL2 Main oscillator amplifier circuit output. To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high / low and rise / fall times specified in the AC Characteristics must be observed. XTAL3 143 I XTAL3 32 kHz oscillator amplifier circuit input XTAL4 144 O XTAL4 32 kHz oscillator amplifier circuit output When 32 kHz oscillator amplifier is not used, to avoid spurious consumption, XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32 in RTCCON register shall be set. 32 kHz oscillator can only be driven by an external crystal, and not by a different clock source. ) s ( ct 140 RSTIN RSTOUT 141 NMI 142 VAREF 37 u d o I Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F271Z1. An internal pull-up resistor permits power-on reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence. O Internal Reset Indication Output. This pin is driven to a low level during hardware, software or watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = `0' in SYSCON register, when the PWRDN (power-down) instruction is executed, the NMI pin must be low in order to force the ST10F271Z1 to go into power-down mode. If NMI is high and PWDCFG ='0', when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. r P e t e l o ) (s s b O t c u d o r - A/D converter reference voltage and analog supply - A/D converter reference and analog ground 84 - Timing pin for the return from interruptible power-down mode and synchronous / asynchronous reset selection. VDD 17, 46, 72,82,93 , 109, 126, 136 - Digital supply voltage = + 5 V during normal operation, idle and power-down modes. It can be turned off when Stand-by RAM mode is selected. VSS 18,45, 55,71, 83,94, 110, 127, 139 - Digital ground V18 56 - 1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF) must be connected between this pin and nearest VSS pin. VAGND P e t e l o RPD s b O 18/185 38 ST10F271Z1 3 Functional description Functional description The architecture of the ST10F271Z1 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F271Z1. Figure 3. Block diagram 16 32 IFlash 128K ) s ( ct 16 Watchdog u d o PEC 16 16 XPWM 16 16 16 16 s b O t e l o Port 6 8 Port 5 16 SSC0 10-bit ADC External Bus Controller t c u ASC0 ) (s b O GPT1 / GPT2 Port 0 Port 4 P e 8 XCAN2 d o r Port 1 16 32kHz Oscillator PLL so XSSC XCAN1 Pr BRG BRG Port 3 15 5V-1.8V Voltage Regulator CAPCOM2 16 XI2C 16 e t e l Interrupt Controller XASC PWM 16 XRTC 4-8 MHz Oscillator Port 7 Port 8 8 8 Port 2 16 16 XRAM 8K (STBY) IRAM 2K CAPCOM1 XRAM 2K (PEC) 16 CPU-Core and MAC Unit 16 19/185 Memory organization 4 ST10F271Z1 Memory organization The memory space of the ST10F271Z1 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 Mbytes. The entire memory space can be accessed Byte wise or Word wise. Particular portions of the on-chip memory have additionally been made directly bit addressable. IFlash: 128 Kbytes of on-chip Flash memory. It is divided in 6 blocks (B0F0...B0F5) that constitute the Bank 0. When Bootstrap mode is selected, the Test-Flash Block B0TF (8 Kbyte) appears at address 00'0000h: refer to Chapter 5: Internal Flash memory on page 24 for more details on memory mapping in boot mode. The summary of address range for IFlash is the following: Table 2. ) s ( ct Summary of IFlash address range u d o Blocks User mode B0TF Not visible B0F0 00'0000h - 00'1FFFh B0F1 00'2000h - 00'3FFFh B0F2 00'4000h - 00'5FFFh B0F3 00'6000h - 00'7FFFh 8K B0F4 01'8000h - 01'FFFFh 32K 02'0000h - 02'FFFFh 64K 03'0000h - 03'FFFFh / RESERVED 64K 04'0000h - 04'FFFFh / RESERVED 64K e t e l so B0F5 (1) )- s ( t c Reserved (1) Reserved Size u d o b O Pr 8K 8K 8K 8K (1) This area must be reserved by the application mapping. r P e IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data, system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0 to R15) and / or Bytewide (RL0, RH0, ..., RL7, RH7) general purpose registers group. t e l o s b O XRAM: 8K+2 Kbytes of on-chip extension RAM (single port XRAM) is provided as a storage for data, user stack and code. The XRAM is divided into 2 areas, the first 2 Kbytes named XRAM1 and the second 8 Kbytes named XRAM2, connected to the internal XBUS and are accessed like an external memory in 16-bit demultiplexed bus-mode without wait state or read/write delay (31.25ns access at 64MHz CPU clock). Byte and Word accesses are allowed. The XRAM1 address range is 00'E000h - 00'E7FFh if XPEN (bit 2 of SYSCON register), and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then any access in the address range 00'E000h - 00'E7FFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. The XRAM2 address range is the one selected programming XADRS3 register, if XPEN (bit 2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is cleared, then any access in the address range programmed for XRAM2 will be directed to 20/185 ST10F271Z1 Memory organization external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. After reset the XRAM2 is mapped from address 09'0000h. XRAM2 represents also the Stand-by RAM, which can be maintained biased through EA / VSTBY pin when main supply VDD is turned off. As the XRAM appears like external memory, it cannot be used as system stack or as register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable. ST10F271 XRAM: 8 K + 2 Kbytes of XRAM The XRAM1 (2 Kbytes) address range is 00'E000h - 00'E7FFh if enabled. ) s ( ct The XRAM2 (8 Kbytes) address range is after reset 09'0000h - 09'1FFFh and is mirrored every 16 Kbyte boundary. u d o SFR/ESFR: 1024 Bytes (2 x 512 Bytes) of address space is reserved for the special function register areas. SFRs are Wordwide registers which are used to control and to monitor the function of the different on-chip units. r P e CAN1: Address range 00'EF00h - 00'EFFFh is reserved for the CAN1 Module access. The CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit 0 of the XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 62.5ns at 64MHz CPU clock. No tri-state wait states are used. t e l o s b O CAN2: Address range 00'EE00h - 00'EEFFh is reserved for the CAN2 Module access. The CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit 1 of the new XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 62.5ns at 64MHz CPU clock. No tri-state wait states are used. ) (s t c u d o r Note: If one or the two CAN modules are used, Port 4 cannot be programmed to output all 8 segment address lines. Thus, only 4 segment address lines can be used, reducing the external memory space to 5 Mbytes (1 Mbyte per CS line). P e s b O t e l o RTC: Address range 00'ED00h - 00'EDFFh is reserved for the RTC Module access. The RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz CPU clock. No tristate waitstate is used. PWM1: Address range 00'EC00h - 00'ECFFh is reserved for the PWM1 Module access. The PWM1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the XPERCON register. Accesses to the PWM1 Module use demultiplexed addresses and a 16bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz CPU clock. No tristate waitstate is used. Only word access is allowed. ASC1: Address range 00'E900h - 00'E9FFh is reserved for the ASC1 Module access. The ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON register. Accesses to the ASC1 Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64 MHz CPU clock. No tristate waitstate is used. 21/185 Memory organization ST10F271Z1 SSC1: Address range 00'E800h - 00'E8FFh is reserved for the SSC1 Module access. The SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON register. Accesses to the SSC1 Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64 MHz CPU clock. No tristate waitstate is used. I2C: Address range 00'EA00h - 00'EAFFh is reserved for the I2C Module access. The I2C is enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register. Accesses to the I2C Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64 MHz CPU clock. No tristate waitstate is used. X-Miscellaneous: Address range 00'EB00h - 00'EBFFh is reserved for the access to a set of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON register and bit 10 of the XPERCON register. Accesses to this additional features use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64 MHz CPU clock. No tristate waitstate is used. The following set of features are provided: ) s ( ct u d o CLKOUT programmable divider XBUS interrupt management registers ADC multiplexing on P1L register Port1L digital disable register for extra ADC channels CAN2 multiplexing on P4.5/P4.6 CAN1-2 main clock prescaler Main Voltage Regulator disable for power-down mode TTL / CMOS threshold selection for Port0, Port1, and Port5. ) (s r P e t e l o s b O In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 Mbytes of external memory can be connected to the microcontroller. t c u d o r Visibility of XBUS peripherals In order to keep the ST10F271Z1 compatible with the ST10F168 / ST10F269, the XBUS peripherals can be selected to be visible on the external address / data bus. Different bits for X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the global enabling with XPEN bit in SYSCON register, the corresponding address space, port pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and not available. Refer to Chapter 23: Register set on page 108. P e t e l o s b O 22/185 ST10F271Z1 ST10F271Z1 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - reset value) Code Segment Data Page FF FFFF 1023 255 Data Page Code Segment 11 FFFF 17 67 Ext. Memory Ext. Memory 0F 0000 0E FFFF 14 0E 0000 0D FFFF 13 0D 0000 0C FFFF 12 0C 0000 0B FFFF 11 0B 0000 0A FFFF 10 0A 0000 09 FFFF 9 09 0000 08 FFFF XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 50 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 43 62 59 56 53 51 49 48 47 46 45 44 16 MB 00 E800 00 E7FF Reserved 1K ESFR 512 XCAN1 XCAN2 XRTC XPWM XMiscellaneous XI2C XASC 256 256 256 256 256 256 256 256 IRAM 2K XSSC Reserved 00 F200 00 F1FF 00 F000 00 EFFF 40 39 e t e ol XRAM1 38 37 36 00 E000 00 DFFF 34 30 28 ) (s 27 Reserved 26 25 24 23 t c u Reserved 22 21 20 2K 1K Pr u d o ESFR 41 ) s ( ct 00 F600 00 F5FF 42 29 512 s b O 19 od Reserved Reserved 18 Ext. Memory 17 8K 16 15 14 13 12 03 0000 02 FFFF 11 Flash 10 9 8 Flash 7 6 1 Ext. Memory 01 0000 00 FFFF 00 0000 00 F000 00 EFFF 52 31 Pr 0 00 F200 00 F1FF 54 32 4 00 0000 2K 55 05 0000 04 FFFF 0 512 57 Reserved 5 IRAM 00 F600 00 F5FF 58 06 0000 05 FFFF 0 SFR 60 33 6 b O 01 0000 00 FFFF 61 07 0000 06 FFFF so 512 00 FE00 00 FDFF 35 7 02 0000 01 FFFF SFR 65 63 Reserved 8 e t e l 00 FE00 00 FDFF 66 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 XRAM2 08 0000 07 FFFF 2 00 FFFF 64 15 3 65 67 10 0000 0F FFFF 04 0000 03 FFFF 66 64 11 0000 10 FFFF 16 RAM / SFR (4 Kbyte) XADRS3 = 800Bh (512K) Figure 4. Memory organization Address Area, where XRAM2 is mirrored every 16 Kbytes boundary after reset 5 4 3 Ext. Memory Flash 2 1 0 Flash + XRAM - 1 Mbyte Bit-addressable Memory 00 C000 Data Page 3 (Segment 0) - 16 Kbyte * The first 32K of Flash may be remapped from segment 0 to segment 1 by setting SYSCON-ROMS1 (before EINIT). Absolute Memory Address are hexadecimal values, while Data Page Number are decimal values. 23/185 Internal Flash memory ST10F271Z1 5 Internal Flash memory 5.1 Overview The on-chip Flash is composed by one matrix module, 128 Kbytes wide. This module is on ST10 Internal bus, so it is called IFlash Figure 5. Flash structure IFlash Control Section Flash Control Registers HV and Ref. Generator Bank 0: 128 Kbyte Program Memory + 8 Kbyte Test-Flash Program/Erase Controller ) s ( ct u d o r P e I-BUS Interface t e l o s b O The programming operations of the Flash are managed by an embedded Flash Program/Erase Controller (FPEC). The High Voltages needed for Program/Erase operations are internally generated. ) (s t c u The Data bus is 32-bit wide for fetch accesses to IFlash, while it is 16 bit wide for read accesses to IFlash. Read/write accesses to IFlash Control Registers area are 16 bit wide. d o r 5.2 Functional description P e t e l o 5.2.1 Structure The following table shows the Address space reserved to the Flash module. s b O Table 3. Address space reserved to the Flash module Description IFlash sectors IFlash reserved sector Reserved IBUS area 1) 2) Registers and Flash internal reserved area Note: 24/185 1 Addresses Size 0x00 0000 to 0x02 FFFF 128 Kbytes 0x03 0000 to 0x04 FFFF 128 Kbytes 0x05 0000 to 0x07 FFFF 192 Kbytes 0x08 0000 to 0x08 FFFF 64 Kbytes The ST10F271Z1 being based on the same silicon as the ST10F272, 256 Kbyte of Flash are implemented on the device. The range 03'0000h - 04'FFFFh is not physically disabled even if not available for use. Therefore this address range MUST be reserved by the ST10F271Z1 Internal Flash memory application mapping. Accesses to this address range will send back the content of the Flash cell (by default FFFFh, blank value when the device is delivered) 2 5.2.2 Accesses to the area will send back the value 009Bh. Module structure The IFlash module is composed by a bank (Bank 0) of 128 Kbyte of Program Memory divided in 6 sectors (B0F0...B0F5). Bank 0 contains also a reserved sector named TestFlash. The Addresses from 0x08 0000 to 0x08 FFFF are reserved for the Control Register Interface and other internal service memory space used by the Flash Program/Erase controller. The following tables show the memory mapping of the Flash when it is accessed in read mode (Table 4: Flash module sectorization (read operations)), and when accessed in write or erase mode (Table 5: Flash modules sectorization (write operations or with ROMS1='1' or bootstrap mode)): note that with this second mapping, the first four banks are remapped into code segment 1 (same as obtained setting bit ROMS1 in SYSCON register). ) s ( ct Table 4. r P e Flash module sectorization (read operations) Bank u d o Description Addresses Size Bank 0 Flash 0 (B0F0) 0x0000 0000 - 0x0000 1FFF 8 KB Bank 0 Flash 1 (B0F1) 0x0000 2000 - 0x0000 3FFF 8 KB 0x0000 4000 - 0x0000 5FFF 8 KB 0x0000 6000 - 0x0000 7FFF 8 KB 0x0001 8000 - 0x0001 FFFF 32 KB Bank 0 Flash 2 (B0F2) Bank 0 Flash 3 (B0F3) )- B0 Bank 0 Flash 4 (B0F4) s ( t c Bank 0 Flash 5 (B0F5) s b O 32-bit (I-BUS) 0x0002 0000 - 0x0002 FFFF 64 KB Reserved (1) 0x0003 0000 - 0x0003 FFFF 64 KB Reserved (1) 0x0004 0000 - 0x0004 FFFF 64 KB du o r P t e l o ST10 Bus size 1. This area must be reserved by the application mapping. e t e l Table 5. o s b Bank O B0 Flash modules sectorization (write operations or with ROMS1='1' or bootstrap mode) Description Addresses Size Bank 0 Test-Flash (B0TF) 0x0000 0000 - 0x0000 1FFF 8 KB Bank 0 Flash 0 (B0F0) 0x0001 0000 - 0x0001 1FFF 8 KB Bank 0 Flash 1 (B0F1) 0x0001 2000 - 0x0001 3FFF 8 KB Bank 0 Flash 2 (B0F2) 0x0001 4000 - 0x0001 5FFF 8 KB Bank 0 Flash 3 (B0F3) 0x0001 6000 - 0x0001 7FFF 8 KB Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB (1) 0x0003 0000 - 0x0003 FFFF 64 KB Reserved (1) 0x0004 0000 - 0x0004 FFFF 64 KB Reserved ST10 bus size 32-bit (I-BUS) 1. This area must be reserved by the application mapping. 25/185 Internal Flash memory ST10F271Z1 The table above refers to the configuration when bit ROMS1 of SYSCON register is set. When Bootstrap mode is entered: Test-Flash is seen and available for code fetches (address 00'0000h) User I-Flash is only available for read and write accesses Write accesses must be made with addresses starting in segment 1 from 01'0000h, whatever ROMS1 bit in SYSCON value Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value. In Bootstrap mode, by default ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in segment 0. Example: ) s ( ct In default configuration, to program address 0, user must put the value 01'0000h in the FARL and FARH registers, but to verify the content of the address 0 a read to 00'0000h must be performed. u d o Next Table 6: Control register interface shows the Control Register interface composition: this set of registers can be addressed by the CPU. Table 6. Control register interface t e l o Addresses Size 0x0008 0000 - 0x0008 0007 8 byte 0x0008 0008 - 0x0008 000F 8 byte 0x0008 0010 - 0x0008 0013 4 byte 0x0008 0014 - 0x0008 0015 2 byte 0x0008 DFB0 - 0x0008 DFB1 2 byte Flash non-volatile access protection Register 0 0x0008 DFB8 - 0x0008 DFB9 2 byte FNVAPR1 Flash non-volatile access protection Register 1 0x0008 DFBC - 0x0008 DFBF 4 byte XFVTAUR0 XBus Flash volatile temporary access 0x0000 EB50 - 0x0000 EB51 2 byte unprotection register 0 Name b O s b O Flash control registers 1-0 FDR1-0 Flash data registers 1-0 FAR Flash address registers FER Flash error register FNVWPIR Flash non volatile protection I Register ete 5.2.3 Description FCR1-0 )- s ( t c du o r P FNVAPR0 l o s r P e Bus size 16-bit Low power mode The Flash module is automatically switched off executing PWRDN instruction. The consumption is drastically reduced, but exiting this state can require a long time (tPD). Recovery time from power-down mode for the Flash modules is anyway shorter than the main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash, it is important to size properly the external circuit on RPD pin. Note: 26/185 PWRDN instruction must not be executed while a Flash program/erase operation is in progress. ST10F271Z1 5.3 Internal Flash memory Write operation The Flash module have one single register interface mapped in the memory space of the IBUS (0x08 0000 to 0x08 0015). All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit registers are used to store Flash Address and Data for Program operations (FARH/L and FDR1H/L-FDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible with 8 and 16-bit instructions (since operates in 16-bit mode when in read/ write). Before accessing the IFlash module (and consequently also the Flash register to be used for program/erasing operations), bit ROMEN in SYSCON register shall be set. During a Flash write operation any attempt to read the Flash itself, that is under modification, will output invalid data (software trap 009Bh). This means that the Flash is not fetchable when a programming operation is active: the write operation commands must be executed from another memory (internal RAM or external memory), as in ST10F269 device. In fact, due to IBUS characteristics, it is not possible to perform a write operation on IFlash, when fetching code from IFlash. ) s ( ct u d o Direct addressing is not allowed for write accesses to IFlash Control Registers. r P e During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the Flash Control Registers. t e l o Power supply drop s b O If during a write operation the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the module is reset to Read mode. At following Power-on, the interrupted Flash write operation must be repeated. ) (s t c u 5.4 Register description 5.4.1 Flash control register 0 low d o r P e The Flash Control Register 0 Low (FCR0L) together with the Flash Control Register 0 High (FCR0H) is used to enable and to monitor all the write operations on the IFlash. The user has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by the user in Bootstrap Mode only. s b O t e l o FCR FCR0L (0x08 0000) 15 14 13 12 11 10 reserved 9 8 Reset Value: 0000h 7 6 5 4 3 2 1 0 LOCK res. res. BSY0 res. R R 27/185 Internal Flash memory Table 7. ST10F271Z1 Flash control register 0 low Bit Function BSY0 Bank 0 Busy (IFlash) This bit indicates that a write operation is running on Bank 0 (IFlash). It is automatically set when bit WMS is set. Setting Protection operation sets bit BSY0 (since protection registers are in this Block). When this bit is set, every read access to Bank 0 will output invalid data (software trap 009Bh), while every write access to the Bank will be ignored. At the end of the write operation or during a Program or Erase Suspend this bit is automatically reset and the Bank returns to read mode. After a Program or Erase Resume this bit is automatically set again. LOCK Flash Registers Access Locked When this bit is set, it means that the access to the Flash Control Registers FCR0H/-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will output invalid data (software trap 009Bh) and any write access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set. This is the only bit the user can always access to detect the status of the Flash: once it is found low, the rest of FCR0L and all the other Flash registers are accessible by the user as well. Note that FER content can be read when LOCK is low, but its content is updated only when also BSY0 bit is reset. ) s ( ct u d o r P e 5.4.2 t e l o Flash control register 0 high s b O The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low (FCR0L) is used to enable and to monitor all the write operations on the IFlash. The user has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by the user in Bootstrap Mode only. ) (s t c u FCR FCR0H (0x08 0002) 15 P e WMS let RW o s b O 28/185 d o r 14 SUSP RW 13 12 11 WPG DWPG SER RW RW RW 10 9 reserved 8 SPR RW Reset value: 0000h 7 6 5 4 3 reserved 2 1 0 ST10F271Z1 Internal Flash memory Table 8. Flash control register 0 high Bit Function SPR Set Protection This bit must be set to select the Set Protection operation. The Set Protection operation allows to program 0s in place of 1s in the Flash non-volatile protection registers. The Flash address in which to program must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L before starting the execution by setting bit WMS. A sequence error is flagged by bit SEQER of FER if the address written in FARH/L is not in the range 0x0E8FB00x08DFBF. SPR bit is automatically reset at the end of the Set Protection operation. SER Sector Erase This bit must be set to select the Sector Erase operation in the Flash modules. The Sector Erase operation allows to erase all the Flash locations to value 0xFF. From 1 to all the sectors of the same Bank (excluded Test-Flash for Bank B0) can be selected to be erased through bits BxFy of FCR1H/L registers before starting the execution by setting bit WMS. It is not necessary to pre-program the sectors to 0x00, because this is done automatically. SER bit is automatically reset at the end of the Sector Erase operation. ) s ( ct u d o r P e t e l o DWPG Double Word Program This bit must be set to select the Double Word (64 bits) Program operation in the Flash module. The Double Word Program operation allows to program 0s in place of 1s. The Flash Address in which to program (aligned with even words) must be written in the FARH/L registers, while the 2 Flash Data to be programmed must be written in the FDR0H/L registers (even word) and FDR1H/L registers (odd word) before starting the execution by setting bit WMS. DWPG bit is automatically reset at the end of the Double Word Program operation. ) (s t c u Word Program This bit must be set to select the Word (32 bits) Program operation in the Flash module. The Word Program operation allows to program 0s in place of 1s. The Flash Address to be programmed must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L registers before starting the execution by setting bit WMS. WPG bit is automatically reset at the end of the Word Program operation. d o r WPG P e t e l o s b O s b O 29/185 Internal Flash memory Table 8. ST10F271Z1 Flash control register 0 high (continued) Bit Function Suspend This bit must be set to suspend the current Program (Word or Double Word) or Sector Erase operation in order to read data in one of the Sectors of the Bank under modification or to program data in another Bank. The Suspend operation resets the Flash Bank to normal read mode (automatically resetting bit BSY0). When in Program Suspend, the Flash module accepts only the following operations: Read and Program Resume. When in Erase Suspend the module accepts only the following operations: Read, Erase Resume and Program (Word or Double Word; Program operations cannot be suspended during Erase Suspend). To resume a suspended operation, the WMS bit must be set again, together with the selection bit corresponding to the operation to resume (WPG, DWPG, SER). Note: It is forbidden to start a new Write operation with bit SUSP already set. SUSP ) s ( ct u d o Write Mode Start This bit must be set to start every write operation in the Flash module. At the end of the write operation or during a Suspend, this bit is automatically reset. To resume a suspended operation, this bit must be set again. It is forbidden to set this bit if bit ERR of FER is high (the operation is not accepted). It is also forbidden to start a new write (program or erase) operation (by setting WMS high) when bit SUSP of FCR0 is high. Resetting this bit by software has no effect. r P e WMS 5.4.3 t e l o Flash control register 1 low s b O The Flash Control Register 1 Low (FCR1L), together with Flash Control Register 1 High (FCR1H), is used to select the Sectors to Erase, or during any write operation to monitor the status of each Sector and Bank. ) (s t c u FCR1L (0x08 0004) 15 14 od 13 r P e t e l o Table 9. bs Bit O B0F(5:0) 30/185 12 11 10 9 FCR 8 reserved Reset value: 0000h 7 6 5 4 3 2 1 0 B0F5 B0F4 B0F3 B0F2 B0F1 B0F0 RS RS RS RS RS RS Flash control register 1 low Function Bank 0 IFlash Sector 5:0 Status These bits must be set during a Sector Erase operation to select the sectors to erase in Bank 0. Besides, during any erase operation, these bits are automatically set and give the status of the 6 sectors of Bank 0 (B0F5-B0F0). The meaning of B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end of a Write operation if no errors are detected. ST10F271Z1 5.4.4 Internal Flash memory Flash control register 1 high The Flash Control Register 1 High (FCR1H), together with Flash Control Register 1 Low (FCR1L), is used to select the Sectors to Erase, or during any write operation to monitor the status of each Sector and Bank. FCR FCR1H (0x08 0006) 15 14 13 12 11 10 9 Reset value: 0000h 8 reserved 7 6 5 B0S 4 3 2 1 0 reserved RS Table 10. Flash control register 1 high Bit ) s ( ct Function Bank 0 Status (IFlash) During any erase operation, this bit is automatically modified and gives the status of the Bank 0. The meaning of B0S bit is given in the next Table 4 Banks (BxS) and Sectors (BxFy) Status bits meaning. This bit is automatically reset at the end of a erase operation if no errors are detected. u d o B0S r P e t e l o During any erase operation, this bit is automatically set and gives the status of the Bank 0. The meaning of B0Fy bit for Sector y of Bank 0 is given by the next Table 4 Banks (BxS) and Sectors (BxFy) Status bits meaning. These bits are automatically reset at the end of an erase operation if no errors are detected. Table 11. 5.4.5 s b O Banks (BxS) and sectors (BxFy) status bits meaning ) (s ERR SUSP B0S = 1 meaning 1 - Erase error in Bank 0 0 1 Erase suspended in Bank 0 0 0 B0Fy = 1 meaning ct du Erase error in sector y of Bank 0 Erase suspended in sector y of Bank 0 ro P e Don't care Don't care Flash data register 0 low s b O t e l o The Flash Address Registers (FARH/L) and the Flash Data Registers (FDR1H/L-FDR0H/L) are used during the program operations to store Flash Address in which to program and Data to program. FCR FDR0L (0x08 0008) 15 14 13 12 11 10 9 8 Reset value: FFFFh 7 6 5 4 3 2 1 0 DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 31/185 Internal Flash memory Table 12. ST10F271Z1 Flash data register 0 low Bit Function Data Input 15:0 These bits must be written with the Data to program the Flash with the following operations: Word Program (32-bit), Double Word Program (64-bit) and Set Protection. DIN(15:0) 5.4.6 Flash data register 0 high FCR FDR0H (0x08 000A) 15 14 13 12 11 10 9 8 Reset value: FFFFh 7 6 5 4 3 ) s ( ct 2 1 0 DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 RW RW Table 13. RW RW RW RW RW RW RW RW RW RW u d o RW RW r P e Function t e l o Data Input 31:16 These bits must be written with the Data to program the Flash with the following operations: word program (32-bit), double word program (64-bit) and set protection. DIN(31:16) Flash data register 1 low FDR1L (0x08 000C) 15 RW Flash data register 0 high Bit 5.4.7 RW 14 13 ) (s t c u 12 d o r 11 10 s b O 9 FCR 8 Reset value: FFFFh 7 6 5 4 3 2 1 0 DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 RW RW P e Table 14. t e l o bs O 5.4.8 RW RW RW RW RW RW RW RW RW RW RW RW RW RW Flash data register 1 low Bit Function Data Input 15:0 These bits must be written with the data to program the Flash with the following operations: word program (32-bit), double word program (64-bit) and set protection. DIN(15:0) Flash data register 1 high FCR FDR1H (0x08 000E) 15 14 13 12 11 10 9 8 Reset value: FFFFh 7 6 5 4 3 2 1 0 DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 RW 32/185 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ST10F271Z1 Internal Flash memory Table 15. Flash data register 1 high Bit Function Data input 31:16 These bits must be written with the data to program the Flash with the following operations: word program (32-bit), double word program (64-bit) and set protection. DIN(31:16) 5.4.9 Flash address register low FCR FARL (0x08 0010) 15 14 13 12 11 10 9 8 Reset value: 0000h 7 6 5 4 3 ) s ( ct 2 ADD15ADD14ADD13ADD12ADD11ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 RW RW Table 16. RW RW RW RW RW RW RW 13 Pr ol O bs Bit ADD(20:16) ) (s t c u 12 od ete reserved RW u d o r P e t e l o FARH (0x08 0012) Table 17. RW 0 Address 15:2 These bits must be written with the address of the Flash location to program in the following operations: word program (32-bit) and double word program (64-bit). in double word program bit ADD2 must be written to `0'. Flash address register high 14 RW Function ADD(15:2) 15 RW Flash address register low Bit 5.4.10 RW 1 11 10 9 s b O Reset value: 0000h FCR 8 7 6 reserved 5 4 3 2 1 0 ADD20 ADD19 ADD18 ADD17 ADD16 RW RW RW RW RW Flash address register high Function Address 20:16 These bits must be written with the address of the Flash location to program in the following operations: word program and double word program. 33/185 Internal Flash memory 5.4.11 ST10F271Z1 Flash error register Flash error register, as well as all the other Flash registers, can be properly read only once LOCK bit of register FCR0L is low. Nevertheless, its content is updated when also BSY0 bit is reset as well; for this reason, it is definitively meaningful reading FER register content only when LOCK bit and BSY0 bit are cleared. FER (0x8 0014h) 15 14 13 12 11 10 9 reserved 8 7 6 RC 3 2 1 0 RC RC RC RC ) s ( ct Flash error register Function u d o ERR Write error This bit is automatically set when an error occurs during a Flash write operation or when a bad write operation setup is done. Once the error has been discovered and understood, ERR bit must be software reset. ERER Erase error This bit is automatically set when an erase error occurs during a Flash write operation. This error is due to a real failure of a Flash cell, that can no more be erased. This kind of error is fatal and the sector where it occurred must be discarded. This bit has to be software reset. PGER Program error This bit is automatically set when a program error occurs during a Flash write operation. This error is due to a real failure of a Flash cell, that can no more be programmed. The word where this error occurred must be discarded. This bit has to be software reset. r P e t e l o ) (s t e l o s b O t c u od r P e 10ER 34/185 4 RC Bit s b O 5 WPF RESER SEQER reserved 10ER PGER ERER ERR RC Table 18. Reset value: 0000h FCR 1 over 0 error This bit is automatically set when trying to program at 1 bits previously set at 0 (this does not happen when programming the protection bits). This error is not due to a failure of the Flash cell, but only flags that the desired data has not been written. This bit has to be software reset. SEQER Sequence error This bit is automatically set when the control registers (FCR1H/L-FCR0H/L, FARH/L, FDR1H/L-FDR0H/L) are not correctly filled to execute a valid write operation. In this case no write operation is executed. This bit has to be software reset. RESER Resume error This bit is automatically set when a suspended program or erase operation is not resumed correctly due to a protocol error. In this case the suspended operation is aborted. This bit has to be software reset. WPF Write Protection Flag This bit is automatically set when trying to program or erase in a sector write protected. In case of multiple sector erase, the not protected sectors are erased, while the protected sectors are not erased and bit WPF is set. This bit has to be software reset. ST10F271Z1 5.5 Internal Flash memory Protection strategy The protection bits are stored in non-volatile Flash cells inside IFlash module, that are read once at reset and stored in 4 Volatile registers. Before they are read from the non-volatile cells, all the available protections are forced active during reset. The protections can be programmed using the set protection operation (see Flash control registers paragraph), that can be executed from all the internal or external memories except from the Flash itself. Two kind of protections are available: write protections to avoid unwanted writings and access protections to avoid piracy. In next paragraphs all different level of protections are shown, and architecture limitations are highlighted as well. 5.5.1 ) s ( ct Protection registers The 4 non-volatile protection registers are one time programmable for the user. u d o One register (FNVWPIR) is used to store the write protection fuses respectively for each sector IFlash module. The other three registers (FNVAPR0 and FNVAPR1L/H) are used to store the access protection fuses. 5.5.2 15 14 13 12 Table 19. 11 10 8 O ) c u d 7 6 Reset value: FFFFh 5 4 3 2 1 0 W0P7W0P6W0P5W0P4W0P3W0P2W0P1W0P0 RW RW RW RW RW RW RW RW Flash non-volatile write protection I register o r P W0P(9:0) s b O 9 t(s Bit e t e ol bs NVR reserved 5.5.3 t e l o Flash non-volatile write protection I register FNVWPIR (0x08 DFB0) r P e Function Write protection bank 0 / sectors 9-0 (IFlash) These bits, if programmed at 0, disable any write access to the sectors of bank 0 (IFlash) Flash non-volatile access protection register 0 FNVAPR0 (0x08 DFB8) 15 14 13 12 NVR 11 10 9 8 reserved Reset value: ACFFh 7 6 5 4 3 2 1 0 DBGP ACCP RW RW 35/185 Internal Flash memory Table 20. ST10F271Z1 Flash non-volatile access protection register 0 Bit 5.5.4 Function ACCP Access protection This bit, if programmed at 0, disables any access (read/write) to data mapped inside IFlash module address space, unless the current instruction is fetched from IFlash. DBGP Debug protection This bit, if erased at 1, allows to by-pass all the protections using the debug features through the Test Interface. If programmed at 0, on the contrary, all the debug features, the Test Interface and all the Flash test modes are disabled. Even STMicroelectronics will not be able to access the device to run any eventual failure analysis. ) s ( ct Flash non-volatile access protection register 1 low FNVAPR1L (0x08 DFBC) 15 14 13 12 NVR 11 10 9 8 7 6 5 e t e ol u d o Pr 4 Delivery value: FFFFh 3 2 1 0 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0 RW RW Table 21. RW RW RW RW RW RW s b O RW RW RW RW RW RW RW Flash non-volatile access protection register 1 low Bit ) (s Function Protections Disable 15-0 If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit PENx-1 has already been programmed at 0. t c u PDS(15:0) d o r 5.5.5 Flash non-volatile access protection register 1 high P e t e l o FNVAPR1H (0x08 DFBE) s b O 15 14 13 12 NVR 11 10 9 8 Delivery value: FFFFh 7 6 5 4 3 2 1 0 PEN15PEN14PEN13PEN12PEN11PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 RW RW Table 22. Bit PEN15-0 36/185 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Flash non-volatile access protection register 1 high Function Protections enable 15-0 If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit ACCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has already been programmed at 0. ST10F271Z1 5.5.6 Internal Flash memory XBus Flash volatile temporary access unprotection register (XFVTAUR0) XFVTAUR0 (0x00 EB50) 15 14 13 12 NVR 11 10 9 8 Reset value: 0000h 7 6 5 4 3 2 1 0 TAUB reserved Table 23. RW XBus Flash volatile temporary access unprotection register Bit Function ) s ( ct TAUB Temporary access unprotection bit If this bit is set to 1, the access protection is temporary disabled. This bit can be written only executing from IFlash.This fact guarantees that only a code executed in IFlash, can unprotect the IFlash, when it is Access Protected. 5.5.7 u d o r P e Access protection The I-Flash module has one level of access protection (access to data both in Reading and Writing): if bit ACCP of FNVAPR0 is programmed at 0 and bit TAUB in XFVTAUR0 is set at 0, the I-Flash module becomes access protected: data in the I-Flash module can be read only if the current execution is from the I-Flash module itself. t e l o s b O To enable Access Protection, the following sequence of operations is recommended: ) (s execution from external memory or internal Rams program TAUB bit at 1 in XFVTAUR0 register program ACCP bit in FNVAPR0 to 0 using Set Protection operation program TAUB bit at 0 in XFVTAUR0 register Access Protection is active when both ACCP bit and TAUB bit are set to 0. t c u d o r Protection can be permanently disabled by programming bit PDS0 of FNVAPR1H, in order to analyze rejects. Protection can be permanently enabled again by programming bit PEN0 of FNVAPR1L. The action to disable and enable again Access Protections in a permanent way can be executed a maximum of 16 times. To execute the above described operations, the Flash has to be temporary unprotected (See Section 5.5.9: Temporary unprotection) P e s b O t e l o Trying to write into the access protected Flash from internal RAM or external memories will be unsuccessful. Trying to read into the access protected Flash from internal RAM or external memories will output a dummy data (software trap 0x009Bh). When the Flash module is protected in access, also the data access through PEC of a peripheral is forbidden. To read/write data in PEC mode from/to a protected bank, first it is necessary to temporary unprotect the Flash module. In the following table a summary of all levels of possible access protection is reported: in particular, supposing to enable all possible access protections, when fetching from a memory as listed in the first column, what is possible and what is not possible to do (see column headers) is shown in the table. 37/185 Internal Flash memory Figure 6. ST10F271Z1 Summary of access protection level Read IFlash / jump to IFlash Read XRAMS or ext mem / jump to XRAM or ext mem Read Flash registers Write Flash registers Fetching from IFlash Yes / Yes Yes / Yes Yes No Fetching from IRAM No / Yes Yes / Yes Yes No Fetching from XRAM No / Yes Yes / Yes Yes No Fetching from external memory No / Yes Yes / Yes Yes No When the Access Protection is enabled, Flash registers can not be written, so no program/erase operation can be run on I-Flash. To enable the access to registers again, the Temporary Access Unprotection procedure has to be followed (see Section 5.5.9). 5.5.8 ) s ( ct u d o Write protection r P e The Flash modules have one level of write protections: each sector of each bank of each Flash module can be software write protected by programming at 0 the related bit W0Px in FNVWPIRL register. 5.5.9 Temporary unprotection t e l o s b O Bits W0Px of FNVWPIRL can be temporary unprotected by executing the set protection operation and by writing 1 into these bits. ) (s To restore the write protection bits it is necessary to reset the microcontroller or to execute a set protection operation and write 0 into the desired bits. t c u In reality, when a temporary write unprotection operation is executed, the corresponding volatile register is written to 1, while the non-volatile registers bits previously written to 0 (for a protection set operation), will continue to maintain the 0. For this reason, the user software must be in charge to track the current write protection status (for instance using a specific RAM area), it is not possible to deduce it by reading the non-volatile register content (a temporary unprotection cannot be detected). d o r P e t e l o s b O 5.6 To temporary unprotect the Flash when the access protection is active, it is necessary to set at 1 the bit TAUB in XFVTAUR0. This bit can be write at 1, only executing from Flash: in this way only an instruction executed from Flash can unprotect the Flash itself. To restore the access protection, it is necessary to reset the microcontroller or to write at 0 the bit TAUB in XFVTAUR0. Write operation examples In the following, examples for each kind of Flash write operation are presented. 38/185 ST10F271Z1 Note: Internal Flash memory The write operation commands must be executed from another memory (internal RAM or external memory), as in ST10F269 device. In fact, due to IBus characteristics, it is not possible to perform write operation in Flash while fetching code from Flash. Moreover, direct addressing is not allowed for write accesses to IFlash control registers. This means that both address and data for a writing operation must be loaded in one of ST10 GPR register (R0...R15). Write operation on IBus registers is 16 bit wide. Example of indirect addressing mode MOV MOV MOV RWm, #ADDRESS; RWn, #DATA; [RWm], RWn; /*Load Add in RWm*/ /*Load Data in RWn*/ /*Indirect addressing*/ ) s ( ct Word program u d o Example: 32-bit word program of data 0xAAAAAAAA at address 0x025554 FCR0H|= FARL = FARH = FDR0L = FDR0H = FCR0H|= 0x2000; 0x5554; 0x0002; 0xAAAA; 0xAAAA; 0x8000; /*Set WPG in FCR0H*/ /*Load Add in FARL*/ /*Load Add in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ /*Operation start*/ r P e t e l o Double word program ) (s s b O Example: double word program (64-bit) of data 0x55AA55AA at address 0x035558 and data 0xAA55AA55 at address 0x03555C in IFlash Module. FCR0H FARL FARH FDR0L FDR0H FDR1L FDR1H FCR0H ct |= 0x1000; = 0x5558; = 0x0003; = 0x55AA; = 0x55AA; = 0xAA55; = 0xAA55; |= 0x8000; u d o r P e s b O t e l o /*Set DWPG/ /*Load Add in FARL*/ /*Load Add in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ /*Load Data in FDR1L*/ /*Load Data in FDR1H*/ /*Operation start*/ Double word program is always performed on the double word aligned on a even word: bit ADD2 of FARL is ignored. Sector erase Example: sector erase of sectors B0F1 and B0F0 of bank 0 in IFlash module. FCR0H FCR1L FCR0H |= 0x0800; |= 0x0003; |= 0x8000; /*Set SER in FCR0H*/ /*Set B0F1, B0F0*/ /*Operation start*/ Suspend and resume Word program, double word program, and sector erase operations can be suspended in the following way: FCR0H |= 0x4000; /*Set SUSP in FCR0H*/ 39/185 Internal Flash memory ST10F271Z1 Then the operation can be resumed in the following way: FCR0H FCR0H |= 0x0800; |= 0x8000; /*Set SER in FCR0H*/ /*Operation resume*/ Before resuming a suspended erase, FCR1H/FCR1L must be read to check if the erase is already completed (FCR1H = FCR1L = 0x0000 if erase is complete). Original setup of select operation bits in FCR0H/L must be restored before the operation resume, otherwise the operation is aborted and bit RESER of FER is set. Erase suspend, program and resume A sector erase operation can be suspended in order to program (word or double word) another sector. ) s ( ct Example: sector erase of sector B0F1 of IFlash module. FCR0H FCR1L FCR0H |= 0x0800; |= 0x0002; |= 0x8000; /*Set SER in FCR0H*/ /*Set B0F1*/ /*Operation start*/ u d o r P e Example: sector erase suspend. FCR0H |= 0x4000; /*Set SUSP in FCR0H*/ do /*Loop to wait for LOCK=0 and WMS=0*/ {tmp1 = FCR0L; tmp2 = FCR0H; } while ((tmp1 && 0x0010) || (tmp2 && 0x8000)); t e l o s b O Example: word program of data 0x5555AAAA at address 0x045554 in IFlash module. ) (s FCR0H &= 0xBFFF; /*Rst SUSP in FCR0H*/ FCR0H|= 0x2000;/*Set WPG in FCR0H*/ FARL = 0x5554; /*Load Add in FARL*/ FARH = 0x0004; /*Load Add in FARH*/ FDR0L = 0xAAAA; /*Load Data in FDR0L*/ FDR0H = 0x5555; /*Load Data in FDR0H*/ FCR0H |= 0x8000; /*Operation start*/ t c u d o r P e Once the program operation is finished, the erase operation can be resumed in the following way: t e l o s b O FCR0H|= 0x0800;/*Set SER in FCR0H*/ FCR0H|= 0x8000;/*Operation resume*/ Notice that during the program operation in erase suspend, bits SER and SUSP are low. A word or double word program during erase suspend cannot be suspended. In summary: A sector erase can be suspended by setting SUSP bit. To perform a word program operation during erase suspend, firstly bits SUSP and SER must be reset, then bit WPG and WMS can be set. To resume the sector erase operation bit SER must be set again. In any case it is forbidden to start any write operation with SUSP bit already set. Set protection Example 1: Enable write protection of sectors B0F3-0 of bank 0 in IFlash module. 40/185 ST10F271Z1 Internal Flash memory FCR0H FARL FARH FDR0L FDR0H FCR0H |= = = = = |= 0x0100; 0xDFB4; 0x0008; 0xFFF0; 0xFFFF; 0x8000; /*Set SPR in FCR0H*/ /*Load Add of register FNVWPIR in FARL*/ /*Load Add of register FNVWPIR in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ /*Operation start*/ Example 2: Enable access and debug protection. FCR0H FARL FARH FDR0L FCR0H |= = = = |= 0x0100; 0xDFB8; 0x0008; 0xFFFC; 0x8000; /*Set SPR in FCR0H*/ /*Load Add of register FNVAPR0 in FARL*/ /*Load Add of register FNVAPR0 in FARH*/ /*Load Data in FDR0L*/ /*Operation start*/ ) s ( ct Example 3: Disable in a permanent way access and debug protection. XFVTAUR0 = 0x0001; FCR0H |= 0x0100; FARL = 0xDFBC; FARH = 0x0008; FDR0L = 0xFFFE; FCR0H |= 0x8000; /*Set TAUB in XFVTAUR0*/ /*Set SPR in FCR0H*/ /*Load Add of register FNVAPR1L in FARL*/ /*Load Add of register FNVAPR1L in FARH*/ /*Load Data in FDR0L for clearing PDS0*/ /*Operation start*/ u d o r P e t e l o Example 4: Enable again in a permanent way access and debug protection, after having disabled them. XFVTAUR0 = 0x0001; FCR0H |= 0x0100; FARL = 0xDFBC; FARH = 0x0008; FDR0H = 0xFFFE; PEN0*/ FCR0H |= 0x8000; XFVTAUR0 = 0x0000; ) (s t c u d o r s b O /*Set TAUB in XFVTAUR0*/ /*Set SPR in FCR0H*/ /*Load Add register FNVAPR1H in FARL*/ /*Load Add register FNVAPR1H in FARH*/ /*Load Data in FDR0H for clearing /*Operation start*/ /*Reset TAUB in XFVTAUR0*/ P e Disable and re-enable of access and debug protection in a permanent way (as shown by examples 3 and 4) can be done for a maximum of 16 times. 5.7 s b O t e l o Write operation summary In general, each write operation is started through a sequence of 3 steps: 1. The first instruction is used to select the desired operation by setting its corresponding selection bit in the Flash control register 0. 2. The second step is the definition of the address and data for programming or the sectors or banks to erase. 3. The last instruction is used to start the write operation, by setting the start bit WMS in the FCR0. Once selected, but not yet started, one operation can be canceled by resetting the operation selection bit. A summary of the available Flash module write operations are shown in the following Table 24: Flash write operations. 41/185 Internal Flash memory ST10F271Z1 Table 24. Flash write operations Operation Select bit Address and data Start bit WPG FARL/FARH FDR0L/FDR0H WMS DWPG FARL/FARH FDR0L/FDR0H FDR1L/FDR1H WMS Sector erase SER FCR1L/FCR1H WMS Set protection SPR FDR0L/FDR0H WMS SUSP None None Word program (32-bit) Double word program (64-bit) Program/erase suspend u d o ) s ( ct r P e t e l o ) (s t c u d o r P e t e l o s b O 42/185 s b O ST10F271Z1 6 Bootstrap loader Bootstrap loader ST10F271Z1 implements boot capabilities in order to: 6.1 Support bootstrap via UART or bootstrap via CAN for the standard bootstrap. Support a selective bootstrap loader, to manage the bootstrap sequence in a different way. Selection among user-code, standard or selective bootstrap The boot modes are triggered with a special combination set on Port0L[5...4]. Those signals, as other configuration signals, are latched on the rising edge of RSTIN pin. ) s ( ct Decoding of reset configuration (P0L.5 = 1, P0L.4 = 1) will select the normal mode (also called User Mode) and select the user Flash to be mapped from address 00'0000h. Decoding of reset configuration (P0L.5 = 1, P0L.4 = 0) will select ST10 standard bootstrap mode (Test-Flash is active and overlaps user Flash for code fetches from address 00'0000h; user Flash is active and available for read accesses). Decoding of reset configuration (P0L.5 = 0, P0L.4 = 1) will activate new verifications to select which bootstrap software to execute: u d o r P e t e l o if the User mode signature in the User Flash is programmed correctly, then a software reset sequence is selected and the User code is executed; - if the User mode signature is not programmed correctly in the user Flash, then the User key location is read again. Its value will determine which communication channel will be enabled for bootstraping . Table 25. P0.5 1 t c u ST10F271Z1 boot mode selection od P0.4 Pr ST10 decoding User mode: user Flash mapped at 00'0000h 0 Standard bootstrap loader: User Flash mapped from 00'0000h, code fetches redirected to Test-Flash at 00'0000h 0 1 Selective boot mode: User Flash mapped from 00'0000h, code fetches redirected to Test-Flash at 00'0000h (different sequence execution in respect of Standard Bootstrap Loader) 0 0 Reserved e t e ol 6.2 ) (s 1 1 s b O s b O - Standard bootstrap loader After entering the standard BSL mode and the respective initialization, the ST10F271Z1 scans the RxD0 line and the CAN1_RxD line to receive either a valid dominant bit from CAN interface, or a start condition from UART line. Start condition on UART RxD: ST10F271Z1 starts standard bootstrap loader. This bootstrap loader is identical to other ST10 devices (example: ST10F269, ST10F168). Valid dominant bit on CAN1 RxD: ST10F271Z1 start bootstrapping via CAN1. 43/185 Bootstrap loader ST10F271Z1 6.3 Alternate and selective boot mode (ABM and SBM) 6.3.1 Activation of the ABM and SBM Alternate boot is activated with the combination `01' on Port0L[5..4] at the rising edge of RSTIN. 6.3.2 User mode signature integrity check The behavior of the selective boot mode is based on the computing of a signature between the content of 2 memory locations and a comparison with a reference signature. This requires that users who use selective boot have reserved and programmed the Flash memory locations. 6.3.3 ) s ( ct Selective boot mode u d o When the user signature is not correct, instead of executing the standard bootstrap loader (triggered by P0L.4 low at reset), additional check is made. r P e Depending on the value at the user key location, following behavior will occur: A jump is performed to the standard bootstrap loader Only UART is enabled for bootstraping Only CAN1 is enabled for bootstraping The device enters an infinite loop. ) (s t c u d o r P e t e l o s b O 44/185 s b O t e l o ST10F271Z1 7 Central processing unit (CPU) Central processing unit (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F271Z1's instructions can be executed in one instruction cycle which requires 31.25 ns at 64 MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted. Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x 16-bit multiplication in 5 cycles and a 32/16-bit division in 10 cycles. ) s ( ct The jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. The CPU uses a bank of 16 word registers to run the current context. This bank of General Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. u d o r P e The number of register banks is only restricted by the available Internal RAM space. For easy parameter passing, a register bank may overlap others. t e l o A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. ) (s s b O Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. Figure 7. t c u CPU block diagram (MAC unit not included) d o r P e t e l o 128 Kbyte Flash memory s b O 16 CPU SP STKOV STKUN Exec. Unit Instr. Ptr 4-Stage Pipeline 32 PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs MDH MDL Mul./Div.-HW Bit-Mask Gen. ALU 2 Kbyte Internal RAM R15 Bank n General Purpose Registers 16-Bit Barrel-Shift CP ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. R0 Bank i 16 Bank 0 45/185 Central processing unit (CPU) 7.1 ST10F271Z1 Multiplier-accumulator unit (MAC) The MAC co-processor is a specialized co-processor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new co-processor with up to 2 operands per instruction cycle. This new co-processor (so-called MAC) contains a fast multiply-accumulate unit and a repeat unit. The co-processor instructions extend the ST10 CPU instruction set with multiply, multiplyaccumulate, 32-bit signed arithmetic operations. Figure 8. Operand 1 16 GPR Pointers * IDX0 Pointer IDX1 Pointer QR0 GPR Offset Register QR1 GPR Offset Register )- MRW Interrupt Controller c u d o r P ST10 CPU ol s b O 7.2 t(s 16 u d o r P e Concatenation s b O Operand 2 16 x 16 signed/unsigned Multiplier t e l o QX0 IDX Offset Register QX1 IDX Offset Register ete ) s ( ct MAC unit architecture 32 32 Mux Sign Extend Scaler 0h 40 Repeat Unit 08000h 0h 40 40 40 40 Mux Mux 40 MCW 40 A B 40-bit Signed Arithmetic Unit MSW Flags MAE 40 MAH MAL Control Unit * Shared with standard ALU 40 8-bit Left/Right Shifter Instruction set summary The Table 26 lists the instructions of the ST10F271Z1. The detailed description of each instruction can be found in the "ST10 Family Programming Manual". 46/185 ST10F271Z1 Central processing unit (CPU) Table 26. Standard instruction set summary Mnemonic Description ADD(B) Add word (byte) operands 2/4 ADDC(B) Add word (byte) operands with Carry 2/4 SUB(B) Subtract word (byte) operands 2/4 SUBC(B) Subtract word (byte) operands with Carry 2/4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR NEG(B) Negate direct word (byte) GPR AND(B) Bit-wise AND, (word/byte operands) OR(B) Bit-wise OR, (word/byte operands) XOR(B) Bit-wise XOR, (word/byte operands) BCLR Clear direct bit BSET Set direct bit BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bit-wise modify masked high/low byte of bit-addressable direct word memory with immediate data o r P CMPD1/2 CMPI1/2 ete 2 c u d ro P e let o s b O ) s ( t c 2 2/4 2/4 2/4 2 2 4 Compare word (byte) operands 2/4 Compare word data to GPR and decrement GPR by 1/2 2/4 Compare word data to GPR and increment GPR by 1/2 2/4 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR 2 SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 MOV(B) Move word (byte) data 2/4 MOVBS Move byte operand to word operand with sign extension 2/4 MOVBZ Move byte operand to word operand with zero extension 2/4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 PRIOR b O ) s ( t du CMP(B) l o s Bytes 47/185 Central processing unit (CPU) Table 26. ST10F271Z1 Standard instruction set summary (continued) Mnemonic Description CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine 4 TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update register with word operand 4 RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine RETP Return from intra-segment subroutine and pop direct word register from system stack 2 RETI Return from interrupt service subroutine 2 SRST Software reset IDLE Enter Idle mode PWRDN Enter power-down mode (supposes NMI-pin being low) 4 SRVWDT Service watchdog timer 4 DISWDT Disable watchdog timer 4 ) (s ATOMIC EXTR od Pr EXTP(R) o r P s b O 2 4 4 Signify end-of-initialization on RSTOUT-pin 4 Begin ATOMIC sequence 2 Begin EXTended register sequence 2 2/4 EXTS(R) Begin EXTended segment (and register) sequence 2/4 NOP Null operation 2 MAC co-processor specific instructions The Table 27 lists the MAC instructions of the ST10F271Z1. The detailed description of each instruction can be found in the "ST10 Family Programming Manual". Note that all MAC instructions are encoded on 4 Bytes. Table 27. MAC instruction set summary Mnemonic 48/185 du Begin EXTended page (and register) sequence e t e ol s b O e t e ol ) s ( ct t c u EINIT 7.3 Bytes Description CoABS Absolute value of the accumulator CoADD(2) Addition CoASHR(rnd) Accumulator arithmetic shift right & optional round CoCMP Compare accumulator with operands ST10F271Z1 Central processing unit (CPU) Table 27. MAC instruction set summary (continued) Mnemonic Description CoLOAD(-,2) Load accumulator with operands CoMAC(R,u,s,-,rnd) (Un)Signed/(un)signed multiply-accumulate & optional round CoMACM(R)(u,s,-,rnd) (Un)Signed/(un)Signed multiply-accumulate with parallel data move & optional round CoMAX / CoMIN Maximum / minimum of operands and accumulator CoMOV Memory to memory move CoMUL(u,s,-,rnd) (Un)Signed/(un)signed multiply & optional round CoNEG(rnd) Negate accumulator & optional round CoNOP No-operation CoRND Round accumulator CoSHL / CoSHR Accumulator logical shift left / right CoSTORE Store a MAC unit register CoSUB(2,R) Substraction ) (s ) s ( ct u d o r P e t e l o s b O t c u d o r P e t e l o s b O 49/185 External bus controller 8 ST10F271Z1 External bus controller All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes: 16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed 16- / 18- / 20- / 24-bit addresses and 16-bit data, multiplexed 16- / 18- / 20- / 24-bit addresses and 8-bit data, multiplexed 16- / 18- / 20- / 24-bit addresses and 8-bit data, demultiplexed ) s ( ct In demultiplexed bus modes addresses are output on PORT1 and data is input / output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input / output. u d o Timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ALE and read / write delay) are programmable giving the choice of a wide range of memories and external peripherals. r P e Up to four independent address windows may be defined (using register pairs ADDRSELx / BUSCONx) to access different resources and bus characteristics. t e l o These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. s b O All accesses to locations not covered by these four address windows are controlled by BUSCON0. Up to five external CS signals (four windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported by a `Ready' function. ) (s t c u A HOLD / HLDA protocol is available for bus arbitration which shares external resources with other bus masters. d o r The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to'1' the slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic. P e t e l o bs O For applications which require less external memory space, the address space can be restricted to 1 Mbyte, 256 Kbytes or to 64 Kbytes. Port 4 outputs all eight address lines if an address space of 16 Mbytes is used, otherwise four, two or no address lines. Chip select timing can be made programmable. By default (after reset), the CSx lines change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON register the CSx lines change with the rising edge of ALE. The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register. 50/185 ST10F271Z1 9 Interrupt system Interrupt system The interrupt response time for internal program execution is from 78 ns to 187.5 ns at 64 MHz CPU clock. The ST10F271Z1 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources (internal or external) to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single Byte or Word data transfer between any two memory locations with an additional increment of either the PEC source or destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F271Z1 has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. ) s ( ct u d o r P e t e l o An interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit-field is dedicated to each existing interrupt source. Thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels. Once starting to be processed by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. ) (s s b O Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. t c u Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). d o r P e Fast external interrupts may also have interrupt sources selected from other peripherals; for example the CANx controller receive signals (CANx_RxD) and I2C serial clock signal can be used to interrupt the system. t e l o O bs Table 28 shows all the available ST10F271Z1 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Table 28. Interrupt sources Source of interrupt or PEC service request Request flag Enable flag Interrupt vector Vector location Trap number CAPCOM register 0 CC0IR CC0IE CC0INT 00'0040h 10h CAPCOM register 1 CC1IR CC1IE CC1INT 00'0044h 11h CAPCOM register 2 CC2IR CC2IE CC2INT 00'0048h 12h CAPCOM register 3 CC3IR CC3IE CC3INT 00'004Ch 13h CAPCOM register 4 CC4IR CC4IE CC4INT 00'0050h 14h CAPCOM register 5 CC5IR CC5IE CC5INT 00'0054h 15h 51/185 Interrupt system ST10F271Z1 Table 28. Interrupt sources (continued) Source of interrupt or PEC service request Request flag Enable flag Interrupt vector Vector location Trap number CAPCOM register 6 CC6IR CC6IE CC6INT 00'0058h 16h CAPCOM register 7 CC7IR CC7IE CC7INT 00'005Ch 17h CAPCOM register 8 CC8IR CC8IE CC8INT 00'0060h 18h CAPCOM register 9 CC9IR CC9IE CC9INT 00'0064h 19h CAPCOM register 10 CC10IR CC10IE CC10INT 00'0068h 1Ah CAPCOM register 11 CC11IR CC11IE CC11INT 00'006Ch 1Bh CAPCOM register 12 CC12IR CC12IE CC12INT 00'0070h CAPCOM register 13 CC13IR CC13IE CC13INT 00'0074h CAPCOM register 14 CC14IR CC14IE CC14INT 00'0078h CAPCOM register 15 CC15IR CC15IE CC15INT 00'007Ch CAPCOM register 16 CC16IR CC16IE CC16INT 00'00C0h 30h CAPCOM register 17 CC17IR CC17IE CC17INT 00'00C4h 31h CAPCOM register 18 CC18IR CC18IE CC18INT 00'00C8h 32h CAPCOM register 19 CC19IR CC19IE 00'00CCh 33h CAPCOM register 20 CC20IR CC20INT 00'00D0h 34h CAPCOM register 21 CC21IR s b O CC19INT CC21IE CC21INT 00'00D4h 35h CC22IE CC22INT 00'00D8h 36h CC23IR CC23IE CC23INT 00'00DCh 37h CC24IR CC24IE CC24INT 00'00E0h 38h CAPCOM register 25 CC25IR CC25IE CC25INT 00'00E4h 39h CAPCOM register 26 CC26IR CC26IE CC26INT 00'00E8h 3Ah CAPCOM register 27 CC27IR CC27IE CC27INT 00'00ECh 3Bh CAPCOM register 28 CC28IR CC28IE CC28INT 00'00F0h 3Ch CAPCOM register 29 CC29IR CC29IE CC29INT 00'0110h 44h CAPCOM register 30 CC30IR CC30IE CC30INT 00'0114h 45h CAPCOM register 31 CC31IR CC31IE CC31INT 00'0118h 46h CAPCOM timer 0 T0IR T0IE T0INT 00'0080h 20h CAPCOM timer 1 T1IR T1IE T1INT 00'0084h 21h CAPCOM timer 7 T7IR T7IE T7INT 00'00F4h 3Dh CAPCOM timer 8 T8IR T8IE T8INT 00'00F8h 3Eh GPT1 timer 2 T2IR T2IE T2INT 00'0088h 22h GPT1 timer 3 T3IR T3IE T3INT 00'008Ch 23h GPT1 timer 4 T4IR T4IE T4INT 00'0090h 24h GPT2 timer 5 T5IR T5IE T5INT 00'0094h 25h ) (s CAPCOM register 22 t c u CAPCOM register 23 CAPCOM register 24 od e t e ol s b O 52/185 Pr CC22IR CC20IE e t e ol u d o ) s ( ct Pr 1Ch 1Dh 1Eh 1Fh ST10F271Z1 Interrupt system Table 28. Interrupt sources (continued) Source of interrupt or PEC service request Request flag Enable flag Interrupt vector Vector location Trap number GPT2 timer 6 T6IR T6IE T6INT 00'0098h 26h GPT2 CAPREL register CRIR CRIE CRINT 00'009Ch 27h A/D conversion complete ADCIR ADCIE ADCINT 00'00A0h 28h A/D overrun error ADEIR ADEIE ADEINT 00'00A4h 29h ASC0 transmit S0TIR S0TIE S0TINT 00'00A8h 2Ah ASC0 transmit buffer S0TBIR S0TBIE S0TBINT 00'011Ch 47h ASC0 receive S0RIR S0RIE S0RINT 00'00ACh ASC0 error S0EIR S0EIE S0EINT 00'00B0h SSC transmit SCTIR SCTIE SCTINT 00'00B4h SSC receive SCRIR SCRIE SCRINT 00'00B8h SSC error SCEIR SCEIE SCEINT PWM channel 0...3 PWMIR PWMIE See paragraph 9.1 XP0IR XP0IE See paragraph 9.1 XP1IR XP1IE See paragraph 9.1 XP2IR See paragraph 9.1 XP3IR ) (s XP3IE Pr 2Ch 2Dh 2Eh 00'00BCh 2Fh PWMINT 00'00FCh 3Fh XP0INT 00'0100h 40h XP1INT 00'0104h 41h XP2INT 00'0108h 42h XP3INT 00'010Ch 43h e t e ol s b O XP2IE u d o ) s ( ct 2Bh Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). t c u d o r The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any other program execution. Hardware trap services cannot not be interrupted by standard interrupt or by PEC interrupts. P e 9.1 s b O t e l o X-Peripheral interrupt The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some constraints on the implementation of the new functionality. In particular, the additional XPeripherals SSC1, ASC1, I2C, PWM1 and RTC need some resources to implement interrupt and PEC transfer capabilities. For this reason, a multiplexed structure for the interrupt management is proposed. In the next Figure 9, the principle is explained through a simple diagram, which shows the basic structure replicated for each of the four X-interrupt available vectors (XP0INT, XP1INT, XP2INT and XP3INT). It is based on a set of 16-bit registers XIRxSEL (x=0,1,2,3), divided in two portions each: Byte High XIRxSEL[15:8] Interrupt enable bits Byte Low XIRxSEL[7:0] Interrupt flag bits When different sources submit an interrupt request, the enable bits (byte high of XIRxSEL register) define a mask which controls which sources will be associated with the unique 53/185 Interrupt system ST10F271Z1 available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits (byte low of XIRxSEL register). Note that the flag bits can also provide information about events which are not currently serviced by the interrupt controller (since masked through the enable bits), allowing an effective software management also in absence of the possibility to serve the related interrupt request: a periodic polling of the flag bits may be implemented inside the user application. Figure 9. X-Interrupt basic structure 7 0 XIRxSEL[7:0] (x = 0, 1, 2, 3) Flag[7:0] IT Source 7 ) s ( ct IT Source 6 IT Source 5 u d o IT Source 4 XPxIC.XPxIR (x = 0, 1, 2, 3) IT Source 3 r P e IT Source 2 t e l o IT Source 1 IT Source 0 s b O XIRxSEL[15:8] (x = 0, 1, 2, 3) Enable[7:0] 15 8 ) (s The Table 29 summarizes the mapping of the different interrupt sources which shares the four X-interrupt vectors. Table 29. t c u X-Interrupt detailed mapping od Pr CAN1 interrupt ete XP0INT s b O XP2INT x CAN2 interrupt ol XP1INT x x x I2C receive x x x I2C transmit x x x I2C error x SSC1 receive x x x SSC1 transmit x x x SSC1 error 54/185 XP3INT x ASC1 receive x x x ASC1 transmit x x x ASC1 transmit buffer x x x ST10F271Z1 Interrupt system Table 29. X-Interrupt detailed mapping (continued) XP0INT XP1INT XP2INT ASC1 error x PLL unlock / OWD x PWM1 channel 3...0 9.2 XP3INT x x Exception and error traps list Table 30 shows all of the possible exceptions or error conditions that can arise during runtime. Table 30. Trap priorities Trap* priority 00'0000h 00'0000h 00'0000h 00h 00h 00h III III III NMITRAP STOTRAP STUTRAP s b O 00'0008h 00'0010h 00'0018h 02h 04h 06h II II II BTRAP BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah I I I I I I Reserved [002Ch - 003Ch] [0Bh - 0Fh] Software traps TRAP instruction Any 0000h - 01FCh in steps of 4h Any [00h - 7Fh] Reset functions: Hardware reset Software reset Watchdog timer overflow Class A hardware traps: Non-maskable interrupt Stack overflow Stack underflow NMI STKOF STKUF Class B hardware traps: Undefined opcode MAC interruption Protected instruction fault Illegal word operand access Illegal instruction access Illegal external bus access ct ) (s u d o r P e let O o s b Note: UNDOPC MACTRP PRTFLT ILLOPA ILLINA ILLBUS Trap vector Vector location RESET RESET RESET u d o Trap number Exception condition Trap flag ) s ( ct r P e t e l o Current CPU Priority * - All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and to the resets. - Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority level. - The resets have the highest priority level and the same trap number. - The PSW.ILVL CPU priority is forced to the highest level (15) when these exceptions are serviced. 55/185 Capture / compare (CAPCOM) units 10 ST10F271Z1 Capture / compare (CAPCOM) units The ST10F271Z1 has two 16-channel CAPCOM units which support generation and control of timing sequences on up to 32 channels with a maximum resolution of 125 ns at 64 MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. ) s ( ct The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. u d o r P e Each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare functions. Each of the 32 registers has one associated port pin which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. t e l o s b O When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. ) (s t c u Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. d o r P e t e l o When a match occurs between the timer value and the value in a capture / compare register, specific actions will be taken based on the selected compare mode. bs O The input frequencies fTx, for the timer input selector Tx, are determined as a function of the CPU clocks. The timer input frequencies, resolution and periods which result from the selected prescaler option in TxI when using a 40 MHz and 64 MHz CPU clock are listed in the Table 32 and Table 33 respectively. The numbers for the timer periods are based on a reload value of 0000h. Note that some numbers may be rounded to 3 significant figures. 56/185 ST10F271Z1 Capture / compare (CAPCOM) units Table 31. Compare modes Compare modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Double register mode Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. Table 32. ) s ( ct u d o CAPCOM timer input frequencies, resolutions and periods at 40 MHz r P e Timer input selection TxI fCPU = 40 MHz 000b 001b 010b 011b 100b 101b 110b 111b 8 16 32 64 128 256 512 1024 Input frequency 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 39.1 kHz Resolution 200 ns 400 ns 0.8 s 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s Period 13.1 ms 26.2 ms 52.4 ms 104.8 ms Prescaler for fCPU c u d ro P e Timer input selection TxI 000b 001b 010b 011b 100b 101b 110b 111b 8 16 32 64 128 256 512 1024 Input frequency 8 MHz 4 MHz 2 MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz Resolution 125 ns 250 ns 0.5 s 1.0 s 2.0 s 4.0 s 8.0 s 16.0 s Period 8.2 ms 16.4 ms let Prescaler for fCPU b O 209.7 ms 419.4 ms 838.9 ms 1.678 s CAPCOM timer input frequencies, resolutions and periods at 64 MHz fCPU = 64 MHz so bs O ) t(s Table 33. t e l o 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 1.049 s 57/185 General purpose timer unit 11 ST10F271Z1 General purpose timer unit The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module. 11.1 GPT1 ) s ( ct Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. u d o In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. r P e In counter mode, the timer is clocked in reference to external events. t e l o Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. s b O Table 34 and Table 35 list the timer input frequencies, resolution and periods for each prescaler option at 40 MHz and 64 MHz CPU clock respectively. ) (s In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. t c u d o r Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. P e Timer T3 has output toggle latches (TxOTL) which changes state on each timer over flow / underflow. The state of this latch may be output on port pins (TxOUT) for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for high resolution of long duration measurements. t e l o s b O Table 34. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. GPT1 timer input frequencies, resolutions and periods at 40 MHz Timer input selection T2I / T3I / T4I fCPU = 40 MHz 000b 001b 010b 011b 100b 101b 110b 111b Prescaler factor 8 16 32 64 128 256 512 1024 Input frequency 5 MHz 2.5 MHz 1.25 MHz 625 kHz Resolution 200 ns 400 ns 0.8 s 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s Period maximum 13.1 ms 26.2 ms 52.4 ms 104.8 ms 209.7 ms 419.4 ms 838.9 ms 1.678 s 58/185 312.5 kHz 156.25 kHz 78.125 kHz 39.1 kHz ST10F271Z1 Table 35. General purpose timer unit GPT1 timer input frequencies, resolutions and periods at 64 MHz Timer input selection T2I / T3I / T4I fCPU = 64 MHz 000b 001b 010b 011b 100b 101b 110b 111b 8 16 32 64 128 256 512 1024 Input freq 8 MHz 4 MHz 2 MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz Resolution 125 ns 250 ns 0.5 s 1.0 s 2.0 s 4.0 s 8.0 s 16.0 s Period maximum 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 1.049 s Prescaler factor Figure 10. Block diagram of GPT1 T2EUD CPU clock Interrupt Request GPT1 Timer T2 T2 Mode Control 2n n=3...10 T2IN CPU clock ) s ( ct U/D 2n n=3...10 T3 Mode Control T3IN T3EUD u d o Reload Capture r P e let GPT1 Timer T3 so T3OUT T3OTL U/D b O Capture T4IN CPU clock 2n n=3...10 11.2 ) (s t c u T4EUD T4 Mode Control Interrupt Request Reload GPT1 Timer T4 Interrupt Request U/D d o r P e GPT2 s b O t e l o The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental Interface Mode. 59/185 General purpose timer unit ST10F271Z1 Table 36 and Table 37 list the timer input frequencies, resolution and periods for each prescaler option at 40MHz and 64MHz CPU clock respectively. Table 36. GPT2 timer input frequencies, resolutions and periods at 40 MHz Timer input selection T5I / T6I fCPU = 40 MHz 000b 001b 010b 011b 100b 101b 110b 111b 4 8 16 32 64 128 256 512 Input freq 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz Resolution 100 ns 200 ns 400 ns 0.8s 1.6 s 3.2 s 6.4 s 12.8 s Period maximum 6.55 ms 13.1ms 26.2 ms 52.4 ms 104.8 ms 209.7ms 419.4 ms 838.9 ms Prescaler factor Table 37. 312.5 kHz 156.25 kHz 78.125 kHz u d o Timer input selection T5I / T6I fCPU = 64 MHz 000b 001b 010b 011b 100b 4 8 16 32 64 Input freq 16 MHz 8 MHz 4 MHz 2 MHz 1 kHz Resolution 62.5 ns 125 ns 250 ns 0.5 s 1.0 s Period maximum 4.1 ms 8.2 ms 16.4 ms 32.8 ms 65.5 ms Prescaler factor T5EUD CPU clock o s b T5 Mode Control o r P 110b 111b 256 512 500 kHz 250 kHz 128 kHz 2.0 s 4.0 s 8.0 s 131.1 ms 262.1 ms 524.3 ms r P e 128 U/D Interrupt Request GPT2 Timer T5 Clear Capture Interrupt Request CAPIN GPT2 CAPREL Reload T6IN CPU clock T6EUD 60/185 t(s c u d T5IN e t e l 2n n=2...9 101b let o s b O ) Figure 11. Block diagram of GPT2 O ) s ( ct GPT2 timer input frequencies, resolutions and periods at 64 MHz 2n n=2...9 T6 Mode Control Interrupt Request Toggle FF GPT2 Timer T6 U/D T60TL T6OUT to CAPCOM Timers ST10F271Z1 12 PWM modules PWM modules Two pulse width modulation modules are available on ST10F271Z1: standard PWM0 and XBus PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate PWM burst signals and single shot outputs. The Table 38 and Table 39 show the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM modules can generate interrupt requests. Figure 12. Block diagram of PWM module PPx Period Register * Clock 1 Input Control Clock 2 * PTx 16-bit Up/Down Counter Run POUTx Enable Write Control s b O PWx Pulse Width Register * ) (s t c u Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU clock/1 25 ns 156.25 kHz 39.1 kHz 9.77 kHz 2.44 Hz 610 Hz CPU clock/64 1.6 s 2.44 kHz 610 Hz 152.6 Hz 38.15 Hz 9.54 Hz Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU clock/1 25 ns 78.12 kHz 19.53 kHz 4.88 kHz 1.22 kHz 305.2 Hz CPU clock/64 1.6 s 1.22 kHz 305.17 Hz 76.29 Hz 19.07 Hz 4.77 Hz d o r P e t e l o O Output Control PWM unit frequencies and resolutions at 40 MHz CPU clock Mode 0 Mode 1 bs u d o r P e t e l o Shadow Register Table 38. Up/Down/ Clear Control Match Comparator * User readable / writeable register ) s ( ct Match Comparator Table 39. PWM unit frequencies and resolutions at 64 MHz CPU clock Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU clock/1 15.6 ns 250 kHz 62.5 kHz 15.63 kHz 3.91 Hz 977 Hz CPU clock/64 1.0 s 3.91 kHz 976.6 Hz 244.1 Hz 61.01 Hz 15.26 Hz Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit CPU clock/1 15.6 ns 125 kHz 31.25 kHz 7.81 kHz 1.95 kHz 488.3 Hz CPU clock/64 1.0 s 1.95 kHz 488.28 Hz 122.07 Hz 30.52 Hz 7.63 Hz 61/185 Parallel ports ST10F271Z1 13 Parallel ports 13.1 Introduction The ST10F271Z1 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. ST10F271Z1 has nine groups of I/O lines gathered as follows: Port 0 is a two time 8-bit port named P0L (Low as less significant byte) and P0H (high as most significant byte) Port 1 is a two time 8-bit port named P1L and P1H Port 2 is a 16-bit port Port 3 is a 15-bit port (P3.14 line is not implemented) Port 4 is a 8-bit port Port 5 is a 16-bit port input only Port 6, Port 7 and Port 8 are 8-bit ports ) s ( ct u d o r P e These ports may be used as general purpose bidirectional input or output, software controlled with dedicated registers. t e l o For example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured (bitwise) for push-pull or open drain operation using ODPx registers. s b O The input threshold levels are programmable (TTL/CMOS) for all the ports. The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured for input or output. The threshold is selected with PICON and XPICON registers control bits. ) (s t c u A write operation to a port pin configured as an input causes the value to be written into the port output latch, while a read operation returns the latched state of the pin itself. A readmodify-write operation reads the value of the pin, modifies it, and writes it back to the output latch. d o r P e Writing to a pin configured as an output (DPx.y=`1') causes the output latch and the pin to have the written value, since the output buffer is enabled. Reading this pin returns the value of the output latch. A read-modify-write operation reads the value of the output latch, modifies it, and writes it back to the output latch, thus also modifying the level at the pin. t e l o s b O I/O lines support an alternate function which is detailed in the following description of each port. 13.2 I/O's special features 13.2.1 Open drain mode Some of the I/O ports of ST10F271Z1 support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired logical function. This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections), and is controlled through the respective Open Drain Control Registers ODPx. 62/185 ST10F271Z1 13.2.2 Parallel ports Input threshold control The standard inputs of the ST10F271Z1 determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds. The Port Input Control registers PICON and XPICON are used to select these thresholds for each Byte of the indicated ports, this means the 8-bit ports P0L, P0H, P1L, P1H, P4, P7 and P8 are controlled by one bit each while ports P2, P3 and P5 are controlled by two bits each. All options for individual direction and output mode control are available for each pin, independent of the selected input threshold. 13.3 ) s ( ct Alternate port functions u d o Each port line has one associated programmable alternate input or output function. t e l o - Input capture lines - 8 additional analog input channels to the A/D converter Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM0 module, of the PWM1 module and of the ASC1. Port 2 is also used for fast external interrupt inputs and for timer 7 input. Port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 4 outputs the additional segment address bit A23...A16 in systems where more than 64 Kbytes of memory are to be access directly. In addition, CAN1, CAN2 and I2C lines are provided. ) (s s b O t c u d o r Port 5 is used as analog input channels of the A/D converter or as timer control signals. P e t e l o s b O r P e PORT0 and PORT1 may be used as address and data lines when accessing external memory. Besides, PORT1 provides also: Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals and the SSC1 lines. If the alternate output function of a pin is to be used, the direction of this pin must be programmed for output (DPx.y=`1'), except for some signals that are used directly after reset and are configured automatically. Otherwise the pin remains in the high-impedance state and is not effected by the alternate output function. The respective port latch should hold a `1', because its output is ANDed with the alternate output data (except for PWM output signals). If the alternate input function of a pin is used, the direction of the pin must be programmed for input (DPx.y=`0') if an external device is driving the pin. The input direction is the default after reset. If no external device is connected to the pin, however, one can also set the direction for this pin to output. In this case, the pin reflects the state of the port output latch. Thus, the alternate input function reads the value stored in the port output latch. This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. 63/185 Parallel ports ST10F271Z1 This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function. There are port lines, however, where the direction of the port line is switched automatically. For instance, in the multiplexed external bus modes of PORT0, the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data. Obviously, this cannot be done through instructions. In these cases, the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled. To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output. ) s ( ct There is one basic structure for all port lines with only an alternate input function. Port lines with only an alternate output function, however, have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode. u d o All port lines that are not used for these alternate functions may be used as general purpose I/O lines. r P e t e l o ) (s t c u d o r P e t e l o s b O 64/185 s b O ST10F271Z1 14 A/D converter A/D converter A 10-bit A/D converter with 16+8 multiplexed input channels and a sample and hold circuit is integrated on-chip. An automatic self-calibration adjusts the A/D converter module to process parameter variations at each reset event. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. The ST10F271 has 16+8 multiplexed input channels on Port 5 and Port 1. The selection between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the User Manual for a detailed description. ) s ( ct A different accuracy is guaranteed (Total Unadjusted Error) on Port 5 and Port 1 analog channels (with higher restrictions when overload conditions occur); in particular, Port 5 channels are more accurate than the Port 1 ones. Refer to Chapter 25: Electrical characteristics for details. u d o The A/D converter input bandwidth is limited by the achievable accuracy: supposing a maximum error of 0.5LSB (2mV) impacting the global TUE (TUE depends also on other causes), in worst case of temperature and process, the maximum frequency for a sine wave analog signal is around 7.5 kHz. Of course, to reduce the effect of the input signal variation on the accuracy down to 0.05LSB, the maximum input frequency of the sine wave shall be reduced to 800 Hz. r P e t e l o s b O If static signal is applied during sampling phase, series resistance shall not be greater than 20 k (this taking into account eventual input leakage). It is suggested to not connect any capacitance on analog input pins, in order to reduce the effect of charge partitioning (and consequent voltage drop error) between the external and the internal capacitance: in case an RC filter is necessary the external capacitance must be greater than 10 nF to minimize the accuracy impact. ) (s t c u Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than 16+8 analog input channels, the remaining channel inputs can be used as digital input port pins. d o r P e s b O t e l o The A/D converter of the ST10F271Z1 supports different conversion modes: Single channel single conversion: The analog level of the selected channel is sampled once and converted. The result of the conversion is stored in the ADDAT register. Single channel continuous conversion: The analog level of the selected channel is repeatedly sampled and converted. The result of the conversion is stored in the ADDAT register. Auto scan single conversion: The analog level of the selected channels are sampled once and converted. After each conversion the result is stored in the ADDAT register. The data can be transferred to the RAM by interrupt software management or using the powerful Peripheral Event Controller (PEC) data transfer. Auto scan continuous conversion: The analog level of the selected channels are repeatedly sampled and converted. The result of the conversion is stored in the ADDAT 65/185 A/D converter ST10F271Z1 register. The data can be transferred to the RAM by interrupt software management or using the PEC data transfer. Wait for ADDAT read mode: When using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated. Then, until the ADDAT register is read, the new result is stored in a temporary buffer and the conversion is on hold. Channel injection mode: When using continuous modes, a selected channel can be converted in between without changing the current operating mode. The 10-bit data of the conversion are stored in ADRES field of ADDAT2. The current continuous mode remains active after the single conversion is completed. A full calibration sequence is performed after a reset. This full calibration lasts up to 40.630 CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It compensates the capacitance mismatch, so the calibration procedure does not need any update during normal operation. ) s ( ct u d o No conversion can be performed during this time: the bit ADBSY shall be polled to verify when the calibration is over, and the module is able to start a convertion. r P e t e l o ) (s t c u d o r P e t e l o s b O 66/185 s b O ST10F271Z1 15 Serial channels Serial channels Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided by up to four serial interfaces: two asynchronous / synchronous serial channels (ASC0 and ASC1) and two high-speed synchronous serial channel (SSC0 and SSC1). Dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning. For transmission, reception and erroneous reception, separate interrupt vectors are provided for ASC0 and SSC0 serial channel. A more complex mechanism of interrupt sources multiplexing is implemented for ASC1 and SSC1 (XBus mapped). 15.1 ) s ( ct Asynchronous / synchronous serial interfaces The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial communication between the ST10F271Z1 and other microcontrollers, microprocessors or external peripherals. u d o 15.2 r P e t e l o ASCx in asynchronous mode In asynchronous mode, 8- or 9-bit data transfer, parity generation and the number of stop bits can be selected. Parity framing and overrun error detection is provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. Fullduplex communication up to 2M Bauds (at 64 MHz of fCPU) is supported in this mode. Table 40. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) ct S0BRS = `0', fCPU = 40 MHz Baud rate (baud) 1 250 000 u d o Deviation error Pr Reload value (hex) S0BRS = `1', fCPU = 40 MHz Baud rate (baud) Deviation error Reload value (hex) 0.0% / 0.0% 0000 / 0000 833 333 0.0% / 0.0% 0000 / 0000 +1.5% / -7.0% 000A / 000B 112 000 +6.3% / -7.0% 0006 / 0007 56 000 +1.5% / -3.0% 0015 / 0016 56 000 +6.3% / -0.8% 000D / 000E 38 400 +1.7% / -1.4% 001F / 0020 38 400 +3.3% / -1.4% 0014 / 0015 19 200 +0.2% / -1.4% 0040 / 0041 19 200 +0.9% / -1.4% 002A / 002B 9 600 +0.2% / -0.6% 0081 / 0082 9 600 +0.9% / -0.2% 0055 / 0056 4 800 +0.2% / -0.2% 0103 / 0104 4 800 +0.4% / -0.2% 00AC / 00AD 2 400 +0.2% / 0.0% 0207 / 0208 2 400 +0.1% / -0.2% 015A / 015B 1 200 0.1% / 0.0% 0410 / 0411 1 200 +0.1% / -0.1% 02B5 / 02B6 600 0.0% / 0.0% 0822 / 0823 600 +0.1% / 0.0% 056B / 056C 300 0.0% / 0.0% 1045 / 1046 300 0.0% / 0.0% 0AD8 / 0AD9 153 0.0% / 0.0% 1FE8 / 1FE9 102 0.0% / 0.0% 1FE8 / 1FE9 e t e l 112 000 o s b O ) (s s b O 67/185 Serial channels Table 41. ST10F271Z1 ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) S0BRS = `0', fCPU = 64 MHz S0BRS = `1', fCPU = 64 MHz Baud rate (baud) Deviation error Reload value (hex) Baud rate (baud) Deviation error Reload value (hex) 2 000 000 0.0% / 0.0% 0000 / 0000 1 333 333 0.0% / 0.0% 0000 / 0000 112 000 +1.5% / -7.0% 0010 / 0011 112 000 +6.3% / -7.0% 000A / 000B 56 000 +1.5% / -3.0% 0022 / 0023 56 000 +6.3% / -0.8% 0016 / 0017 38 400 +1.7% / -1.4% 0033 / 0034 38 400 +3.3% / -1.4% 0021 / 0022 19 200 +0.2% / -1.4% 0067 / 0068 19 200 +0.9% / -1.4% 0044 / 0045 9 600 +0.2% / -0.6% 00CF / 00D0 9 600 +0.9% / -0.2% 4 800 +0.2% / -0.2% 019F / 01A0 4 800 +0.4% / -0.2% 2 400 +0.2% / 0.0% 0340 / 0341 2 400 +0.1% / -0.2% 1 200 0.1% / 0.0% 0681 / 0682 1 200 +0.1% / -0.1% 600 0.0% / 0.0% 0D04 / 0D05 600 300 0.0% / 0.0% 1A09 / 1A0A 300 245 0.0% / 0.0% 1FE2 / 1FE3 163 t e l o 0114 / 0115 du ro P e ) s ( ct 0089 / 008A 022A / 015B 0456 / 0457 +0.1% / 0.0% 08AD / 08AE 0.0% / 0.0% 115B / 115C 0.0% / 0.0% 1FF2 / 1FF3 s b O Note: The deviation errors given in the Table 40 and Table 41 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency). 15.3 ASCx in synchronous mode ) (s t c u In synchronous mode, data is transmitted or received synchronously to a shift clock which is generated by the ST10F271Z1. Half-duplex communication up to 8 Mbaud (at 40 MHz of fCPU) is possible in this mode. d o r Table 42. P e ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) let S0BRS = `0', fCPU = 40 MHz so S0BRS = `1', fCPU = 40 MHz Baud rate (baud) Deviation error Reload value 5 000 000 0.0% / 0.0% 112 000 b O 68/185 Baud rate (baud) Deviation error Reload value 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000 +1.5% / -0.8% 002B / 002C 112 000 +2.6% / -0.8% 001C / 001D 56 000 +0.3% / -0.8% 0058 / 0059 56 000 +0.9% / -0.8% 003A / 003B 38 400 +0.2% / -0.6% 0081 / 0082 38 400 +0.9% / -0.2% 0055 / 0056 19 200 +0.2% / -0.2% 0103 / 0104 19 200 +0.4% / -0.2% 00AC / 00AD 9 600 +0.2% / 0.0% 0207 / 0208 9 600 +0.1% / -0.2% 015A / 015B 4 800 +0.1% / 0.0% 0410 / 0411 4 800 +0.1% / -0.1% 02B5 / 02B6 2 400 0.0% / 0.0% 0822 / 0823 2 400 +0.1% / 0.0% 056B / 056C 1 200 0.0% / 0.0% 1045 / 1046 1 200 0.0% / 0.0% 0AD8 / 0AD9 (hex) (hex) ST10F271Z1 Table 42. Serial channels ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) S0BRS = `0', fCPU = 40 MHz S0BRS = `1', fCPU = 40 MHz Baud rate (baud) Deviation error Reload value 15B2 / 15B3 600 0.0% / 0.0% 15B2 / 15B3 1FE8 / 1FE9 407 0.0% / 0.0% 1FFD / 1FFE Baud rate (baud) Deviation error Reload value 900 0.0% / 0.0% 612 0.0% / 0.0% Table 43. (hex) ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) S0BRS = `0', fCPU = 64 MHz S0BRS = `1', fCPU = 64 MHz Baud rate (baud) Deviation error Reload value 8 000 000 0.0% / 0.0% 112 000 ) s ( ct Reload value Baud rate (baud) Deviation error 0000 / 0000 5 333 333 0.0% / 0.0% +0.6% / -0.8% 0046 / 0047 112 000 +1.3% / -0.8% 56 000 +0.6% / -0.1% 008D / 008E 56 000 +0.3% / -0.8% 38 400 +0.2% / -0.3% 00CF / 00D0 38 400 +0.6% / -0.1% 0089 / 008A 19 200 +0.2% / -0.1% 019F / 01A0 19 200 +0.3% / -0.1% 0114 / 0115 9 600 +0.0% / -0.1% 0340 / 0341 9 600 +0.1% / -0.1% 022A / 022B 4 800 0.0% / 0.0% 0681 / 0682 4 800 0.0% / -0.1% 0456 / 0457 2 400 0.0% / 0.0% 0D04 / 0D05 2 400 0.0% / 0.0% 08AD / 08AE 1 200 0.0% / 0.0% 1A09 / 1A0A 1 200 0.0% / 0.0% 115B / 115C 977 0.0% / 0.0% 900 0.0% / 0.0% 1724 / 1725 652 0.0% / 0.0% 1FF2 / 1FF3 (hex) ) (s ct du Note: 1FFB / 1FFC u d o e t e ol s b O (hex) Pr 0000 / 0000 002E / 002F 005E / 005F o r P The deviation errors given in the Table 42 and Table 43 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency) e speed synchronous serial interfaces t High e ol 15.4 bs O (hex) The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible highspeed serial communication between the ST10F271Z1 and other microcontrollers, microprocessors or external peripherals. The SSCx supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSCx itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit Baud rate generator provides the SSCx with a separate serial clock signal. The serial channel SSCx has its own dedicated 16-bit Baud rate generator with 16-bit reload capability, allowing Baud rate generation independent from the timers. 69/185 Serial channels ST10F271Z1 Table 44 and Table 45 list some possible Baud rates against the required reload values and the resulting bit times for 40 MHz and 64 MHz CPU clock respectively. The maximum is anyway limited to 8 Mbaud. Table 44. SSC synchronous baud rate and reload values (fCPU = 40 MHz) Baud rate Bit time Reload value Reserved --- 0000h Can be used only with fCPU = 32 MHz (or lower) --- 0001h 6.6 Mbaud 150 ns 0002h 5 Mbaud 200 ns 0003h 2.5 Mbaud 400 ns 0007h 1 Mbaud 1 s 0013h 100 Kbaud 10 s 10 Kbaud 100 s 1 Kbaud 1 ms e t e l 306 baud Table 45. 3.26 ms Pr 07CFh 4E1Fh FF4Eh Reload value --- 0000h --- 0001h --- 0002h 125 ns 0003h 4 Mbaud 250 ns 0007h 1 Mbaud 1 s 001Fh 100 Kbaud 10 s 013Fh 10 Kbaud 100 s 0C7Fh 1 Kbaud 1 ms 7CFFh 489 baud 2.04 ms FF9Eh O ) s ( t c Can be used only with fCPU = 32 MHz (or lower) du Can be used only with fCPU = 48 MHz (or lower) o r P 8 Mbaud e t e l 70/185 00C7h Bit time Reserved O u d o SSC synchronous baud rate and reload values (fCPU = 64 MHz) Baud rate o s b o s b ) s ( ct ST10F271Z1 16 I2C interface I2C interface The integrated I2C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I2C Bus specification. The I2C Module can operate in slave mode, in master mode or in multi-master mode. It can receive and transmit data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s (both Standard and Fast I2C bus modes are supported). The module can generate three different types of interrupt: Requests related to bus events, like start or stop events, arbitration lost, etc. Requests related to data transmission Requests related to data reception ) s ( ct These requests are issued to the interrupt controller by three different lines, and identified as Error, Transmit, and Receive interrupt lines. u d o When the I2C module is enabled by setting bit XI2CEN in XPERCON register, pins P4.4 and P4.7 (where SCL and SDA are respectively mapped as alternate functions) are automatically configured as bidirectional open-drain: the value of the external pull-up resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin configuration. r P e t e l o When the I2C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O controlled by P4, DP4 and ODP4. s b O The speed of the I2C interface may be selected between Standard mode (0 to 100 kHz) and Fast I2C mode (100 to 400 kHz). ) (s t c u d o r P e t e l o s b O 71/185 CAN modules 17 ST10F271Z1 CAN modules The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active). It is based on the C-CAN specification. Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Because of duplication of the CAN controllers, the following adjustments are to be considered: Note: Same internal register addresses of both CAN controllers, but with base addresses differing in address bit A8; separate chip select for each CAN module. Refer to Chapter 4: Memory organization on page 20. The CAN1 transmit line (CAN1_TxD) is the alternate function of the Port P4.6 pin and the receive line (CAN1_RxD) is the alternate function of the Port P4.5 pin. The CAN2 transmit line (CAN2_TxD) is the alternate function of the Port P4.7 pin and the receive line (CAN2_RxD) is the alternate function of the Port P4.4 pin. Interrupt request lines of the CAN1 and CAN2 modules are connected to the XBUS interrupt lines together with other X-Peripherals sharing the four vectors. The CAN modules must be selected with corresponding CANxEN bit of XPERCON register before the bit XPEN of SYSCON register is set. The reset default configuration is: CAN1 enabled, CAN2 disabled. ) s ( ct u d o r P e t e l o s b O If one or both CAN modules is used, Port 4 cannot be programmed to output all 8 segment address lines. Thus, only four segment address lines can be used, reducing the external memory space to 5 Mbytes (1 Mbyte per CS line). ) (s t c 17.1 Configurationusupport d o r P e t e l o s b O It is possible that both CAN controllers are working on the same CAN bus, supporting together up to 64 message objects. In this configuration, both receive signals and both transmit signals are linked together when using the same CAN transceiver. This configuration is especially supported by providing open drain outputs for the CAN1_Txd and CAN2_TxD signals. The open drain function is controlled with the ODP4 register for port P4: in this way it is possible to connect together P4.4 with P4.5 (receive lines) and P4.6 with P4.7 (transmit lines configured to be configured as Open-Drain). The user is also allowed to map internally both CAN modules on the same pins P4.5 and P4.6. In this way, P4.4 and P4.7 may be used either as general purpose I/O lines, or used for I2C interface. This is possible by setting bit CANPAR of XMISC register. To access this register it is necessary to set bit XMISCEN of XPERCON register and bit XPEN of SYSCON register. 17.2 CAN bus configurations Depending on application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F271Z1 is able to support these two cases. 72/185 ST10F271Z1 CAN modules Single CAN bus The single CAN Bus multiple interfaces configuration may be implemented using two CAN transceivers as shown in Figure 13. Figure 13. Connection to single CAN bus via separate CAN transceivers XMISC.CANPAR = 0 CAN1 RX TX P4.5 CAN2 RX TX P4.6 P4.4 CAN Transceiver CAN_H ) s ( ct P4.7 CAN Transceiver u d o CAN bus CAN_L r P e t e l o The ST10F271Z1 also supports single CAN Bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Figure 14. Thanks to the OR-Wired Connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment. s b O Figure 14. Connection to single CAN bus via common CAN transceivers ct u d o +5V Pr 2.7kW s b O e t e ol ) (s CAN1 RX TX P4.5 XMISC.CANPAR = 0 CAN2 RX TX P4.6 P4.4 OD P4.7 OD CAN Transceiver CAN_H CAN_L CAN bus OD = Open Drain output Multiple CAN bus The ST10F271Z1 provides two CAN interfaces to support such kind of bus configuration as shown in Figure 15. 73/185 CAN modules ST10F271Z1 Figure 15. Connection to two different CAN buses (e.g. for gateway application) XMISC.CANPAR = 0 CAN1 RX TX P4.5 CAN2 RX TX P4.6 P4.4 CAN Transceiver P4.7 CAN Transceiver CAN_H CAN_H CAN_L ) s ( ct CAN_L CAN bus 1 CAN bus 2 u d o Parallel Mode r P e In addition to previous configurations, a parallel mode is supported. This is shown in Figure 16. t e l o Figure 16. Connection to one CAN bus with internal parallel mode enabled s b O CAN1 RX TX ) (s CAN2 RX TX XMISC.CANPAR = 1 (Both CAN enabled) t c u d o r P e let o s b O 74/185 P4.5 P4.6 P4.4 P4.7 CAN Transceiver CAN_H CAN_L CAN bus 1. P4.4 and P4.7 when not used as CAN functions can be used as general purpose I/O while they cannot be used as external bus address lines. ST10F271Z1 18 Real-time clock Real-time clock The Real-Time Clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that it can be kept on running even in Idle or power-down mode (if enabled to). Registers access is implemented onto the XBUS. This module is designed with the following characteristics: Generation of the current time and date for the system Cyclic time based interrupt, on Port2 external interrupts every 'RTC basic clock tick' and after n 'RTC basic clock ticks' (n is programmable) if enabled 58-bit timer for long term measurement Capability to exit the ST10 chip from power-down mode (if PWDCFG of SYSCON set) after a programmed delay ) s ( ct u d o The real-time clock is based on two main blocks of counters. The first block is a prescaler which generates a basic reference clock (for example a 1 second period). This basic reference clock is coming out of a 20-bit DIVIDER. This 20-bit counter is driven by an input clock derived from the on-chip CPU clock, pre-divided by a 1/64 fixed counter. This 20-bit counter is loaded at each basic reference clock period with the value of the 20-bit PRESCALER register. The value of the 20-bit RTCP register determines the period of the basic reference clock. r P e t e l o s b O A timed interrupt request (RTCSI) may be sent on each basic reference clock period. The second block of the RTC is a 32-bit counter that may be initialized with the current system time. This counter is driven with the basic reference clock signal. In order to provide an alarm function the contents of the counter is compared with a 32-bit alarm register. The alarm register may be loaded with a reference date. An alarm interrupt request (RTCAI), may be generated when the value of the counter matches the alarm register. ) (s t c u The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external interrupt via EXISEL register of port 2 and wake-up the ST10 chip when running powerdown mode. Using the RTCOFF bit of RTCCON register, the user may switch off the clock oscillator when entering the power-down mode. d o r P e s b O t e l o The last function implemented in the RTC is to switch off the main on-chip oscillator and the 32 kHz on chip oscillator if the ST10 enters the power-down mode, so that the chip can be fully switched off (if RTC is disabled). At power on, and after Reset phase, if the presence of a 32 kHz oscillation on XTAL3 / XTAL4 pins is detected, then the RTC counter is driven by this low frequency reference clock: when power-down mode is entered, the RTC can either be stopped or left running, and in both the cases the main oscillator is turned off, reducing the power consumption of the device to the minimum required to keep on running the RTC counter and relative reference oscillator. This is valid also if Stand-by mode is entered (switching off the main supply VDD), since both the RTC and the low power oscillator (32 kHz) are biased by the VSTBY. Vice versa, when at power on and after Reset, the 32 kHz is not present, the main oscillator drives the RTC counter, and since it is powered by the main power supply, it cannot be maintained running in Stand-by mode, while in power-down mode the main oscillator is maintained running to provide the reference to the RTC module (if not disabled). 75/185 Watchdog timer 19 ST10F271Z1 Watchdog timer The Watchdog timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Therefore, the chip start-up procedure is always monitored. The software must be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset. ) s ( ct Each of the different reset sources is indicated in the WDTCON register: Watchdog timer reset in case of an overflow Software reset in case of execution of the SRST instruction Short, long and Power-On Reset in case of hardware reset (and depending of reset pulse duration and RPD pin configuration) u d o r P e t e l o The indicated bits are cleared with the EINIT instruction. The source of the reset can be identified during the initialization phase. The Watchdog timer is 16-bit, clocked with the system clock divided by 2 or 128. The high Byte of the watchdog timer register can be set to a pre-specified reload value (stored in WDTREL). ) (s s b O Each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced t c u The Table 46 and Table 47 show the watchdog time range for 40 MHz and 64 MHz CPU clock respectively. d o r Table 46. P e WDTREL reload value (fCPU = 40 MHz) Prescaler for fCPU = 40 MHz Reload value in WDTREL t e l o s b O Table 47. 2 (WDTIN = `0') 128 (WDTIN = `1') FFh 12.8 s 819.2 s 00h 3.277 ms 209.7 ms WDTREL reload value (fCPU = 64 MHz) Prescaler for fCPU = 64 MHz Reload value in WDTREL 76/185 2 (WDTIN = `0') 128 (WDTIN = `1') FFh 8 s 512 s 00h 2.048 ms 131.1 ms ST10F271Z1 20 System reset System reset System reset initializes the MCU in a predefined state. There are six ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 48. Table 48. Reset event definition Reset source Power-on reset Flag RPD status PONR Low Power-on Low tRSTIN > 1) High tRSTIN > (1032 + 12) TCL + max(4 TCL, 500 ns) tRSTIN > max(4 TCL, 500 ns) tRSTIN (1032 + 12) TCL + max(4 TCL, 500 ns) Asynchronous hardware reset LHWR Synchronous long hardware reset Synchronous short hardware reset SHWR High Watchdog timer reset WDTR 3) SWR 3) Software reset 20.1 Conditions ) s ( ct u d o r P e WDT overflow t e l o SRST instruction execution 1) RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0. 2) See next Section 20.1 for more details on minimum reset pulse duration. 3) The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to Sections 20.4, 20.5 and 20.6). ) (s s b O t c u Input filter d o r On RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all the spikes shorter than 50 ns. On the other side, a valid pulse shall be longer than 500 ns to grant that ST10 recognizes a reset command. In between 50 ns and 500 ns a pulse can either be filtered or recognized as valid, depending on the operating conditions and process variations. P e t e l o s b O 20.2 For this reason all minimum durations mentioned in this Chapter for the different kind of reset events shall be carefully evaluated taking into account of the above requirements. In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input reset pulse duration, the operating frequency is a key factor. Examples: For a CPU clock of 64 MHz, 4 TCL is 31.25 ns, so it would be filtered. In this case the minimum becomes the one imposed by the filter (that is 500 ns). For a CPU clock of 4 MHz, 4 TCL is 500 ns. In this case the minimum from the formula is coherent with the limit imposed by the filter. Asynchronous reset An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low level. Then the ST10F271Z1 is immediately (after the input filter delay) forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it aborts 77/185 System reset ST10F271Z1 all internal/external bus cycles, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high Port0 pins. Note: If an asynchronous reset occurs during a read or write phase in internal memories, the content of the memory itself could be corrupted: to avoid this, synchronous reset usage is strongly recommended. Power-on reset The asynchronous reset must be used during the power-on of the device. Depending on crystal or resonator frequency, the on-chip oscillator needs about 1ms to 10ms to stabilize (Refer to Electrical Characteristics Section), with an already stable VDD. The logic of the ST10F271Z1 does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the device clock signal is stabilized and the system configuration value on Port0 is settled. ) s ( ct u d o At Power-on it is important to respect some additional constraints introduced by the start-up phase of the different embedded modules. r P e In particular the on-chip voltage regulator needs at least 1ms to stabilize the internal 1.8V for the core logic: this time is computed from when the external reference (VDD) becomes stable (inside specification range, that is at least 4.5 V). This is a constraint for the application hardware (external voltage regulator): the RSTIN pin assertion shall be extended to guarantee the voltage regulator stabilization. t e l o s b O A second constraint is imposed by the embedded Flash. When booting from internal memory, starting from RSTIN releasing, it needs a maximum of 1 ms for its initialization: before that, the internal reset (RST signal) is not released, so the CPU does not start code execution in internal memory. ) (s t c u Note: This is not true if external memory is used (pin EA held low during reset phase). In this case, once RSTIN pin is released, and after few CPU clock (Filter delay plus 3...8 TCL), the internal reset signal RST is released as well, so the code execution can start immediately after. Obviously, an eventual access to the data in internal Flash is forbidden before its initialization phase is completed: an eventual access during starting phase will return FFFFh (just at the beginning), while later 009Bh (an illegal opcode trap can be generated). d o r P e t e l o s b O At Power-on, the RSTIN pin shall be tied low for a minimum time that includes also the startup time of the main oscillator (tSTUP = 1ms for resonator, 10 ms for crystal) and PLL synchronization time (tPSUP = 200 s): this means that if the internal Flash is used, the RSTIN pin could be released before the main oscillator and PLL are stable to recover some time in the start-up phase (Flash initialization only needs stable V18, but does not need stable system clock since an internal dedicated oscillator is used). Warning: 78/185 It is recommended to provide the external hardware with a current limitation circuitry. This is necessary to avoid permanent damages of the device during the power-on transient, when the capacitance on V18 pin is charged. For the on-chip voltage regulator functionality 10nF are sufficient: anyway, a maximum of 100 nF on V18 pin should not generate problems of over-current (higher value is allowed if current is limited by the external hardware). External current limitation is anyway recommended also to avoid risks of damage in case of temporary short between ST10F271Z1 System reset V18 and ground: the internal 1.8V drivers are sized to drive currents of several tens of Ampere, so the current shall be limited by the external hardware. The limit of current is imposed by power dissipation considerations (Refer to Electrical Characteristics Section). In next Figures 17 and 18 Asynchronous Power-on timing diagrams are reported, respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded Flash module when selected. Note: Never power the device without keeping RSTIN pin grounded: the device could enter in unpredictable states, risking also permanent damages. ) s ( ct Figure 17. Asynchronous power-on RESET (EA = 1) 1.2 ms (for resonator oscillation + PLL stabilization) 10.2 ms (for crystal oscillation + PLL stabilization) u d o r P e 1 ms (for on-chip VREG stabilization) VDD let o s b V18 XTAL1 O ) RPD s ( t c RSTIN u d o RSTF (After Filter) r P e t e l o O bs 2 TCL ... 50 ns 500 ns 3..4 TCL not t. P0[15:13] transparent P0[12:2] transparent not t. P0[1:0] not transparent not t. not t. 7 TCL IBUS-CS (Internal) 1 ms FLARST RST Latching point of Port0 for system start-up configuration 79/185 System reset ST10F271Z1 Figure 18. Asynchronous power-on RESET (EA = 0) 1.2 ms (for resonator oscillation + PLL stabilization) 10.2 ms (for crystal oscillation + PLL stabilization) 1 ms (for on-chip VREG stabilization) VDD 3..8 TCL1) V18 ... XTAL1 ) s ( ct RPD RSTIN 50 ns 500 ns RSTF (After Filter) 3..4 TCL P0[15:13] transparent P0[12:2] transparent u d o r P e t e l o s b O not transparent P0[1:0] ) (s ALE t c u RST od r P e not t. not t. not t. 8 TCL Latching point of Port0 for system start-up configuration Note 1. 3 to 8 TCL depending on clock source selection. t e l o Hardware reset s b O 80/185 The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggered by the hardware of the application. Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figures 30, 31 and 32. It occurs when RSTIN is low and RPD is detected (or becomes) low as well. ST10F271Z1 System reset Figure 19. Asynchronous hardware reset (EA = 1) 1) 2 TCL RPD 50 ns 500 ns RSTIN 50 ns 500 ns RSTF (After Filter) 3..4 TCL P0[15:13] not transparent transparent P0[12:2] not transparent transparent not t. ) s ( ct not t. u d o not transparent P0[1:0] not t. r P e IBUS-CS (internal) not t. 7 TCL 1 ms t e l o FLARST RST ) (s s b O Latching point of Port0 for system start-up configuration Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed) Longer than 500 ns to take into account of Input Filter on RSTIN pin t c u d o r P e t e l o s b O 81/185 System reset ST10F271Z1 Figure 20. Asynchronous hardware reset (EA = 0) 1) 3..8 TCL2) RPD 50 ns 500 ns RSTIN 50 ns 500 ns RSTF (After Filter) 3..4 TCL P0[15:13] not transparent transparent not t. P0[12:2] not transparent transparent not t. ) s ( ct u d o not transparent P0[1:0] not t. 8 TCL r P e ALE t e l o RST s b O Latching point of Port0 for system start-up configuration Note 1. Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed) Longer than 500ns to take into account of Input Filter on RSTIN pin Note 2. 3 to 8 TCL depending on clock source selection. ) (s t c u Exit from asynchronous reset state d o r When the RSTIN pin is pulled high, the device restarts: as already mentioned, if internal Flash is used, the restarting occurs after the embedded Flash initialization routine is completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F271Z1 starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of asynchronous Hardware Reset sequence are summarized in Figure 19 and Figure 20. P e t e l o s b O 20.3 Synchronous reset (warm reset) A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high level. In order to properly activate the internal reset logic of the device, the RSTIN pin must be held low, at least, during 4 TCL (2 periods of CPU clock): refer also to Section 20.1 for details on minimum reset pulse duration. The I/O pins are set to high impedance and RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of 12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are cancelled and the current internal access cycle if any is completed. External bus cycle is aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON register was previously set by software. Note that this bit is always cleared on power-on or after a reset sequence. 82/185 ST10F271Z1 System reset Short and long synchronous reset Once the first maximum 16 TCL are elapsed (4+12 TCL), the internal reset sequence starts. It is 1024 TCL cycles long: at the end of it, and after other 8 TCL the level of RSTIN is sampled (after the filter, see RSTF in the drawings): if it is already at high level, only Short Reset is flagged (Refer to Chapter 19: Watchdog timer for details on reset flags); if it is recognized still low, the Long reset is flagged as well. The major difference between Long and Short reset is that during the Long reset, also P0(15:13) become transparent, so it is possible to change the clock options. Warning: In case of a short pulse on RSTIN pin, and when Bidirectional reset is enabled, the RSTIN pin is held low by the internal circuitry. At the end of the 1024 TCL cycles, the RTSIN pin is released, but due to the presence of the input analog filter the internal input reset signal (RSTF in the drawings) is released later (from 50 to 500 ns). This delay is in parallel with the additional 8 TCL, at the end of which the internal input reset line (RSTF) is sampled, to decide if the reset event is Short or Long. In particular: ) s ( ct u d o r P e t e l o If 8 TCL > 500 ns (FCPU < 8 MHz), the reset event is always recognized as Short If 8 TCL < 500 ns (FCPU > 8 MHz), the reset event could be recognized either as Short or Long, depending on the real filter delay (between 50 and 500 ns) and the CPU frequency (RSTF sampled High means Short reset, RSTF sampled Low means Long reset). Note that in case a Long Reset is recognized, once the 8 TCL are elapsed, the P0(15:13) pins becomes transparent, so the system clock can be re-configured. The port returns not transparent 3-4 TCL after the internal RSTF signal becomes high. ) (s s b O t c u The same behavior just described, occurs also when unidirectional reset is selected and RSTIN pin is held low till the end of the internal sequence (exactly 1024 TCL + max 16 TCL) and released exactly at that time. Note: d o r P e When running with CPU frequency lower than 40 MHz, the minimum valid reset pulse to be recognized by the CPU (4 TCL) could be longer than the minimum analog filter delay (50ns); so it might happen that a short reset pulse is not filtered by the analog input filter, but on the other hand it is not long enough to trigger a CPU reset (shorter than 4 TCL): this would generate a Flash reset but not a system reset. In this condition, the Flash answers always with FFFFh, which leads to an illegal opcode and consequently a trap event is generated. s b O t e l o Exit from synchronous reset state The reset sequence is extended until RSTIN level becomes high. Besides, it is internally prolonged by the Flash initialization when EA=1 (internal memory selected). Then, the code execution restarts. The system configuration is latched from Port0, and ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F271Z1 starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of synchronous reset sequence are summarized in Figures 21 and 22 where a Short Reset event is shown, with particular highlighting on the fact that it can degenerate into Long Reset: the two figures show the behavior when booting from internal or external memory respectively. Figures 23 and 24 reports the timing of a typical synchronous Long Reset, again when booting from internal or external memory. 83/185 System reset ST10F271Z1 Synchronous reset and RPD pin Whenever the RSTIN pin is pulled low (by external hardware or as a consequence of a Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance (if any) on RPD pin is slowly discharged through the internal weak pull-down. If the voltage level on RPD pin reaches the input low threshold (around 2.5 V), the reset event becomes immediately asynchronous. In case of hardware reset (short or long) the situation goes immediately to the one illustrated in Figure 19. There is no effect if RPD comes again above the input threshold: the asynchronous reset is completed coherently. To grant the normal completion of a synchronous reset, the value of the capacitance shall be big enough to maintain the voltage on RPD pin sufficient high along the duration of the internal reset sequence. For a software or watchdog reset events, an active synchronous reset is completed regardless of the RPD status. ) s ( ct It is important to highlight that the signal that makes RPD status transparent under reset is the internal RSTF (after the noise filter). u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 84/185 s b O ST10F271Z1 System reset Figure 21. Synchronous short / long hardware RESET (EA = 1) 4 TCL4) 12 TCL < 1032 TCL 1) RSTIN 50 ns 500 ns 3) 50 ns 500 ns 50 ns 500 ns 2 TCL RSTF (After Filter) P0[15:13] not transparent P0[12:2] not t. P0[1:0] transparent not t. not transparent not t. 7 TCL u d o IBUS-CS (Internal) 1 ms r P e FLARST t e l o 1024 TCL RST bs RSTOUT O ) RPD s ( t c 200A Discharge ) s ( ct 8 TCL At this time RSTF is sampled HIGH or LOW so it is SHORT or LONG reset 2) VRPD > 2.5V Asynchronous Reset not entered u d o Notes: 1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration. r P e 2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), s b O t e l o the asynchronous reset is then immediately entered. 3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. 4. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1). 85/185 System reset ST10F271Z1 Figure 22. Synchronous short / long hardware reset (EA = 0) 4 TCL5) 12 TCL RSTIN 1) 50 ns 500 ns < 1032 TCL 4) 50 ns 500 ns 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent P0[12:2] not t. P0[1:0] transparent not t. not transparent not t. u d o 3..8 TCL3) ALE 1024 TCL t e l o RSTOUT )- RPD 200mA Discharge u d o s b O 86/185 s ( t c s b O At this time RSTF is sampled HIGH or LOW so it is SHORT or LONG reset 2) VRPD > 2.5V Asynchronous Reset not entered 1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration. 2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation) the asynchronous reset is then immediately entered. 3. 3 to 8 TCL depending on clock source selection. 4. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. 5. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1). r P e t e l o 8 TCL r P e 8 TCL RST Notes: ) s ( ct ST10F271Z1 System reset Figure 23. Synchronous long hardware reset (EA = 1) 4 TCL2) 12 TCL 1024+8 TCL RSTIN 50 ns 500 ns 50 ns 500 ns 50 ns 500 ns RSTF (After Filter) 2 TCL P0[15:13] 3..4 TCL transparent P0[12:2] not transparent not t. P0[1:0] not t. transparent not t. not transparent not t. 7 TCL IBUS-CS (Internal) FLARST t e l o 1024+8 TCL RST bs O ) RSTOUT s ( t c RPD u d o 200A Discharge At this time RSTF is sampled LOW so it is definitely LONG reset 1) VRPD > 2.5V Asynchronous Reset not entered r P e let o s b u d o r P e 1 ms Notes: ) s ( ct 1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. Even if RPD returns above the threshold, the reset is defnitively taken as asynchronous. 2. Minimum RSTIN low pulse duration shall also be longer than 500 ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1). O 87/185 System reset ST10F271Z1 Figure 24. Synchronous long hardware reset (EA = 0) 4 TCL2) 12 TCL 1024+8 TCL RSTIN 50 ns 500 ns 50 ns 500 ns 50 ns 500 ns RSTF (After Filter) 3..4 TCL P0[15:13] not transparent not t. transparent P0[12:2] transparent P0[1:0] not transparent ) s ( ct not t. not t. u d o 3) 3..8 TCL 8 TCL r P e ALE 1024+8 TCL t e l o RST At this time RSTF is sampled LOW so it is LONG reset RSTOUT ) (s RPD 200A Discharge s b O 1) VRPD > 2.5V Asynchronous Reset not entered t c u Notes: d o r 1. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5 V for 5 V operation), the asynchronous reset is then immediately entered. 2. Minimum RSTIN low pulse duration shall also be longer than 500 ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1). 3. 3 to 8 TCL depending on clock source selection. P e t e l o s b O 20.4 Software reset A software reset sequence can be triggered at any time by the protected SRST (software reset) instruction. This instruction can be deliberately executed within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals system failure. On execution of the SRST instruction, the internal reset sequence is started. The microcontroller behavior is the same as for a synchronous short reset, except that only bits P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits P0.7...P0.2 are cleared (that is written at `1'). A Software reset is always taken as synchronous: there is no influence on Software Reset behavior with RPD status. In case Bidirectional Reset is selected, a Software Reset event pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low even though Bidirectional Reset is selected. 88/185 ST10F271Z1 System reset Refer to next Figures 25 and 26 for unidirectional SW reset timing, and to Figures 27, 28 and 29 for bidirectional. 20.5 Watchdog timer reset When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after the programmed wait states. When READY is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. Then the internal reset sequence is started. ) s ( ct Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared (that is written at `1'). u d o A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled low even though Bidirectional Reset is selected. r P e t e l o Refer to next Figures 25 and 26 for unidirectional SW reset timing, and to Figures 27, 28 and 29 for bidirectional. s b O Figure 25. SW / WDT unidirectional reset (EA = 1) ) (s RSTIN ct P0[15:13] u d o r P e s b O t e l o 2 TCL not transparent P0[12:8] transparent P0[7:2] not transparent P0[1:0] not transparent not t. not t. 7 TCL IBUS-CS (Internal) 1 ms FLARST 1024 TCL RST RSTOUT 89/185 System reset ST10F271Z1 Figure 26. SW / WDT unidirectional reset (EA = 0) RSTIN P0[15:13] not transparent P0[12:8] transparent P0[7:2] not transparent P0[1:0] not transparent not t. ) s ( ct not t. 8 TCL ALE u d o 1024 TCL r P e RST t e l o RSTOUT 20.6 Bidirectional reset ) (s s b O As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization routine, until the protected EINIT instruction (End of Initialization) is completed. t c u d o r The Bidirectional Reset function is useful when external devices require a reset signal but cannot be connected to RSTOUT pin, because RSTOUT signal lasts during initialization. It is, for instance, the case of external memory running initialization routine before the execution of EINIT instruction. P e t e l o s b O 90/185 Bidirectional reset function is enabled by setting bit 3 (BDRSTEN) in SYSCON register. It only can be enabled during the initialization routine, before EINIT instruction is completed. When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal, for the duration of the internal reset sequence (synchronous/asynchronous hardware, synchronous software and synchronous watchdog timer resets). At the end of the internal reset sequence the pull down is released and: After a Short Synchronous Bidirectional Hardware Reset, if RSTF is sampled low 8 TCL periods after the internal reset sequence completion (refer to Figure 21 and Figure 22), the Short Reset becomes a Long Reset. On the contrary, if RSTF is sampled high the device simply exits reset state. After a Software or Watchdog Bidirectional Reset, the device exits from reset. If RSTF remains still low for at least 4 TCL periods (minimum time to recognize a Short Hardware reset) after the reset exiting (refer to Figure 27 and Figure 28), the Software or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains low for less than 4 TCL, the device simply exits reset state. ST10F271Z1 System reset The Bidirectional reset is not effective in case RPD is held low, when a Software or Watchdog reset event occurs. On the contrary, if a Software or Watchdog Bidirectional reset event is active and RPD becomes low, the RSTIN pin is immediately released, while the internal reset sequence is completed regardless of RPD status change (1024 TCL). Note: The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of SYSCON is cleared). To be activated again it must be enabled during the initialization routine. WDTCON flags Similarly to what already highlighted in the previous section when discussing about Short reset and the degeneration into Long reset, similar situations may occur when Bidirectional reset is enabled. The presence of the internal filter on RSTIN pin introduces a delay: when RSTIN is released, the internal signal after the filter (see RSTF in the drawings) is delayed, so it remains still active (low) for a while. It means that depending on the internal clock speed, a short reset may be recognized as a long reset: the WDTCON flags are set accordingly. ) s ( ct u d o r P e Besides, when either Software or Watchdog bidirectional reset events occur, again when the RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal (after the filter) remains low for a while, and depending on the clock frequency it is recognized high or low: 8TCL after the completion of the internal sequence, the level of RSTF signal is sampled, and if recognized still low a hardware reset sequence starts, and WDTCON will flag this last event, masking the previous one (Software or Watchdog reset). Typically, a short hardware reset is recognized, unless the RSTIN pin (and consequently internal signal RSTF) is sufficiently held low by the external hardware to inject a long hardware reset. After this occurrence, the initialization routine is not able to recognize a software or watchdog bidirectional reset event, since a different source is flagged inside WDTCON register. This phenomenon does not occur when internal Flash is selected during reset (EA = 1), since the initialization of the Flash itself extend the internal reset duration well beyond the filter delay. t e l o ) (s s b O t c u d o r Next Figures 27, 28 and 29 summarize the timing for software and watchdog timer bidirectional reset events: In particular Figure 29 shows the degeneration into hardware reset. P e t e l o s b O 91/185 System reset ST10F271Z1 Figure 27. SW / WDT bidirectional RESET (EA=1) RSTIN 50 ns 500 ns 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent P0[12:8] transparent P0[7:2] not transparent P0[1:0] not transparent not t. u d o 2 TCL IBUS-CS (Internal) r P e 1 ms FLARST t e l o 1024 TCL RST RSTOUT t c u ) (s d o r P e t e l o s b O 92/185 s b O ) s ( ct not t. 7 TCL ST10F271Z1 System reset Figure 28. SW / WDT bidirectional reset (EA = 0) RSTIN 50 ns 500 ns 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent P0[12:8] transparent P0[7:2] not transparent P0[1:0] not transparent not t. u d o not t. r P e ALE 8 TCL t e l o 1024 TCL RST bs RSTOUT ) s ( ct At this time RSTF is sampled HIGH so SW or WDT Reset is flagged in WDTCON O ) s ( t c u d o r P e t e l o s b O 93/185 System reset ST10F271Z1 Figure 29. SW / WDT bidirectional reset (EA=0) followed by a HW RESET RSTIN 50 ns 500 ns 50 ns 500 ns RSTF (After Filter) P0[15:13] not transparent P0[12:8] transparent P0[7:2] not transparent P0[1:0] not transparent not t. r P e t e l o 1024 TCL RST bs RSTOUT 20.7 Reset circuitry O ) u d o not t. ALE ) s ( ct 8 TCL At this time RSTF is sampled LOW so HW Reset is entered s ( t c u d o Internal reset circuitry is described in Figure 32. The RSTIN pin provides an internal pull-up resistor of 50 k to 250 k (The minimum reset time must be calculated using the lowest value). r P e t e l o It also provides a programmable (BDRSTEN bit of SYSCON register) pull-down to output internal reset state signal (synchronous reset, watchdog timer reset or software reset). bs O This bidirectional reset function is useful in applications where external devices require a reset signal but cannot be connected to RSTOUT pin. This is the case of an external memory running codes before EINIT (end of initialization) instruction is executed. RSTOUT pin is pulled high only when EINIT is executed. The RPD pin provides an internal weak pull-down resistor which discharges external capacitor at a typical rate of 200 A. If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any capacitor connected on RPD pin. The simplest way to reset the ST10F271Z1 is to insert a capacitor C1 between RSTIN pin and VSS, and a capacitor between RPD pin and VSS (C0) with a pull-up resistor R0 between RPD pin and VDD. The input RSTIN provides an internal pull-up device equalling a resistor of 50 k to 250 k (the minimum reset time must be determined by the lowest value). Select C1 that produce a sufficient discharge time to permit the internal or external oscillator and / or internal PLL and the on-chip voltage regulator to stabilize. 94/185 ST10F271Z1 System reset To ensure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long period of time to stabilize, an asynchronous hardware reset is required during power-up. For this reason, it is recommended to connect the external R0-C0 circuit shown in Figure 30 to the RPD pin. On power-up, the logical low level on RPD pin forces an asynchronous hardware reset when RSTIN is asserted low. The external pull-up R0 will then charge the capacitor C0. Note that an internal pull-down device on RPD pin is turned on when RSTIN pin is low, and causes the external capacitor (C0) to begin discharging at a typical rate of 100-200A. With this mechanism, after power-up reset, short low pulses applied on RSTIN produce synchronous hardware reset. If RSTIN is asserted longer than the time needed for C0 to be discharged by the internal pull-down device, then the device is forced in an asynchronous reset. This mechanism insures recovery from very catastrophic failure. ) s ( ct Figure 30. Minimum external reset circuitry RSTOUT RSTIN a) Hardware Reset t e l o VCC s b O R0 ) (s t c u r P e + C1 RPD u d o External Hardware + b) For Power-up Reset (and Interruptible Power-down mode) C0 ST10F271Z1 d o r The minimum reset circuit of Figure 30 is not adequate when the RSTIN pin is driven from the ST10F271Z1 itself during software or watchdog triggered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above VIL after the end of the internal reset sequence, and thus will trigger an asynchronous reset sequence. P e s b O t e l o Figure 31 shows an example of a reset circuit. In this example, R1-C1 external circuit is only used to generate power-up or manual reset, and R0-C0 circuit on RPD is used for power-up reset and to exit from power-down mode. Diode D1 creates a wired-OR gate connection to the reset pin and may be replaced by open-collector Schmitt trigger buffer. Diode D2 provides a faster cycle time for repetitive power-on resets. R2 is an optional pull-up for faster recovery and correct biasing of TTL open collector drivers. 95/185 System reset ST10F271Z1 Figure 31. System reset circuit VDD VDD R2 External Hardware R1 D2 RSTIN + VDD D1 C1 External Reset Source o.d. ) s ( ct R0 Open Drain Inverter RPD u d o + C0 ST10F271Z1 r P e t e l o Figure 32. Internal (simplified) reset circuitry EINIT Instruction s b O Clr Q RSTOUT Set ct ) (s e t e ol bs O u d o Pr Internal Reset Signal Reset State Machine Clock VDD SRST instruction watchdog overflow Trigger RSTIN Clr BDRSTEN Reset Sequence (512 CPU clock cycles) VDD Asynchronous Reset RPD From/to Exit Powerdown Circuit 96/185 Weak Pulldown (~200A) ST10F271Z1 20.8 System reset Reset application examples Next two timing diagrams (Figure 33 and Figure 34) provides additional examples of bidirectional internal reset events (software and watchdog) including in particular the external capacitances charge and discharge transients (refer also to Figure 31 for the external circuit scheme). not transparent transparent Latching point Latching point Latching point not transparent not transparent not transparent P0[1:0] not transparent P0[7:2] not transparent P0[12:8] P0[15:13] 04h RST VIL RPD not transparent 4 TCL Tfilter RST < 500 ns RSTF ideal VIH VIL RSTIN RSTOUT s b O 1024 TCL (12.8 us) P e t e l o < 4 TCL 0Ch d o r transparent t c u WDTCON [5:0] 1 ms (C1 charge) ) (s s b O ) s ( ct u d o r P e t e l o transparent Tfilter RST < 500 ns 1Ch 3..8 TCL Latching point not transparent EINIT 00h Figure 33. Example of software or watchdog bidirectional reset (EA = 1) 97/185 s b O 98/185 VIL P0[1:0] not transparent not transparent 0Ch transparent Tfilter RST < 500 ns transparent r P e P0[7:2] 4 TCL s b O not transparent not transparent 1 ms (C1 charge) t e l o P0[12:8] P0[15:13] t c u Tfilter RST < 500 ns 04h ) (s WDTCON [5:0] RST RPD VIL VIH d o r RSTF ideal RSTIN t e l o RSTOUT P e 1024 TCL (12.8 us) < 4 TCL 1Ch u d o transparent Latching point Latching point not transparent not transparent not transparent not transparent Latching point Latching point 3..8 TCL 00h EINIT System reset ST10F271Z1 Figure 34. Example of software or watchdog bidirectional reset (EA = 0) ) s ( ct ST10F271Z1 20.9 System reset Reset summary A summary of the different reset events is reported in the table below. o s b O Long hardware reset (synchronous) LHWR SHWR SWR WDTR e t e l PONR Short hardware reset (synchronous) (1) WDTCON flags 1 1 1 1 0 1 1 1 0 0 1 1 1 0 - 0 1 1 1 0 - 0 1 1 1 0 - 0 1 1 1 0 1032 + 12 TCL + max(4 TCL, 500ns) 0 0 1 1 0 max (4 TCL, 500 ns) 1032 + 12 TCL + max(4 TCL, 500ns) 0 0 1 1 0 max (4 TCL, 500 ns) 1032 + 12 TCL + max(4 TCL, 500ns) 0 0 1 1 0 0 0 1 1 0 min max - - 1 0 0 N Asynch. 1 ms (VREG) 1.2 ms (Reson. + PLL) 10.2 ms (Crystal + PLL) 0 1 N Asynch. 1 ms (VREG) 1 x x FORBIDDEN x x Y NOT APPLICABLE 0 0 N Asynch. 500 ns 0 1 N Asynch. 500 ns 0 0 Y Asynch. 500 ns 0 1 Y Asynch. 500 ns 1 0 N Synch. 1 1 N Synch. 1 0 Y c u d Power-on reset Hardware reset (asynchronous) RSTIN Synch. asynch. Bidir Event EA Reset event RPD Table 49. o r P 1 1 Y -O max (4 TCL, 500 ns) ) s ( t r P e - let o s b Synch. u d o ) s ( ct Activated by internal logic for 1024 TCL max (4 TCL, 500 ns) Synch. 1032 + 12 TCL + max(4 TCL, 500ns) Activated by internal logic for 1024 TCL 1 0 N Synch. 1032 + 12 TCL + max(4 TCL, 500ns) - 0 1 1 1 0 1 1 N Synch. 1032 + 12 TCL + max(4 TCL, 500ns) - 0 1 1 1 0 1032 + 12 TCL + max(4 TCL, 500 ns) 0 1 1 1 0 0 1 1 1 0 1 0 Y Synch. Activated by internal logic only for 1024 TCL 1 1 Y Synch. 1032 + 12 TCL + max(4 TCL, 500 ns) - Activated by internal logic only for 1024 TCL 99/185 System reset SHWR SWR WDTR Synch. asynch. LHWR Watchdog reset (2) WDTCON flags PONR Software reset (2) RSTIN EA Event Bidir Reset event (continued) RPD Table 49. ST10F271Z1 x 0 N Synch. Not activated 0 0 0 1 0 x 0 N Synch. Not activated 0 0 0 1 0 0 1 Y Synch. Not activated 0 0 0 1 0 1 1 Y Synch. Activated by internal logic for 1024 TCL 0 0 0 1 0 x 0 N Synch. Not activated 0 0 0 1 1 x 0 N Synch. Not activated 0 0 0 1 1 0 1 Y Synch. Not activated 0 1 1 Y Synch. Activated by internal logic for 1024 TCL min max ct du 0 (s) 0 0 1 1 0 0 1 1 o r P 1. It can degenerate into a Long Hardware Reset and consequently differently flagged (see Section 20.3 for details). 2. When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently flagged (see Section 20.6 for details). e t e ol The start-up configurations and some system features are selected on reset sequences as described in Table 50 and Figure 35. s b O Table 50 describes what is the system configuration latched on PORT0 in the six different reset modes. Figure 35 summarizes the state of bits of PORT0 latched in RP0H, SYSCON, BUSCON0 registers. ) (s PORT0 latched configuration for the different reset events Reserved BSL Reserved Reserved Adapt mode Emu mode P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0 P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0 Software reset - - - X X X X X X X - - - - - - Watchdog reset - - - X X X X X X X - - - - - - Synchronous short hardware reset - - - X X X X X X X X X X X X X Synchronous long hardware reset X X X X X X X X X X X X X X X X Asynchronous hardware reset X X X X X X X X X X X X X X X X Asynchronous power-on reset X X X X X X X X X X X X X X X X r P e t e l o bs Sample event O 100/185 Bus type X: Pin is sampled -: Pin is not sampled WR config. P0H.6 Chip selects P0H.7 u d o PORT0 Clock options ct Segm. addr. lines Table 50. ST10F271Z1 System reset Figure 35. PORT0 bits latched into the different registers after reset PORT0 H.7 H.6 H.5 H.4 CLKCFG H.3 H.2 H.1 H.0 SALSEL CSSEL WRC CLKCFG SALSEL CSSEL WRC Clock Generator Port 4 Logic Port 6 Logic L.7 L.6 L.5 BUSTYP L.4 L.3 BSL L.2 Res. L.1 L.0 ADP EMU RP0H Bootstrap Loader Internal Control Logic 2 EA / VSTBY ) s ( ct P0L.7 u d o P0L.7 SYSCON ROMEN BYTDIS 10 9 8 BUSCON0 7 10 ) (s r P e BUS ALE ACT0 CTL0 WRCFG 9 BTYP 7 t e l o 6 s b O t c u d o r P e t e l o s b O 101/185 Power reduction modes 21 ST10F271Z1 Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F271Z1. In Idle mode only CPU is stopped, while peripheral still operate. In power-down mode both CPU and peripherals are stopped. In Stand-by mode the main power supply (VDD) can be turned off while a portion of the internal RAM remains powered via VSTBY dedicated power pin. Idle and power-down modes are software activated by a protected instruction and are terminated in different ways as described in the following sections. Stand-by mode is entered simply removing VDD, holding the MCU under reset state. Note: 21.1 ) s ( ct All external bus actions are completed before Idle or power-down mode is entered. However, Idle or power-down mode is not entered if READY is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access. u d o r P e Idle mode t e l o Idle mode is entered by running IDLE protected instruction. The CPU operation is stopped and the peripherals still run. s b O Idle mode is terminate by any interrupt request. Whatever the interrupt is serviced or not, the instruction following the IDLE instruction will be executed after return from interrupt (RETI) instruction, then the CPU resumes the normal program. ) 21.2 Power-down mode(s t c u d o r P e t e l o s b O Power-down mode starts by running PWRDN protected instruction. Internal clock is stopped, all MCU parts are on hold including the watchdog timer. The only exception could be the Real-Time Clock if opportunely programmed and one of the two oscillator circuits as a consequence (either the main or the 32 kHz on-chip oscillator). When Real-Time Clock module is used, when the device is in power-down mode a reference clock is needed. In this case, two possible configurations may be selected by the user application according to the desired level of power reduction: A 32 kHz crystal is connected to the on-chip low-power oscillator (pins XTAL3 / XTAL4) and running. In this case the main oscillator is stopped when power-down mode is entered, while the Real-Time Clock continue counting using 32 kHz clock signal as reference. The presence of a running low-power oscillator is detected after the Poweron: this clock is immediately assumed (if present, or as soon as it is detected) as reference for the Real-Time Clock counter and it will be maintained forever (unless specifically disabled via software). Only the main oscillator is running (XTAL1 / XTAL2 pins). In this case the main oscillator is not stopped when power-down is entered, and the Real-Time Clock continue counting using the main oscillator clock signal as reference. There are two different operating power-down modes: protected mode and interruptible mode. 102/185 ST10F271Z1 Power reduction modes Before entering power-down mode (by executing the instruction PWRDN), bit VREGOFF in XMISC register must be set. Note: Leaving the main voltage regulator active during power-down may lead to unexpected behavior (ex: CPU wake-up) and power consumption higher than what specified. 21.2.1 Protected power-down mode This mode is selected when PWDCFG (bit 5) of SYSCON register is cleared. The protected power-down mode is only activated if the NMI pin is pulled low when executing PWRDN instruction (this means that the PWRD instruction belongs to the NMI software routine). This mode is only deactivated with an external hardware reset on RSTIN pin. 21.2.2 ) s ( ct Interruptible power-down mode This mode is selected when PWDCFG (bit 5) of SYSCON register is set. u d o The Interruptible power-down mode is only activated if all the enabled Fast External Interrupt pins are in their inactive level. r P e This mode is deactivated with an external reset applied to RSTIN pin or with an interrupt request applied to one of the Fast External Interrupt pins, or with an interrupt generated by the Real-Time Clock, or with an interrupt generated by the activity on CAN's and I2C module interfaces. To allow the internal PLL and clock to stabilize, the RSTIN pin must be held low according the recommendations described in Chapter 20: System reset on page 77. t e l o s b O An external RC circuit must be connected to RPD pin, as shown in the Figure 36. ) (s Figure 36. External RC circuitry on RPD pin t c u od e t e ol bs O21.3 Pr ST10F271Z1 VDD R0 220k minimum RPD + C0 1 F Typical To exit power-down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be asserted for at least 40 ns. Stand-by mode In Stand-by mode, it is possible to turn off the main VDD provided that VSTBY is available through the dedicated pin of the ST10F271Z1. To enter Stand-by mode it is mandatory to held the device under reset: once the device is under reset, the RAM is disabled (see XRAM2EN bit of XPERCON register), and its digital interface is frozen in order to avoid any kind of data corruption. A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65 V in Stand-by mode) to bias all those circuits that shall remain active: the portion of XRAM (8 Kbytes), the RTC counters and 32 kHz on-chip oscillator amplifier. 103/185 Power reduction modes ST10F271Z1 In normal running mode (that is when main VDD is on) the VSTBY pin can be tied to VSS during reset to exercise the EA functionality associated with the same pin: the voltage supply for the circuitries which are usually biased with VSTBY (see in particular the 32 kHz oscillator used in conjunction with Real-Time Clock module), is granted by the active main VDD. It must be noted that Stand-by Mode can generate problems associated with the usage of different power supplies in CMOS systems; particular attention must be paid when the ST10F271Z1 I/O lines are interfaced with other external CMOS integrated circuits: if VDD of ST10F271Z1 becomes (for example in Stand-by Mode) lower than the output level forced by the I/O lines of these external integrated circuits, the ST10F271Z1 could be directly powered through the inherent diode existing on ST10F271Z1 output driver circuitry. The same is valid for ST10F271Z1 interfaced to active/inactive communication buses during Stand-by mode: current injection can be generated through the inherent diode. Furthermore, the sequence of turning on/off of the different voltage could be critical for the system (not only for the ST10F271Z1 device). The device Stand-by mode current (ISTBY) may vary while VDD to VSTBY (and vice versa) transition occurs: some current flows between VDD and VSTBY pins. System noise on both VDD and VSTBY can contribute to increase this phenomenon. ) s ( ct u d o 21.3.1 r P e Entering stand-by mode t e l o As already said, to enter Stand-by Mode XRAM2EN bit in the XPERCON Register must be cleared: this allows to freeze immediately the RAM interface, avoiding any data corruption. As a consequence of a RESET event, the RAM Power Supply is switched to the internal low-voltage supply V18SB (derived from VSTBY through the low-power voltage regulator). The RAM interface will remain frozen until the bit XRAM2EN is set again by software initialization routine (at next exit from main VDD power-on reset sequence). ) (s s b O t c u Since V18 is falling down (as a consequence of VDD turning off), it can happen that the XRAM2EN bit is no longer able to guarantee its content (logic "0"), being the XPERCON Register powered by internal V18. This does not generate any problem, because the Standby Mode switching dedicated circuit continues to confirm the RAM interface freezing, irrespective the XRAM2EN bit content; XRAM2EN bit status is considered again when internal V18 comes back over internal stand-by reference V18SB. d o r P e t e l o s b O 104/185 If internal V18 becomes lower than internal stand-by reference (V18SB) of about 0.3 to 0.45 V with bit XRAM2EN set, the RAM Supply switching circuit is not active: in case of a temporary drop on internal V18 voltage versus internal V18SB during normal code execution, no spurious Stand-by Mode switching can occur (the RAM is not frozen and can still be accessed). The ST10F271Z1 Core module, generating the RAM control signals, is powered by internal V18 supply; during turning off transient these control signals follow the V18, while RAM is switched to V18SB internal reference. It could happen that a high level of RAM write strobe from ST10F271Z1 Core (active low signal) is low enough to be recognized as a logic "0" by the RAM interface (due to V18 lower than V18SB): The bus status could contain a valid address for the RAM and an unwanted data corruption could occur. For this reason, an extra interface, powered by the switched supply, is used to prevent the RAM from this kind of potential corruption mechanism. ST10F271Z1 Power reduction modes Warning: 21.3.2 During power-off phase, it is important that the external hardware maintains a stable ground level on RSTIN pin, without any glitch, in order to avoid spurious exiting from reset status with unstable power supply. Exiting stand-by mode After the system has entered the Stand-by Mode, the procedure to exit this mode consists of a standard Power-on sequence, with the only difference that the RAM is already powered through V18SB internal reference (derived from VSTBY pin external voltage). ) s ( ct It is recommended to held the device under RESET (RSTIN pin forced low) until external VDD voltage pin is stable. Even though, at the very beginning of the power-on phase, the device is maintained under reset by the internal low voltage detector circuit (implemented inside the main voltage regulator) till the internal V18 becomes higher than about 1.0 V, there is no warranty that the device stays under reset status if RSTIN is at high level during power ramp up. So, it is important the external hardware is able to guarantee a stable ground level on RSTIN along the power-on phase, without any temporary glitch. u d o r P e t e l o The external hardware shall be responsible to drive low the RSTIN pin until the VDD is stable, even though the internal LVD is active. s b O Once the internal Reset signal goes low, the RAM (still frozen) power supply is switched to the main V18. ) (s At this time, everything becomes stable, and the execution of the initialization routines can start: XRAM2EN bit can be set, enabling the RAM. 21.3.3 t c u d o r Real-time clock and stand-by mode When Stand-by mode is entered (turning off the main supply VDD), the Real-Time Clock counting can be maintained running in case the on-chip 32 kHz oscillator is used to provide the reference to the counter. This is not possible if the main oscillator is used as reference for the counter: being the main oscillator powered by VDD, once ths is switched off, the oscillator is stopped. P e t e l o s b O 21.3.4 Power reduction modes summary In the following Table 51: Power reduction modes summary, a summary of the different Power reduction modes is reported. 105/185 Power reduction modes CPU Peripherals RTC Main OSC 32 kHz OSC STBY XRAM XRAM Mode VSTBY Power reduction modes summary VDD Table 51. ST10F271Z1 on on off on off run off biased biased on on off on on run on biased biased on on off off off off off biased biased on on off off on on off biased biased on on off off on off on biased biased off on off off off off off biased off off on off off on off on Idle Power-down Stand-by e t e ol ) (s t c u d o r P e t e l o s b O 106/185 s b O o r P du ) s ( ct biased off ST10F271Z1 22 Programmable output clock divider Programmable output clock divider A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON, it is possible to program the clock prescaling factor: in this way on P3.15 a prescaled value of the CPU clock can be output. When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15 does not output any clock signal, even though XCLKOUTDIV register is programmed. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 107/185 Register set 23 ST10F271Z1 Register set This section summarizes all registers implemented in the ST10F271Z1, ordered by name. 23.1 Special function registers The following table lists all SFRs which are implemented in the ST10F271Z1 in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Table 52. ) s ( ct List of special function registers Physical address Name 8-bit address Description u d o r P e Reset value ADCIC b FF98h CCh A/D converter end of conversion interrupt control register - - 00h ADCON b FFA0h D0h A/D converter control register 0000h ADDAT FEA0h 50h A/D converter result register 0000h ADDAT2 F0A0h 50h A/D converter 2 result register 0000h ADDRSEL1 FE18h 0Ch Address select register 1 0000h ADDRSEL2 FE1Ah 0Dh ADDRSEL3 FE1Ch ADDRSEL4 FE1Eh ADEIC FF9Ah BUSCON0 b FF0Ch bs O ) t(s Address select register 2 0000h 0Eh Address select register 3 0000h 0Fh Address select register 4 0000h CDh A/D converter overrun error interrupt control register - - 00h 86h Bus configuration register 0 0xx0h c u d o r P b e t e l E t e l o BUSCON1 b FF14h 8Ah Bus configuration register 1 0000h BUSCON2 b o s b FF16h 8Bh Bus configuration register 2 0000h BUSCON3 b FF18h 8Ch Bus configuration register 3 0000h BUSCON4 b FF1Ah 8Dh Bus configuration register 4 0000h CAPREL FE4Ah 25h GPT2 capture/reload register 0000h CC0 FE80h 40h CAPCOM register 0 0000h FF78h BCh CAPCOM register 0 interrupt control register - - 00h FE82h 41h CAPCOM register 1 0000h FF7Ah BDh CAPCOM register 1 interrupt control register - - 00h FE84h 42h CAPCOM register 2 0000h FF7Ch BEh CAPCOM register 2 interrupt control register - - 00h FE86h 43h CAPCOM register 3 0000h FF7Eh BFh CAPCOM register 3 interrupt control register - - 00h O CC0IC b CC1 CC1IC b CC2 CC2IC b CC3 CC3IC 108/185 b ST10F271Z1 Table 52. Register set List of special function registers (continued) Physical address Name CC4 CC4IC b CC5 CC5IC b CC6 CC6IC b CC7 CC7IC b CC8 CC8IC b CC9 CC9IC b CC10 CC10IC b CC11 CC11IC b CC12 CC12IC b CC13 b CC14 44h CAPCOM register 4 0000h FF80h C0h CAPCOM register 4 interrupt control register - - 00h FE8Ah 45h CAPCOM register 5 0000h FF82h C1h CAPCOM register 5 interrupt control register - - 00h FE8Ch 46h CAPCOM register 6 0000h FF84h C2h CAPCOM register 6 interrupt control register - - 00h FE8Eh 47h CAPCOM register 7 FF86h C3h CAPCOM register 7 interrupt control register FE90h 48h CAPCOM register 8 FF88h C4h CAPCOM register 8 interrupt control register FE92h 49h CAPCOM register 9 FF8Ah C5h CAPCOM register 9 interrupt control register - - 00h FE94h 4Ah CAPCOM register 10 0000h FF8Ch C6h CAPCOM register 10 interrupt control register - - 00h FE96h 4Bh CAPCOM register 11 0000h FF8Eh C7h CAPCOM register 11 interrupt control register - - 00h FE98h 4Ch CAPCOM register 12 0000h FF90h t c u CAPCOM register 12 interrupt control register - - 00h CAPCOM register 13 0000h C9h CAPCOM register 13 interrupt control register - - 00h 4Eh CAPCOM register 14 0000h FF94h CAh CAPCOM register 14 interrupt control register - - 00h FE9Eh 4Fh CAPCOM register 15 0000h FF96h CBh CAPCOM register 15 interrupt control register - - 00h FE60h 30h CAPCOM register 16 0000h B0h CAPCOM register 16 interrupt control register - - 00h 31h CAPCOM register 17 0000h B1h CAPCOM register 17 interrupt control register - - 00h 32h CAPCOM register 18 0000h B2h CAPCOM register 18 interrupt control register - - 00h 33h CAPCOM register 19 0000h B3h CAPCOM register 19 interrupt control register - - 00h 34h CAPCOM register 20 0000h B4h CAPCOM register 20 interrupt control register - - 00h FF92h C8h e t e ol CC15 CC15IC s b O CC16IC b b b CC17 CC17IC b b E F162h E F164h E FE66h b CC20 CC20IC F160h FE64h CC19 CC19IC od FE62h CC18 CC18IC 4Dh Pr FE9Ch CC14IC F166h E FE68h b Reset value Description FE88h FE9Ah CC13IC CC16 8-bit address F168h E e t e ol ) (s ) s ( ct 0000h u d o Pr s b O - - 00h 0000h - - 00h 0000h 109/185 Register set Table 52. ST10F271Z1 List of special function registers (continued) Physical address Name CC21 8-bit address FE6Ah CC21IC b CC22 F16Ah E FE6Ch CC22IC b CC23 F16Ch E FE6Eh CC23IC b CC24 F16Eh E FE70h CC24IC b CC25 F170h E FE72h CC25IC b CC26 F172h E FE74h CC26IC b CC27 F174h E FE76h CC27IC b CC28 F176h E FE78h CC28IC b CC29 F178h E FE7Ah CC29IC b CC30 b CC31 F18Ch e t e ol 0000h B5h CAPCOM register 21 interrupt control register - - 00h 36h CAPCOM register 22 0000h B6h CAPCOM register 22 interrupt control register - - 00h 37h CAPCOM register 23 0000h B7h CAPCOM register 23 interrupt control register - - 00h 38h CAPCOM register 24 B8h CAPCOM register 24 interrupt control register 39h CAPCOM register 25 B9h CAPCOM register 25 interrupt control register 3Ah CAPCOM register 26 BAh CAPCOM register 26 interrupt control register - - 00h 3Bh CAPCOM register 27 0000h BBh CAPCOM register 27 interrupt control register - - 00h 3Ch CAPCOM register 28 0000h BCh CAPCOM register 28 interrupt control register - - 00h CAPCOM register 29 0000h CAPCOM register 29 interrupt control register - - 00h CAPCOM register 30 0000h C6h CAPCOM register 30 interrupt control register - - 00h 3Fh CAPCOM register 31 0000h CAh CAPCOM register 31 interrupt control register - - 00h C2h 3Eh od Pr FE7Eh CAPCOM register 21 e t e ol ) (s t c u E FE7Ch CC30IC 35h 3Dh F184h E ) s ( ct 0000h u d o Pr s b O - - 00h 0000h - - 00h 0000h CC31IC b F194h CCM0 b FF52h A9h CAPCOM Mode Control register 0 0000h b FF54h AAh CAPCOM Mode Control register 1 0000h b FF56h ABh CAPCOM Mode Control register 2 0000h CCM3 b FF58h ACh CAPCOM mode Control register 3 0000h CCM4 b FF22h 91h CAPCOM Mode Control register 4 0000h CCM5 b FF24h 92h CAPCOM Mode Control register 5 0000h CCM6 b FF26h 93h CAPCOM Mode Control register 6 0000h CCM7 b FF28h 94h CAPCOM Mode Control register 7 0000h FE10h 08h CPU Context Pointer register FC00h FF6Ah B5h GPT2 CAPREL interrupt control register - - 00h FE08h 04h CPU Code Segment Pointer register (read only) 0000h 80h P0L direction control register - - 00h CCM1 s b O CCM2 CP CRIC b CSP DP0L 110/185 b F100h E Reset value Description E ST10F271Z1 Table 52. Register set List of special function registers (continued) Physical address Name 8-bit address Reset value Description DP0H b F102h E 81h P0h direction control register - - 00h DP1L b F104h E 82h P1L direction control register - - 00h DP1H b F106h E 83h P1h direction control register - - 00h DP2 b FFC2h E1h Port 2 direction control register 0000h DP3 b FFC6h E3h Port 3 direction control register 0000h DP4 b FFCAh E5h Port 4 direction control register - - 00h DP6 b FFCEh E7h Port 6 direction control register DP7 b FFD2h E9h Port 7 direction control register DP8 b FFD6h EBh Port 8 direction control register DPP0 FE00h 00h CPU data page pointer 0 register (10-bit) DPP1 FE02h 01h CPU data page pointer 1 register (10-bit) 0001h DPP2 FE04h 02h CPU data page pointer 2 register (10-bit) 0002h DPP3 FE06h 03h CPU data page pointer 3 register (10-bit) 0003h EMUCON FE0Ah 05h Emulation control register e t e ol ) s ( ct - - 00h - - 00h u d o Pr s b O - - 00h 0000h - - XXh EXICON b F1C0h E E0h External interrupt control register 0000h EXISEL b F1DAh E EDh External interrupt source selection register 0000h IDCHIP F07Ch E 3Eh Device identifier register (n is the device revision) 110nh IDMANUF F07Eh E 0403h IDMEM F07Ah E On-chip memory identifier register 3040h IDPROG F078h t c u Manufacturer identifier register 3Ch Programming voltage identifier register 0040h 84h MAC unit address pointer 0 0000h FF0Ah 85h MAC unit address pointer 1 0000h FE5Eh 2Fh MAC unit accumulator - high word 0000h FE5Ch 2Eh MAC unit accumulator - low word 0000h b FFDCh EEh MAC unit control word 0000h b FF0Eh 87h CPU multiply divide control register 0000h MDH FE0Ch 06h CPU multiply divide register - high word 0000h MDL FE0Eh 07h CPU multiply divide register - low word 0000h IDX0 b IDX1 e t e ol MAH MAL s b O MCW MDC b Pr od FF08h E 3Fh 3Dh ) (s MRW b FFDAh EDh MAC unit repeat word 0000h MSW b FFDEh EFh MAC unit status word 0200h ODP2 b F1C2h E E1h Port 2 open drain control register 0000h ODP3 b F1C6h E E3h Port 3 open drain control register 0000h ODP4 b F1CAh E E5h Port 4 open drain control register - - 00h ODP6 b F1CEh E E7h Port 6 open drain control register - - 00h 111/185 Register set Table 52. ST10F271Z1 List of special function registers (continued) Physical address Name 8-bit address Reset value Description ODP7 b F1D2h E E9h Port 7 open drain control register - - 00h ODP8 b F1D6h E EBh Port 8 open drain control register - - 00h ONES b FF1Eh 8Fh Constant value 1's register (read only) FFFFh P0L b FF00h 80h PORT0 low register (lower half of PORT0) - - 00h P0H b FF02h 81h PORT0 high register (upper half of PORT0) - - 00h P1L b FF04h 82h PORT1 low register (lower half of PORT1) - - 00h P1H b FF06h 83h PORT1 high register (upper half of PORT1) P2 b FFC0h E0h Port 2 register P3 b FFC4h E2h Port 3 register P4 b FFC8h E4h Port 4 register (8-bit) P5 b FFA2h D1h Port 5 register (read only) P6 b FFCCh E6h Port 6 register (8-bit) P7 b FFD0h E8h Port 7 register (8-bit) - - 00h P8 b FFD4h EAh Port 8 register (8-bit) - - 00h P5DIDIS b FFA4h D2h Port 5 digital disable register 0000h PECC0 FEC0h 60h PEC channel 0 control register 0000h PECC1 FEC2h 61h PEC channel 1 control register 0000h PECC2 FEC4h 0000h PECC3 FEC6h PEC channel 3 control register 0000h PECC4 FEC8h t c u PEC channel 2 control register 64h PEC channel 4 control register 0000h PECC5 FECAh 65h PEC channel 5 control register 0000h e t e ol 62h 63h od Pr 0000h e t e ol ) (s ) s ( ct - - 00h Pr u d o s b O 0000h - - 00h XXXXh - - 00h PECC6 FECCh 66h PEC channel 6 control register 0000h PECC7 FECEh 67h PEC channel 7 control register 0000h PICON F1C4h E E2h Port input threshold control register - - 00h F038h E 1Ch PWM module period register 0 0000h PP1 F03Ah E 1Dh PWM module period register 1 0000h PP2 F03Ch E 1Eh PWM module period register 2 0000h PP3 F03Eh E 1Fh PWM module period register 3 0000h 88h CPU program status word 0000h s b O PP0 PSW b b FF10h PT0 F030h E 18h PWM module up/down counter 0 0000h PT1 F032h E 19h PWM module up/down counter 1 0000h PT2 F034h E 1Ah PWM module up/down counter 2 0000h PT3 F036h E 1Bh PWM module up/down counter 3 0000h PW0 FE30h 18h PWM module pulse width register 0 0000h 112/185 ST10F271Z1 Table 52. Register set List of special function registers (continued) Physical address Name 8-bit address Reset value Description PW1 FE32h 19h PWM module pulse width register 1 0000h PW2 FE34h 1Ah PWM module pulse width register 2 0000h PW3 FE36h 1Bh PWM module pulse width register 3 0000h PWMCON0 b FF30h 98h PWM module control register 0 0000h PWMCON1 b FF32h 99h PWM module control register 1 0000h PWMIC F17Eh E BFh PWM module interrupt control register - - 00h QR0 F004h E 02h MAC unit offset register r0 QR1 F006h E 03h MAC unit offset register R1 QX0 F000h E 00h MAC unit offset register X0 QX1 F002h E 01h MAC unit offset register X1 F108h E 84h System start-up configuration register (read only) FEB4h 5Ah Serial channel 0 baud rate generator reload register 0000h RP0H b b S0BG e t e ol ) s ( ct 0000h 0000h u d o Pr 0000h 0000h - - XXh S0CON b FFB0h D8h Serial channel 0 control register 0000h S0EIC b FF70h B8h Serial channel 0 error interrupt control register - - 00h FEB2h 59h Serial channel 0 receive buffer register (read only) - - XXh B7h Serial channel 0 receive interrupt control register - - 00h Serial channel 0 transmit buffer interrupt control reg. - - 00h Serial channel 0 transmit buffer register (write only) 0000h Serial channel 0 transmit interrupt control register - - 00h 09h CPU system stack pointer register FC00h 5Ah SSC Baud rate register 0000h S0RBUF S0RIC b FF6Eh S0TBIC b F19Ch S0TBUF S0TIC E t c u FEB0h b 58h FF6Ch SP FE12h SSCBR F0B4h e t e ol B6h od Pr ) (s CEh E s b O SSCCON b FFB2h D9h SSC control register 0000h SSCEIC b FF76h BBh SSC error interrupt control register - - 00h 59h SSC receive buffer (read only) BAh SSC receive interrupt control register - - 00h 58h SSC transmit buffer (write only) 0000h FF72h B9h SSC transmit interrupt control register - - 00h STKOV FE14h 0Ah CPU stack overflow pointer register FA00h STKUN FE16h 0Bh CPU stack underflow pointer register FC00h FF12h 89h CPU system configuration register FE50h 28h CAPCOM timer 0 register 0000h SSCRB s b O SSCRIC F0B2h b SSCTB SSCTIC SYSCON FF74h F0B0h b b T0 E E XXXXh 0xx0h 1) T01CON b FF50h A8h CAPCOM timer 0 and timer 1 control register 0000h T0IC b FF9Ch CEh CAPCOM timer 0 interrupt control register - - 00h FE54h 2Ah CAPCOM timer 0 reload register 0000h T0REL 113/185 Register set Table 52. ST10F271Z1 List of special function registers (continued) Physical address Name T1 8-bit address Reset value Description FE52h 29h CAPCOM timer 1 register 0000h FF9Eh CFh CAPCOM timer 1 interrupt control register - - 00h T1REL FE56h 2Bh CAPCOM timer 1 reload register 0000h T2 FE40h 20h GPT1 timer 2 register 0000h T1IC b T2CON b FF40h A0h GPT1 timer 2 control register 0000h T2IC b FF60h B0h GPT1 timer 2 interrupt control register - - 00h FE42h 21h GPT1 timer 3 register T3 T3CON b FF42h A1h GPT1 timer 3 control register T3IC b FF62h B1h GPT1 timer 3 interrupt control register FE44h 22h GPT1 timer 4 register T4 ) s ( ct 0000h 0000h u d o Pr - - 00h 0000h T4CON b FF44h A2h GPT1 timer 4 control register T4IC b FF64h B2h GPT1 timer 4 interrupt control register - - 00h FE46h 23h GPT2 timer 5 register 0000h T5 e t e ol 0000h T5CON b FF46h A3h GPT2 timer 5 control register 0000h T5IC b FF66h B3h GPT2 timer 5 interrupt control register - - 00h FE48h 24h GPT2 timer 6 register 0000h GPT2 timer 6 control register 0000h GPT2 timer 6 interrupt control register - - 00h CAPCOM timer 7 register 0000h T6 b FF48h A4h T6IC b FF68h t c u ) (s T6CON T7 F050h CAPCOM timer 7 and 8 control register 0000h E BDh CAPCOM timer 7 interrupt control register - - 00h F054h E 2Ah CAPCOM timer 7 reload register 0000h F052h E 29h CAPCOM timer 8 register 0000h F17Ch E BEh CAPCOM timer 8 interrupt control register - - 00h F056h E 2Bh CAPCOM timer 8 reload register 0000h FFACh D6h Trap Flag register 0000h FEAEh 57h Watchdog timer register (read only) 0000h FFAEh D7h Watchdog timer control register 00xxh 2) 800Bh FF20h T7IC b F17Ah e t e ol T8 s b O T8REL TFR b b WDT WDTCON b XADRS3 28h 90h b T7REL E od T78CON T8IC B4h s b O Pr F01Ch E 0Eh XPER address select register 3 XP0IC b F186h E C3h See Section 9.1 - - 00h 3) XP1IC b F18Eh E C7h See Section 9.1 - - 00h 3) XP2IC b F196h E CBh See Section 9.1 - - 00h 3) XP3IC b F19Eh E CFh See Section 9.1 - - 00h 3) 114/185 ST10F271Z1 Table 52. Register set List of special function registers (continued) Physical address Name XPERCON b F024h ZEROS FF1Ch Note: b 8-bit address E Reset value Description 12h XPER configuration register - - 05h 8Eh Constant value 0's register (read only) 0000h 1. The system configuration is selected during reset. SYSCON reset value is 0000 0xx0 x000 0000b. 2. Reset Value depends on different triggered reset event. 3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software controlled interrupt requests may be generated by setting the XPnIR bits (of XPnIC register) of the unused X-Peripheral nodes. 23.2 ) s ( ct u d o XBus registers r P e The following table lists all XBus registers which are implemented in the ST10F271Z1 ordered by their name. Note: t e l o The XBus registers are not bit-addressable. Table 53. List of XBus registers Physical address Name CAN1BRPER EF0Ch CAN1BTR EF06h CAN1CR Description Reset value CAN1: BRP extension register 0000h CAN1: Bit timing register 2301h EF00h CAN1: CAN control register 0001h EF04h CAN1: error counter 0000h EF18h CAN1: IF1 arbitration 1 0000h CAN1IF1A2 EF1Ah CAN1: IF1 arbitration 2 0000h CAN1IF1CM EF12h CAN1: IF1 command mask 0000h CAN1IF1CR EF10h CAN1: IF1 command request 0001h CAN1IF1DA1 EF1Eh CAN1: IF1 data A 1 0000h CAN1IF1DA2 EF20h CAN1: IF1 data A 2 0000h CAN1IF1DB1 EF22h CAN1: IF1 data B 1 0000h CAN1IF1DB2 EF24h CAN1: IF1 data B 2 0000h CAN1IF1M1 EF14h CAN1: IF1 mask 1 FFFFh CAN1IF1M2 EF16h CAN1: IF1 mask 2 FFFFh CAN1IF1MC EF1Ch CAN1: IF1 message control 0000h CAN1IF2A1 EF48h CAN1: IF2 arbitration 1 0000h CAN1IF2A2 EF4Ah CAN1: IF2 arbitration 2 0000h CAN1IF2CM EF42h CAN1: IF2 command mask 0000h Pr CAN1IF1A1 e t e ol s ( t c u d o CAN1EC s b O )- s b O 115/185 Register set ST10F271Z1 Table 53. List of XBus registers (continued) Physical address Name CAN1IF2CR EF40h CAN1: IF2 command request 0001h CAN1IF2DA1 EF4Eh CAN1: IF2 data A 1 0000h CAN1IF2DA2 EF50h CAN1: IF2 data A 2 0000h CAN1IF2DB1 EF52h CAN1: IF2 data B 1 0000h CAN1IF2DB2 EF54h CAN1: IF2 data B 2 0000h CAN1IF2M1 EF44h CAN1: IF2 Mask 1 FFFFh CAN1IF2M2 EF46h CAN1: IF2 mask 2 CAN1IF2MC EF4Ch CAN1: IF2 message control CAN1IP1 EFA0h CAN1: interrupt pending 1 CAN1IP2 EFA2h CAN1: interrupt pending 2 ) s ( ct CAN1IR EF08h CAN1: interrupt register CAN1MV1 EFB0h CAN1: message valid 1 CAN1MV2 EFB2h CAN1: message valid 2 0000h CAN1ND1 EF90h CAN1: new data 1 0000h CAN1ND2 EF92h CAN1: new data 2 0000h CAN1SR EF02h CAN1: status register 0000h CAN1TR EF0Ah CAN1: test register 00x0h EF80h CAN1: transmission request 1 0000h EF82h CAN1: transmission request 2 0000h EE0Ch CAN2: BRP extension register 0000h EE06h CAN2: bit timing register 2301h CAN2CR EE00h CAN2: CAN control register 0001h CAN2EC EE04h CAN2: error counter 0000h CAN2IF1A1 EE18h CAN2: IF1 arbitration 1 0000h CAN2IF1A2 EE1Ah CAN2: IF1 arbitration 2 0000h CAN2IF1CM EE12h CAN2: IF1 command mask 0000h CAN2IF1CR EE10h CAN2: IF1 command request 0001h CAN2IF1DA1 EE1Eh CAN2: IF1 data A 1 0000h CAN2IF1DA2 EE20h CAN2: IF1 data A 2 0000h CAN2IF1DB1 EE22h CAN2: IF1 data B 1 0000h CAN2IF1DB2 EE24h CAN2: IF1 data B 2 0000h CAN2IF1M1 EE14h CAN2: IF1 mask 1 FFFFh CAN2IF1M2 EE16h CAN2: IF1 mask 2 FFFFh CAN2IF1MC EE1Ch CAN2: IF1 message control 0000h t c u CAN1TR2 CAN2BRPER e t e ol 116/185 od Pr CAN2BTR e t e ol ) (s CAN1TR1 s b O Reset value Description s b O FFFFh 0000h Pr u d o 0000h 0000h 0000h 0000h ST10F271Z1 Register set Table 53. List of XBus registers (continued) Physical address Name CAN2IF2A1 EE48h CAN2: IF2 arbitration 1 0000h CAN2IF2A2 EE4Ah CAN2: IF2 arbitration 2 0000h CAN2IF2CM EE42h CAN2: IF2 command mask 0000h CAN2IF2CR EE40h CAN2: IF2 command request 0001h CAN2IF2DA1 EE4Eh CAN2: IF2 data A 1 0000h CAN2IF2DA2 EE50h CAN2: IF2 data A 2 0000h CAN2IF2DB1 EE52h CAN2: IF2 data B 1 CAN2IF2DB2 EE54h CAN2: IF2 data B 2 CAN2IF2M1 EE44h CAN2: IF2 mask 1 CAN2IF2M2 EE46h CAN2: IF2 mask 2 ) s ( ct CAN2IF2MC EE4Ch CAN2: IF2 message control CAN2IP1 EEA0h CAN2: interrupt pending 1 CAN2IP2 EEA2h CAN2: interrupt pending 2 0000h CAN2IR EE08h CAN2: interrupt register 0000h CAN2MV1 EEB0h CAN2: message valid 1 0000h CAN2MV2 EEB2h CAN2: message valid 2 0000h CAN2ND1 EE90h CAN2: new data 1 0000h EE92h CAN2: new data 2 0000h EE02h CAN2: status register 0000h EE0Ah CAN2: test register 00x0h EE80h CAN2: transmission request 1 0000h CAN2TR2 EE82h CAN2: Transmission request 2 0000h I2CCCR1 EA06h I2C clock control register 1 0000h I2CCCR2 EA0Eh I2C clock control register 2 0000h I2CCR EA00h I2C control register 0000h I2CDR EA0Ch I2C data register 0000h I2COAR1 EA08h I2C own address register 1 0000h I2COAR2 EA0Ah I2C own address register 2 0000h I2CSR1 EA02h I2C status register 1 0000h I2CSR2 EA04h I2C status register 2 0000h RTCAH ED14h RTC alarm register high byte XXXXh RTCAL ED12h RTC alarm register low byte XXXXh RTCCON ED00H RTC control register 000Xh RTCDH ED0Ch RTC divider counter high byte XXXXh t c u CAN2SR CAN2TR e t e ol od Pr CAN2TR1 e t e ol ) (s CAN2ND2 s b O Reset value Description s b O 0000h 0000h Pr u d o FFFFh FFFFh 0000h 0000h 117/185 Register set ST10F271Z1 Table 53. List of XBus registers (continued) Physical address Name RTCDL ED0Ah RTC divider counter low byte XXXXh RTCH ED10h RTC programmable counter high byte XXXXh RTCL ED0Eh RTC programmable counter low byte XXXXh RTCPH ED08h RTC prescaler register high byte XXXXh RTCPL ED06h RTC prescaler register low byte XXXXh XCLKOUTDIV EB02h CLKOUT divider control register - - 00h XEMU0 EB76h XBUS emulation register 0 (write only) XEMU1 EB78h XBUS emulation register 1 (write only) XEMU2 EB7Ah XBUS emulation register 2 (write only) XEMU3 EB7Ch XBUS emulation register 3 (write only) XIR0CLR EB14h X-Interrupt 0 clear register (write only) XIR0SEL EB10h X-Interrupt 0 selection register XIR0SET EB12h X-Interrupt 0 set register (write only) 0000h XIR1CLR EB24h X-Interrupt 1 clear register (write only) 0000h XIR1SEL EB20h X-Interrupt 1 selection register 0000h XIR1SET EB22h X-Interrupt 1 set register (write only) 0000h XIR2CLR EB34h X-Interrupt 2 clear register (write only) 0000h EB30h X-Interrupt 2 selection register 0000h EB32h X-Interrupt 2 set register (write only) 0000h EB44h X-Interrupt 3 clear selection register (write only) 0000h EB40h X-Interrupt 3 selection register 0000h XIR3SET EB42h X-Interrupt 3 set selection register (write only) 0000h XMISC EB46h XBUS miscellaneous features register 0000h XP1DIDIS EB36h Port 1 digital disable register 0000h XPEREMU EB7Eh XPERCON copy for emulation (write only) XXXXh XPICON EB26h Extended port input threshold control register - - 00h XPOLAR EC04h XPWM module channel polarity register 0000h XPP0 EC20h XPWM module period register 0 0000h XPP1 EC22h XPWM module period register 1 0000h XPP2 EC24h XPWM module period register 2 0000h XPP3 EC26h XPWM module period register 3 0000h XPT0 EC10h XPWM module up/down counter 0 0000h XPT1 EC12h XPWM module up/down counter 1 0000h XPT2 EC14h XPWM module up/down counter 2 0000h t c u XIR2SET XIR3CLR e t e ol 118/185 od Pr XIR3SEL e t e ol ) (s XIR2SEL s b O Reset value Description u d o ) s ( ct Pr s b O XXXXh XXXXh XXXXh XXXXh 0000h 0000h ST10F271Z1 Register set Table 53. List of XBus registers (continued) Physical address Name XPT3 EC16h XPWM module up/down counter 3 0000h XPW0 EC30h XPWM module pulse width register 0 0000h XPW1 EC32h XPWM module pulse width register 1 0000h XPW2 EC34h XPWM module pulse width register 2 0000h XPW3 EC36h XPWM module pulse width register 3 0000h XPWMCON0 EC00h XPWM module control register 0 0000h XPWMCON0CLR EC08h XPWM module clear control reg. 0 (write only) XPWMCON0SET EC06h XPWM module set control register 0 (write only) XPWMCON1 EC02h XPWM module control register 1 XPWMCON1CLR EC0Ch XPWM module clear control reg. 0 (write only) XPWMCON1SET EC0Ah XPWM module set control register 0 (write only) 0000h XPWMPORT EC80h XPWM module port control register 0000h XS1BG E906h XASC Baud rate generator reload register 0000h XS1CON E900h XASC control register 0000h XS1CONCLR E904h XASC clear control register (write only) 0000h XS1CONSET E902h XASC set control register (write only) 0000h XS1PORT E980h XASC port control register 0000h E90Ah XASC receive buffer register 0000h E908h XASC transmit buffer register 0000h E80Ah XSSC Baud rate register 0000h E800h XSSC control register 0000h XSSCCONCLR E804h XSSC clear control register (write only) 0000h XSSCCONSET E802h XSSC set control register (write only) 0000h XSSCPORT E880h XSSC port control register 0000h XSSCRB E808h XSSC receive buffer XXXXh XSSCTB E806h XSSC transmit buffer 0000h t c u XS1TBUF XSSCBR e t e ol 23.3 od Pr XSSCCON e t e ol ) (s XS1RBUF s b O Reset value Description u d o ) s ( ct Pr s b O 0000h 0000h 0000h 0000h Flash registers ordered by name The following table lists all Flash Control Registers which are implemented in the ST10F271Z1 ordered by their name. These registers are physically mapped on the IBus, except for XFVTAUR0, which is mapped on XBus. Note: These registers are not bit-addressable. 119/185 Register set ST10F271Z1 Table 54. List of Flash registers Physical address Name Description Reset value FARH 0x0008 0012 Flash address register - high 0000h FARL 0x0008 0010 Flash address register - low 0000h FCR0H 0x0008 0002 Flash control register 0 - high 0000h FCR0L 0x0008 0000 Flash control register 0 - low 0000h FCR1H 0x0008 0006 Flash control register 1 - high 0000h FCR1L 0x0008 0004 Flash control register 1 - low 0000h FDR0H 0x0008 000A Flash data register 0 - high FDR0L 0x0008 0008 Flash data register 0 - low FDR1H 0x0008 000E Flash data register 1 - high FDR1L 0x0008 000C Flash data register 1 - low FER 0x0008 0014 Flash error register FNVAPR0 0x0008 DFB8 Flash non-volatile access protection reg.0 ACFFh FNVAPR1H 0x0008 DFBE Flash non-volatile access protection reg.1 - high FFFFh FNVAPR1L 0x0008 DFBC Flash non-volatile access protection reg.1 - low FFFFh FNVWPIR 0x000E DFB0 Flash non-volatile protection I register FFFFh XFVTAUR0 0x0000 EB50 XBus Flash volatile temporary access unprotection register 0 FFFFh ) s ( ct FFFFh FFFFh du e t e ol )- o r P s b O FFFFh FFFFh 0000h s ( t 23.4 Identification registers c u d o r P e t e l o s b O The ST10F271Z1 has four Identification registers, mapped in ESFR space. These registers contain: Note: A manufacturer identifier A chip identifier with its revision A internal Flash and size identifier Programming voltage description As the ST10F271Z1 device is supported with the silicon of the ST10F272 (commercial version of the same product), the identification registers provide the values corresponding to the ST10F272 device. IDMANUF (F07Eh / 3Fh) 15 14 13 12 11 ESFR 10 MANUF R 120/185 9 8 Reset Value: 0403h 7 6 5 4 3 2 1 0 0 0 0 1 1 R ST10F271Z1 Register set Table 55. IDMANUF Bit Function Manufacturer identifier 020h: STMicroelectronics manufacturer (JTAG worldwide normalization). MANUF IDCHIP (F07Ch / 3Eh) 15 14 13 Table 56. 12 ESFR 11 10 9 8 14 13 12 11 9 )- u d o IDMEM r P e MEMTYP 10 s ( t c R 1 8 0 u d o r P e t e l o s b O ESFR MEMTYP O 2 ) s ( ct Function IDMEM (F07Ah / 3Dh) o s b 3 IDCHIP REVID let 4 R Device revision identifier Xh: According to revision number. MEMSIZE 5 R Device identifier 110h: ST10F271Z1 identifier (272). Bit 6 REVID IDCHIP Table 57. 7 IDCHIP Bit 15 Reset Value: 110Xh 7 6 Reset Value: 3040h 5 4 3 2 1 0 MEMSIZE R Function Internal memory size Internal memory size is 4 x (MEMSIZE) (in Kbyte) 040h for 256 Kbytes (ST10F272) Internal memory type `0h': ROM-Less `1h': (M) ROM memory `2h': (S) Standard Flash memory `3h': (H) High performance Flash memory (ST10F271Z1) `4h...Fh': Reserved 121/185 Register set ST10F271Z1 IDPROG (F078h / 3Ch) 15 14 Table 58. 13 12 ESFR 11 10 9 8 Reset Value: 0040h 7 5 4 3 PROGVPP PROGVDD R R 2 1 0 IDPROG Bit Note: 6 Function PROGVDD Programming VDD voltage VDD voltage when programming EPROM or Flash devices is calculated using the following formula: VDD = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F271Z1 (5V). PROGVPP Programming VPP voltage (no need of external VPP) - 00h ) s ( ct All identification words are read only registers. u d o The values written inside different Identification Register bits are valid only after the Flash initialization phase is completed. When code execution is started from internal memory (pin EA held high during reset), the Flash has certainly completed its initialization, so the bits of identification registers are immediately ready to be read out. On the contrary, when code execution is started from external memory (pin EA held low during reset), the Flash initialization is not yet completed, so the bits of identification registers are not ready. The user can poll bits 15 and 14 of IDMEM register: when both bits are read low, the Flash initialization is complete, so all identification register bits are correct. r P e t e l o s b O Before Flash initialization completion, the default setting of the different identification registers are the following: IDMANUF 0403h IDCHIP 110xh (x = silicon revision) IDMEM F040h IDPROG t e l o 122/185 t c u od r P e s b O ) (s 0040h ST10F271Z1 24 Known limitations Known limitations This section describes all functional and electrical limitations identified on the silicon revision A of the ST10F271Z1. They are listed in Table 59: List of limitations on page 123 The revision number of the device can be read in the IDCHIP register (@F07Ch) which is set to 1102h for this device (refer to 23.4: Identification registers). Table 59. List of limitations Limitation 24.1: Injected conversion stalling the ADC ) s ( ct 24.2: Concurrent transmission requests in DAR-mode (C-CAN module) 24.3: Transmission request disabled (C-CAN module) u d o 24.4: Spurious BREQ pulse in slave mode during external bus arbitration phase 24.5: Flash wake-up from idle mode r P e 24.6: Executing PWRDN instruction t e l o 24.7: Flash wake-up from power-down mode 24.8: Behavior of CAPCOM outputs in compare mode 3 ) (s s b O t c u d o r P e t e l o s b O 123/185 Known limitations 24.1 ST10F271Z1 Injected conversion stalling the ADC Description Whenever a new injection request occurs before the ADDAT2 register has been read by the CPU (that is, when the result of the previous injection request has not been read), the ADC is stalled and no further conversions are performed. Workaround The following actions make it possible to unlock the ADC module: 1. Read the ADDAT2 register twice at the end of every injected conversion. This action also prevents the ADC from being stalled). 2. Disable and then enable again the wait for read mode Application conditions ) s ( ct u d o This problem can occur if all the following conditions are fulfilled: r P e Injection requests are hardware triggered (via CapCom CC31) The result of injected conversions is read via a PEC transfer. This prevents from reading twice the ADDAT2 register by software) A high level task is disabling the PEC transfer for a long time (2 analog conversions + time between 2 injection requests) t e l o s b O Therefore, to prevent the locking situation from occurring, it is important to make sure that, at application level, no task can disable interrupts for a period of time during which 2 injection requests can occur before a read operation is performed. Detailed analysis ) (s t c u Channel injection mode allows the conversion of a specific analog channel without changing the current operating mode. It can also be used while the ADC is running in a continuous or auto scan mode. The following main points need to be highlighted: P e t e l o s b O d o r Wait for ADDAT read mode is needed in order for the ADC Channel Injection mode to operate properly At the end of the injected conversion the data is available in the alternate result register ADDAT2 and a Channel Injection Complete Interrupt request is generated (ADEIR Flag) If the temporary data register used for ADDAT2 read mode is full, the next conversion (standard or injected) is suspended. The temporary register then stores the content of ADDAT (standard conversion) or ADDAT2 (from an injected conversion). If the temporary data register used for ADDAT2 read mode is full and a new injection request occurs then the new converted value is stored into a temporary data register until the previous one is read from ADDAT2. To ensure a correct operation as soon as ADDAT2 register is read, the last converted value should be moved from temporary register to ADDAT2 and the ADEINT interrupt should be requested. The last converted value can then be read by the CPU. See Figure 37. In real circumstances, as soon as ADDAT2 register is read then the last converted value is correctly moved from temporary register to ADDAT2 but the ADEINT interrupt request is not received by the Interrupt Controller (see Figure 38). As a consequence, the CPU/PEC can 124/185 ST10F271Z1 Known limitations not know that a new converted value is ready to be read in ADDAT2 register. Therefore at the following injection request the ADC fills the temporary register again (without generating any ADEINT interrupt request) and then the ADC is stalled for any further conversion. The ADC stays in the "wait for read ADDAT2 register" condition forever. Figure 37. ADC injection theoretical operation ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 125/185 Known limitations ST10F271Z1 Figure 38. ADC injection actual operation ) s ( ct u d o ADEINT Interrupt not generated let r P e o s b O ) s ( t c u d o r P e t e l o s b O 126/185 ADDAT2 correctly updated and can be read by software ST10F271Z1 24.2 Known limitations Concurrent transmission requests in DAR-mode (C-CAN module) Description When the C-CAN module is configured to operate in DAR-mode (Disable Automatic Retransmission) and the host requests the transmission of several messages at the same time, only two of these messages are transmitted. For all other requested transmit messages, the TxRqst bits are reset but no transmission starts, NewDat and IntPnd are kept unchanged. For the two messages which are transmitted, the TxRqst and NewDat bits are reset and IntPnd is set if it has been enabled by TxIE. The normal operation mode (DAR = 0) is not affected by this phenomenon. ) s ( ct Workaround The DAR-mode is intended to support time triggered operation (TTCAN level 1), accepting the transmission of a message only in its dedicated time window. It is an error to request the transmission of several messages at the same time. So no workaround is necessary for TTCAN applications. u d o r P e The progress of a requested transmission can be monitored by checking the message object's TxRqst and NewDat [optionally IntPnd] bits. In DAR-Mode, when a message transmission has failed either because the transmission was disturbed or because it has not started, it is necessary to request the message transmission again. t e l o s b O For details on DAR mode and message control registers, refer to user manual UM0409. ) (s t c u d o r P e t e l o s b O 127/185 Known limitations 24.3 ST10F271Z1 Transmission request disabled (C-CAN module) Description The transmission request of a message object may remain disabled (even if the host immediately enables it again) in the following situations: 1. if the host disables the pending transmission request of the lowest-priority message object (number 32 by default) in the short time window during which the message handler state machine prepares the transmission of the message 2. if the transmission has not started. Reading the transmission request bit of this message object does not show that the transmission request is disabled. This only happens when this message object is the only one with a pending transmission request. ) s ( ct If the transmission request is blocked in the disabled state, it will be re-enabled by the first activity detected on the CAN bus or by setting the transmission request of any other message object. r P e u d o The other message objects are not affected by this phenomenon. Workaround t e l o It is usually not necessary to disable the transmission request of a message object. If the message object is to be used for another message, it is sufficient to prepare the new content for this message object in the CPU interface register (Identifier, DLC, Data, with TxRqst and NewDat [optionally TxIE] bits) and to transfer this content into the message object. The new content is transmitted at the next opportunity. It is not altered by a possibly ongoing transmission of the previous content of the same message object. ) (s t c u d o r P e t e l o s b O 128/185 s b O ST10F271Z1 24.4 Known limitations Spurious BREQ pulse in slave mode during external bus arbitration phase Description Sporadic bus errors may occur when external bus arbitration is used via the HOLD function and the ST10F272Z2 is configured as a slave. After the slave has been granted access to the bus, the slave disables the BREQ signal sporadically for a short time, even though slave access to the bus has not been completed. The master starts then its own bus access, generating a bus conflict between master and slave. ) s ( ct Workaround To avoid producing any spurious BREQ pulse during a slave external bus arbitration phase, it is necessary to guarantee that the time between the HLDA assertion (Bus Acknowledge from Master device) and the following HOLD falling edge (Bus Request from Master) is longer than three clock cycles. u d o r P e This can be implemented by delaying the HOLD signal with an RC circuit as shown in Figure 3. t e l o Figure 39. ST10 in Slave mode HOLD ) (s t e l o BREQ (P6.7) HLDA HLDA (P6.6) BREQ HOLD (P6.5) t c u od r P e s b O ST10 in Slave mode Master VSS s b O 129/185 Known limitations 24.5 ST10F271Z1 Flash wake-up from idle mode Description When waking up from idle mode, the Flash response time is slower than in running mode. This can lead to an incorrect data read or code fetch when the CPU frequency is higher than 55 MHz. As a consequence, the use of IDLE instruction is not allowed for frequencies higher than 55 MHz. Workaround There is no workaround for frequencies higher than 55 MHz. 24.6 Executing PWRDN instruction ) s ( ct u d o Description r P e The power-down mode is not entered and the PWRDN instruction is ignored in the following cases: t e l o The PWRDN instruction is executed while NMI is high (PWDCFG bit of the SYSCON register cleared) The PWRDN instruction is executed while at least one of the Port 2 pins used to exit from power-down mode (PWDCFG bit of the SYSCON register is set) is at the active level. ) (s s b O However, under the conditions described below, the PWRDN instruction is not ignored, and no further instructions are fetched from external memory, that is, the CPU is in a quasi-idle state. t c u This problem only occurs in the following situations: 1. P e t e l o 2. s b O Note: d o r The instructions following the PWRDN instruction are located in an external memory and a multiplexed bus configuration with memory tristate waitstate (bit MTTCx = 0) is used. The instruction preceding the PWRDN instruction writes to external memory or an XPeripheral (such as XRAM or CAN) and the instructions following the PWRDN instruction are located in external memory. In this case, the problem occurs for any bus configuration. The on-chip peripherals still work correctly, in particular the watchdog timer. if the watchdog timer is not disabled, it resets the device upon an overflow. However, interrupts and PEC transfers cannot be processed. If NMI is asserted low while the device is in this quasi-idle state, power-down mode is entered. No problem occurs if the NMI pin is low (if PWDCFG = 0) or if all Port 2 pins used to exit from power-down mode are at inactive level (if PWDCFG = 1): the chip enters normally power-down mode. Workaround Ensure that no instruction that writes to external memory or to an XPeripheral precedes the PWRDN instruction. Otherwise, insert a NOP instruction in front of PWRDN. When a 130/185 ST10F271Z1 Known limitations multiplexed bus with memory tristate wait state is used, the PWRDN instruction must be executed from internal RAM or XRAM. 24.7 Flash wake-up from power-down mode Description When waking up from interruptible power-down mode, the Flash response time is slower than in running mode. This can lead to an incorrect data read or code fetch when the CPU frequency is higher than 55 MHz. As a consequence, exiting from interruptible power-down mode with an external interrupt is not supported for frequencies greater than 55 MHz. ) s ( ct Workaround u d o There is no workaround for frequencies greater than 55 MHz. Exiting from interruptible power-down mode with an external reset is supported at all frequencies. 24.8 r P e t e l o Behavior of CAPCOM outputs in compare mode 3 Description s b O When a CAPCOM channel is configured in compare mode 3, then the related output level switches to high when the allocated timer, Tx, matches the related CAPCOM register, CCy. When an overflow occurs on the CAPCOM timer Tx, it is reloaded with TxREL content and the output pin is cleared. The output pin level does not change if TxREL and CCy have the same value. ) (s t c u d o r The related CAPCOM output stays low when the CAPCOM channel is configured in compare mode 3 and TxREL and Tx related timer registers are loaded with the same value as CCy. This is obtained by executing the following instructions: P e s b O t e l o MOV TxREL, #CCy value x =0,1,7,8 MOV Tx, #CCy value x = 0,1,7,8 MOV TxxCON, #data or bfldl/bfldh TxxCON , #mask, #data i.e. an access is made to the T01CON or T78CON register. Workarounds The following workarounds make the CAPCOM output toggle as expected: 1) Invert the TxREL and Tx configuration as follow: MOV Tx, #CCy value MOV TxREL, #CCy value bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data 2) Insert a NOP instruction before the T01CON or T78CON configuration: MOV Tx, #value MOV TxREL, #value NOP bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data 131/185 Known limitations ST10F271Z1 3) Load the Tx timer with the CCy register minus 1: MOV TxREL, #value MOV Tx, #( value-1) bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 132/185 s b O ST10F271Z1 Electrical characteristics 25 Electrical characteristics 25.1 Absolute maximum ratings Table 60. Absolute maximum ratings Symbol Parameter Values Unit VDD Voltage on VDD pins with respect to ground (VSS) -0.5 to +6.5 V VSTBY Voltage on VSTBY pin with respect to ground (VSS) -0.5 to +6.5 V VAREF Voltage on VAREF pins with respect to ground (VSS) -0.3 to VDD V VAGND Voltage on VAGND pins with respect to ground (VSS) VSS VIO Voltage on any pin with respect to ground (VSS) IOV Input current on any pin during overload condition ITOV Absolute sum of all input currents during overload condition TST Storage temperature ESD ESD Susceptibility (Human Body Model) Note: V ct -0.5 to VDD + 0.5 du 10 ro V mA | 75 | mA -65 to +150 C 2000 V P e t e l o (s) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined by the Absolute Maximum Ratings. ) (s s b O t c u During Power-on and Power-off transients (including Standby entering/exiting phases), the relationships between voltages applied to the device and the main VDD shall be always respected. In particular power-on and power-off of VAREF shall be coherent with VDD transient, in order to avoid undesired current injection through the on-chip protection diodes. d o r P e t e l o s b O 133/185 Electrical characteristics ST10F271Z1 25.2 Recommended operating conditions Table 61. Recommended operating conditions Value Symbol VDD VSTBY VAREF Parameter Unit Operating supply voltage Operationg stand-by supply voltage (1) Operating analog reference voltage (2) min max 4.5 5.5 V 4.5 5.5 V C TA Ambient temperature under bias -40 +125 TJ Junction temperature under bias -40 +150 ) s ( ct C 1. The value of the VSTBY voltage is specified in the range 4.5 - 5.5 Volt. Nevertheless, it is acceptable to exceed the upper limit (up to 6.0 Volt) for a maximum of 100 hours over the global 300000 hours, representing the lifetime of the device (about 30 years). On the other hand, it is possible to exceed the lower limit (down to 4.0 Volt) whenever RTC and 32kHz on-chip oscillator amplifier are turned off (only Stand-by RAM powered through VSTBY pin in Stand-by mode). When VSTBY voltage is lower than main VDD, the input section of VSTBY/EA pin can generate a spurious static consumption on VDD power supply (in the range of tenth of A). r P e 2. For details on operating conditions concerning the usage of A/D Converter refer to Section 25.7. 25.3 u d o t e l o Power considerations s b O The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation: ) (s TJ = TA + (PD x JA) (1) Where: t c u TA is the Ambient Temperature in C, JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, d o r PD is the sum of PINT and PI/O (PD = PINT + PI/O), P e PINT is the product of IDD and VDD, expressed in Watt. This is the Chip Internal Power, t e l o PI/O represents the Power Dissipation on Input and Output Pins; User Determined. s b O Most of the time for the applications PI/O < PINT and may be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273C) (2) Therefore (solving equations 1 and 2): K = PD x (TA + 273C) + JA x PD2 (3) Where: K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA. 134/185 ST10F271Z1 Electrical characteristics Table 62. Thermal characteristics Symbol Description Value (typical) Unit JA Thermal Resistance Junction-Ambient PQFP 144 - 28 x 28 x 3.4 mm / 0.65 mm pitch LQFP 144 - 20 x 20 mm / 0.5 mm pitch LQFP 144 - 20 x 20 mm / 0.5 mm pitch on four layer FR4 board (2 layers signals / 2 layers power) 30 40 35 C/W Based on thermal characteristics of the package and with reference to the power consumption figures provided in next tables and diagrams, the following product classification can be proposed. Anyhow, the exact power consumption of the device inside the application must be computed according to different working conditions, thermal profiles, real thermal resistance of the system (including printed circuit board or other substrata), I/O activity, and so on. Table 63. 25.4 ) s ( ct u d o Package characteristics Package Ambient temperature range PQFP 144 -40 / +125 C LQFP 144 C -40 / +125 Parameter interpretation r P e CPU frequency range let o s b 1 - 64 MHz 1 - 40 MHz O ) The parameters listed in the following tables represent the characteristics of the ST10F271Z1 and its demands on the system. s ( t c Where the ST10F271Z1 logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics, is included in the "Symbol" column. Where the external system must provide signals with their respective timing characteristics to the ST10F271Z1, the symbol "SR" for System Requirement, is included in the "Symbol" column. u d o r P 25.5 DCecharacteristics t e l o s b O VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C Table 64. DC characteristics Parameter Limit values Symbol min. max. Unit Test condition Input low voltage (TTL mode) (except RSTIN, EA, NMI, RPD, XTAL1, READY) VIL SR - 0.3 0.8 V - Input low voltage (CMOS mode) (except RSTIN, EA, NMI, RPD, XTAL1, READY) VILS SR - 0.3 0.3 VDD V - Input low voltage RSTIN, EA, NMI, RPD VIL1 SR - 0.3 0.3 VDD V - Input low voltage XTAL1 (CMOS only) VIL2 SR - 0.3 0.3 VDD V Direct Drive mode 135/185 Electrical characteristics Table 64. ST10F271Z1 DC characteristics (continued) Limit values Parameter Symbol Unit Test condition 0.8 V - 2.0 VDD + 0.3 V - min. max. - 0.3 Input low voltage READY (TTL only) VIL3 SR Input high voltage (TTL mode) (except RSTIN, EA, NMI, RPD, XTAL1) VIH Input high voltage (CMOS mode) (except RSTIN, EA, NMI, RPD, XTAL1) VIHS SR 0.7 VDD VDD + 0.3 V - Input high voltage RSTIN, EA, NMI, RPD VIH1 SR 0.7 VDD VDD + 0.3 V - Input high voltage XTAL1 (CMOS only) VIH2 SR 0.7 VDD VDD + 0.3 V Direct Drive mode Input high voltage READY (TTL only) VIH3 SR 2.0 VDD + 0.3 V - Input Hysteresis (TTL mode) (except RSTIN, EA, NMI, XTAL1, RPD) VHYS CC 400 700 mV Input Hysteresis (CMOS mode) (except RSTIN, EA, NMI, XTAL1, RPD) VHYSSCC 750 1400 Input Hysteresis RSTIN, EA, NMI VHYS1CC 750 Input Hysteresis XTAL1 VHYS2CC 0 Input Hysteresis READY (TTL only) VHYS3CC Input Hysteresis RPD VHYS4CC Output low voltage (P6[7:0], ALE, RD, WR/WRL, BHE/WRH, CLKOUT, RSTIN, RSTOUT) s b O VOL CC SR e t e ol u d o Pr mV ) s ( ct (1) (1) mV (1) 50 mV (1) 700 mV (1) 1500 mV (1) - 0.4 0.05 V IOL = 8 mA IOL = 1 mA VOL1 CC - 0.4 0.05 V IOL1 = 4 mA IOL1 = 0.5 mA VOL2 CC - VDD 0.5 VDD 0.3 VDD V IOL2 = 85 A IOL2 = 80 A IOL2 = 60 A Output high voltage (P6[7:0], ALE, RD, WR/WRL, BHE/WRH, CLKOUT, RSTOUT) VOH CC VDD - 0.8 VDD - 0.08 - V IOH = - 8 mA IOH = - 1 mA Output high voltage (2) (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0], P4[7:0], P7[7:0], P8[7:0]) VOH1 CC VDD - 0.8 VDD - 0.08 - V IOH1 = - 4 mA IOH1 = - 0.5 mA Output high voltage RPD VOH2 CC 0 0.3 VDD 0.5 VDD - V IOH2 = - 2 mA IOH2 = - 750 A IOH2 = - 150 A Input leakage current (P5[15:0]) (3) |IOZ1 | CC - 0.2 A - Input leakage current (all except P5[15:0], P2[0], RPD, P3[12], P3[15]) |IOZ2 | CC - 0.5 A - s ( t c u d o Output low voltage (P0[15:0], P1[15:0], P2[15:0], P3[15,13:0], P4[7:0], P7[7:0], P8[7:0]) r P e t e l o Output low voltage RPD s b O 136/185 )- 400 500 1400 ST10F271Z1 Table 64. Electrical characteristics DC characteristics (continued) Limit values Parameter Symbol min. max. Unit Test condition Input leakage current (P2[0]) (4) |IOZ3 | CC - +1.0 -0.5 A - Input leakage current (RPD) |IOZ4 | CC - 3.0 A - Input leakage current ( P3[12], P3[15]) |IOZ5 | CC - 1.0 A - Overload current (all except P2[0]) |IOV1 | SR - 5 mA (1) (5) Overload current (P2[0]) (4) |IOV2 | SR - +5 -1 mA (1) (5) RSTIN pull-up resistor RRST CC 50 250 k 100 k nominal IRWH - -40 A VOUT = 2.4 V IRWL -500 - A IALEL 20 - IALEH - 300 IP6H - Read/Write inactive current (6) (7) Read/Write active current ALE inactive current ALE active current (6) (8) (6) (7) (6) (8) Port 6 inactive current (P6[4:0]) (6) (7) e t e ol u d o Pr A A ) s ( ct VOUT = 0.4 V VOUT = 0.4 V VOUT = 2.4 V -40 A VOUT = 2.4 V - A VOUT = 0.4 V -10 A VIN = 2.0 V -100 - A VIN = 0.8 V - 10 pF (1) (6) - 15 + 1.5 fCPU mA - ICC2 - 15 + 1.5 fCPU mA - IID - 15 + 0.6 fCPU mA - Power-down supply current (12) (RTC off, Oscillators off, Main Voltage Regulator off) IPD1 - 200 A TA = 25 C Power-down supply current (12) (RTC on, Main Oscillator on, Main Voltage Regulator off) IPD2 - 400 Typical Value A TA = 25 C Power-down supply current (12) (RTC on, 32kHz Oscillator on, Main Voltage Regulator off) IPD3 - 200 A TA = 25 C - 120 A VSTBY = 5.5 V TA = TJ = 25 C - 500 A VSTBY = 5.5 V TA = TJ = 125 C Port 6 active current (P6[4:0]) (6) (8) IP6L PORT0 configuration current (6) -500 IP0H 6) IP0L 7) - )- Pin Capacitance (Digital inputs / outputs) CIO CC Run Mode Power supply current (9) (Execution from Internal RAM) s ( t c u d o Run Mode Power supply current (1) (10) (Execution from Internal Flash) r P e Idle mode supply current (11) t e l o s b O Stand-by supply current (12) (RTC off, Oscillators off, VDD off, VSTBY on) ICC1 s b O ISB1 137/185 Electrical characteristics Table 64. ST10F271Z1 DC characteristics (continued) Limit values Parameter Symbol Stand-by supply current (12) (RTC on, 32 kHz Oscillator on, main VDD off, VSTBY on) ISB2 Stand-by supply current (1) (12) (VDD transient condition) ISB3 Unit Test condition 120 A VSTBY = 5.5 V TA = TJ = 125 C - 500 A VSTBY = 5.5 V TA = TJ = 125 C - 2.5 mA - min. max. - 1. Not 100% tested, guaranteed by design characterization. ) s ( ct 2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage is imposed by the external circuitry. 3. Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default, after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins. u d o 4. The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes) implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits: failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 40: Port2 test mode structure for a scheme of the input circuitry. r P e 5. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.3 V or VOV < -0.3 V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The supply voltage must remain within the specified limits. t e l o 6. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. s b O 7. The maximum current may be drawn while the respective signal line remains inactive. 8. The minimum current must be drawn in order to drive the respective signal line active. ) (s 9. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is illustrated in the Figure 41 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is doing the following: t c u Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules Watchdog Timer is enabled and regularly serviced RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6) ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5 All interrupts generated by XPWM, RTC, Timers and ADC are not serviced d o r P e t e l o 10. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is illustrated in the Figure 38 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is doing the following: - Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM - Watchdog Timer is enabled and regularly serviced - RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles - Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling - Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6) - ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5 - All interrupts generated by XPWM, RTC, Timers and ADC are not serviced s b O 11. The Idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is illustrated in the Figure 37 below. These parameters are tested and at maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min. 12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VAREF = 0 V, all outputs (including pins configured as outputs) disconnected. Besides, the Main Voltage Regulator is assumed off: in case it is not, additional 1mA shall be assumed. 138/185 ST10F271Z1 Electrical characteristics Figure 40. Port2 test mode structure P2.0 CC0IO Output buffer Clock Alternate data input Input latch Fast external interrupt input ) s ( ct Test mode Flash sense amplifier and column decoder u d o Figure 41. Supply current versus the operating frequency (run and idle modes) r P e 150 t e l o 100 I [mA] ) (s s b O ICC1 = ICC2 t c u IID d o r 50 P e s b O t e l o 0 0 10 20 30 40 fCPU [MHz] 50 60 70 139/185 Electrical characteristics 25.6 ST10F271Z1 Flash characteristics VDD = 5 V 10%, VSS = 0 V Table 65. Flash characteristics Parameter Typical Maximum TA = 25 C TA = 125 C Unit Notes 0 cycles(1) 0 cycles(1) 100k cycles 35 80 290 s - Double word program (64-bit) 60 150 570 s - Bank 0 program (128K) (double word program) 1.6 2.0 3.9 s - Sector erase (8K) 0.6 0.5 0.9 0.8 1.0 0.9 s not preprogrammed preprogrammed Sector erase (32K) 1.1 0.8 2.0 1.8 2.7 2.5 s Sector erase (64K) 1.7 1.3 3.7 3.3 5.1 4.7 s not preprogrammed preprogrammed Bank 0 erase (128K) (3) 5.6 4.0 13.6 11.9 19.2 17.5 s not preprogrammed preprogrammed 40 40 s 10 10 s - 30 30 s 20 20 20 ms 40 90 300 s Word program (32-bit) (2) (2)) Recovery from power-down (tPD) - Program suspend latency (4) - Erase suspend latency (4) Erase suspend request rate (4) Set protection (4) e t e ol t(s c u d o r P O ) bs e t e ol ) s ( ct u d o Pr not preprogrammed preprogrammed (4) Min delay between 2 requests 1. The figures are given after about 100 cycles due to testing routines (0 cycles at the final customer). 2. Word and Double Word Programming times are provided as average values derived from a full sector programming time: absolute value of a Word or Double Word Programming time could be longer than the average value. s b O 3. Bank Erase is obtained through a multiple Sector Erase operation (setting bits related to all sectors of the Bank). As ST10F271Z1 implements only one bank, the Bank Erase operation is equivalent to Module and Chip Erase operations. 4. Not 100% tested, guaranteed by Design Characterization. 140/185 ST10F271Z1 Table 66. Electrical characteristics Flash data retention characteristics Data retention time Number of program / erase cycles (average ambient temperature 60C) (-40 C TA 125 C) 128 Kbyte (code store) 64 Kbyte (EEPROM emulation) (1) 0 - 100 > 20 years > 20 years 1,000 - > 20 years 10,000 - 10 years 100,000 - 1 year 1. Two 64 Kbyte Flash Sectors may be typically used to emulate up to 4, 8 or 16 Kbyte of EEPROM. Therefore, in case of an emulation of a 16 Kbyte EEPROM, 100,000 Flash Program / Erase cycles are equivalent to 800,000 EEPROM Program/Erase cycles. For an efficient use of the EEPROM Emulation please refer to dedicated Application Note document (AN2061 - "EEPROM Emulation with ST10F2xx"). Contact your local field service, local sales person or STMicroelectronics representative to get copy of such a guideline document. ) s ( ct 25.7 u d o A/D converter characteristics r P e VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C, 4.5 V VAREF VDD, VSS VAGND VSS + 0.2 V Table 67. t e l o A/D converter characteristics s b O Limit values Parameter Symbol ) (s VAREF SR min. Unit Test condition max. 4.5 VDD V VAGND SR VSS VSS + 0.2 V VAIN SR VAGND VAREF V IAREF CC - - 5 1 mA A Running mode 3) Power-down mode tS CC 1 - s 4) tC CC 3 - s 5) DNL CC -1 +1 LSB No overload INL CC -1.5 +1.5 LSB No overload OFS CC -1.5 +1.5 LSB No overload Total unadjusted error 6) TUE CC -2.0 -5.0 -7.0 +2.0 +5.0 +7.0 LSB Port5 Port1 - No overload 3) Port1 - Overload 3) Coupling factor between inputs 3) 7) K CC - 10-6 - On both Port5 and Port1 CP1 CC - 3 pF CP2 CC - 4 6 pF CS - 3.5 pF Analog reference voltage 1) ct Analog ground voltage du Analog input voltage 2) o r P Reference supply current e t e ol Sample time Conversion time Differential non linearity 6) s b O Integral non linearity Offset error 6) 6) Input pin capacitance 3) 8) Sampling capacitance 3) 8) CC Port5 Port1 141/185 Electrical characteristics Table 67. ST10F271Z1 A/D converter characteristics Limit values Parameter Symbol Unit min. Analog switch resistance 3) 8) Test condition max. RSW CC - - 600 1600 W RAD CC - 1300 W Port5 Port1 1. VAREF can be tied to ground when A/D Converter is not in use: an extra consumption (around 200A) on main VDD is added due to internal analogue circuitry not completely turned off: so, it is suggested to maintain the VAREF at VDD level even when not in use, and eventually switch off the A/D Converter circuitry setting bit ADOFF in ADCON register. 2. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 0x000H or 0x3FFH, respectively. ) s ( ct 3. Not 100% tested, guaranteed by design characterization. 4. During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depends on programming and can be taken from Table 68: A/D converter programming. u d o r P e 5. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from next Table 68. t e l o 6. DNL, INL, OFS and TUE are tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 5.0 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. `LSB' has a value of VAREF/1024. For Port5 channels, the specified TUE ( 2LSB) is guaranteed also with an overload condition (see IOV specification) occurring on maximum 2 not selected analog input pins of Port5 and the absolute sum of input overload currents on all Port5 analog input pins does not exceed 10 mA. For Port1 channels, the specified TUE is guaranteed when no overload condition is applied to Port1 pins: when an overload condition occurs on maximum 2 not selected analog input pins of Port1 and the input positive overload current on all analog input pins does not exceed 10 mA (either dynamic or static injection), the specified TUE is degraded ( 7LSB). To get the same accuracy, the negative injection current on Port1 pins shall not exceed -1mA in case of both dynamic and static injection. ) (s s b O t c u 7. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channels with the overload current within the different specified ranges (for both positive and negative injection current). d o r 8. Refer to scheme reported in Figure 43: A/D converter input pins scheme. 25.7.1 P e Conversion timing control t e l o s b O When a conversion is started, first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as sample time. Next the sampled voltage is converted to a digital value several successive steps, which correspond to the 10-bit resolution of the ADC. During these steps the internal capacitances are repeatedly charged and discharged via the VAREF pin. The current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes, because the capacitors must reach their final voltage level within the given time, at least with a certain approximation. The maximum current, however, that a source can deliver, depends on its internal resistance. The time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the ST10F271Z1 relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller. This allows adjusting the A/D converter of the ST10F271Z1 to the properties of the system: 142/185 ST10F271Z1 Electrical characteristics Fast conversion can be achieved by programming the respective times to their absolute possible minimum. This is preferable for scanning high frequency signals. The internal resistance of analog source and analog supply must be sufficiently low, however. High internal resistance can be achieved by programming the respective times to a higher value, or the possible maximum. This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible. The conversion rate in this case may be considerably lower, however. The conversion times are programmed via the upper four bits of register ADCON. Bit fields ADCTC and ADSTC are used to define the basic conversion time and in particular the partition between sample phase and comparison phases. The table below lists the possible combinations. The timings refer to the unit TCL, where fCPU = 1/2TCL. A complete conversion time includes the conversion itself, the sample time and the time required to transfer the digital value to the result register. Table 68. A/D converter programming ADCTC ADSTC u d o Pr Total conversion TCL * 120 TCL * 240 TCL * 28 00 01 TCL * 140 TCL * 280 TCL * 16 TCL * 436 00 10 TCL * 200 TCL * 280 TCL * 52 TCL * 532 00 11 TCL * 400 TCL * 280 TCL * 44 TCL * 724 11 00 TCL * 240 TCL * 480 TCL * 52 TCL * 772 11 01 TCL * 280 TCL * 560 TCL * 28 TCL * 868 11 10 TCL * 400 TCL * 560 TCL * 100 TCL * 1060 11 11 TCL * 800 TCL * 560 TCL * 52 TCL * 1444 10 00 TCL * 480 TCL * 960 TCL * 100 TCL * 1540 10 01 TCL * 560 TCL * 1120 TCL * 52 TCL * 1732 10 TCL * 800 TCL * 1120 TCL * 196 TCL * 2116 11 TCL * 1600 TCL * 1120 TCL * 164 TCL * 2884 e t e ol 25.7.2 Extra 00 10 s b O Comparison 00 10 Note: Sample ) s ( ct t c u od Pr ) (s e t e ol s b O TCL * 388 The total conversion time is compatible with the formula valid for ST10F269, while the meaning of the bit fields ADCTC and ADSTC is no longer compatible: the minimum conversion time is 388 TCL, which at 40 MHz CPU frequency corresponds to 4.85 s (see ST10F269). A/D conversion accuracy The A/D Converter compares the analog voltage sampled on the selected analog input channel to its analog reference voltage (VAREF) and converts it into 10-bit digital data. The absolute accuracy of the A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: Offset error (OFS) Gain Error (GE) Quantization error Non-Linearity Error (differential and integral) 143/185 Electrical characteristics ST10F271Z1 These four error quantities are explained below using Figure 42: A/D conversion characteristic. Offset error Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) 00 to 01 (Figure 42, see OFS). Gain error Gain error is the deviation between the actual and ideal A/D conversion characteristics when the digital output value changes from the 3FE to the maximum 3FF, once offset error is subtracted. Gain error combined with offset error represents the so-called full-scale error (Figure 42, OFS + GE). ) s ( ct Quantization error u d o Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB. r P e Non-linearity error Non-Linearity error is the deviation between actual and the best-fitting A/D conversion characteristics (see Figure 42): t e l o Differential Non-Linearity error is the actual step dimension versus the ideal one (1 LSBIDEAL). Integral Non-Linearity error is the distance between the center of the actual step and the center of the bisector line, in the actual characteristics. Note that for Integral NonLinearity error, the effect of offset, gain and quantization errors is not included. ) (s s b O t c u Note: Bisector characteristic is obtained drawing a line from 1/2 LSB before the first step of the real characteristic, and 1/2 LSB after the last step again of the real characteristic. 25.7.3 Total unadjusted error P e d o r The Total Unadjusted Error specifies the maximum deviation from the ideal characteristic: the number provided in the datasheet represents the maximum error with respect to the entire characteristic. It is a combination of the Offset, Gain and Integral Linearity errors. The different errors may compensate each other depending on the relative sign of the offset and gain errors. Refer to Figure 42, see TUE. t e l o s b O 144/185 ST10F271Z1 Electrical characteristics Figure 42. A/D conversion characteristic Offset Error OFS Gain Error GE 3FF 3FE (6) 3FD Ideal Characteristic 3FC 3FB 3FA Bisector Characteristic (2) Digital Out (HEX) 007 (7) ) s ( ct (1) 006 u d o 005 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential Non-Linearity Error (DNL) (4) Integral Non-Linearity Error (INL) (5) Center of a step of the actual transfer curve (6) Quantization Error (1/2 LSB) (7) Total Unadjusted Error (TUE) (5) 004 r P e (4) 003 002 (3) 001 1 2 3 4 5 Offset Error OFS 25.7.4 t e l o 1 LSB (ideal) 000 bs 6 7 1018 1020 VAIN (LSBIDEAL) [LSBIDEAL = VAREF / 1024] 1022 1024 O ) s ( t c Analog reference pins u d o The accuracy of the A/D converter depends on how accurate is its analog reference: a noise in the reference results in at least that much error in a conversion. A low pass filter on the A/D converter reference source (supplied through pins VAREF and VAGND), is recommended in order to clean the signal, minimizing the noise. A simple capacitive bypassing may be sufficient in most of the cases; in presence of high RF noise energy, inductors or ferrite beads may be necessary. r P e t e l o O bs In this architecture, VAREF and VAGND pins represents also the power supply of the analog circuitry of the A/D converter: there is an effective DC current requirement from the reference voltage by the internal resistor string in the R-C DAC array and by the rest of the analog circuitry. An external resistance on VAREF could introduce error under certain conditions: for this reasons, series resistance are not advisable, and more in general any series devices in the filter network should be designed to minimize the DC resistance. Analog input pins To improve the accuracy of the A/D converter, it is definitively necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device, can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; 145/185 Electrical characteristics ST10F271Z1 besides, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter, can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC Filter). The RC filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth). Figure 43. A/D converter input pins scheme External circuit Internal circuit scheme VDD Source Filter RS Current Limiter RF VA Channel Selection Sampling RSW RAD RL CF CP1 RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW Channel Selection Switch Impedance RADSampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance e t e ol ) (s ) s ( ct du CP2 CS o r P s b O Input leakage and external circuit The series resistor utilized to limit the current to a pin (see RL in Figure 43), in combination with a large source impedance can lead to a degradation of A/D converter accuracy when input leakage is present. t c u d o r Data about maximum input leakage current at each pin are provided in the Data Sheet (Electrical Characteristics section). Input leakage is greatest at high operating temperatures, and in general it decreases by one half for each 10 C decrease in temperature. P e t e l o s b O Considering that, for a 10-bit A/D converter one count is about 5mV (assuming VAREF = 5 V), an input leakage of 100 nA acting though an RL = 50 k of external resistance leads to an error of exactly one count (5 mV); if the resistance were 100 k the error would become two counts. Eventual additional leakage due to external clamping diodes must also be taken into account in computing the total leakage affecting the A/D converter measurements. Another contribution to the total leakage is represented by the charge sharing effects with the sampling capacitance: being CS substantially a switched capacitance, with a frequency equal to the conversion rate of a single channel (maximum when fixed channel continuous conversion mode is selected), it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 250 kHz, with CS equal to 4 pF, a resistance of 1 M is obtained (REQ = 1 / fCCS, where fC represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the following relation: R S + R F + R L + R SW + R AD 1 V A ------------------------------------------------------------------------------ < --- LSB R EQ 2 146/185 ST10F271Z1 Electrical characteristics The formula above provides a constraints for external network design, in particular on resistive path. A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 40), when the sampling phase is started (A/D switch close), a charge sharing phenomena is installed. Figure 44. Charge sharing timing diagram during sampling phase Voltage Transient on CS VCS VA VA2 V < 0.5 LSB 1 ) s ( ct 2 1 < (RSW + RAD) CS << TS u d o 2 = RL (CS + CP1 + CP2) VA1 TS r P e t t e l o In particular two different transient periods can be distinguished (see Figure 41): A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitance CP and CS are in series, and the time constant is: ) (s t c u s b O CP CS 1 = ( R SW + R AD ) ----------------------CP + CS This relation can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D Converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant: d o r P e s b O t e l o 1 < ( R SW + R AD ) C S < < T S The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to the following equation: V A1 ( C S + C P1 + C P2 ) = V A ( C P1 + C P2 ) A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: 2 < R L ( C S + C P1 + C P2 ) In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on 147/185 Electrical characteristics ST10F271Z1 RL sizing is obtained: 10 2 = 10 R L ( C S + C P1 + C P2 ) TS Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. The following equation must be respected (charge balance assuming now CS already charged at VA1): VA2 ( C S + C P1 + C P2 + C F ) = V A C F + V A1 ( C P1 + C P2 + C S ) ) s ( ct The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing (see Figure 45). u d o r P e Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. t e l o ) (s s b O Figure 45. Anti-aliasing filter and conversion rate t c u Analog Source Bandwidth (VA) d o r P e let o s b Noise TC 2 RFCF (Conversion Rate vs. Filter Pole) fF = f0 (Anti-aliasing Filtering Condition) 2 f0 fC (Nyquist) f0 f Anti-Aliasing Filter (fF = RC Filter pole) Sampled Signal Spectrum (fC = conversion Rate) O fF f f0 fC f The considerations above lead to impose new constraints to the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive the following relation between the ideal and real sampled voltage on CS: VA C P1 + C P2 + C F ----------- = -----------------------------------------------------------V A2 C P1 + C P2 + C F + C S 148/185 ST10F271Z1 Electrical characteristics From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count (~2.44 mV), it is immediately evident a constraints on CF value: C F > 2048 C S In the next section an example of how to design the external network is provided, assuming some reasonable values for the internal parameters and making hypothesis on the characteristics of the analog signal to be sampled. Example of external network sizing The following hypothesis are formulated in order to proceed in designing the external network on A/D Converter input pins: Analog signal source bandwidth (f0): 10 kHz Conversion rate (fC): 25 kHz Sampling time (TS): 1 s Pin input capacitance (CP1): 5 pF Pin input routing capacitance (CP2): 1 pF Sampling capacitance (CS): 4 pF Maximum input current injection (IINJ): 3 mA Maximum analog source voltage (VAM): 12 V Analog source impedance (RS): Channel switch resistance (RSW): Sampling switch resistance (RAD): )- ) s ( ct u d o r P e t e l o s b O 100 500 200 s ( t c u d o r P e t e l o s b O 149/185 Electrical characteristics 1. ST10F271Z1 Supposing to design the filter with the pole exactly at the maximum frequency of the signal, the time constant of the filter is: 1 R C C F = ------------ = 15.9s 2f 0 2. Using the relation between CF and CS and taking some margin (4000 instead of 2048), it is possible to define CF: C F = 4000 C S = 16nF 3. As a consequence of step 1 and 2, RC can be chosen: 1 R F = --------------------- = 995 1k 2f 0 C F 4. ) s ( ct Considering the current injection limitation and supposing that the source can go up to 12V, the total series resistance can be defined as: V AM R S + R F + R L = ------------- = 4k I INJ from which is now simple to define the value of RL: u d o r P e t e l o V AM R L = ------------- - R F - R S = 2.9k I INJ 5. s b O Now the three element of the external circuit RF, CF and RL are defined. Some conditions discussed in the previous paragraphs have been used to size the component, the other must now be verified. The relation which allow to minimize the accuracy error introduced by the switched capacitance equivalent resistance is in this case: ) (s ct u d o 1 R EQ = --------------- = 10M fC CS So the error due to the voltage partitioning between the real resistive path and CS is less then half a count (considering the worst case when VA = 5V): r P e t e l o bs O R S + R F + R L + R SW + R AD 1 V A --------------------------------------------------------------------------- = 2.35mV < --- LSB 2 R EQ The other conditions to be verified is the time constants of the transients are really and significantly shorter than the sampling period duration TS: 1 = ( R SW + R AD ) C S = 2.8ns << TS = 1s 10 2 = 10 R L( C S + C P1 + C P2 ) = 290ns < TS = 1s For complete set of parameters characterizing the ST10F271Z1 A/D Converter equivalent circuit, refer to Section 25.7: A/D converter characteristics on page 141. 150/185 ST10F271Z1 Electrical characteristics 25.8 AC characteristics 25.8.1 Test waveforms Figure 46. Input / output waveforms 2.4V 2.0V 2.0V Test Points 0.8V 0.4V 0.8V ) s ( ct AC inputs during testing are driven at 2.4 V for a logic `1' and 0.4 V for a logic `0'. Timing measurements are made at VIH min. for a logic `1' and VIL max for a logic `0'. u d o Figure 47. Float waveforms r P e VOH let VLOAD + 0.1V Timing Reference Points o s b VLOAD VLOAD - 0.1V O ) VOH - 0.1V VOL + 0.1V VOL s ( t c For timing purposes a port pin is no longer floating when VLOAD changes of 100 mV. It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA). 25.8.2 u d o Definition of internal timing r P e The internal operation of the ST10F271Z1 is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. s b O t e l o The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL". The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10F271Z1. The example for PLL operation shown in Figure 48 refers to a PLL factor of 4. The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). 151/185 Electrical characteristics ST10F271Z1 Figure 48. Generation mechanisms for the CPU clock Phase Locked Loop operation fXTAL fCPU TCLTCL Direct clock drive fXTAL fCPU ) s ( ct TCLTCL Prescaler operation fXTAL u d o fCPU r P e TCL 25.8.3 TCL t e l o Clock generation modes s b O Next Table 69 associates the combinations of these three bits with the respective clock generation mode. Table 69. ) (s On-chip clock generator selections P0.15-13 CPU frequency 1 1 1 1 External clock input range 1) 3) FXTAL x 4 4 to 8MHz FXTAL x 3 5.3 to 8MHz 1 0 d o r 1 FXTAL x 8 4 to 8MHz let 1 0 0 FXTAL x 5 6.4 to 8MHz 0 1 1 FXTAL x 1 1 to 64MHz 0 1 0 FXTAL x 10 4 to 6.4MHz 0 0 1 FXTAL / 2 4 to 8MHz 0 0 0 FXTAL x 16 4MHz so b O 1 fCPU = fXTAL x F t c u (P0H.7-5) P e 0 Notes Default configuration See Table 70 Direct drive (oscillator bypassed) 2) CPU clock via prescaler 3) 1. The external clock input range refers to a CPU clock range of 1...64 MHz. Besides, the PLL usage is limited to 4-8 MHz. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the internal oscillator amplifier (apart from Direct Drive): vice versa, the clock can be forced through an external clock source only in Direct Drive mode (on-chip oscillator amplifier disabled, so no crystal or resonator can be used). 2. The maximum depends on the duty cycle of the external clock signal: when 64 MHz is used, 50% duty cycle shall be granted (low phase = high phase = 7.8 ns); when 32 MHz is selected a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 7.8 ns). 3. The limits on input frequency are 4-8 MHz since the usage of the internal oscillator amplifier is required. Also when the PLL is not used and the CPU clock corresponds to FXTAL/2, an external crystal or resonator shall be used: it is not possible to force any clock though an external clock source. 152/185 ST10F271Z1 25.8.4 Electrical characteristics Prescaler operation When pins P0.15-13 (P0H.7-5) equal '001' during reset, the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fXTAL. The timings listed in the AC Characteristics that refer to TCL therefore can be calculated using the period of fXTAL for any TCL. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. 25.8.5 ) s ( ct Direct drive When pins P0.15-13 (P0H.7-5) equal '011' during reset the on-chip phase locked loop is disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by the input clock signal on XTAL1 pin. u d o r P e The frequency of CPU clock (fCPU) directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. t e l o Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value can be calculated by the following formula: s b O TCL min = 1 f XTALl xlDC min DC = duty cycle ) (s For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated, so the duration of 2TCL is always 1/fXTAL. t c u The minimum value TCLmin has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula: d o r P e 2TCL = 1 f XTAL t e l o s b O 25.8.6 The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLmin. Similarly to what happen for Prescaler Operation, if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. Oscillator watchdog (OWD) An on-chip watchdog oscillator is implemented in the ST10F271Z1. This feature is used for safety operation with external crystal oscillator (available only when using direct drive mode with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the frequency of the external crystal oscillator). This watchdog oscillator operates as following. The reset default configuration enables the watchdog oscillator. It can be disabled by setting the OWDDIS (bit 4) of SYSCON register. When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the watchdog counter. On each transition of external clock, the watchdog counter is cleared. If 153/185 Electrical characteristics ST10F271Z1 an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply current. 25.8.7 Phase Locked Loop (PLL) ) s ( ct For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and it provides the CPU clock (see Table 69). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (fCPU = fXTAL x F). With every F'th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, so the CPU clock frequency does not change abruptly. u d o r P e t e l o Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. s b O The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. ) (s The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to one TCL period. t c u This is especially important for bus cycles using wait states and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower Baud rates, etc.) the deviation caused by the PLL jitter is negligible. Refer to next Section 25.8.9: PLL Jitter for more details. d o r P e t e l o 25.8.8 Voltage Controlled Oscillator bs The ST10F271Z1 implements a PLL which combines different levels of frequency dividers with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. In the following table, a detailed summary of the internal settings and VCO frequency is reported. O Table 70. Internal PLL divider mechanism P0.15-13 (P0H.7-5) 1 1 1 XTAL frequency 4 to 8 MHz 1 1 0 5.3 to 8 MHz 1 0 1 4 to 8 MHz 1 0 0 0 1 1 154/185 6.4 to 8 MHz 1) 1) 1 to 64 MHz Input prescaler PLL Output prescaler CPU frequency fCPU = fXTAL x F Multiply by Divide by FXTAL / 4 64 4 - FXTAL x 4 FXTAL / 4 48 4 - FXTAL x 3 FXTAL / 4 64 2 - FXTAL x 8 FXTAL / 4 40 2 - FXTAL x 5 - FXTAL x 1 - PLL bypassed ST10F271Z1 Table 70. Internal PLL divider mechanism (continued) P0.15-13 (P0H.7-5) 0 1 Electrical characteristics XTAL frequency 0 4 to 6.4MHz 1) 0 0 1 0 0 0 4 to 8MHz Input prescaler PLL Multiply by Divide by 40 2 FXTAL / 2 - PLL bypassed FXTAL / 2 4MHz 64 2 Output prescaler CPU frequency fCPU = fXTAL x F - FXTAL x 10 FPLL / 2 FXTAL / 2 - FXTAL x 16 The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is 64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 64 MHz. ) s ( ct Example 1 fXTAL = 10 MHz P0(15:13) = `110' (multiplication by 3) PLL input frequency = 2.5 MHz VCO frequency = 120 MHz PLL output frequency = 30 MHz (VCO frequency divided by 4) fCPU = 30 MHz (no effect of output prescaler) Example 2 25.8.9 u d o r P e t e l o s b O fXTAL = 8 MHz P0(15:13) = `100' (multiplication by 5) PLL input frequency = 2 MHz VCO frequency = 80 MHz PLL output frequency = 40 MHz (VCO frequency divided by 2) fCPU = 40 MHz (no effect of Output Prescaler) ) (s t c u d o r P e PLL Jitter t e l o The following terminology is hereafter defined: s b O Self referred single period jitter Also called "period jitter", it can be defined as the difference of the Tmax and Tmin, where Tmax is maximum time period of the PLL output clock and Tmin is the minimum time period of the PLL output clock. Self referred long term jitter Also called "N period jitter", it can be defined as the difference of Tmax and Tmin, where Tmax is the maximum time difference between N+1 clock rising edges and Tmin is the minimum time difference between N+1 clock rising edges. Here N should be kept sufficiently large to have the long term jitter. For N=1, this becomes the single period jitter. Jitter at the PLL output can be due to the following reasons: Jitter in the input clock Noise in the PLL loop. 155/185 Electrical characteristics ST10F271Z1 Jitter in the input clock PLL acts like a low pass filter for any jitter in the input clock. Input clock jitter with the frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency jitter (frequency > PLL bandwidth) is attenuated @20 dB/decade. Noise in the PLL loop This contribution again can be caused by the following sources: Device noise of the circuit in the PLL Noise in supply and substrate. Device noise of the circuit in the PLL ) s ( ct The long term jitter is inversely proportional to the bandwidth of the PLL: the wider is the loop bandwidth, the lower is the jitter due to noise in the loop. Besides, the long term jitter is practically independent on the multiplication factor. u d o The most noise sensitive circuit in the PLL circuit is definitively the VCO (Voltage Controlled Oscillator). There are two main sources of noise: thermal (random noise, frequency independent so practically white noise) and flicker (low frequency noise, 1/f). For the frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a 1/f2 region in the output noise spectrum, while the flicker noise in a 1/f3. Assuming a noiseless PLL input and supposing that the VCO is dominated by its 1/f2 noise, the R.M.S. value of the accumulated jitter is proportional to the square root of N, where N is the number of clock periods within the considered time interval. On the contrary, assuming again a noiseless PLL input and supposing that the VCO is dominated by its 1/f3 noise, the R.M.S. value of the accumulated jitter is proportional to N, where N is the number of clock periods within the considered time interval. r P e t e l o ) (s s b O t c u The jitter in the PLL loop can be modelized as dominated by the i1/f2 noise for N smaller than a certain value depending on the PLL output frequency and on the bandwidth characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f3 noise component. Lastly, for N greater than a second value of N, a saturation effect is evident, so the jitter does not grow anymore when considering a longer time interval (jitter stable increasing the number of clock periods N). The PLL loop acts as a high pass filter for any noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation value corresponds to what has been called self referred long term jitter of the PLL. In Figure 49 the maximum jitter trend versus the number of clock periods N (for some typical CPU frequencies) is reported: the curves represent the very worst case, computed taking into account all corners of temperature, power supply and process variations: the real jitter is always measured well below the given worst case values. d o r P e t e l o s b O Noise in supply and substrate Digital supply noise adds deterministic components to the PLL output jitter, independent on multiplication factor. Its effects is strongly reduced thanks to particular care used in the physical implementation and integration of the PLL module inside the device. Anyhow, the contribution of the digital noise to the global jitter is widely taken into account in the curves provided in Figure 49. 156/185 ST10F271Z1 Electrical characteristics Figure 49. ST10F271Z1 PLL jitter 5 16MHz 24MHz 32MHz 40MHz 64MHz 4 Jitter [ns] 3 2 ) s ( ct 1 u d o TJIT 0 25.8.10 0 400 200 Pr 1000 600 800 N (CPU clock periods) e t e ol PLL lock / unlock 1200 1400 s b O During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the CPU is generated, and the reference clock (oscillator) is automatically disconnected from the PLL input: in this way, the PLL goes into free-running mode, providing the system with a backup clock signal (free running frequency Ffree). This feature allows to recover from a crystal failure occurrence without risking to go in an undefined configuration: the system is provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe mode. ) (s t c u d o r The path between reference clock and PLL input can be restored only by a hardware reset, or by a bidirectional software or watchdog reset event that forces the RSTIN pin low. Note: P e The external RC circuit on RSTIN pin shall be properly sized in order to extend the duration of the low pulse to grant the PLL gets locked before the level at RSTIN pin is recognized high: bidirectional reset internally drives RSTIN pin low for just 1024 TCL (definitively not sufficient to get the PLL locked starting from free-running mode). s b O t e l o 157/185 Electrical characteristics Table 71. ST10F271Z1 PLL characteristics (VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C) Value Symbol Parameter Conditions Unit min. max. TPSUP PLL Start-up time 1) Stable VDD and reference clock - 300 s TLOCK PLL Lock-in time Stable VDD and reference clock, starting from free-running mode - 250 s TJIT Single Period Jitter 1) (cycle to cycle = 2 TCL) 6 sigma time period variation (peak to peak) -500 +500 ps Ffree PLL free running frequency Multiplication Factors: 3, 4 Multiplication Factors: 5, 8, 10, 16 250 500 2000 4000 kHz ) s ( ct 1. Not 100% tested, guaranteed by design characterization. 25.8.11 u d o Main oscillator specifications VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C Table 72. Main oscillator characteristics Symbol Parameter t e l o Conditions gm Oscillator transconductance VOSC Oscillation amplitude 1) t c u 1) Oscillation voltage level tSTUP Oscillator start-up time 1) od Value Unit s b O min. typ. max. 1.4 2.6 4.2 mA/V Peak to peak - 1.5 - V Sine wave middle - 0.8 - V Stable VDD - Crystal - 6 10 ms Stable VDD - Resonator - 1 2 ms ) (s VAV r P e r P e 1. Not 100% tested, guaranteed by design characterization. t e l o Figure 50. Crystal oscillator and resonator connection diagram crystal CA 158/185 XTAL2 XTAL1 XTAL2 XTAL1 s b O ST10F271Z1 ST10F271Z1 Resonator CA ST10F271Z1 Electrical characteristics Table 73. Main oscillator negative resistance (module) CA = 15 pF CA = 25 pF CA = 35 pF min. typ. max. min. typ. max. min. typ. max. 4 MHz 545 1035 - 550 1050 - 430 850 - 8 MHz 240 450 - 170 350 - 120 250 - The given values of CA do not include the stray capacitance of the package and of the printed circuit board: the negative resistance values are calculated assuming additional 5pF to the values in the table. The crystal shunt capacitance (C0) and the package capacitance between XTAL1 and XTAL2 pins is globally assumed equal to 10 pF. ) s ( ct The external resistance between XTAL1 and XTAL2 is not necessary, since already present on the silicon. 25.8.12 u d o 32 kHz oscillator specifications r P e VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C Table 74. Symbol gm32 Parameter )- s ( t c du Oscillation voltage level 2) o r P Value Conditions Oscillator transconductance 1) VOSC32 Oscillation amplitude 2) VAV32 t e l o 32kHz oscillator characteristics tSTUP32 Oscillator start-up time 2) s b O Unit min. typ. max. Start-up 20 31 50 A/V Normal run 8 17 30 A/V Peak to peak 0.5 1.0 2.4 V Sine wave middle 0.7 0.9 1.2 V - 1 5 s Stable VDD 1. At power-on a high current biasing is applied for faster oscillation start-up. Once the oscillation is started, the current biasing is reduced to lower the power consumption of the system. e t e ol 2. Not 100% tested, guaranteed by design characterization. Figure 51. 32 kHz crystal oscillator connection diagram XTAL4 ST10F271Z1 XTAL3 O bs crystal CA CA 159/185 Electrical characteristics Table 75. ST10F271Z1 Minimum values of negative resistance (module) for 32 kHz oscillator CA = 6 pF CA = 12 pF CA = 15 pF CA = 18 pF CA = 22 pF CA = 27 pF CA = 33 pF 32 kHz - - - - 150 k 120 k 90 kW The given values of CA do not include the stray capacitance of the package and of the printed circuit board: the negative resistance values are calculated assuming additional 5pF to the values in the table. The crystal shunt capacitance (C0) and the package capacitance between XTAL3 and XTAL4 pins is globally assumed equal to 4 pF. The external resistance between XTAL3 and XTAL4 is not necessary, since already present on the silicon. Warning: 25.8.13 ) s ( ct Direct driving on XTAL3 pin is not supported. Always use a 32 kHz crystal oscillator. u d o External clock drive XTAL1 r P e When Direct Drive configuration is selected during reset, it is possible to drive the CPU clock directly from the XTAL1 pin, without particular restrictions on the maximum frequency, since the on-chip oscillator amplifier is bypassed. The speed limit is imposed by internal logic that targets a maximum CPU frequency of 64 MHz. t e l o s b O In all other clock configurations (Direct Drive with Prescaler or PLL usage) the on-chip oscillator amplifier is not bypassed, so it determines the input clock speed limit. Then, when the on-chip oscillator is enabled it is forbidden to use any external clock source different from crystal or ceramic resonator. ) (s Table 76. t c u External clock drive od Pr Parameter e t e ol Symbol XTAL1 period 1, 2 tOSC SR s b O Direct drive fCPU = fXTAL Direct drive with prescaler fCPU = fXTAL / 2 PLL usage fCPU = fXTAL x F Unit min. max. min. max. min. max. 15.625 - 83.3 250 83.3 250 ns High time 3 t1 SR 6 - 3 - 6 - ns Low time 3 t2 SR 6 - 3 - 6 - ns Rise time 3 t3 SR - 2 - 2 - 2 ns Fall time 3 t4 SR - 2 - 2 - 2 ns 1. The minimum value for the XTAL1 signal period shall be considered as the theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 2. 4-8 MHz is the input frequency range when using an external clock source. 64 MHz can be applied with an external clock source only when Direct Drive mode is selected: in this case, the oscillator amplifier is bypassed so it does not limit the input frequency. 3. The input clock signal must reach the defined levels VIL2 and VIH2. 160/185 ST10F271Z1 Electrical characteristics Figure 52. External clock drive XTAL1 t3 t1 t4 VIH2 VIL2 t2 tOSC Note: When Direct Drive is selected, an external clock source can be used to drive XTAL1. The maximum frequency of the external clock source depends on the duty cycle: when 64MHz is used, 50% duty cycle shall be granted (low phase = high phase = 7.8 ns); when for instance 32 MHz is used, a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 7.8ns). 25.8.14 ) s ( ct u d o Memory cycle variables r P e The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 77. Memory cycle variables Description Symbol ALE extension ) (s Memory cycle time wait states t c u Memory tri-state time 25.8.15 s b O t e l o Values tA TCL x [ALECTL] tC 2TCL x (15 - [MCTC]) tF 2TCL x (1 - [MTTC]) d o r External memory bus timing The following sections include the External Memory Bus timings. The given values are computed for a maximum CPU clock of 40MHz. P e t e l o s b O Obviously, when higher CPU clock frequency is used (up to 64MHz), some numbers in the timing formulas become zero or negative which, in most cases is not acceptable or not meaningless at all. In these cases, it is necessary to relax the speed of the bus setting properly tA, tC and tF. Note: All External Memory Bus Timings and SSC Timings reported in the following tables are granted by Design Characterization and not fully tested in production. 25.8.16 Multiplexed bus VDD = 5 V 10%, VSS = 0V, TA = -40 to +125 C, CL = 50 pF, ALE cycle time = 6 TCL + 2tA + tC + tF (75 ns at 40 MHz CPU clock without wait states) 161/185 Electrical characteristics Multiplexed bus timings Symbol FCPU = 40 MHz TCL = 12.5 ns Parameter Variable CPU clock 1/2 TCL = 1 to 64MHz Unit Table 78. ST10F271Z1 min. max. min. max. 4 + tA - TCL - 8.5 + tA - ns 1.5 + tA - TCL - 11 + tA - ns t5 CC ALE high time t6 CC Address setup to ALE t7 CC Address hold after ALE 4 + tA - TCL - 8.5 + tA - ns t8 CC ALE falling edge to RD, WR (with RW-delay) 4 + tA - TCL - 8.5 + tA - ns t9 CC ALE falling edge to RD, WR (no RW-delay) - 8.5 + tA - - 8.5 + tA - t10 CC Address float after RD, WR (with RW-delay)1 - 6 - t11 CC Address float after RD, WR (no RW-delay)1 - 18.5 - t c u t12 CC RD, WR low time (with RW-delay) 15.5 + tC - t13 CC RD, WR low time (no RW-delay) 28 + tC - t14 SR RD to valid data in (with RW-delay) t15 SR RD to valid data in (no RW-delay) t16 SR ALE low to valid data in ct t17 SR t18 t19 6 (s) d o r ns ns TCL + 6 ns 2TCL - 9.5 + tC - ns 3TCL - 9.5 + tC - ns 6 + tC - 2TCL - 19 + tC ns 18.5 + tC - 3TCL - 19 + tC ns - 17.5 + + tA + tC - 3TCL - 20 + + tA + tC ns Address/Unlatched CS to valid data in - 20 + 2tA + + tC - 4TCL - 30 + + 2tA + tC ns SR Data hold after RD rising edge 0 - 0 - ns SR Data float after RD1 - 16.5 + tF - 2TCL - 8.5 + tF ns 10 + tC - 2TCL - 15 + tC - ns - ) (s - u d o r P e t e l o bs P e t e l o s b O t22 CC Data valid to WR t23 CC Data hold after WR 4 + tF - 2TCL - 8.5 + tF - ns t25 CC ALE rising edge after RD, WR 15 + tF - 2TCL - 10 + tF - ns t27 CC Address/Unlatched CS hold after RD, WR 10 + tF - 2TCL - 15 + tF - ns t38 CC ALE falling edge to Latched CS - 4 - tA 10 - tA - 4 - tA 10 - tA ns t39 SR Latched CS low to Valid Data In - 16.5 + tC + + 2tA - 3TCL - 21 + + tC + 2tA ns t40 CC Latched CS hold after RD, WR 27 + tF - 3TCL - 10.5 + tF - ns t42 CC ALE fall. edge to RdCS, WrCS (with RW delay) 7 + tA - TCL - 5.5 + tA - ns O 162/185 ST10F271Z1 Multiplexed bus timings (continued) Symbol FCPU = 40 MHz TCL = 12.5 ns Parameter Variable CPU clock 1/2 TCL = 1 to 64MHz Unit Table 78. Electrical characteristics min. max. min. max. - 5.5 + tA - - 5.5 + tA - ns t43 CC ALE fall. edge to RdCS, WrCS (no RW delay) t44 CC Address float after RdCS, WrCS (with RW delay)1 - 1.5 - 1.5 ns t45 CC Address float after RdCS, WrCS (no RW delay)1 - 14 - TCL + 1.5 ns t46 SR RdCS to Valid Data In (with RW delay) - 4 + tC - 2TCL - 21 + tC t47 SR RdCS to Valid Data In (no RW delay) - 16.5 + tC - 3TCL - 21 + tC t48 CC RdCS, WrCS Low Time (with RW delay) 15.5 + tC - 2TCL - 9.5 + tC t49 CC RdCS, WrCS Low Time (no RW delay) 28 + tC - t50 CC Data valid to WrCS 10 + tC t51 SR Data hold after RdCS 0 t52 SR Data float after RdCS1 - t54 CC Address hold after RdCS, WrCS t56 CC Data hold after WrCS u d o c u d o r P ns ns - ns 3TCL - 9.5 + tC - ns 2TCL - 15 + tC - ns - 0 - ns 16.5 + tF - 2TCL - 8.5 + tF ns 6 + tF - 2TCL - 19 + tF - ns 6 + tF - 2TCL - 19 + tF - ns (s) ct ) s ( t o s b e t e l - -O r P e t e l o s b O 163/185 Electrical characteristics ST10F271Z1 Figure 53. External memory cycle: multiplexed bus, with/without read/write delay, normal ALE t5 t25 t16 ALE t6 t38 t40 t17 t27 t39 CSx t6 t27 t17 A23-A16 (A15-A8) BHE t16 t6 Read cycle Address/data bus (P0) t7 Data in t(s uc t e l o P e bs O WR WRL WRH t12 t13 t1 t15 t23 Address Data out t8 t22 t9 t12 t13 164/185 t19 O ) RD d o r o s b t10 t14 Write cycle r P e let Address t9 u d o t1 t8 Address/data bus (P0) ) s ( ct Address Address ST10F271Z1 Electrical characteristics Figure 54. External memory cycle: multiplexed bus, with/without read/write delay, extended ALE t16 t5 t25 ALE t6 t38 t40 t17 t39 t27 CSx t6 t17 A23-A16 (A15-A8) BHE t27 Read cycle t6 Address/data bus (P0) ct u d o Write cycle O bs ol Pr t10 t e l o s b O t11 ) (s RD ete r P e Address t9 Address/Data Bus (P0) u d o t7 t8 WR WRL WRH ) s ( ct Address Data in t18 t19 t14 t15 t12 t13 Address Data out t23 t8 t9 t10 t11 t13 t22 t12 165/185 Electrical characteristics ST10F271Z1 Figure 55. External memory cycle: multiplexed bus, with/without r/w delay, normal ALE, r/w CS CLKOUT t5 t16 t25 ALE t6 t27 t17 A23-A16 (A15-A8) BHE ) s ( ct Address u d o t16 t6 Read cycle Address/data bus (P0) t7 Address Data In t42 t e l o t44 s b O t46 RdCSx )- s ( t c t43 Write cycle Address/data Bus (P0) e t e ol s b O WrCSx 166/185 o r P du r P e t51 t52 t48 t49 t45 t47 t55 Address Data Out t42 t50 t43 t48 t49 Address ST10F271Z1 Electrical characteristics Figure 56. External memory cycle: multiplexed bus, with/without r/w delay, extended ALE, r/w CS CLKOUT t16 t5 t25 ALE t6 t17 A23-A16 (A15-A8) BHE t54 Read cycle t6 Address/data bus (P0) u d o r P e t7 t43 t c u s b O Data in t18 t19 t46 t48 t47 t49 d o r P e t e l o t44 t45 ) (s RdCSx s b O t e l o Address t42 Write cycle Address/data bus (P0) ) s ( ct Address Address Data out t42 t43 t56 t44 t45 t50 WrCSx t48 t49 167/185 Electrical characteristics 25.8.17 ST10F271Z1 Demultiplexed bus VDD = 5 V 10%, VSS = 0V, TA = -40 to +125 C, CL = 50 pF, ALE cycle time = 4 TCL + 2tA + tC + tF (50 ns at 40 MHz CPU clock without wait states). Demultiplexed bus timings Symbol FCPU = 40 MHz TCL = 12.5 ns Parameter Variable CPU clock 1/2 TCL = 1 to 64 MHz Unit Table 79. min. max. min. max. 4 + tA - TCL - 8.5 + tA - ns 1.5 + tA - TCL - 11 + tA - ns - ns t5 CC ALE high time t6 CC Address setup to ALE t80 CC Address/Unlatched CS setup to RD, WR (with RW-delay) 12.5 + 2tA - 2TCL - 12.5 + + 2tA t81 CC Address/Unlatched CS setup to RD, WR (no RW-delay) 0.5 + 2tA - TCL - 12 + 2tA t12 CC RD, WR low time (with RW-delay) 15.5 + tC - t13 CC RD, WR low time (no RW-delay) 28 + tC - t14 SR RD to valid data in (with RW-delay) t15 SR RD to valid data in (no RW-delay) t16 SR ALE low to valid data in t17 SR t18 SR ) s ( ct u d o Pr - ns 2TCL - 9.5 + tC - ns 3TCL - 9.5 + tC - ns 6 + tC - 2TCL - 19 + tC ns - 18.5 + tC - 3TCL - 19 + tC ns - 17.5 + tA + + tC - 3TCL - 20 + + tA + tC ns Address/Unlatched CS to valid data in - 20 + 2tA + + tC - 4TCL - 30 + + 2tA + tC ns Data hold after RD rising edge 0 - 0 - ns Data float after RD rising edge (with RW-delay)31 - 16.5 + tF - 2TCL - 8.5 + + tF + 2tA ns SR Data float after RD rising edge (no RW-delay) 1 - 4 + tF - TCL - 8.5 + + tF + 2tA ns t22 CC Data valid to WR 10 + tC - 2TCL - 15 + tC - ns t24 CC Data hold after WR 4 + tF - TCL - 8.5 + tF - ns t26 CC ALE rising edge after RD, WR -10 + tF - -10 + tF - ns t28 CC Address/unlatched CS hold after RD, WR 2 0 + tF - 0 + tF - ns t28h CC Address/unlatched CS hold after WRH - 5 + tF - - 5 + tF - ns b O t21 SR 168/185 ) (s t c u d o r P e let so t20 - so e t e l b O ST10F271Z1 Demultiplexed bus timings (continued) Symbol FCPU = 40 MHz TCL = 12.5 ns Parameter Variable CPU clock 1/2 TCL = 1 to 64 MHz min. max. min. max. - 4 - tA 6 - tA - 4 - tA 6 - tA ns - 16.5 + + tC + 2tA - 3TCL - 21 + + tC + 2tA ns 2 + tF - TCL - 10.5 + tF - ns - t38 CC ALE falling edge to latched CS t39 SR Latched CS low to valid data In t41 CC Latched CS hold after RD, WR t82 CC Address setup to RdCS, WrCS (with RW-delay) 14 + 2tA - 2TCL - 11 + 2tA t83 CC Address setup to RdCS, WrCS (no RW-delay) 2 + 2tA - TCL -10.5 + 2tA t46 SR RdCS to valid data in (with RW-delay) - 4 + tC t47 SR RdCS to valid data in (no RW-delay) - t48 CC RdCS, WrCS low time (with RW-delay) 15.5 + tC t49 CC RdCS, WrCS low time (no RW-delay) t50 CC Data valid to WrCS t51 SR Data hold after RdCS t53 SR Data float after RdCS (with RW-delay) 3 t68 SR e t e l so t55 b O t57 du CC CC o r P Data float after RdCS (no RW-delay) 3 Address hold after RdCS, WrCS Data hold after WrCS ) s ( ct ns u d o - ns - 2TCL - 21 + tC ns 16.5 + tC - 3TCL - 21 + tC ns - 2TCL - 9.5 + tC - ns - 3TCL - 9.5 + tC - ns 10 + tC - 2TCL - 15 + tC - ns 0 - 0 - ns - 16.5 + tF - 2TCL - 8.5 + tF ns - 4 + tF - TCL - 8.5 + tF ns - 8.5 + tF - - 8.5 + tF - ns 2 + tF - TCL - 10.5 + tF - ns ) (s 28 + tC ct Unit Table 79. Electrical characteristics r P e t e l o s b O 1. RW-delay and tA refer to the next following bus cycle. 2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. 3. Partially tested, guaranteed by design characterization. 169/185 Electrical characteristics ST10F271Z1 Figure 57. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE CLKOUT t5 t26 t9 ALE t6 t38 t41 t17 t41u t39 CSx t6 A23-A16 A15-A0 (P1) BHE t28 (or t28h) t17 Address t e l o t18 Read cycle Data bus (P0) (D15-D8) D7-D0 t80 )- s ( t c RD e t e l Data bus (P0) (D15-D8) D7-D0 o s b O t15 u d o t20 t21 t12 Pr t13 Data out t80 t22 t81 WR WRL WRH t12 t13 170/185 s b O Data in t14 t81 Write cycle r P e t24 u d o ) s ( ct ST10F271Z1 Electrical characteristics Figure 58. Exteral memory cycle: demultiplexed bus, with/without r/w delay, extended ALE CLKOUT t5 t26 t16 ALE t6 t38 t41 t17 t28 t39 ) s ( ct CSx t6 t17 A23-A16 A15-A0 (P1) BHE t28 u d o r P e Address t e l o Read cycle Data bus (P0) (D15-D8) D7-D0 t80 )- t81 s b O s ( t c u d o RD Write cycle e t e ol Data bus (P0) (D15-D8) D7-D0 bs O Pr t18 Data in t20 t14 t15 t21 t12 t13 Data out t80 t22 t81 WR WRL WRH t24 t12 t13 171/185 Electrical characteristics ST10F271Z1 Figure 59. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE, r/w CS CLKOUT t5 t26 t16 ALE t6 A23-A16 A15-A0 (P1) BHE t17 t55 t47 RdCSx )- t(s o r P c u d t e l o t53 t46 t83 s b O t68 s b O t48 t49 Data out t82 t50 t83 WrCSx 172/185 r P e Data in t82 e t e ol u d o t5 Read cycle Data bus (P0) (D15-D8) D7-D0 Write cycle Data bus (P0) (D15-D8) D7-D0 ) s ( ct Address t48 t49 t57 ST10F271Z1 Electrical characteristics Figure 60. External memory cycle: demultiplexed bus, without r/w delay, extended ALE, r/w CS CLKOUT t5 t26 t16 ALE t6 t55 t17 A23-A16 A15-A0 (P1) BHE Address t51 u d o Read cycle Data bus (P0) (D15-D8) D7-D0 Data in t46 t82 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 ) (s P e s b O t53 t68 t48 t49 t c u d o r r P e t e l o t47 t83 t e l o ) s ( ct Data out t82 t83 t50 t57 WrCSx s b O t48 t49 173/185 Electrical characteristics 25.8.18 ST10F271Z1 CLKOUT and READY VDD = 5 V 10%, VSS = 0 V, TA = -40 to + 125 C, CL = 50 pF CLKOUT and READY timings Symbol FCPU = 40 MHz TCL = 12.5 ns Parameter Variable CPU clock 1/2 TCL = 1 to 64 MHz min. max. min. max. Unit Table 80. t29 CC CLKOUT cycle time 25 25 2TCL 2TCL ns t30 CC CLKOUT high time 9 - TCL - 3.5 - ns t31 CC CLKOUT low time 10 - TCL - 2.5 - t32 CC CLKOUT rise time - 4 - t33 CC CLKOUT fall time - 4 - t34 CC CLKOUT rising edge to ALE falling edge - 2 + tA 8 + tA - 2 + tA t35 SR Synchronous READY setup time to CLKOUT 17 - t36 SR Synchronous READY hold time after CLKOUT 2 t37 SR Asynchronous READY low time 35 t58 SR Asynchronous READY setup time 1 t59 SR Asynchronous READY hold time 1 t60 SR Async. READY hold time after RD, WR high (Demultiplexed Bus) 2 d o r P e t e l o o r P c u d 4 4 ns ns ns 8 + tA ns 17 - ns 2 - ns - 2TCL + 10 - ns 17 - 17 - ns 2 - 2 - ns 0 2tA + tC + tF 0 2tA + tC + tF ns ) (s t c u ) s ( t e t e l so - b O 1. These timings are given for characterization purposes only, in order to assure recognition at a specific clock edge. s b O 174/185 2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle. ST10F271Z1 Electrical characteristics Figure 61. CLKOUT and READY READY wait state Running cycle 1) t32 CLKOUT MUX / Tri-state 6) t33 t30 t29 t31 t34 ALE 7) RD, WR ) s ( ct 2) t35 Synchronous READY t36 t35 t36 t58 Asynchronous READY t59 t58 r P e t59 t60 4) 3) 3) u d o 3) 3) t37 let 5) o s b 6) 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). O ) 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle. s ( t c 4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). u d o 5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4). r P e 6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here. For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus without MTTC wait state this delay is zero. t e l o 7. The next external bus cycle may start here. s b O 175/185 Electrical characteristics 25.8.19 ST10F271Z1 External bus arbitration VDD = 5 V 10 %, VSS = 0 V, TA = -40 to +125 C, CL = 50 pF External bus arbitration timings Symbol FCPU = 40 MHz TCL = 12.5 ns Parameter Variable CPU clock 1/2 TCL = 1 to 64 MHz min. max. min. max. t61 SR HOLD input setup time to CLKOUT 18.5 - 18.5 - t62 CC CLKOUT to HLDA high or BREQ low delay - 12.5 - 12.5 ns t63 CC CLKOUT to HLDA low or BREQ high delay - 12.5 - 12.5 ns t64 CC CSx release 1) - 20 - t65 CC CSx drive -4 15 - 20 t66 CC Other signals release t67 CC Other signals drive 1) 15 20 ns -4 15 ns - 20 ns -4 15 ns o s b Figure 62. External bus arbitration (releasing the bus) CLKOUT HOLD e t e l O du o r P HLDA O ) s ( t c t61 t63 1) t62 2) BREQ t64 3) CSx (P6.x) 1) t66 Others 1. The ST10F271Z1 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t64. 176/185 ns ) s ( ct u d o Pr e t e l -4 1. Partially tested, guaranteed by design characterization. o s b Unit Table 81. ST10F271Z1 Electrical characteristics Figure 63. External bus arbitration (regaining the bus) 2) CLKOUT t61 HOLD t62 HLDA t62 t62 t63 ) s ( ct 1) BREQ t65 CSx (On P6.x) r P e t67 Other signals u d o t e l o s b O 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F271Z1 requesting the bus. 2. The next ST10F271Z1 driven bus cycle may start here. ) (s t c u d o r P e t e l o s b O 177/185 Electrical characteristics 25.8.20 ST10F271Z1 High-speed synchronous serial interface (SSC) timing Master mode VDD = 5 V 10%, VSS = 0 V, TA = -40 to +125 C, CL = 50 pF Table 82. SSC master mode timings Symbol Variable baudrate Max. baudrate 6.6 MBd (1) @fCPU = 40 MHz (<SSCBR> = 0002h) Parameter (<SSCBR> = 0001h FFFFh) min. max. min. max. Unit (s) t300 CC SSC clock cycle time(2)) 150 150 8TCL 262144 TCL ns t301 CC SSC clock high time 63 - t300 / 2 - 12 ns t302 CC SSC clock low time 63 - t300 / 2 - 12 t303 CC SSC clock rise time - 10 - ct 10 ns t304 CC SSC clock fall time - 10 10 ns t305 CC Write data valid after shift edge u d o - - ns 15 Pr - 15 ns - -2 - ns - 2TCL + 12.5 - ns 50 - 4TCL - ns t307 Read data setup time before latch SR edge, phase error detection off (SSCPEN = 0) 25 - 2TCL - ns t308 Read data hold time after latch SR edge, phase error detection off (SSCPEN = 0) 0 - 0 - ns t306 CC Write data hold after shift -2 t307p Read data setup time before latch SR edge, phase error detection on (SSCPEN = 1) 37.5 t308p Read data hold time after latch SR edge, phase error detection on (SSCPEN = 1) bs O ) s ( t c du e t e ol e t e ol - edge(3) o r P - 1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to `3h', or with 48 MHz CPU clock and <SSCBR> set to `2h'. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6 Mbaud (<SSCBR> = `2h') due to the limited granularity of <SSCBR>. Value `1h' for <SSCBR> can be used only with CPU clock equal to (or lower than) 32 MHz. s b O 2. Formula for SSC clock cycle time: t300 = 4 TCL x (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t300 is 125 ns (corresponding to 8Mbaud). 3. Partially tested, guaranteed by design characterization. 178/185 ST10F271Z1 Electrical characteristics Figure 64. SSC master timing t300 1) t301 t302 2) SCLK t304 t305 t305 1st out bit MTSR t303 t305 t306 2nd out bit Last out bit t307 t308 MRST t307 t308 2nd In bit 1st in bit ) s ( ct Last in bit u d o r P e 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received. t e l o Slave mode s b O VDD = 5V 10%, VSS = 0 V, TA = -40 to +125 C, CL = 50 pF Table 83. SSC slave mode timings Symbol Parameter ) (s u d o ct Max. baudrate 6.6 MBd (1)) @FCPU = 40 MHz (<SSCBR> = 0002h) Variable baudrate (<SSCBR> = 0001h FFFFh) Unit min. max. min. max. 150 150 8TCL 262144 TCL ns SR SSC clock high time 63 - t310 / 2 - 12 - ns SR SSC clock low time 63 - t310 / 2 - 12 - ns SR SSC clock rise time - 10 - 10 ns t314 SR SSC clock fall time - 10 - 10 ns t315 CC Write data valid after shift edge - 55 - 2TCL + 30 ns t316 CC Write data hold after shift edge 0 - 0 - ns t317p Read data setup time before latch SR edge, phase error detection on (SSCPEN = 1) 62 - 4TCL + 12 - ns t318p Read data hold time after latch SR edge, phase error detection on (SSCPEN = 1) 87 - 6TCL + 12 - ns t e l o t311 t312 bs t313 O r P e SR SSC clock cycle time(2) t310 179/185 Electrical characteristics Table 83. ST10F271Z1 SSC slave mode timings (continued) Symbol Max. baudrate 6.6 MBd (1)) @FCPU = 40 MHz (<SSCBR> = 0002h) Parameter Variable baudrate (<SSCBR> = 0001h FFFFh) min. max. min. max. Unit t317 Read data setup time before latch SR edge, phase error detection off (SSCPEN = 0) 6 - 6 - ns t318 Read data hold time after latch SR edge, phase error detection off (SSCPEN = 0) 31 - 2TCL + 6 - ns ) s ( ct 1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64MHz CPU clock and <SSCBR> set to `3h', or with 48 MHz CPU clock and <SSCBR> set to `2h'. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6 Mbaud (<SSCBR> = `2h') due to the limited granularity of <SSCBR>. Value `1h' for <SSCBR> may be used only with CPU clock lower than 32 MHz (after checking that resulting timings are suitable for the master). u d o 2. Formula for SSC clock cycle time: t310 = 4 TCL * (<SSCBR> + 1) Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer. Minimum limit allowed for t310 is 125 ns (corresponding to 8Mbaud). r P e t e l o Figure 65. SSC slave timing t310 1) t311 bs t312 O ) SCLK t314 t(s t315 t315 uc MRST 1st out bit od r P e MTSR t e l o bs O 180/185 2) t313 t316 2nd out bit t317 t318 1st in bit t315 Last out bit t317 t318 2nd in bit Last in bit 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received. ST10F271Z1 26 Package information Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 181/185 Package information ST10F271Z1 Figure 66. PQFP144 - 144-pin plastic quad flatpack 28 x 28 mm, 0.65 mm pitch, package outline ddd D A A2 D1 A1 D3 108 73 72 144 E E1 E3 b B 109 37 1 u d o 36 C L t e l o ) (s Symbol Typ t c u A od A1 b e t e l Pr 3.420 C so b O K s b O Min Max inches(1) Typ Min 4.070 Max 0.1602 0.250 0.0098 3.170 3.670 0.220 0.1346 0.1248 0.1445 0.380 0.0087 0.0150 0.130 0.230 0.0051 0.0091 D 31.200 30.950 31.450 1.2283 1.2185 1.2382 D1 28.000 27.900 28.100 1.1024 1.0984 1.1063 D3 22.750 0.8957 e 0.650 0.0256 E 31.200 30.950 31.450 1.2283 1.2185 1.2382 E1 28.000 27.900 28.100 1.1024 1.0984 1.1063 E3 22.750 L 0.800 0.0256 0.0374 L1 1.600 0 7 K ddd 0.8957 0.650 0.0315 0.0630 0 0.101 0.950 7 0.0040 1. Values in inches are converted from mm and rounded up to 4 decimal places. 182/185 7G_ME PQFP144 - 144-pin plastic quad flatpack 28 x 28 mm, 0.65 mm pitch, package mechanical data mm A2 r P e L1 e Table 84. ) s ( ct ST10F271Z1 Package information Figure 67. LQFP144 - 144 pin low profile quad flat package 20x20 mm, 0.5 mm pitch, package outline D D1 A A2 D3 A1 108 109 73 72 0.08 mm .003 in. b Seating Plane b E E1 E3 ) s ( ct u d o 37 144 1 36 r P e e L1 L t e l o Table 85. h s b O LQFP144 - 144 pin low profile quad flat package 20x20mm, 0.5 mm pitch, package mechanical data ) (s inches(1) mm ct Dim. Min u d o A A1 A2 e t e l b O o s b c Pr Typ Max Min Typ 1.60 0.05 Max 0.063 0.15 0.002 0.006 1.35 1.40 1.45 0.053 0.057 0.17 0.22 0.27 0.007 0.011 0.20 0.004 0.008 c 0.09 D 21.80 22.00 22.20 0.858 0.867 0.874 D1 19.80 20.00 20.20 0.780 0.787 0.795 D3 17.50 0.689 E 21.80 22.00 22.20 0.858 0.867 0.874 E1 19.80 20.00 20.20 0.780 0.787 0.795 E3 17.50 0.689 e 0.50 0.020 K 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 0.039 1. Values in inches are converted from mm and rounded up to 4 decimal places. 183/185 Revision history 27 ST10F271Z1 Revision history Table 86. Document revision history Date Revision 30-Jun-2006 1 Initial release. 2 ST10F271 replaced by ST10F271Z1 Added Section 24: Known limitations on page 123 Modified example 1 in Section 25.8.8: Voltage Controlled Oscillator on page 154 Section 26: Package information on page 181: added information on ECOPACK specifications and modified figures and tables 18-Jan-2008 Changes ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 184/185 s b O ST10F271Z1 ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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