MAX1280EVC16 - Maxim Integrated

General Description

The MAX1280/MAX1281 12-bit ADCs combine an 8-chan-

nel analog-input multiplexer, high-bandwidth track/hold,

and serial interface with high conversion speed and low

power consumption. The MAX1280 operates from a single

+4.5V to +5.5V supply; the MAX1281 operates from a sin-

gle +2.7V to +3.6V supply. Both devices’ analog inputs

are software configurable for unipolar/bipolar and single-

ended/pseudo-differential operation.

The 4-wire serial interface connects directly to

SPI™/QSPI™/MICROWIRE™ devices without external

logic. A serial strobe output allows direct connection to

TMS320-family digital signal processors. The MAX1280/

MAX1281 use an external serial-interface clock to per-

form successive-approximation analog-to-digital con-

versions. Both parts feature an internal +2.5V reference

and a reference-buffer amplifier with a ±1.5% voltage-

adjustment range. An external reference with a 1V to

VDD1 range may also be used.

The MAX1280/MAX1281 provide a hard-wired SHDN

pin and four software-selectable power modes (normal

operation, reduced power, fast power-down, and full

power-down). These devices can be programmed to

automatically shut down at the end of a conversion or to

operate with reduced power. When using the power-

down modes, accessing the serial interface automatical-

ly powers up the devices, and the quick turn-on time

allows them to be powered down between all conver-

sions. This technique can cut supply current to under

100µA at reduced sampling rates.

The MAX1280/MAX1281 are available in 20-pin TSSOP

packages. These devices are higher-speed versions of

the MAX146/MAX147 (for more information, see the

respective data sheet).

Applications

Portable Data Logging

Data Acquisition

Medical Instruments

Battery-Powered Instruments

Pen Digitizers

Process Control

Features

♦8-Channel Single-Ended or 4-Channel

Pseudo-Differential Inputs

♦Internal Multiplexer and Track/Hold

♦Single-Supply Operation

+4.5V to +5.5V (MAX1280)

+2.7V to +3.6V (MAX1281)

♦Internal +2.5V Reference

♦400ksps Sampling Rate (MAX1280)

♦Low Power 2.5mA (400ksps)

1.3mA (Reduced-Power Mode)

0.9mA (Fast Power-Down Mode)

2µA (Full Power-Down)

♦SPI/QSPI/MICROWIRE/TMS320-Compatible

4-Wire Serial Interface

♦Software-Configurable Unipolar or Bipolar Inputs

♦20-Pin TSSOP Package

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

________________________________________________________________ Maxim Integrated Products 1

19-1684; Rev 2; 10/10

Pin Configuration

Ordering Information

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

TOP VIEW

TSSOP

VDD1

VDD2

DIN

SSTRB

DOUT

GND

REFADJ

REF

COM

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

MAX1280

MAX1281

SHDN

SCLK

EVALUATION KIT

AVAILABLE

PART TEMP

RANGE

PIN-

PACKAGE

INL

(LSB)

MAX1280BCUP+ 0°C to +70°C 20 TSSOP ±1

MAX1280BEUP+ -40°C to +85°C 20 TSSOP ±1

MAX1281BCUP+ 0°C to +70°C 20 TSSOP ±1

MAX1281BEUP+ -40°C to +85°C 20 TSSOP ±1

+Denotes a lead(Pb)-free/RoHS-compliant package.

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS—MAX1280

(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD_ to GND ............................................................ -0.3V to +6V

VDD1 to VDD2 ........................................................ -0.3V to +0.3V

CH0–CH7, COM to GND.......................... -0.3V to (VDD1 + 0.3V)

REF, REFADJ to GND .............................. -0.3V to (VDD1 + 0.3V)

Digital Inputs to GND .............................................. -0.3V to +6V

Digital Outputs to GND ............................ -0.3V to (VDD2 + 0.3V)

Digital Output Sink Current .................................................25mA

Continuous Power Dissipation (TA= +70°C)

20-Pin TSSOP (derate 7.0mW/°C above +70°C) .........559mW

Operating Temperature Ranges

MAX128_BCUP.................................................. 0°C to +70°C

MAX128_BEUP ............................................... -40°C to +85°C

Storage Temperature Range ............................ -60°C to +150°C

Lead Temperature (soldering, 10s) ................................ +300°C

Soldering Temperature (reflow) ...................................... +260°C

SINAD > 68dB

-3dB point

fIN = 200kHz, VIN = 2.5Vp-p

fIN1= 99kHz, fIN2= 102kHz

No missing codes over temperature

Up to the 5th harmonic

CONDITIONS

MHz

0.5 6.4

fSCLK

Serial Clock Frequency

<50

Aperture Jitter

Aperture Delay

468

tACQ

Track/Hold Acquisition Time

µs

2.5

tCONV

Conversion Time (Note 5)

kHz

350

Full-Linear Bandwidth

MHz

Full-Power Bandwidth

-78

Channel-to-Channel Crosstalk

(Note 4)

IMDIntermodulation Distortion

SFDRSpurious-Free Dynamic Range

-81

THDTotal Harmonic Distortion

Bits

Resolution

SINAD

Signal-to-Noise plus Distortion

Ratio

LSB

±0.1

Channel-to-Channel Offset-Error

Matching

ppm/°C

±0.8

Gain-Error Temperature

Coefficient

±1.0

LSB

±1.0

DNLDifferential Nonlinearity

LSB

±6.0

Offset Error

LSB

±7.0

Gain Error (Note 3)

UNITSMIN TYP MAXSYMBOLPARAMETER

40 60

Duty Cycle

DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)

DC ACCURACY (Note 1)

CONVERSION RATE

LSBINLRelative Accuracy (Note 2)

ELECTRICAL CHARACTERISTICS—MAX1280

(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS—MAX1280 (continued)

(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

To power down the internal reference

For small adjustments, from 1.22V

0 to 1mA output load

On/off leakage current, VCH_ = 0 or VDD1

TA= +25°C

Bipolar, VCOM or VCH_ = VREF/2,

referenced to COM or CH_

Unipolar, VCOM = 0

V/V

2.05

Buffer Voltage Gain

1.33 VDD1

REFADJ Buffer Disable

Threshold

±50

REFADJ Input Range

1.22

REFADJ Output Voltage

µF

0.01 10

Capacitive Bypass at REFADJ

µF

4.7 10

Capacitive Bypass at REF

mV/mA

0.1 2.0

Load Regulation (Note 7)

ppm/°C

±15

TC VREF

REF Output Temperature

Coefficient

REF Short-Circuit Current

2.480 2.500 2.520

VREF

REF Output Voltage

pF18Input Capacitance

µA

±0.001 ±1

Multiplexer Leakage Current

±VREF/2 V

VREF

VCH_

Input Voltage Range, Single-

Ended and Differential (Note 6)

VIN = 0 or VDD2

In power-down, fSCLK = 0

VREF = 2.500V, fSCLK = 0

VREF = 2.500V, fSCLK = 6.4MHz

(Note 8)

pFCIN

Input Capacitance

µA±1IIN

Input Leakage

V0.2VHYST

Input Hysteresis

V0.8VINL

Input Low Voltage

V3.0VINH

Input High Voltage

320 µA

200 350

REF Input Current

1.0 VDD1 +

50mV

REF Input Voltage Range

ISINK = 5mA V0.4VOL

Output Voltage Low

ISOURCE = 1mA V4VOH

Output Voltage High

CS = 5V µA±10IL

Three-State Leakage Current

CS = 5V pF15COUT

Three-State Output Capacitance

ANALOG INPUTS (CH7–CH0, COM)

EXTERNAL REFERENCE (Reference buffer disabled, reference applied to REF)

INTERNAL REFERENCE

DIGITAL INPUTS (DIN, SCLK, CS, SHDN)

DIGITAL OUTPUTS (DOUT, SSTRB)

Supply Current

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

4 _______________________________________________________________________________________

CONDITIONS

2.5 4.0

IVDD1 +

IVDD2

Supply Current

V4.5 5.5

VDD1,

VDD2

Positive Supply Voltage

(Note 9)

1.3 2.0

0.9 1.5

µA210

UNITSMIN TYP MAXSYMBOLPARAMETER

VDD1 =

VDD2 = 5.5V

ELECTRICAL CHARACTERISTICS—MAX1281

(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

SINAD > 68dB

-3dB point

fIN = 150kHz, VIN = 2.5Vp-p

fIN1 = 73kHz, fIN2 = 77kHz

No missing codes over temperature

Up to the 5th harmonic

CONDITIONS

kHz

250

Full-Linear Bandwidth

MHz

Full-Power Bandwidth

-78

Channel-to-Channel Crosstalk

(Note 4)

IMDIntermodulation Distortion

SFDR

Spurious-Free Dynamic

Range

-81

THDTotal Harmonic Distortion

LSB

±1.0

INLRelative Accuracy (Note 2)

Bits

Resolution

SINAD

Signal-to-Noise plus

Distortion Ratio

LSB

±0.2

Channel-to-Channel Offset-

Error Matching

ppm/°C

±1.6

Gain-Error Temperature

Coefficient

LSB

±1.0

DNLDifferential Nonlinearity

LSB

±6.0

Offset Error

LSB

±7.0

Gain Error (Note 3)

UNITSMIN TYP MAXSYMBOLPARAMETER

Operating mode (Note 10)

Reduced-power mode (Note 11)

Fast power-down (Note 11)

Full power-down (Note 11)

VDD1 = VDD2 = 5V ±10%, midscale input mV±0.5 ±2.0PSRPower-Supply Rejection

POWER SUPPLY

DC ACCURACY (Note 1)

DYNAMIC SPECIFICATIONS (75kHz sine-wave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bipolar input mode)

ELECTRICAL CHARACTERISTICS—MAX1280 (continued)

(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS—MAX1281 (continued)

(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

Normal operating mode

CONDITIONS

MHz

0.5 4.8

fSCLK

Serial Clock Frequency

< 50

Aperture Jitter

Aperture Delay

625

tACQ

Track/Hold Acquisition Time

µs

3.3

tCONV

Conversion Time (Note 5)

UNITSMIN TYP MAXSYMBOLPARAMETER

To power down the internal reference

For small adjustments, from 1.22V

0 to 0.75mA output load

On/off leakage current, VCH_ = 0 or VDD1

TA= +25°C

Bipolar, VCOM or VCH_ = VREF/2,

referenced to COM or CH_

Unipolar, VCOM = 0

V/V

2.05

Buffer Voltage Gain

1.33 VDD1 - 1

REFADJ Buffer Disable

Threshold

±50

REFADJ Input Range

1.22

REFADJ Output Voltage

µF

0.01 10

Capacitive Bypass at REFADJ

µF

4.7 10

Capacitive Bypass at REF

mV/mA

0.1 2.0

Load Regulation (Note 7)

ppm/°C

±15

TC VREF

REF Output Temperature

Coefficient

REF Short-Circuit Current

2.480 2.500 2.520

VREF

REF Output Voltage

pF18Input Capacitance

µA

±0.001 ±1

Multiplexer Leakage Current

±VREF/2

40 60

Duty Cycle

VREF

VCH_

Input Voltage Range, Single-

Ended and Differential (Note 6)

VIN = 0 or VDD2

In power-down, fSCLK = 0

VREF = 2.500V, fSCLK = 0

VREF = 2.500V, fSCLK = 4.8MHz

(Note 8)

CIN

Input Capacitance

µA

±1

IIN

Input Leakage

0.2

VHYST

Input Hysteresis

0.8

VINL

Input Low Voltage

2.0

VINH

Input High Voltage

REF Input Current 320 µA

200 350

1.0 VDD1 +

50mV

REF Input Voltage Range

CONVERSION RATE

ANALOG INPUTS (CH7–CH0, COM)

INTERNAL REFERENCE

EXTERNAL REFERENCE (Reference buffer disabled, reference applied to REF)

DIGITAL INPUTS (DIN, SCLK, CS, SHDN)

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

6 _______________________________________________________________________________________

VDD1 =

VDD2 = 3.6V

ISOURCE = 0.5mA

CONDITIONS

2.5 3.5

IVDD1 +

IVDD2

Supply Current (Note 10)

V2.7 3.6

VDD1,

VDD2

VVDD2 - 0.5VVOH

Output Voltage High

Positive Supply Voltage

(Note 9)

1.3 2.0

0.9 1.5

µA210

UNITSMIN TYP MAXSYMBOLPARAMETER

ISINK = 5mA V0.4VOL

Output Voltage Low

CS = 3V µA±10IL

Three-State Leakage Current

CS = 3V pF15COUT

Three-State Output

Capacitance

ELECTRICAL CHARACTERISTICS—MAX1281 (continued)

(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

TIMING CHARACTERISTICS—MAX1280

(Figures 1, 2, 6, 7; VDD1 = VDD2 = +4.5V to +5.5V; TA= TMIN to TMAX; unless otherwise noted.)

CLOAD = 20pF

CONDITIONS

100

tCSW

CS Pulse Width High

tSTE

CS Fall to SSTRB Enable

tDOE

CS Fall to DOUT Enable

10 65

tSTD

CS Rise to SSTRB Disable

10 65

tDOD

CS Rise to DOUT Disable

tSTV

SCLK Rise to SSTRB Valid

tDOV

SCLK Rise to DOUT Valid

tCL

SCLK Pulse Width Low

tCH

156

tCP

SCLK Period

SCLK Pulse Width High

10 20

tSTH

SCLK Rise to SSTRB Hold

10 20

tDOH

SCLK Rise to DOUT Hold

tCS1

CS Rise to SCLK Rise Ignore

tCSO

SCLK Rise to CS Fall Ignore

tDS

DIN to SCLK Setup

tDH

DIN to SCLK Hold

tCSS

CS Fall to SCLK Rise Setup

tCSH

SCLK Rise to CS Rise Hold

UNITSMIN TYP MAXSYMBOLPARAMETER

Operating mode

Reduced-power mode (Note 11)

Fast power-down (Note 11)

Full power-down (Note 11)

VDD1 = VDD2 = 2.7V to 3.6V, midscale input mV±0.5 ±2.0PSRPower-Supply Rejection

DIGITAL OUTPUTS (DOUT, SSTRB)

POWER SUPPLY

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 7

TIMING CHARACTERISTICS—MAX1281

(Figures 1, 2, 6, 7; VDD1 = VDD2 = +2.7V to +3.6V; TA= TMIN to TMAX; unless otherwise noted.)

CLOAD = 20pF

CONDITIONS

100

tCSW

CS Pulse Width High

tSTE

CS Fall to SSTRB Enable

tDOE

CS Fall to DOUT Enable

13 85

tSTD

CS Rise to SSTRB Disable

13 85

tDOD

CS Rise to DOUT Disable

100

tSTV

SCLK Rise to SSTRB Valid

100

tDOV

SCLK Rise to DOUT Valid

tCL

SCLK Pulse Width Low

tCH

208

tCP

SCLK Period

SCLK Pulse Width High

120

tSTH

SCLK Rise to SSTRB Hold

13 20

tDOH

SCLK Rise to DOUT Hold

tCS1

CS Rise to SCLK Rise Ignore

tCSO

SCLK Rise to CS Fall ignore

tDS

DIN to SCLK Setup

tDH

DIN to SCLK Hold

tCSS

CS Fall to SCLK Rise Setup

tCSH

SCLK Rise to CS Rise Hold

UNITSMIN TYP MAXSYMBOLPARAMETER

Note 1: MAX1280 tested at VDD1 = VDD2 = +5V, MAX1281 tested at VDD1 = VDD2 = +3V; COM = GND; unipolar single-ended

input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset

error have been nulled.

Note 3: Offset nulled.

Note 4: Ground “on” channel; sine wave applied to all “off” channels.

Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 6: The absolute voltage range for the analog inputs (CH7–CH0, and COM) is from GND to VDD1.

Note 7: External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA is a result

of production test limitations.

Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.

Note 9: Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) to VDD1(MAX) = VDD2(MAX). For operations beyond

this range, see the Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.

Note 10: AIN = midscale. Unipolar mode.MAX1280 tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 6.4MHz, 0 to 5V.

MAX1281 tested with same loads, fSCLK = 4.8MHz, 0 to 3V. DOUT = FFF hex.

Note 11:

PD1 PD0 MODE

0 0 Full power-down.

0 1 Fast power-down.

1 0 Reduced power mode.

1 1 Normal operation (operating mode).

Typical Operating Characteristics

(MAX1280: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1281: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor

at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

8 _______________________________________________________________________________________

0 1500 2000500 1000 2500 3000 3500 4000 4500

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1280/1-01

DIGITAL OUTPUT CODE

INL (LSB)

-0.1

-0.3

0.1

0.3

0.5

-0.2

0.2

0.4

-0.6

-0.4

-0.2

0.2

0.4

0.6

0 1000500 1500 2000 2500 3000 3500 4000 4500

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1280/1-02

DNL (LSB)

DIGITAL OUTPUT CODE

3.5

3.0

2.5

2.0

1.5

2.5 4.03.0 3.5 4.5 5.0 5.5

SUPPLY CURRENT vs. SUPPLY

VOLTAGE (CONVERTING)

MAX1280/1-03

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

2.0

2.4

2.2

2.8

2.6

3.0

3.2

-40 20 40-20 0 60 80 100

SUPPLY CURRENT vs. TEMPERATURE

MAX1280/1-04

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

MAX1281

MAX1280

NORMAL OPERATION (PD1 = PD0 = 1)

REDP (PD1 = 1, PD0 = 0)

FASTDP (PD1 = 0, PD0 = 1)

0.5

1.5

1.0

2.0

2.5

2.5 3.53.0 4.0 4.5 5.0 5.5

SUPPLY CURRENT vs. SUPPLY

VOLTAGE (STATIC)

MAX1280/1-05

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

0.5

1.5

1.0

2.0

2.5

-40 0-20 20406080100

SUPPLY CURRENT vs. TEMPERATURE

(STATIC)

MAX1280/1-06

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

MAX1280 (PD1 = 1, PD0 = 1)

MAX1280 (PD1 = 1, PD0 = 0)

MAX1280 (PD1 = 0, PD0 = 1)

MAX1281 (PD1 = 1, PD0 = 1)

MAX1281 (PD1 = 1, PD0 = 0)

MAX1281 (PD1 = 0, PD0 = 1)

2.5 3.53.0 4.0 4.5 5.0 5.5

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX1280/1-07

SUPPLY VOLTAGE (V)

SHUTDOWN CURRENT (µA)

(PD1 = PD0 = 0)

0.5

1.5

1.0

2.0

2.5

-40 0-20 20406080100

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

MAX1280/1-08

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

MAX1281

MAX1280

(PD1 = PD0 = 0)

2.4995

2.4997

2.5001

2.4999

2.5003

2.5005

2.5 3.53.0 4.0 4.5 5.0 5.5

REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

MAX1280/1-09

SUPPLY VOLTAGE (V)

REFERENCE VOLTAGE (V)

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 9

-3

-1

-2

2.7 3.33.0 3.6

GAIN ERROR vs. SUPPLY VOLTAGE

MAX1280/1-13

VDD (V)

GAIN ERROR (LSB)

Typical Operating Characteristics (continued)

(MAX1280: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1281: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor

at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)

2.4988

2.4992

2.4990

2.4996

2.4994

2.5000

2.4998

2.5002

-40 0 20-20 40 60 80 100

REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1280/1-10

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

MAX1281

MAX1280

-2.5

-2.0

-1.0

-1.5

-0.5

OFFSET ERROR vs. SUPPLY VOLTAGE

MAX1280/1-11

VDD (V)

OFFSET ERROR (LSB)

2.7 3.33.0 3.6

-2.5

-1.5

-2.0

-0.5

-1.0

0.5

-40 10-15 35 60 85

OFFSET ERROR vs. TEMPERATURE

MAX1280/1-12

TEMPERATURE (°C)

OFFSET ERROR (LSB)

-2.0

-1.5

-0.5

-1.0

0.5

GAIN ERROR vs. TEMPERATURE

MAX1280/1-14

TEMPERATURE (°C)

GAIN ERROR (LSB)

-40 10-15 35 60 85

MAX1281

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

10 ______________________________________________________________________________________

Pin Description

Positive Supply VoltageVDD2

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD1.REFADJ12

Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped-

ance when CS is high.

SSTRB15

Serial Data Input. Data is clocked in at SCLK’s rising edge.DIN16

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT

and SSTRB are high impedance.

Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed. (Duty

cycle must be 40% to 60%.)

SCLK18

Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.

In internal reference mode, the reference buffer provides a +2.500V nominal output, externally

adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to

VDD1.

REF11

Analog and Digital GroundGND13

Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.

DOUT14

Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA

(typ).

SHDN

Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be

stable to ±0.5LSB.

COM9

Sampling Analog InputsCH0–CH71–8

FUNCTIONNAME

VDD2

GND

DOUT

CLOAD

20pF

CLOAD

20pF

GND

DOUT

a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL

VDD2

GND

DOUT

CLOAD

20pF

CLOAD

20pF

GND

DOUT

a) VOH to High-Z b) VOL to High-Z

Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time

Positive Supply VoltageVDD1

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 11

Detailed Description

The MAX1280/MAX1281 analog-to-digital converters

(ADCs) use a successive-approximation conversion tech-

nique and input track/hold (T/H) circuitry to convert an

analog signal to a 12-bit digital output. A flexible serial

interface provides easy interface to microprocessors

(µPs). Figure 3 shows a functional diagram of the

MAX1280/MAX1281.

Pseudo-Differential Input

The equivalent input circuit of Figure 4 shows the

MAX1280/MAX1281’s input architecture, which is com-

posed of a T/H, input multiplexer, input comparator,

switched-capacitor DAC, and reference.

In single-ended mode, the positive input (IN+) is con-

nected to the selected input channel and the negative

input (IN-) is set to COM. In differential mode, IN+ and

IN- are selected from the following pairs: CH0/CH1,

CH2/CH3, CH4/CH5, and CH6/CH7. Configure the

channels according to Tables 2 and 3.

The MAX1280/MAX1281 input configuration is pseudo-

differential in that only the signal at IN+ is sampled. The

return side (IN-) is connected to the sampling capacitor

while converting and must remain stable within ±0.5LSB

(±0.1LSB for best results) with respect to GND during a

conversion.

If a varying signal is applied to the selected IN-, its ampli-

tude and frequency must be limited to maintain accuracy.

The following equations determine the relationship

between the maximum signal amplitude and its frequency

in order to maintain ±0.5LSB accuracy. Assuming a sinu-

soidal signal at IN-, the input voltage is determined by:

The maximum voltage variation is determined by:

A 650mVp-p 60Hz signal at IN- will generate ±0.5LSB

of error when using a +2.5V reference voltage and a

2.5µs conversion time (15/fSCLK). When a DC reference

voltage is used at IN-, connect a 0.1µF capacitor to

GND to minimize noise at the input.

During the acquisition interval, the channel selected as

the positive input (IN+) charges capacitor CHOLD. The

acquisition interval spans three SCLK cycles and ends

on the falling SCLK edge after the last bit of the input

control word has been entered. At the end of the acqui-

sition interval, the T/H switch opens, retaining charge

on CHOLD as a sample of the signal at IN+. The conver-

sion interval begins with the input multiplexer switching

CHOLD from IN+ to IN-. This unbalances node ZERO at

the comparator’s input. The capacitive DAC adjusts

during the remainder of the conversion cycle to restore

node ZERO to VDD1/2 within the limits of 12-bit

resolution. This action is equivalent to transferring a

12pF x (VIN+ - VIN-) charge from CHOLD to the binary-

weighted capacitive DAC, which in turn forms a digital

representation of the analog input signal.

max d-

d - 2f 1LSB

t V

tIN CONV

REF

12 CONV

νπ=

()

≤=V

νπ

IN IN--

sin(2 ft)=

()

INPUT

SHIFT

LOGIC

INT

CLOCK

OUTPUT

SHIFT

+1.22V

REFERENCE

T/H

ANALOG

INPUT

MUX

12-BIT

SAR

ADC

DOUT

SSTRB

VDD1

VDD2

GND

SCLK

DIN

COM

REFADJ

REF

OUT

REF

CLOCK

+2.500V

17kΩ

CH6 7

CH7 8

CH4 5

CH5 6

CH1 2

CH2 3

CH3 4

CH0 1

MAX1280

MAX1281

SHDN

≈ 2.05*

Figure 3. Functional Diagram

CHOLD

RIN

800Ω

12pF

HOLD

INPUT

MUX

CSWITCH*

*INCLUDES ALL INPUT PARASITICS

SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.

PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM

PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES FROM

THE SELECTED IN+ CHANNEL TO

THE SELECTED IN- CHANNEL.

CH0

REF

GND

CH1

CH2

CH3

CH4

CH5

CH6

CH7

ZERO

VDD1/2

COMPARATOR

CAPACITATIVE

DAC

6pF

TRACK

Figure 4. Equivalent Input Circuit

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

12 ______________________________________________________________________________________

10µF0.1µF

2.5V

VDD1

VDD2

GND

COM

SCLK

DIN

DOUT

SSTRB

SHDN

TO VDD2

0.01µF

CH7

REFADJ

REF

4.7µF

0V TO

2.500V

ANALOG

INPUT

OSCILLOSCOPE

CH1 CH2 CH3 CH4

*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)

MAX1280

MAX1281

+3V or +5V

EXTERNAL CLOCK

SCLK

SSTRB

DOUT*

0.01µF

Figure 5. Quick-Look Circuit

Track/Hold

The T/H enters its tracking mode on the falling clock

edge after the fifth bit of the 8-bit control word has been

shifted in. It enters its hold mode on the falling clock

edge after the eighth bit of the control word has been

shifted in. If the converter is set up for single-ended

inputs, IN- is connected to COM and the converter con-

verts the “+” input. If the converter is set up for differen-

tial inputs, the difference of [(IN+) - (IN-)] is converted.

At the end of the conversion, the positive input con-

nects back to IN+ and CHOLD charges to the input sig-

nal.

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens, and more time must be

allowed between conversions. The acquisition time,

tACQ, is the maximum time the device takes to acquire

the signal and is also the minimum time needed for the

signal to be acquired. It is calculated by the following

equation:

tACQ = 9 ✕(RS+ RIN) ✕12pF

where RIN = 800Ω, RS= the source impedance of the

input signal; tACQ is never less than 468ns (MAX1280)

or 625ns (MAX1281). Note that source impedances

below 2kΩdo not significantly affect the ADC’s AC per-

formance.

Input Bandwidth

The ADC’s input tracking circuitry has a 6MHz

(MAX1280) or 3MHz (MAX1281) small-signal band-

width, so it is possible to digitize high-speed transient

events and measure periodic signals with bandwidths

exceeding the ADC’s sampling rate by using under-

sampling techniques. To avoid high-frequency signals

being aliased into the frequency band of interest, anti-

alias filtering is recommended.

Analog Input Protection

Internal protection diodes, which clamp the analog

input to VDD1 and GND, allow the channel input pins to

swing from GND - 0.3V to VDD1 + 0.3V without dam-

age. However, for accurate conversions near full scale,

the inputs must not exceed VDD1 by more than 50mV or

be lower than GND by 50mV.

If the analog input exceeds 50mV beyond the sup-

plies, do not allow the input current to exceed 2mA.

Quick Look

To quickly evaluate the MAX1280/MAX1281’s analog

performance, use the circuit of Figure 5. The MAX1280/

MAX1281 require a control byte to be written to DIN

before each conversion. Connecting DIN to VDD2 feeds

in control bytes of $FF (HEX), which trigger single-

ended unipolar conversions on CH7 without powering

down between conversions. The SSTRB output pulses

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 13

high for one clock period before the MSB of the 12-bit

conversion result is shifted out of DOUT. Varying the

analog input to CH7 will alter the sequence of bits from

DOUT. A total of 16 clock cycles is required per con-

version. All transitions of the SSTRB and DOUT outputs

typically occur 20ns after the rising edge of SCLK.

Starting a Conversion

Start a conversion by clocking a control byte into DIN.

With CS low, each rising edge on SCLK clocks a bit from

DIN into the MAX1280/MAX1281’s internal shift register.

After CS falls, the first arriving logic “1” bit defines the

control byte’s MSB. Until this first “start” bit arrives, any

number of logic “0” bits can be clocked into DIN with no

effect. Table 1 shows the control-byte format.

The MAX1280/MAX1281 are compatible with SPI/QSPI

and MICROWIRE devices. For SPI, select the correct

clock polarity and sampling edge in the SPI control reg-

isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,

and QSPI all transmit a byte and receive a byte at the

same time. Using the Typical Operating Circuit, the

simplest software interface requires only three 8-bit

transfers to perform a conversion (one 8-bit transfer to

configure the ADC, and two more 8-bit transfers to

clock out the 12-bit conversion result). See Figure 17

for MAX1280/MAX1281 QSPI connections.

Simple Software Interface

Make sure the CPU’s serial interface runs in master

mode, so the CPU generates the serial clock. Choose a

clock frequency from 500kHz to 6.4MHz (MAX1280) or

4.8MHz (MAX1281).

1) Set up the control byte and call it TB1. TB1 should

be of the format 1XXXXXXX binary, where the Xs

denote the particular channel, selected conversion

mode, and power mode.

2) Use a general-purpose I/O line on the CPU to pull

CS low.

3) Transmit TB1 and, simultaneously, receive a byte

and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and, simultane-

ously, receive byte RB2.

5) Transmit a byte of all zeros ($00 hex) and, simultane-

ously, receive byte RB3.

6) Pull CS high.

Figure 6 shows the timing for this sequence. Bytes RB2

and RB3 contain the result of the conversion, padded

with three leading zeros and one trailing zero. The total

conversion time is a function of the serial-clock fre-

quency and the amount of idle time between 8-bit

transfers. To avoid excessive T/H droop, make sure the

total conversion time does not exceed 120µs.

Digital Output

In unipolar input mode, the output is straight binary

(Figure 14). For bipolar input mode, the output is two’s

complement (Figure 15). Data is clocked out on the ris-

ing edge of SCLK in MSB-first format.

184 9 12 16 2420

DIN

tACQ

SEL

UNI/

BIP PD1 PD0

RB1

SCLK

START

SSTRB HIGH-Z

DOUT

B6B8 B7B9B10B11 B1 B0B2B3B5 B4

RB2

CONVERSIONIDLE IDLE

ACQUISITION

RB3

SGL/

DIF

HIGH-Z

HIGH-ZHIGH-Z

Figure 6. Single-Conversion Timing

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

14 ______________________________________________________________________________________

BIT NAME DESCRIPTION

7 (MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.

6 SEL2 These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).

5 SEL1

4 SEL0

3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an

analog input signal from 0 to VREF can be converted; in bipolar mode, the differential signal can

range from -VREF/2 to +VREF/2.

2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-

ended mode, input signal voltages are referred to COM. In differential mode, the voltage

difference between two channels is measured (Tables 2 and 3).

1 PD1 Select operating mode.

0 (LSB) PD0 PD1 PD0 Mode

0 0 Full power-down

0 1 Fast power-down

1 0 Reduced Power

1 1 Normal Operation

Table 1. Control-Byte Format

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

(MSB) (LSB)

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1)

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

00 0 + –

00 1 + –

01 0 + –

01 1 +–

10 0 + –

10 1 + –

11 0 + –

11 1 + –

Table 3. Channel Selection in Psuedo-Differential Mode (SGL/DIF = 0)

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

00 0 + –

00 1 + –

01 0 + –

01 1 +–

10 0 – +

10 1 – +

11 0 – +

11 1 –+

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 15

Serial Clock

The external serial clock not only shifts data in and out,

but also drives the analog-to-digital conversion steps.

SSTRB pulses high for one clock period after the last bit

of the control byte. Successive-approximation bit deci-

sions are made and appear at DOUT on each of the next

12 SCLK falling edges (Figure 6). SSTRB and DOUT go

into a high-impedance state when CS goes high; after

the next CS rising edge, SSTRB outputs a logic low.

Figure 7 shows the detailed serial-interface timing.

The conversion must complete in 120µs or less, or

droop on the sample-and-hold capacitors may degrade

conversion results.

Data Framing

The falling edge of CS does not start a conversion. The

first logic high clocked into DIN is interpreted as a start

bit and defines the first bit of the control byte. A conver-

sion starts on SCLK’s falling edge after the eighth bit of

the control byte (the PD0 bit) is clocked into DIN. The

start bit is defined as follows:

The first high bit clocked into DIN with CS low any

time the converter is idle, e.g., after VDD1 and VDD2

are applied.

The first high bit clocked into DIN after bit 6 of a con-

version in progress is clocked onto the DOUT pin.

Once a start bit has been recognized, the current con-

version may only be terminated by pulling SHDN low.

The fastest the MAX1280/MAX1281 can run with CS

held low between conversions is 16 clocks per conver-

sion. Figure 8 shows the serial-interface timing neces-

sary to perform a conversion every 16 SCLK cycles. If

CS is tied low and SCLK is continuous, guarantee a

start bit by first clocking in 16 zeros.

Applications Information

Power-On Reset

When power is first applied, and if SHDN is not pulled

low, internal power-on reset circuitry activates the

MAX1280/MAX1281 in normal operating mode, ready to

convert with SSTRB = low. The MAX1280/MAX1281

require 10µs to reset after the power supplies stabilize;

no conversions should be initiated during this time. If

CS is low, the first logic 1 on DIN is interpreted as a

start bit. Until a conversion takes place, DOUT shifts out

zeros. Additionally, wait for the reference to stabilize

when using the internal reference.

Power Modes

You can save power by placing the converter in one of

the two low-current operating modes or in full power-

down between conversions. Select the power mode

through bit 1 and bit 0 of the DIN control byte (Tables 1

and 4), or force the converter into hardware shutdown

by driving SHDN to GND.

The software power-down modes take effect after the

conversion is completed; SHDN overrides any software

power mode and immediately stops any conversion in

SCLK

DIN

DOUT

SSTRB

tCSS tCH

tCSO tCL

tDH

tDS

tDOE

tSTE

tCSW

tCP tCSH

tCS1

tSTD

tDOD

tDOV

tDOH

tSTV

tSTH

Figure 7. Detailed Serial-Interface Timing

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

16 ______________________________________________________________________________________

progress. In software power-down mode, the serial

interface remains active, waiting for a new control byte

to start conversion and switch to full-power mode.

Once the conversion is completed, the device goes

into the programmed power mode until a new control

byte is written.

The power-up delay is dependent on the power-down

state. Software low-power modes will be able to start

conversion immediately when running at decreased

clock rates (see Power-Down Sequencing). During

power-on reset, when exiting software full power-down

mode or exiting hardware shutdown, the device goes

immediately into full-power mode and is ready to con-

vert after 2µs when using an external reference. When

using the internal reference, wait for the typical power-

up delay from a full power-down (software or hard-

ware), as shown in Figure 9.

Software Power-Down

Software power-down is activated using bits PD1 and

PD0 of the control byte. When software shutdown is

asserted, the ADC completes the conversion in

progress and powers down into the specified low-

quiescent-current state (2µA, 0.9mA, or 1.3mA).

The first logic 1 on DIN is interpreted as a start bit and

puts the MAX1280/MAX1281 into their full-power mode.

Following the start bit, the data input word or control

byte also determines the next power-down state. For

example, if the DIN word contains PD1 = 0 and PD0 =

1, a 0.9mA power-down starts after the conversion.

112

B11 B6 B0 B11 B6 B0 B11 B6

168 1 12 1685 1 12 16851

SETCS CONTROL BYTE 2S CONTROL BYTE 1SDIN

SCLK

DOUT

SSTRB

CONTROL BYTE 0

CONVERSION RESULT 0 CONVERSION RESULT 1

HIGH-Z

Figure 8. Continuous 16-Clock/Conversion Timing

PD1/PD0 MODE

CONVERTING AFTER

CONVERSION INPUT COMPARATOR REFERENCE

00 Full Power-Down

(FULLPD) 2.5mA 2µA Off Off

01 Fast Power-Down

(FASTPD) 2.5mA 0.9mA Reduced Power On

10 Reduced-Power

Mode (REDPD) 2.5mA 1.3mA Reduced Power On

11 Operating Mode 2.5mA 2.0mA Full Power On

CIRCUIT SECTIONS*TOTAL SUPPLY CURRENT

Table 4. Software-Controlled Power Modes

*Circuit operation between conversions; during conversion, all circuits are fully powered up.

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 17

Table 4 details the four power modes with the corre-

sponding supply current and operating sections. For

data rates achievable in software power-down modes,

see Power-Down Sequencing section.

Hardware Power-Down

Pulling SHDN low places the converter in hardware

power-down. Unlike software power-down mode, the

conversion is terminated immediately. When returning

to normal operation from SHDN with an external refer-

ence, the MAX1280/MAX1281 can be considered fully

powered-up within 2µs of actively pulling SHDN high.

When using the internal reference, the conversion

should be initiated only after the reference has settled;

its recovery time depends on the external bypass

capacitors and shutdown duration.

Power-Down Sequencing

The MAX1280/MAX1281’s automatic power-down

modes can save considerable power when operating at

less than maximum sample rates. Figures 10 and 11

show the average supply current as a function of the

sampling rate.

Using Full Power-Down Mode

Full power-down mode (FULLPD) achieves the lowest

power consumption at up to 1000 conversions per

channel per second. Figure 10a shows the MAX1281’s

power consumption for 1- or 8-channel conversions

using full power-down mode (PD1 = PD0 = 0), with the

internal reference and the maximum clock speed. A

0.01µF bypass capacitor plus the internal 17kΩrefer-

ence resistor at REFADJ forms an RC filter with a 200µs

time constant. To achieve full 12-bit accuracy, 10 time

constants or 2ms are required after power-up if the

bypass capacitor is fully discharged between conver-

sions. Waiting this 2ms in FASTPD mode or reduced-

power mode (REDP) instead of full power-down mode

can further reduce power consumption. This is

achieved by using the sequence shown in Figure 12a.

Figure 10b shows the MAX1281’s power consumption

for 1- or 8-channel conversions using FULLPD mode

(PD1 = PD0 = 0), an external reference, and the maxi-

mum clock speed. One dummy conversion to power-up

the device is needed, but no wait-time is necessary to

start the second conversion, thereby achieving lower

power consumption at up to the full sampling rate.

Using Fast Power-Down and

Reduced-Power Modes

FASTPD and REDP modes achieve the lowest power

consumption at speeds close to the maximum sample

rate. Figure 11 shows the MAX1281’s power consump-

tion in FASTPD mode (PD1 = 0, PD0 = 1), REDP mode

(PD1 = 1, PD0 = 0), and (for comparison) normal

operating mode (PD1 = 1, PD0 = 1). The figure shows

0.50

0.25

1.00

0.75

1.25

1.50

0.0001 0.010.001 0.1 1 10

TIME IN SHUTDOWN (s)

REFERENCE POWER-UP DELAY (ms)

MAX1281

VDD1 = VDD2 = 3.0V

CLOAD = 20pF

CODE = 101010000000

1000

100

0.1 101 100 1k 10k

SAMPLING RATE (sps)

SUPPLY CURRENT (µA)

8 CHANNELS

1 CHANNEL

10,000

1000

100

1 10010 1k 10k 100k

SAMPLING RATE (sps)

SUPPLY CURRENT (µA)

MAX1281

VDD1 = VDD2 = 3.0V

CLOAD = 20pF

CODE = 101010000000

8 CHANNELS

1 CHANNEL

Figure 9. Reference Power-Up Delay vs. Time in Shutdown

Figure 10a. Average Supply Current vs. Sample Rate (Using

FULLPD and Internal Reference)

Figure 10b. Average Supply Current vs. Sampling Rate (Using

FULLPD and External Reference)

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

18 ______________________________________________________________________________________

power consumption using the specified power-down

mode, with the internal reference and the maximum

clock speed. The clock speed in FASTPD or REDP

should be limited to 4.8MHz for the MAX1280/

MAX1281. FULLPD mode may provide increased power

savings in applications where the MAX1280/

MAX1281 are inactive for long periods of time, but

where intermittent bursts of high-speed conversions are

required.

Internal and External References

The MAX1280/MAX1281 can be used with an internal

or external reference. An external reference can be

connected directly at REF or at the REFADJ pin.

An internal buffer is designed to provide 2.5V at REF for

both the MAX1280/MAX1281. The internally trimmed

1.22V reference is buffered with a gain of +2.05V/V.

Internal Reference

The MAX1280/MAX1281’s full-scale range with the inter-

nal reference is 2.5V for unipolar inputs and ±1.25V for

bipolar inputs. The internal reference voltage is

adjustable to ±100mV with the circuit of Figure 13.

External Reference

An external reference can be placed at either the input

(REFADJ) or the output (REF) of the internal reference-

buffer amplifier. The REFADJ input impedance is typical-

ly 17kΩ. At REF, the DC input resistance is a minimum of

2.5

2.0

1.0

1.5

0.5

0150 250

100

50 200 300 350

SAMPLING RATE (sps)

SUPPLY CURRENT (mA)

MAX1281, VDD1 = VDD2 = 3.0V

CLOAD = 20pF

CODE = 101010000000

REDP

FASTPD

NORMAL OPERATION

Figure 11. Average Supply Current vs. Sampling Rate (Using

REPD, FASTPD, and Normal Operation and Internal Reference)

Figure 12a. Full Power-Down Timing

RE FADJ 1.22V 1.22V

2.5mA 2.5mA

1.3mA OR 0.9mA

DIN

IVDD1 + IVDD2

REF

FULLPD REDP

WAIT 2ms (10 x RC)

FULLPD

10011

γ = RC = 17kΩ x 0.01µF

DUMMY CONVERSION

1000

2.5V

2.5mA

0mA 0mA

2.5V

Figure 12b. Reduced-Power/Fast Power-Down Timing

2.5V (ALWAYS ON)

2.5mA 2.5mA

DIN

IVDD1 + IVDD2

REF

REDPD REDP FASTPD

11011

1001

2.5mA

1.3mA 1.3mA 0.9mA

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 19

18kΩ. During conversion, an external reference at REF

must deliver up to 350µA DC load current and have 10Ω

or less output impedance. If the reference has a higher

output impedance or is noisy, bypass it close to the REF

pin with a 4.7µF capacitor.

Using the REFADJ input makes buffering the external

reference unnecessary. To use the direct REF input,

disable the internal buffer by connecting REFADJ to

VDD1.

Transfer Function

Table 5 shows the full-scale voltage ranges for unipolar

and bipolar modes. Figure 14 depicts the nominal,

unipolar input/output (I/O) transfer function, and Figure

15 shows the bipolar I/O transfer function. Code transi-

tions occur halfway between successive-integer LSB

values. Output coding is binary, with 1LSB = 610µV

for unipolar and bipolar operation.

Layout, Grounding, and Bypassing

For best performance, use printed circuit boards; wire-

wrap boards are not recommended. Board layout

should ensure that digital and analog signal lines are

separated from each other. Do not run analog and digi-

tal (especially clock) lines parallel to one another, or

digital lines underneath the ADC package.

Figure 16 shows the recommended system ground

connections. Establish a single-point analog ground

(star ground point) at GND. Connect all analog grounds

to the star ground. Connect the digital system ground

to star ground at this point only. For lowest-noise opera-

tion, the ground return to the star ground’s power sup-

ply should be low impedance and as short as possible.

High-frequency noise in the VDD1 power supply may

affect the high-speed comparator in the ADC. Bypass

the supply to the star ground with 0.1µF and 10µF

capacitors, located close to pin 20 of the MAX1280/

MAX1281. Minimize capacitor lead lengths for best

supply-noise rejection. If the power supply is very

noisy, a 10Ωresistor can be connected as a lowpass

filter (Figure 16).

+3.3V

510kΩ

24kΩ

100kΩ

0.01µF

12 REFADJ

MAX1281

Figure 13. MAX1281 Reference-Adjust Circuit

OUTPUT CODE

FULL-SCALE

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000

123

(COM)

FS - 3/2LSB

FS = VREF + VCOM

ZS = VCOM

INPUT VOLTAGE (LSB)

1 LSB = VREF

4096

Figure 14. Unipolar Transfer Function, Full Scale (FS) = VREF

+ VCOM, Zero Scale (ZS) = VCOM

011 . . . 111

011 . . . 110

000 . . . 010

000 . . . 001

000 . . . 000

111 . . . 111

111 . . . 110

111 . . . 101

100 . . . 001

100 . . . 000

- FS COM*

INPUT VOLTAGE (LSB)

OUTPUT CODE

ZS = COM

+FS - 1LSB

*VCOM VREF / 2

+ VCOM

FS = VREF

-FS = + VCOM

-VREF

1 LSB = VREF

4096

≤

Figure 15. Bipolar Transfer Function, Full Scale (FS) =

VREF / 2 + VCOM, Zero Scale (ZS) = VCOM

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

20 ______________________________________________________________________________________

High-Speed Digital Interfacing with QSPI

The MAX1280/MAX1281 can interface with QSPI using

the circuit in Figure 17 (fSCLK = 4.0MHz, CPOL = 0,

CPHA = 0). This QSPI circuit can be programmed to do

a conversion on each of the eight channels. The result

is stored in memory without taxing the CPU, since QSPI

incorporates its own microsequencer.

TMS320LC3x Interface

Figure 18 shows an application circuit that interfaces

the MAX1280/MAX1281 to the TMS320 in external clock

mode. The timing diagram for this interface circuit is

shown in Figure 19.

Use the following steps to initiate a conversion in the

MAX1280/MAX1281 and to read the results:

1) The TMS320 should be configured with CLKX (trans-

mit clock) as an active-high output clock and with

CLKR (TMS320 receive clock) as an active-high

input clock. CLKX and CLKR on the TMS320 are

connected with the MAX1280/MAX1281’s SCLK

input.

2) The MAX1280/MAX1281’s CS pin is driven low by

the TMS320’s XF_ I/O port to enable data to be

clocked into the MAX1280/MAX1281’s DIN pin.

3) An 8-bit word (1XXXXX11) should be written to the

MAX1280/MAX1281 to initiate a conversion and

place the device into normal operating mode. See

Table 1 to select the proper XXXXX bit values for

your specific application.

4) The MAX1280/MAX1281’s SSTRB output is moni-

tored through the TMS320’s FSR input. A falling

edge on the SSTRB output indicates that the conver-

sion is in progress and data is ready to be received

from the MAX1280/MAX1281.

5) The TMS320 reads in one data bit on each of the

next 16 rising edges of SCLK. These data bits repre-

sent the 12-bit conversion result followed by four

trailing bits, which should be ignored.

6) Pull CS high to disable the MAX1280/MAX1281 until

the next conversion is initiated.

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line

drawn between the endpoints of the transfer function,

once offset and gain errors have been nullified. The

static linearity parameters for the MAX1280/MAX1281

are measured using the endpoint method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1LSB. A

DNL error specification of less than 1LSB guarantees

no missing codes and a monotonic transfer function.

Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation in

the time between the samples.

VDD1 VDD2

GND

SUPPLIES

DGNDVDD

VDD2

COM

GNDVDD1

DIGITAL

CIRCUITRY

R* = 10Ω

*OPTIONAL

MAX1280

MAX1281

Figure 16. Power-Supply Grounding Connection

UNIPOLAR MODE BIPOLAR MODE

Full Scale Zero Scale Positive Zero Negative

Full Scale Scale Full Scale

VREF + VCOM COM VREF / 2 VCOM -VREF / 2

+ VCOM + VCOM

Table 5. Full Scale and Zero Scale

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 21

Aperture Delay

Aperture delay (tAD) is the time defined between the

falling edge of the sampling clock and the instant when

an actual sample is taken.

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital

samples, Signal-to-noise ratio (SNR) is the ratio of full-

scale analog input (RMS value) to the RMS quantization

error (residual error). The ideal theoretical minimum

analog-to-digital noise is caused by quantization error

only and results directly from the ADC’s resolution (N

bits):

SNR = (6.02 ✕N + 1.76)dB

In reality, there are other noise sources besides quanti-

zation noise, including thermal noise, reference noise,

clock jitter, etc. Therefore, SNR is calculated by taking

the ratio of the RMS signal to the RMS noise, which

includes all spectral components minus the fundamen-

tal, the first five harmonics, and the DC offset.

Signal-to-Noise Plus Distortion

Signal-to-noise ratio plus distortion (SINAD) is the ratio

of the fundamental input frequency’s RMS amplitude to

RMS equivalent of all other ADC output signals.

SINAD (dB) = 20 ✕log (SignalRMS / NoiseRMS)

MAX1280

MAX1281 MC683XX

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

SHDN

VDD2

VDD1

SCLK

DIN

SSTRB

DOUT

GND

REFADJ

REF

VDD1

(POWER SUPPLIES)

SCK

PCS0

MOSI

MISO

0.1µF10µF

(GND)

4.7µF0.01µF

ANALOG

INPUTS

+3V OR +5V +3V OR +5V

Figure 17. QSPI Connections

CLKX

CLKR

FSR

SCLK

DIN

DOUT

SSTRB

TMS320LC3x

MAX1280

MAX1281

Figure 18. MAX1280/MAX1281-to-TMS320 Serial Interface

Effective Number of Bits

Effective number of bits (ENOB) indicates the global

accuracy of an ADC at a specific input frequency and

sampling rate. An ideal ADC’s error consists of quanti-

zation noise only. With an input range equal to the full-

scale range of the ADC, calculate the effective number

of bits as follows:

ENOB = (SINAD - 1.76) / 6.02

Total Harmonic Distortion (THD)

Total harmonic distortion (THD) is the ratio of the RMS

sum of the first five harmonics of the input signal to the

fundamental itself. This is expressed as:

where V1is the fundamental amplitude, and V2through

V5 are the amplitudes of the 2nd- through 5th-order har-

monics, respectively.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of RMS

amplitude of the fundamental (maximum signal compo-

nent) to the RMS value of the next-largest distortion

component.

THD 20 log

VVVVV

2232424252

=×

++++

⎛

⎝

⎜⎞

⎠

⎟

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

22 ______________________________________________________________________________________

SCLK

DIN

DOUT

SSTRB

SEL2START SEL1 SEL0 PD1 PD0

UNI/BIP SGI/DIF

B10 B1

MSB B0

HIGH IMPEDANCE

Figure 19. MAX1280/MAX1281-to-TMS320 Serial Interface

VDD

I/O

SCK (SK)

MOSI (SO)

MISO (SI)

VSS

SSTRB

DOUT

DIN

SCLK

COM

GND

VDD2

VDD1

CH8

4.7µF

0.1µF

CH0

0 TO

+2.5V

ANALOG

INPUTS MAX1280

MAX1281 CPU

SHDN

+5V OR

+3V

REF

0.01µF

REFADJ

Typical Operating Circuit

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 23

Package Information

For the latest package outline information and land patterns, go

to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in

the package code indicates RoHS status only. Package draw-

ings may show a different suffix character, but the drawing per-

tains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

20 TSSOP U20+2 21-0066

Chip Information

PROCESS: BiCMOS

MAX1280/MAX1281

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 5/00 Initial release —

1 4/10 Changed specifications due to single pass flow qualifications and added lead-

free information 1–5

2 10/10 Changed multiplexer leakage current condition, added note to supply current

condition, changed Note 11, changed Figures 4 and 12b 5, 6, 7, 11, 18