SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
512 × 18-Bit Organization Array (SN74V215)
D
1024 × 18-Bit Organization Array
(SN74V225)
D
2048 × 18-Bit Organization Array
(SN74V235)
D
4096 × 18-Bit Organization Array
(SN74V245)
D
7.5-ns Read/Write Cycle Time
D
3.3-V VCC, 5-V Input Tolerant
D
First-Word or Standard Fall-Through
Timing
D
Single or Double Register-Buffered Empty
and Full Flags
D
Easily Expandable in Depth and Width
D
Asynchronous or Coincident Read and
Write Clocks
D
Asynchronous or Synchronous
Programmable Almost-Empty and
Almost-Full Flags With Default Settings
D
Half-Full Flag Capability
D
Output Enable Puts Output Data Bus in
High-Impedance State
D
High-Performance Submicron CMOS
Technology
D
Packaged in 64-Pin Thin Quad Flat Package
D
DSP and Microprocessor Interface Control
Logic
D
Provide a DSP Glueless Interface to Texas
Instruments TMS320 DSPs
description
The SN74V215, SN74V225, SN74V235, and SN74V245 are very high-speed, low-power CMOS clocked first-in
first-out (FIFO) memories. They support clock frequencies up to 133 MHz and have read-access times as fast
as 5 ns. These DSP-Sync FIFO memories feature read and write controls for use in applications such as
DSP-to-processor communication, DSP-to-analog front end (AFE) buffering, network, video, and data
communications.
These are synchronous FIFOs, which means each port employs a synchronous interface. All data transfers
through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals.
The continuous clocks for each port are independent of one another and can be asynchronous or coincident.
The enables for each port are arranged to provide a simple interface between DSPs, microprocessors, and/or
buses controlled by a synchronous interface. An output-enable (OE) input controls the 3-state output.
The synchronous FIFOs have two fixed flags, empty flag/output ready (EF/OR) and full flag/input ready (FF/IR),
and two programmable flags, almost-empty (PAE) and almost-full (PAF). The offset loading of the
programmable flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD). A
half-full flag (HF) is available when the FIFO is used in a single-device configuration.
Two timing modes of operation are possible with these devices: first-word fall-through (FWFT) mode and
standard mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three
transitions of the RCLK signal. A read enable (REN) does not have to be asserted for accessing the first word.
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a
specific read operation is performed. A read operation, which consists of activating REN and enabling a rising
RCLK edge, shifts the word from internal memory to the data output lines.
These devices are depth expandable, using a daisy-chain technique or FWFT mode. The XI and XO pins are
used to expand the FIFOs. In depth-expansion configuration, first load (FL) is grounded on the first device and
set to high for all other devices in the daisy chain.
The SN74V215, SN74V225, SN74V235, and SN74V245 are characterized for operation from 0°C to 70°C.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DSP-SYNC and TMS320 are trademarks of Texas Instruments.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PAG PACKAGE
(TOP VIEW)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
Q6
Q5
GND
Q4
VCC
D16
D17
GND
WEN
WXI
PAE
FL
WCLK
REN
LD
OE
Q17
RS
GND
Q15
RCLK
RXO
PAF
RXI
WXO/HF
GND
Q2
Q3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
Q16
Q1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GND
FF/IR
Q0
VCC
EF/OR
VCC
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Write-Control
Logic
RAM ARRAY
512 ×18, 1024 ×18,
2048 ×18, 4096 ×18
Offset
Register
Input
Register
Flag
Logic
Read
Pointer
Read-Control
Logic
Output
Register
Write
Pointer
Expansion
Logic
Reset
Logic
(HF)/WXO
WXI
FL
RXI
RXO
RS
WEN
WCLK
D0–D17 LD
HF/(WXO)
PAE
EF/OR
PAF
FF/IR
Q0–Q17
OE RENRCLK
19
20
18
21
26
24
27
57
59
58 61 60
25
23
54
17
26
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
D0–D17 1–16, 63,
64 IData inputs. Data inputs for an 18-bit bus.
EF/OR 54 O Memory-empty/valid-data-available flag. In the standard mode, the EF function is selected. EF indicates
whether the FIFO memory is empty. In FWFT mode, the OR function is selected. OR indicates whether
there is valid data available at the outputs.
FF/IR 25 O Memory-full/space-available flag. In the standard mode, the FF function is selected. FF indicates whether
the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether there is space
available for writing to the FIFO memory.
FL 18 I
Mode selection. In the single-device or width-expansion configuration, FL, together with WXI and RXI,
determines if the mode is standard mode or first-word fall-through (FWFT) mode, as well as whether the
PAE/PAF flags are synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion
configuration, FL is grounded on the first device (first-load device) and set to high for all other devices in
the daisy chain.
GND 30, 35, 40,
46, 51, 55,
62 Ground
LD 59 I Read/write control. When LD is low , data on the inputs D0–D1 1 is written to the offset and depth registers
on the low-to-high transition of the WCLK, when WEN is low . When LD is low, data on the outputs Q0–Q11
is read from the offset and depth registers on the low-to-high transition of RCLK when REN is low.
OE 58 I Output enable. When OE is low, the data output bus is active. If OE is high, the output data bus is in the
high-impedance state.
PAE 17 O Programable almost-empty flag. When PAE is low, the FIFO is almost empty, based on the offset
programmed into the FIFO. The default offset at reset is 63 from empty for SN74V215, and 127 from empty
for SN74V225, SN74V235, and SN74V245.
PAF 23 O Programable almost-full flag. When PAF is low , the FIFO is almost full, based on the of fset programmed
into the FIFO. The default of fset at reset is 63 from full for SN74V215, and 127 from full for SN74V225,
SN74V235, and SN74V245.
Q0–Q17
28, 29, 31,
32, 34,
36–39, 41,
42, 44, 45,
47, 48, 50,
52, 53
OData outputs. Data outputs for an 18-bit bus.
RCLK 61 I Read clock. When REN is low , data is read from the FIFO on a low-to-high transition of RCLK, if the FIFO
is not empty.
REN 60 I Read enable. When REN is low, data is read from the FIFO on every low-to-high transition of RCLK. When
REN is high, the output register holds the previous data. Data is not read from the FIFO if EF is low.
RS 57 I Reset. When RS is set low , internal read and write pointers are set to the first location of the RAM array,
FF and PAF go high, and PAE and EF go low. A reset is required before an initial write after power up.
RXI 24 I
Read expansion. In the single-device or width-expansion configuration, RXI, together with FL and WXI,
determines if the mode is standard mode or FWFT mode, as well as whether the PAE/PAF flags are
synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion configuration, RXI is
connected to RXO (read expansion out) of the previous device.
RXO 27 O Last-location-read flag. In the depth-expansion configuration, a pulse is sent from RXO to RXI of the next
device when the last location in the FIFO is read.
VCC 22, 33, 43,
49, 56 Supply voltage. +3.3-V power-supply pins.
WCLK 19 I Write clock. When WEN is low , data is written into the FIFO on a low-to-high transition of WCLK if the FIFO
is not full.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
WEN 20 I Write enable. When WEN is low, data is written into the FIFO on every low-to-high transition of WCLK.
When WEN is high, the FIFO holds the previous data. Data is not written into the FIFO if FF is low.
WXI 21 I
Width expansion. In the single-device or width-expansion configuration, WXI, together with FL and RXI,
determines if the mode is standard mode or FWFT mode, as well as whether the PAE/PAF flags are
synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion configuration, WXI is
connected to WXO (write expansion out) of the previous device.
WXO/HF 26 O Half-full flag. In the single-device or width-expansion configuration, the device is more than half full when
HF is low. In the depth-expansion configuration, a pulse is sent from WXO to WXI of the next device when
the last location in the FIFO is written.
detailed description
INPUTS:
DATA IN (D0–D17)
Data inputs for 18-bit-wide data.
CONTROLS:
RESET (RS)
Reset is accomplished when RS is taken low. During reset, both internal read and write pointers are set to the
first location. A reset is required after power up before a write operation can take place. The half-full flag (HF)
and programmable almost-full flag (PAF) is reset to high after tRSF. The programmable almost-empty flag (P AE)
is reset to low after tRSF. The full flag (FF) resets to high. The empty flag (EF) resets to low in standard mode,
but resets to high in FWFT mode. During reset, the output register is initialized to all zeros, and the offset
registers are initialized to their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the low-to-high transition of WCLK. Data setup and hold times must be met with
respect to the low-to-high transition of WCLK.
The write and read clocks can be asynchronous or coincident.
WRITE ENABLE (WEN)
When WEN is low, data can be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the
device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation.
When WEN is high, no new data is written in the RAM array on each WCLK cycle.
T o prevent data overflow in the standard mode, FF goes low, inhibiting further write operations. Upon completion
of a valid read cycle, FF goes high, allowing a write to occur. The FF flag is updated on the rising edge of WCLK.
To prevent data overflow in the FWFT mode, IR goes high, inhibiting further write operations. Upon completion
of a valid read cycle, IR goes low , allowing a write to occur . The IR flag is updated on the rising edge of WCLK.
WEN is ignored when the FIFO is full in either FWFT or standard mode.
READ CLOCK (RCLK)
Data can be read on the outputs on the low-to-high transition of RCLK when OE is low.
The write and read clocks can be asynchronous or coincident.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
READ ENABLE (REN)
When REN is low , data is loaded from the RAM array into the output register on the rising edge of every RCLK
cycle if the device is not empty.
When REN is high, the output register holds the previous data and no new data is loaded into the output register.
Data outputs Q0–Qn maintain the previous data value.
In the standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be
requested using REN. When the last word has been read from the FIFO, the empty flag (EF) goes low, inhibiting
further read operations. REN is ignored when the FIFO is empty. After a write is performed, EF goes high,
allowing a read to occur. The EF flag is updated on the rising edge of RCLK.
In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third
valid low-to-high transition of RCLK + tSKEW after the first write. REN need not be asserted low. To access all
other words, a read must be executed using REN. The RCLK low-to-high transition after the last word has been
read from the FIFO, output ready (OR) goes high with a true read (RCLK with REN low), inhibiting further read
operations. REN is ignored when the FIFO is empty.
OUTPUT ENABLE (OE)
When OE is low, the parallel output buffers transmit data from the output register. When OE is high, the Q-output
data bus is in the high-impedance state.
LOAD (LD)
The SN74V215, SN74V225, SN74V235, and SN74V245 devices contain two 12-bit offset registers with data
on the inputs, or read on the outputs. When LD is low and WEN is low , data on the inputs D0–D1 1 is written into
the empty offset register on the first low-to-high transition of the write clock (WCLK). When LD and WEN are
held low, data is written into the full offset register on the second low-to-high transition of WCLK (see Tables 1
and 2). The third transition of WCLK again writes to the empty-offset register.
However , writing to all offset registers need not occur at one time. One or two offset registers can be written and
then, by bringing LD high, the FIFO is returned to normal read/write operation. When LD is low, and WEN is low,
the next offset register in sequence is written.
Table 1. Writing to Offset Registers
LD WEN WCLK SELECTION†
L L ↑Writing to offset registers:
Empty offset
Full offset
L H ↑No operation
H L ↑Write into FIFO
H H ↑No operation
†The same selection sequence applies to reading from the
registers. REN is enabled and read is performed on the
low-to-high transition of RCLK.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
Table 2. Offset Register Location and Default Values†
17 12 11 0
Empty Offset Register
Not used Default Value
003FH (74V215):
007FH (74V225/74V235/74V245)
17 12 11 0
Full Offset Register
Not used Default Value
003FH (74V215):
007FH (74V225/74V235/74V245)
†Any bits of the offset register not being programmed should be set to zero.
When LD is low and WEN is high, the WCLK input is disabled; then, a signal at this input can neither increment
the write-offset-register pointer, nor execute a write.
The contents of the offset registers can be read on the output lines when LD is low and REN is low; then, data
can be read on the low-to-high transition of RCLK. Reading the control registers employs a dedicated
read-offset-register pointer . (The read and write pointers operate independently .) Offset register content can be
read out in the standard mode only. It is inhibited in the FWFT mode.
A read from and a write to the offset registers should not be performed simultaneously.
FIRST LOAD (FL)
For the single-device mode, see Table 5 for additional information. In the daisy-chain depth-expansion
configuration, FL is grounded to indicate it is the first device loaded and is set high for all other devices in the
daisy chain (see Operating Configurations for further details).
WRITE EXPANSION INPUT (WXI)
This is a dual-purpose pin. For single-device mode, see Table 5 for additional information. WXI is connected
to write expansion out (WXO) of the previous device in the daisy-chain depth-expansion mode.
READ EXPANSION INPUT (RXI)
This is a dual-purpose pin. For single-device mode, see Table 5 for additional information. RXI is connected to
read expansion out (RXO) of the previous device in the daisy-chain depth-expansion mode.
OUTPUTS:
FULL FLAG/INPUT READY (FF/IR)
This is a dual-purpose pin. In FWFT mode, the input ready (IR) function is selected. IR goes low when memory
space is available for writing data. When there is no free space left, IR goes high, inhibiting further write
operations.
In standard mode, the FF function is selected. When the FIFO is full, FF goes low, inhibiting further write
operations. When FF is high, the FIFO is not full. If no reads are performed after a reset, FF goes low after
D writes to the FIFO. D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235, and 4096
for the SN74V245.
IR goes high after D writes to the FIFO. D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the
SN74V235, and 4097 for the SN74V245. The additional word in FWFT mode is due to the capacity of the
memory plus output register.
FF/IR is synchronous and updated on the rising edge of WCLK.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
EMPTY FLAG/OUTPUT READY (EF/OR)
This is a dual-purpose pin. In FWFT mode, the OR function is selected. OR goes low at the same time the first
word written to an empty FIFO appears valid on the outputs. OR stays low after the RCLK low-to-high transition
that shifts the last word from the FIFO memory to the outputs. OR goes high only with a true read (RCLK with
REN low). The previous data stays at the outputs, indicating that the last word was read. Further data reads
are inhibited until OR goes low again.
In the standard mode, the EF function is selected. When the FIFO is empty , EF goes low , inhibiting further read
operations. When EF is high, the FIFO is not empty.
EF/OR is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
PAF goes low when the FIFO reaches the almost-full condition. In FWFT mode, if no reads are performed, P AF
goes low after 513 – m for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235, and 4097 for the
SN74V245. Default values for m are in Table 3 and Table 4.
In standard mode, if no reads are performed after reset (RS), PAF goes low after (512 – m) writes for the
SN74V215, (1024 – m) writes for the SN74V225, (2048 – m) writes for the SN74V235, and (4096 – m) writes
for the SN74V245. The offset m is defined in the full offset register.
If asynchronous P AF configuration is selected, P AF is asserted low on the low-to-high transition of WCLK. PAF
is reset to high on the low-to-high transition of RCLK. If synchronous PAF configuration is selected (see T able 5),
PAF is updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
PAE goes low when the FIFO reaches the almost-empty condition. In FWFT mode, PAE goes low when there
are n + 1 words, or fewer , in the FIFO. In standard mode, PAE goes low when there are n words or fewer in the
FIFO. The offset n is defined as the empty offset. The default values for n are noted in Table 3 and Table 4.
If there is no empty offset specified, PAE is low when the device is 63 away from completely empty for
SN74V215, and 127 away from completely empty for SN74V225, SN74V235, and SN74V245.
If asynchronous PAE configuration is selected, PAE is asserted low on the low-to-high transition of the read clock
(RCLK). PAE is reset to high on the low-to-high transition of the write clock (WCLK). If synchronous PAE
configuration is selected (see Table 5), PAE is updated on the rising edge of RCLK.
WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF)
This is a dual-purpose output. In the single-device and width-expansion mode, when write expansion in (WXI)
and/or read expansion in (RXI) are grounded, this output acts as an indication of a half-full memory.
After one-half of the memory is filled, and at the low-to-high transition of the next write cycle, the half-full flag
(HF) goes low and remains set until the difference between the write pointer and read pointer is less than or
equal to one-half of the total memory of the device. HF is then reset to high by the low-to-high transition of the
read clock (RCLK). HF is asynchronous.
In the daisy-chain depth-expansion mode, WXI is connected to WXO of the previous device. This output acts
as a signal to the next device in the daisy chain by providing a pulse when the previous device writes to the last
location of memory.
READ EXPANSION OUT (RXO)
In the daisy-chain depth-expansion configuration, read expansion in (RXI) is connected to read expansion out
(RXO) of the previous device. This output acts as a signal to the next device in the daisy chain by providing a
pulse when the previous device reads from the last location of memory.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
DATA OUTPUTS (Q0–Q17)
Q0–Q17 are data outputs for 18-bit-wide data.
functional description
TIMING MODES:
STANDARD vs FIRST-WORD FALL-THROUGH (FWFT) MODE
The SN74V215, SN74V225, SN74V235, and SN74V245 support two different timing modes. The selection of
the mode of operation is determined during configuration at reset (RS). During an RS operation, the first load
(FL), read expansion input ( RXI), and write-expansion input (WXI) pins are used to select the timing mode as
shown in the truth table (see T able 5). In standard mode, the first word written to an empty FIFO does not appear
on the data output lines unless a specific read operation is performed. A read operation, which consists of
activating read enable (REN) and enabling a rising read clock (RCLK) edge, shifts the word from internal
memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to
the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted to access
the first word.
V arious signals, both input and output signals, operate differently , depending on which timing mode is in effect.
FIRST-WORD FALL-THROUGH MODE (FWFT)
In this mode, status flags IR, PAF, HF, PAE, and OR operate in the manner outlined in Table 3. To write data
into the FIFO, WEN must be low. Data presented to the data-in lines is clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the output ready (OR) flag goes low . Subsequent writes
continue to fill the FIFO. P AE goes high after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for this value is stated in the footnote of Table 3. This parameter also is user
programmable. See the Programmable Flag Offset Loading section.
If data continues to be written into the FIFO, and no read operations are taking place, HF switches to low when
the 258th (SN74V215), 514th (SN74V225), 1026th (SN74V235), and 2050th (SN74V245) word, respectively,
is written into the FIFO. Continuing to write data into the FIFO causes PAF to go low. Again, if no reads are
performed, PAF goes low after (513 – m) writes for the SN74V215, (1025 – m) writes for the SN74V225,
(2049 – m) writes for the SN74V235, and (4097 – m) writes for the SN74V245, where m is the full offset value.
The default setting for this value is stated in the footnote of Table 3.
When the FIFO is full, the input ready (IR) flag goes high, inhibiting further write operations. If no reads are
performed after a reset, IR goes high after D writes to the FIFO. D = 513 for the SN74V215, 1025 for the
SN74V225, 2049 for the SN74V235, and 4097 for the SN74V245. The additional word in FWFT mode is due
to the capacity of the memory plus output register.
If the FIFO is full, the first read operation causes the IR flag to go low . Subsequent read operations cause P AF
and HF to go high at the conditions described in Table 3. If further read operations occur without write
operations, PAE goes low when there are n + 1 words in the FIFO, where n is the empty of fset value. If there
is no empty offset specified, PAE is low when the device is 64 away from empty for SN74V215, and 128 away
from empty for SN74V225, SN74V235, and SN74V245. Continuing read operations cause the FIFO to be
empty . When the last word has been read from the FIFO, OR goes high, inhibiting further read operations. REN
is ignored when the FIFO is empty.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional description (continued)
Table 3. Status Flags for FWFT Mode
NUMBER OF WORDS IN FIFO
IR
PAF
HF
PAE
OR
SN74V215 SN74V225 SN74V235 SN74V245
IR
PAF
HF
PAE
OR
0 0 0 0 L H H L H
1 to (n+1)†1 to (n+1)†1 to (n+1)†1 to (n+1)†L H H L L
(n+2) to 257 (n+2) to 513 (n+2) to 1025 (n+2) to 2049 L H H H L
258 to [513–(m+1)]‡514 to [1025–(m+1)]‡1026 to [2049–(m+1)]‡2050 to [4097–(m+1)]‡L H L H L
(513–m) to 512 (1025–m) to 1024 (2049–m) to 2048 (4097–m) to 4096 L L L H L
513 1025 2049 4097 H L L H L
†n = Empty offset (SN74V215 n = 63; SN74V225, SN74V235, and SN74V245 n = 127)
‡m = Full offset (SN74V215 m = 63; SN74V225, SN74V235, and SN74V245 m = 127)
STANDARD MODE
In this mode, status flags FF, P AF , HF, P AE, and EF operate in the manner outlined in Table 4. To write data into
the FIFO, write enable (WEN) must be low. Data presented to the data-in lines is clocked into the FIFO on
subsequent transitions of the write clock (WCLK). After the first write is performed, the empty flag (EF) goes
high. Subsequent writes continue to fill the FIFO. The programmable almost-empty flag (PAE) goes high after
n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for this value
is stated in the footnote of Table 4. This parameter also is user programmable. See the Programmable Flag
Offset Loading section.
If data continues to be written into the FIFO, and no read operations are taking place, the half-full flag (HF)
switches to low when the 257th (SN74V215), 513th (SN74V225), 1025th (SN74V235), and 2049th (SN74V245)
word, is written into the FIFO. Continuing to write data into the FIFO causes the programmable almost-full flag
(PAF) to go low . Again, if no reads are performed, P AF goes low after (512 – m) writes for the SN74V215, (1024
– m) writes for the SN74V225, (2048 – m) writes for the SN74V235 and (4096 – m) writes for the SN74V245.
Offset m is the full of fset value. This parameter also is user programmable. See the Programmable Flag Offset
Loading section. If there is no full offset specified, P AF is low when the device is 63 away from full for SN74V215,
and 127 away from full for the SN74V225, SN74V235, and SN74V245.
When the FIFO is full, the full flag (FF) goes low, inhibiting further write operations. If no reads are performed
after a reset, FF goes low after D writes to the FIFO. D = 512 for the SN74V215, 1024 for the SN74V225, 2048
for the SN74V235, and 4096 for the SN74V245.
If the FIFO is full, the first read operation causes FF to go high. Subsequent read operations cause PAF and
the half-full flag (HF) to go high under the conditions described in Table 4. If further read operations occur,
without write operations, the programmable almost-empty flag (PAE) goes low when there are n words in the
FIFO, where n is the empty offset value. If there is no empty of fset specified, PAE is low when the device is 63
away from completely empty for SN74V215, and 127 away from completely empty for SN74V225, SN74V235,
and SN74V245. Continuing read operations cause the FIFO to be empty. When the last word has been read
from the FIFO, EF goes low, inhibiting further read operations. REN is ignored when the FIFO is empty.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional description (continued)
Table 4. Status Flags for Standard Mode
NUMBER OF WORDS IN FIFO
FF
PAF
HF
PAE
EF
SN74V215 SN74V225 SN74V235 SN74V245
FF
PAF
HF
PAE
EF
0 0 0 0 H H H L L
1 to n†1 to n†1 to n†1 to n†H H H L H
(n+1) to 256 (n+1) to 512 (n+1) to 1024 (n+1) to 2048 H H H H H
257 to [512–(m+1)]‡513 to [1025–(m+1)]‡1025 to [2048–(m+1)]‡2049 to [4096–(m+1)]‡H H L H H
(512–m) to 511 (1024–m) to 1023 (2048–m) to 2047 (4096–m) to 4095 H L L H H
512 1024 2048 4096 L L L H H
†n = Empty offset (SN74V215 n = 63; SN74V225, SN74V235, and SN74V245 n = 127)
‡m = Full offset (SN74V215 m = 63; SN74V225, SN74V235, and SN74V245 m = 127)
PROGRAMMABLE FLAG LOADING
Full- and empty-flag offset values can be user programmable. The SN74V215, SN74V225, SN74V235, and
SN74V245 have internal registers for these of fsets. Default settings are stated in the footnotes of Table 3 and
Table 4. Of fset values are loaded into the FIFO using the data input lines D0–D11. To load the offset registers,
the load (LD) pin and WEN pin must be held low. Data present on D0–D11 is transferred to the empty offset
register on the first low-to-high transition of WCLK. By continuing to hold the LD and WEN pins low, data present
on D0–D1 1 is transferred into the full offset register on the next transition of the WCLK. The third transition again
writes to the empty offset register. Writing to all of fset registers does not have to occur at the same time. One
or two offset registers can be written and, then, by bringing the LD pin high, the FIFO is returned to normal
read/write operation. When the LD pin and WEN again are set low, the next offset register in sequence is written.
The contents of the offset registers can be read on the data output lines Q0–Q11 when the LD pin is set low,
and REN is set low. Data then can be read on the next low-to-high transition of RCLK. The first transition of RCLK
presents the empty offset value to the data output lines. The next transition of RCLK presents the full offset
value. Offset register content can be read in the standard mode only. It cannot be read in the FWFT mode.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION
The SN74V215, SN74V225, SN74V235, and SN74V245 can be configured during the configuration-at-reset
cycle (see Table 5) with either asynchronous or synchronous timing for PAE and PAF flags.
If asynchronous PAE/PAF configuration is selected (see Table 5), the PAE is asserted low on the low-to-high
transition of RCLK. PAE is reset to high on the low-to-high transition of WCLK. Similarly, the PAF is asserted
low on the low-to-high transition of WCLK, and PAF is reset to high on the low-to-high transition of RCLK. For
detailed timing diagrams, see Figure 9 for asynchronous PAE timing and Figure 10 for asynchronous PAF
timing.
If synchronous PAE/PAF configuration is selected, PAE is asserted and updated on the rising edge of RCLK
only, but not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only, but not RCLK.
For detailed timing diagrams, see Figure 18 for synchronous PAE timing and Figure 19 for synchronous PAF
timing.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional description (continued)
Table 5. Truth Table for Configuration at Reset
FL RXI WXI EF/OR FF/IR PAE, PAF FIFO TIMING MODE
0 0 0 Single register-buffered
empty flag Single register-buffered
full flag Asynchronous Standard
0 0 1 T riple register-buffered
output-ready flag Double register-buffered
input ready flag Asynchronous FWFT
0 1 0 Double register-buffered
empty flag Double register-buffered
full flag Asynchronous Standard
0†1 1 Single register-buffered
empty flag Single register-buffered
full flag Asynchronous Standard
1 0 0 Single register-buffered
empty flag Single register-buffered
full flag Synchronous Standard
1 0 1 T riple register-buffered
output-ready flag Double register-buffered
input ready flag Synchronous FWFT
1 1 0 Double register-buffered
empty flag Double register-buffered
full flag Synchronous Standard
1‡1 1 Single register-buffered
empty flag Single register-buffered
full flag Asynchronous Standard
†In daisy-chain depth expansion, FL is held low for the first-load device. The RXI and WXI inputs are driven by the
corresponding RXO and WXO outputs of the preceding device.
‡In daisy-chain depth expansion, FL is held high for members of the expansion other than the first-load device. The RXI and
WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.
REGISTER-BUFFERED FLAG OUTPUT SELECTION
The SN74V215, SN74V225, SN74V235, and SN74V245 can be configured during the configuration-at-reset
cycle (see Table 7) with single, double, or triple register-buffered flag output signals. The various combinations
available are described in Table 6 and T able 7. In general, going from single to double or triple register-buffered
flag outputs removes the possibility of metastable flag indications on boundary states (empty or full conditions).
The tradeoff is the addition of clock-cycle delays for the respective flag to be asserted. Not all combinations of
register-buffered flag outputs are supported. Register-buffered outputs apply to the empty flag and full flag only .
Partial flags are not affected. Table 6 and Table 7 summarize the options available.
Table 6. Register-Buffered Flag Output Options, FWFT Mode
OUTPUT READY
(OR)
INPUT READY
(IR)
PARTIAL
FLAGS
PROGRAMMING
AT RESET FLAG TIMING
DIAGRAMS
(OR)
(IR)
FLAGS
FL RXI WXI
DIAGRAMS
Triple Double Asynchronous 0 0 1 Figure 23
Triple Double Synchronous 1 0 1 Figure 16, Figure 17
Table 7. Register-Buffered Flag Output Options, Standard Mode
EMPTY FLAG
(
EF
)
FULL FLAG
(
FF
)
PARTIAL
FLAGS
PROGRAMMING AT
RESET FLAG TIMING
DIAGRAMS
(EF)
BUFFERED OUTPUT
(FF)
BUFFERED OUTPUT
FLAGS
TIMING MODE FL RXI WXI
DIAGRAMS
Single Single Asynchronous 0 0 0 Figure 5, Figure 6
Single Single Synchronous 1 0 0 Figure 5, Figure 6
Double Double Asynchronous 0 1 0 Figure 20, Figure 22
Double Double Synchronous 1 1 0 Figure 20, Figure 22
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
REN, WEN, LD
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
tRS
tRSR
tRSS tRSR
Configuration Setting
tRSF
tRSF
tRSF
tRSF
tRSF
RS
FL, RXI, WXI
(see Note A)
RCLK, WCLK
(see Note B)
FF/IR
EF/OR
PAF,
WXO/HF, RXO
PAE
Q0–Q17
Standard Mode
FWFT Mode
FWFT Mode
Standard Mode
OE = 1
OE = 0
(see Note C)
NOTES: A. Single-device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC
or GND).
B. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
C. In FWFT mode, IR goes low based on the WCLK edge after reset.
D. After reset, the outputs are low if OE = 0 and 3-state if OE = 1.
(see Note D)
Figure 1. Reset Timing
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÏÏÏÏ
ÏÏÏÏ
ÌÌÌ
ÌÌÌ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÌÌ
ÌÌ
WCLK
tCLKH tCLKL
tCLK
tDH
tDS
Data
Invalid
tENH
tENS
D0–D17
WEN No Operation
tWFF tWFF
tSKEW1 (see Note A)
FF
RCLK
REN
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high during the current
clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, FF might not change
state until the next WCLK edge.
B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.
Figure 2. Write-Cycle Timing With Single Register-Buffered FF (Standard Mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÎÎÎÎÎ
ÎÎÎÎÎ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÌÌÌ
ÌÌÌ
ÌÌÌ
tCLK
tCLKH tCLKL
RCLK
tENH
tENS
No Operation
REN
tREF tREF
EF
tA
tOE
tOLZ tOHZ
tSKEW1
(see Note A)
Q0–D17
OE
WCLK
WEN
NOTES: A. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high during the current
clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, EF might not change
state until the next RCLK edge.
B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.
Figure 3. Read-Cycle Timing With Single Register-Buffered EF (Standard Mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tDS
D0 (First Valid Write) D1 D2 D3 D4
WCLK
D0–D17
WEN
tENS
tFRL
(see Note A)
tSKEW1
RCLK
tREF
tENS
tAtA
D0 D1
tOLZ
tOE
EF
REN
Q0–Q17
OE
NOTES: A. When tSKEW1 is at the minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 is less than the
minimum specification, tFRL (maximum) = either (2 ×tCLK) + tSKEW1 or tCLK + tSKEW1. The latency timing applies only at the
empty boundary (EF is low).
B. The first word always is available the cycle after EF goes high.
C. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.
Figure 4. First-Data-Word Latency with Single Register-Buffered EF (Standard Mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Data Write Data
Write
Data ReadData In Output Register Next Data Read
WCLK
D0–D17
FF
tDS
tSKEW1
(see Note A)
tWFF tWFF tWFF
tSKEW1
(see Note A) tDS
WEN
RCLK
tENS tENH tENS tENH
OE
REN
Low
tAtA
Q0–Q17
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high during the current
clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, FF might not change
state until the next WCLK edge.
B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
No Write
No Write
Figure 5. Single Register-Buffered Full-Flag Timing (Standard Mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÎÎÎ
ÎÎÎ
Data Write 1
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Data Write 2
ÌÌÌ
ÌÌÌ
Data ReadData In Output Register
WCLK
D0–D17
EF
WEN
RCLK
OE
REN
Q0–Q17
tDS tDS
tENS
tENH
tENS tENH
tSKEW1
tFRL
(see Note A) tFRL
(see Note A)
tSKEW1
tREF tREF tREF
Low
tA
NOTES: A. When tSKEW1 is at the minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 is less than the minimum
specification, tFRL (maximum) = either (2 × tCLK) + tSKEW1 or tCLK + tSKEW1. The latency timing applies only at the empty
boundary (EF is low).
B. Select standard mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during reset.
Figure 6. Single Register-Buffered Empty Flag Timing (Standard Mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
tCLKH tCLKL
tCLK
WCLK
WEN
tENS tENH
LD
tENS
tDS tDH
D0–D15
D0–D11
PAE Offset PAF Offset
PAE Offset
Figure 7. Write Programmable Registers (Standard and FWFT Modes)
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÏÏÏÏÏ
ÏÏÏÏÏ
tCLKH tCLKL
tCLK
RCLK
REN
tENS tENH
LD
tENS
tA
Q0–Q15 PAE Offset PAF Offset PAE Offset
Unknown
Figure 8. Read Programmable Registers (Standard Mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÏÏÏÏ
ÏÏÏÏ
WCLK
WEN
tCLKH tCLKL
tENH
tENS
tPAEA
n Words in FIFO
(see Note B)
n + 1 Words in FIFO
(see Note C) n + 1 Words in FIFO
(see Note B)
n + 2 Words in FIFO
(see Note C)
n Words in FIFO
(see Note B)
n + 1 Words in FIFO
(see Note C)
tPAEA
PAE
RCLK
tENS
REN
NOTES: A. n = PAE offset
B. For standard mode
C. For FWFT mode
D. PAE is asserted low on RCLK transition and reset to high on WCLK transition.
E. Select the asynchronous modes by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during reset.
Figure 9. Asynchronous Programmable Almost-Empty-Flag Timing (Standard and FWFT Modes)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌ
ÌÌÌ
ÏÏÏ
ÏÏÏ
WCLK
WEN
tCLKH tCLKL
tENH
tENS
tPAFA
D – (m + 1) Words in FIFO
(see Notes A and B) D – (m + 1) Words
in FIFO
tPAFA
PAF
RCLK
tENS
REN
D – m Words
in FIFO
NOTES: A. m = PAF offset
B. D = maximum FIFO depth
In FWFT mode: D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235 and 4097 for the SN74V245
In standard mode: D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235 and 4096 for the SN74V245
C. PAF is asserted to low on WCLK transition and reset to high on RCLK transition.
D. Select asynchronous modes by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during reset.
Figure 10. Asynchronous Programmable Almost-Full-Flag Timing (Standard and FWFT Modes)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÏÏÏÏ
ÏÏÏÏ
WCLK
WEN
tCLKH tCLKL
tENH
tENS
tHF
D/2 Words in FIFO,
(see Notes A and B)
tHF
HF
RCLK
tENS
REN
D – 1
2+ 1 Words in FIFO
(see Notes A and C)
D – 1
2+ 2 D/2 Words in FIFO,
(see Notes A and B)
D – 1
2+ 1
NOTES: A. D = maximum FIFO depth
In FWFT mode: D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235 and 4097 for the SN74V245
In standard mode: D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235 and 4096 for the SN74V245
B. For standard mode
C. For FWFT mode
D. Select single-device mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset.
D/2+1 Words in FIFO,
(see Notes A and B)
Words in FIFO
(see Notes A
and C)
Words in FIFO
(see Notes A
and C)
Figure 11. Half-Full-Flag Timing (Standard and FWFT Modes)
ÌÌÌ
ÌÌÌ
ÏÏÏ
ÏÏÏ
tCLKH
tXO
See
Note A
tENS
WCLK
WEN
WXO
NOTE A: Write to last physical location.
Figure 12. Write-Expansion-Out Timing
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌ
ÌÌÌÌ
ÏÏÏÏ
ÏÏÏÏ
tCLKH
tXO
See
Note A
tENS
RCLK
REN
RXO
NOTE A: Read from last physical location.
Figure 13. Read-Expansion-Out Timing
tXIS
tXI
WCLK
WXI
Figure 14. Write-Expansion-In Timing
tXIS
tXI
RCLK
RXI
Figure 15. Read-Expansion-In Timing
SN74V215, SN74V225, SN74V235, SN74V245
512 18, 1024 18, 2048 18, 4096 18××× ×
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E -– APRIL 2000 -– REVISED SEPTEMBER 2002
TM
24 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
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ÎÎÎ
1 1
WCLK
D0–D17
tENS
WEN
tDH
tDS tDS
tDS tDS tENH
W1 W2 W3 W4 W[n+2] W[n+3] W[n+4] D – 1+ 1
W2D – 1+ 2
W2D – 1+ 3
W2W[D-m-2] W[D-m-1] W[D-m] W[D-m+1] W[D-m+2] W[D] W[D+1]
tSKEW1
RCLK
REN
Q0–Q17
12 3
tA
Data in Output Register W1
tREF
OR
tSKEW2 (see Note B)
tPAES
PAE
tHF
HF
tPAFS
PAF
tWFF
IR
NOTES: A. t SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go low after two RCLK cycles plus tREF . If the time between the rising
edge of WLCK and the rising edge of RCLK is less than t SKEW1, the OR deassertion might be delayed one extra RCLK cycle.
B. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for P AE to go high during the current clock cycle. If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW2, the PAE deassertion might be delayed one extra RCLK cycle.
C. LD is high, OE is low.
D. n = PAE offset, m = PAF offset, D = maximum FIFO depth = 513 words for the SN74V215, 1025 words for the SN74V225, 2049 words for the SN74V235, and 4097 words
for the SN74V245.
E. Select synchronous FWFT mode by setting ( FL , RXI , WXI ) = (1,0,1) during reset.
Figure 16. Write Timing With Synchronous Programmable Flags (FWFT Mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 18, 1024 18, 2048 18, 4096 18××××
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E -– APRIL 2000 -– REVISED SEPTEMBER 2002
TM
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•25
WCLK
ÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
WD
tENH
tENS
WEN
tSKEW1
(see Note A)
12
tSKEW2
(see Note B)
tDH
tDS
D0–D17
RCLK
tENS tENS
REN
OE
tOE
tOHZ tA
tAtAtA
tAtA
tREF
Q0–Q17
tPAES
tHF
tPAFS
tWFF
tWFF
OR
PAE
HF
PAF
IR
W1 W1 W2 W3 W[m+3]Wm+2 W[m+4] D – 1+ 1
W2D – 1+ 2
W2W[D-n-1] W[D-n] W[D-n+1] W[D-n+2] W[D-1] WD
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that IR goes low after one WCLK plus tWFF. If the time between the rising
edge of RLCK and the rising edge of WCLK is less than tSKEW1, the IR assertion might be delayed an extra WCLK cycle.
B. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for P AF to go high during the current clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW2, the PAF deassertion time may be delayed an extra WCLK cycle.
C. LD is high.
D. n = P AE of fset, m = P AF offset, D = maximum FIFO depth = 513 words for the SN74V215, 1025 words for the SN74V225, 2049 words for SN74V235, and 4097 words
for SN74V245.
E. Select synchronous FWFT mode by setting ( FL , RXI , WXI ) = (1,0,1) during reset.
Figure 17. Read Timing With Synchronous Programmable Flags (FWFT Mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÎÎÎÎ
ÎÎÎÎ
ÏÏÏ
ÏÏÏ
ÎÎ
ÏÏÏ
WCLK
WEN
tCLKH tCLKL
tENH
tENS
PAE
n Words in FIFO,
(see Note B)
n + 1 Words in FIFO
(see Note C) n + 1 Words in FIFO,
(see Note B)
n + 2 Words in FIFO
(see Note C)
n Words in FIFO
(see Note B),
n + 1 Words in FIFO
(see Note C)
tPAES
(see Note C)
tSKEW2
(see Note D)
tPAES
RCLK
REN
tENH
tENS
NOTES: A. n = PAE offset
B. For standard mode
C. For FWFT mode
D. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go high during the current clock cycle.
If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, the PAE deassertion might be delayed
one extra RCLK cycle.
E. PAE is asserted and updated on the rising edge of RCLK only.
F. Select synchronous modes by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during reset.
Figure 18. Synchronous Programmable Almost-Empty-Flag Timing (Standard and FWFT Modes)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÎÎÎÎ
ÎÎÎÎ
ÏÏÏ
ÏÏÏ
ÎÎ
ÎÎ
ÏÏÏ
ÏÏÏ
WCLK
WEN
tCLKH tCLKL
tENH
tENS
PAF
tPAFS
RCLK
REN
tENH
tENS
tPAFS
D – (m + 1) Words in FIFO D – m Words in FIFO D – (m + 1) Words
in FIFO
tSKEW2
(see Note C)
N
OTES: A. m = PAF offset
B. D = maximum FIFO depth
In FWFT mode: D = 513 for the SN74V215, 1025 for the SN74V225, 2049 for the SN74V235, and 4097 for the SN74V245.
In standard mode: D = 512 for the SN74V215, 1024 for the SN74V225, 2048 for the SN74V235, and 4096 for the SN74V245.
C. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go high during the current clock cycle.
If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, the PAF deassertion time might
be delayed an extra WCLK cycle.
D. PAF is asserted and updated on the rising edge of WCLK only.
E. Select synchronous modes by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during reset.
Figure 19. Synchronous Programmable Almost-Full-Flag Timing (Standard and FWFT Modes)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
WCLK
WEN
tSKEW1
(see Note A) tDS tSKEW1
(see Note A) tDS
12 1 2
WdD0–D17
tWFF tWFF tWFF
Data Write
FF
RCLK
tENS tENH tENS tENH
OE Low
tAtA
Data in Output Register Data Read Next Data Read
REN
Q0–Q17
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high after one WCLK
cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, the FF deassertion
time might be delayed an extra WCLK cycle.
B. LD is high.
C. Select double register-buf fered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.
No
Write No
Write
Figure 20. Double Register-Buffered Full-Flag Timing (Standard Mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
ÎÎÎ
ÎÎÎ
ÏÏÏ
ÏÏÏ
ÎÎ
ÎÎ
WCLK
WEN
D0–D17
tCLK
tCLKH tCLKL
tDS tDH
Data in
Valid
tENS tENH
tWFF
tWFF
No Operation
FF
tSKEW1
(see Note A)
RCLK
REN
NOTES: A. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high after one WCLK
cycle plus tRFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, the FF deassertion
might be delayed an extra WCLK cycle.
B. LD is high.
C. Select double register-buf fered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.
Figure 21. Write-Cycle Timing With Double Register-Buffered FF (Standard Mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
RCLK
WEN
Q0–Q17
ÏÏÏ
ÏÏÏ
ÎÎÎÎ
ÎÎÎÎ
ÌÌÌÌ
ÌÌÌÌ
tCLK
tCLKH tCLKL
tENS tENH
REN No Operation
tREF tREF
EF
tA
tOLZ tOE tOHZ
tSKEW1
(see Note A)
tENS
tENH
WCLK
OE
Last Word
tDH
tDS
First WordD0–D17
NOTES: A. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high after one RCLK
cycle plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, the EF deassertion
might be delayed an extra RCLK cycle.
B. LD is high.
C. Select double register-buf fered standard mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during reset.
Figure 22. Read-Cycle Timing With Double Register-Buffered EF (Standard Timing)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÌÌÌ
ÌÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
Ì
Ì
ÌÌ
ÌÌ
ÌÌ
ÌÌ
WCLK
WEN
tENS tENH
tDS tDH
D0–D17
tDS
W1 W2 W3 W4
tSKEW1
(see Note A)
12 3
RCLK
REN
tA
Q0–Q17
tREF tREF
OR
W[n+2] W[n+3]
NOTES: A. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go high during the current cycle. If
the time between the rising edge of WLCK and the rising edge of RCLK is less than tSKEW1, the OR deassertion might be delayed
one extra RCLK cycle.
B. LD is high, OE is low.
C. Select FWFT mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during reset.
Data In Output Register W1
ÌÌ
ÌÌ
Figure 23. OR-Flag Timing and First Word Fall Through When FIFO is Empty (FWFT mode)
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating configurations
SINGLE-DEVICE CONFIGURATION
A single SN74V215, SN74V225, SN74V235, or SN74V245 can be used when the application requirements are
for 512/1024/2048/4096 words or fewer, respectively. These FIFOs are in a single-device configuration when
the first load (FL), write expansion in (WXI) and read expansion in (RXI) control inputs are configured as
(FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (see Figure 24).
Half-Full Flag (HF)
Programmable (PAE)
Full Flag/Input Ready (FF/IR)
Data In (D0–D17)
Load (LD)
Write Enable (WEN)
Write Clock (WCLK) Read Clock (RCLK)
Read Enable (REN)
Output Enable (OE)
Data Out (Q0–Q17)
Empty Flag/Output Ready (EF/OR)
Programmable (PAF)
Reset (RS)
FL RXI WXI
74V215
74V225
74V235
74V245
Figure 24. Block Diagram of Single 512 × 18, 1024 × 18, 2048 × 18, or 4096 × 18 Synchronous FIFO
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating configurations (continued)
WIDTH-EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control signals of multiple devices. Status flags
can be detected from any one device. The exceptions are the empty flag/output ready and full flag/input ready .
Because of variations in skew between RCLK and WCLK, it is possible for flag assertion and deassertion to vary
by one cycle between FIFOs. To avoid problems, the user must create composite flags by gating the empty
flags/output ready of every FIFO, and separately gating all full flags/input ready. Figure 25 demonstrates a
36-word width by using two SN74V215, SN74V225, SN74V235, or SN74V245 memories. Any word width can
be attained by adding additional SN74V215, SN74V225, SN74V235, or SN74V245 memories. These FIFOs
are in a single-device configuration when the first load (FL), write expansion in (WXI), and read expansion in
(RXI) control inputs are configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during
reset (see Figure 25).
WXI WXI
Half-Full Flag (HF)
Programmable (PAE)
Full Flag/
Input Ready
(FF/IR)
Data In (D)
Load (LD)
Write Enable (WEN)
Write Clock (WCLK) Read Clock (RCLK)
Read Enable (REN)
Output Enable (OE)
Data Out (Q)
Empty Flag/
Output Ready
(EF/OR)
Programmable (PAF)
Reset (RS)
74V215
74V225
74V235
74V245
Reset (RS)
FL RXI
FF/IR EF/OR
FL RXI
FF/IR EF/OR
74V215
74V225
74V235
74V245
36 18
18 18
18
36
NOTE A: Do not connect any output control signals directly together.
Figure 25. Block Diagram of 512 × 36, 1024 × 36, 2048 × 36, or 4096 × 36
Synchronous FIFO Memory Used in a Width-Expansion Configuration
DEPTH-EXPANSION CONFIGURATION, DAISY-CHAIN TECHNIQUE (WITH PROGRAMMABLE FLAGS)
These devices can be adapted easily to applications requiring more than 512, 1024, 2048, or 4096 words of
buffering. Figure 26 shows depth expansion using three SN74V215, SN74V225, SN74V235, or SN74V245
memories. Maximum depth is limited only by signal loading.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RCLK
REN
OE
Qn
EF/OR
PAE
RCLK
REN
OE
Qn
EF/OR
PAE
RCLK
REN
OE
Qn
EF/OR
PAE
WXO RXO
WXI RXI
WXO RXO
WXI RXI
WXO RXO
WXI RXI
WCLK
WEN
RS
LD
Dn
FL
FF/IR
PAF
WCLK
WEN
RS
LD
Dn
FL
FF/IR
PAF
WCLK
WEN
RS
LD
Dn
FF/IR
PAF
VCC
VCC
Data In
Write Clock Read Clock
Read Enable
Output Enable
Write Enable
Data Out
Reset
Load
FF/IR
PAF
First Load (FL)
PAE
EF/OR
74V215
74V225
74V235
74V245
74V215
74V225
74V235
74V245
74V215
74V225
74V235
74V245
NOTES: A. The first device must be designated by grounding the first load (FL) control input.
B. All other devices must have FL in the high state.
C. The write expansion out (WXO) pin of each device must be tied to the write expansion in (WXI) pin of the next device.
D. The read expansion out (RXO) pin of each device must be tied to the read expansion in (RXI) pin of the next device.
E. All load (LD) pins are tied together.
F. The half-full flag (HF) is not available in this depth-expansion configuration.
G. EF, FF, PAE, and PAF are created with composite flags by ORing together every respective flag for monitoring. The composite
PAE and PAF flags are not precise.
H. In daisy-chain mode, the flag outputs are single-register buffered and the partial flags are in asynchronous timing mode.
Figure 26. Block Diagram of 1536 × 18, 3072 × 18, 6144 × 18, 12288 × 18
Synchronous FIFO Memory With Programmable Flags Used in Depth-Expansion Configuration
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating configurations (continued)
DEPTH-EXPANSION CONFIGURATION (FWFT MODE)
In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs
of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. NO TAG shows a depth expansion using two
SN74V215, SN74V225, SN74V235, or SN74V245 memories.
Care should be taken to select FWFT mode during master reset for all FIFOs in the depth expansion
configuration. The first word written to an empty configuration passes from one FIFO to the next (ripple down)
until it finally appears at the outputs of the last FIFO in the chain. No read operation is necessary , but the RCLK
of each FIFO must be free running. Each time the data word appears at the outputs of one FIFO, that device’s
OR line goes low, enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go low
(i.e., valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the sum
of the delays for each individual FIFO:
(N – 1) ×(4 ×transfer clock) + 3 ×TRCLK
Where: N is the number of FIFOs in the expansion and TRCLK is the RCLK period. Extra cycles should be added
for the possibility that the tSKEW1 specification is not met between WCLK and transfer clock, or RCLK and
transfer clock, for the OR flag.
The ripple-down delay is noticeable only for the first word written to an empty depth-expansion configuration.
There is no delay evident for subsequent words written to the configuration.
The first free location created by reading from a full depth-expansion configuration bubbles up from the last FIFO
to the previous one until finally it moves into the first FIFO of the chain. Each time a free location is created in
one FIFO of the chain, that FIFO’s IR line goes low, enabling the preceding FIFO to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go low after
a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
(N – 1) ×(3 ×transfer clock) + 2TWCLK
Where: N is the number of FIFOs in the expansion and TWCLK is the WCLK period. Extra cycles should be added
for the possibility that the tSKEW1 specification is not met between RCLK and transfer clock, or WCLK and
transfer clock, for the IR flag.
The transfer clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result
in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
REN
Data In
Write Enable
Write Clock
74V215
74V225
74V235
74V245
74V215
74V225
74V235
74V245
(0,1)
GND
VCC (0,1)
GND
VCC
WXI
RXIFL WXIRXIFL
HF
PAF Transfer Clock
WCLK
WEN
IR
Dn
RCLK
OR
REN
OE
Qn
WCLK
WEN
IR
Dn
RCLK
OR
OE
Qn
HF
PAE
Read Clock
Read Enable
Input Ready Output Ready
Output Enable
Data Out
GND
nnn
Figure 27. Block Diagram of 1024 × 18, 2048 × 18, 4096 × 18, 8192 × 18
Synchronous FIFO Memory With Programmable Flags Used in Depth-Expansion Configuration
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
MIN TYP MAX UNIT
VCC Supply voltage 3.0 3.3 3.6 V
GND Supply voltage 0 0 0 V
VIH High-level input voltage 2 5 V
VIL Low-level input voltage 0.8 V
TAOperating free-air temperature 0 70 °C
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH VCC = 3.0 V, IOH = –2 mA 2.4 V
VOL VCC = 3.0 V, IOL = 8 mA 0.4 V
IIVCC = 3.6 V, VI = VCC to 0.4 V ±1µA
IOZ VCC = 3.6 V, OE ≥ VIH, VO = VCC to 0.4 V ±10 µA
ICC1 VCC = 3.3 V, See Notes 1, 2, and 3 35 mA
ICC2 VCC = 3.6 V, See Notes 1 and 4 5 mA
CIN VI = 0, TA = 25°C, f = 1 MHz 10 pF
COUT VO = 0, TA = 25°C, f = 1 MHz, Output deselected, (OE ≥ VIH) 10 pF
NOTES: 1. Tested with outputs disabled (IOUT = 0)
2. RCLK and WCLK switch at 20 MHz and data inputs switch at 10 MHz.
3. Typical ICC1 = 2.04 + 0.88 ×fS + 0.02 ×CL ×fS (in mA). These equations are valid under the following conditions:
VCC = 3.3 V , T A = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive
load (in pF).
4. All inputs = (VCC – 0.2 V) or (GND + 0.2 V), except RCLK and WCLK, which switch at 20 MHz.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figure 28 through Figure 23)
’74V215-7
’74V225-7
’74V235-7
’74V245-7
’74V215-10
’74V225-10
’74V235-10
’74V245-10
’74V215-15
’74V225-15
’74V235-15
’74V245-15
’74V215-20
’74V225-20
’74V235-20
’74V245-20 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock cycle frequency 133 100 66.7 50 MHz
tAData access time 2 5 2 6.5 2 10 2 12 ns
tCLK Clock cycle time 7.5 10 15 20 ns
tCLKH Clock high time 3.5 4.5 6 8 ns
tCLKL Clock low time 3.5 4.5 6 8 ns
tDS Data setup time 2.5 3 4 5 ns
tDH Data hold time 0.5 0.5 1 1 ns
tENS Enable setup time 2.5 3 4 5 ns
tENH Enable hold time 0.5 0.5 1 1 ns
tLDS Load setup time 3.5 3.5 4 4 ns
tLDH Load hold time 0.5 0.5 1 1 ns
tRS Reset pulse width†10 10 15 20 ns
tRSS Reset setup time 8 8 10 12 ns
tRSR Reset recovery time 8 8 10 12 ns
tRSF Reset to flag and output time 15 15 15 20 ns
tOLZ Output enable to output in low Z 0 0 0 0 ns
tOE Output enable to output valid 6 6 3 8 3 10 ns
tOHZ Output enable to output in high Z 1 6 1 6 3 8 3 10 ns
tWFF Write clock to Full flag 5 6.5 10 12 ns
tREF Read clock to Empty flag 5 6.5 10 12 ns
tPAFA Clock to asynchronous programmable
Almost-Full flag 12.5 17 20 22 ns
tPAFS Write clock to synchronous programmable
Almost-Full flag 5 8 10 12 ns
tPAEA Clock to asynchronous programmable
Almost-Empty flag 12.5 17 20 22 ns
tPAES Read clock to synchronous programmable
Almost-Empty flag 5 8 10 12 ns
tHF Clock to Half-Full flag 12.5 17 20 22 ns
tXO Clock to expansion out 5 6.5 10 12 ns
tXI Expansion in pulse duration 2.5 3 6.5 8 ns
tXIS Expansion in setup time 2.5 3 5 8 ns
tSKEW1 Skew time between read clock and write clock for
FF/IR and EF/OR 5 5 6 8 ns
tSKEW2 Skew time between read clock and write clock for
PAE and PAF (synchronous only) 7 14 18 20 ns
†Pulse durations less than minimum values are not allowed.
SN74V215, SN74V225, SN74V235, SN74V245
512 × 18, 1024 × 18, 2048 × 18, 4096 × 18
DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
(see Note A)
510 Ω
330 Ω
3.3 V
NOTE A: Includes probe and jig capacitance
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load for tCLK = 10 ns, 15 ns
Output Load for tCLK = 7.5 ns
GND to 3.0 V
3 ns
1.5 V
1.5 V
See A
See B and C
AC TEST CONDITIONS
50 Ω
VCC/2
ZO = 50 Ω
I/O
B. AC TEST LOAD FOR 7.5 SPEED GRADE
A. OUTPUT LOAD CIRCUIT
FOR 10, 15, AND 20 SPEED GRADES
0
1
2
3
4
5
6
0 20 40 60 80 100 120 140 160 180 200
C. LUMPED CAPACITIVE LOAD, TYPICAL DERATING
Capacitance – pF
Typical –t∆CD – ns
Figure 28. Load Circuits
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CV215-10PAGG4 ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
CV235-7PAGG4 ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
CV245-10PAGG4 ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
CV245-7PAGG4 ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V215-10PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V215-15PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V215-20PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V215-7PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V225-10PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V225-15PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V225-20PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V225-7PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V235-10PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V235-15PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V235-20PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V235-7PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V245-10PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V245-15PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V245-20PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
SN74V245-7PAG ACTIVE TQFP PAG 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74V245 :
•Enhanced Product: SN74V245-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
4040282/C 11/96
Gage Plane
33
0,17
0,27
16
48
1
7,50 TYP
49
64
SQ
9,80
1,05
0,95
11,80
12,20
1,20 MAX
10,20 SQ
17
32
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
IMPORTANT NOTICE
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