Features * 32-bit RISC Architecture * Two Instruction Sets: ARM High-performance 32-bit Instruction Set Thumb High-code-density 16-bit Instruction Set * Very Low Power Consumption: Industry-leader in MIPS/Watt * 4G Bytes Linear Address Space * Von Neumann Load/Store Architecture: Single 32-bit Data Bus for Instructions and Data * 3-Stage Pipeline Architecture: Fetch, Decode and Execute Stage * 8-, 16-, and 32-bit Data Types * Single Cycle 32x8 Hardware Multiplier: Multiplication is Accelerated when Upper Bytes Are All Zero or One * On-chip JTAG Debug and In Circuit Emulation Description The ARM7TDMI embedded microcontroller core is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance and very lower power consumption. Its outstanding feature is the 16-bit Thumb subset of the most commonly 32-bit instructions. These are expanded at run time with no less of system performance. This gives 16-bit code density (saving memory area and cost) coupled with 32-bit processor performance. The ARM architecture is based on Reduced Instruction Set Computer (RISC) princi- ples, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard dynamic RAMs. The ARM memory interface is also ideally suited to interfacing, either on-chip or off- chip, with Atmels Flash memory blocks. These give the benefits of in-system pro- grammability and security, reducing time-to-market and system cost. ey () Embedded RISC Microcontroller Core ARM7TDMI Rev. 0673BS03/99 Note: This is a summary document. For the complete 204 page A MEL document, please visit our Website at www.atmel.com or e-mail at literature@atmel.com and request literature #0673B. ayARM7TDMI Input/Output Signals Figure 1. ARM7TDMI Input/Output Signals Clocks Interrupts Bus Controls Power Debug a NGS \ NC ANIME MCLK nWAIT ECLK Sl niIRQ@ > nFIQ $> ISYNC nRESET BUSEN HIGHZ BIGEND nENIN nENOUT nENOUTI BUSDIS ECAPCLK VDD oP VSS P DBGRQ > BREAKPT DBGACK nEXEC EXTERN 14 EXTERN 0 DBGEN RANGEOUTO RANGEOUT1 DBGRQI! COMMRX COMMTX ARM7TDMI ' TCK TMS TDI nTRST TDO TAPSM[3:0] IR[3:0] nT DOEN TCK1 TCK2 SCREG[3:0] mn nM[4:0] TBIT ul A[31:0] DOUT[31:0] DIN[31:0] ety nMREQ SEQ nRW MAST[1:0] BL[3:0 LOCK nTRANS ABORT nOPC nCPI CPA CPB i LUX Boundary Scan Boundary Scan Control Signals Processor Mode Processor State Memory Interface Memory Management Interface Coprocessor InterfaceARM7TDMI Block Diagram Figure 2. ARM7TDMI Block Diagram Scan Chain 0 Scan Chain 2 RANGEOUTO RANGEOUT1 EXTERN1 EXTERNO nOPC nRW MAS[1:0] nTRANS nMREQ A[31:0] ICEBreaker All Other Signals Scan Chain 1 D[31:0] DIN[31:0] Bus Splitter DOUT[31:0] TAP controller TDO TAPSM[3:0] IR[3:0] SCREG[3:0] TCK TMS nTRST TDI data bus D[31:0] is split into uni-directional input and output buses for compatibility with a wide range of external memories. As shown in Figure 1 and Figure 2, the ARM7TDMI con- sists of a processor, a TAP controller for boundary scan, and an in-circuit emulator (ICEBreaker). The bi-directional AIMELANIME ARM7TDMI Processor Figure 3. ARM7TDMI Processor 32-Bit Address Bus Address Register Address Incrementer ARM Instruction Decoder Contral Logic I Instruction Increment Bus 3/ 32-Bit: Registers {including 6 status registers). 32x38 Multiplier g we a Barrel a 3 Shifter | a aE * Instruction 32-Bit ALU Decompressor Write Data Register Pipeline | 32-Bit Data Bus The ARM7TDMI processor is built around a bank of 37 32- bit registers and 6 status registers. It features an integral 32x8 multiplier and 32-bit barrel shifter. Five independent internal buses (the PC Bus, the Increment Bus, the ALU Bus and the A- and B-Buses) allow a high degree of paral- lelism in instruction execution. Operating Modes ARM7TDMI supports seven modes of operation: * User (usr): The normal ARM program execution state * FIQ (fig): Designed to support a data transfer or channel process * IRQ (irq): Used for general-purpose interrupt handling * Supervisor (svc): Protected mode for the operating system * Abort mode (abt): Entered after a data or instruction prefetch abort * System (sys): A privileged user mode for the operating system * Undefined (und): Entered when an undefined instruction is executed Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs will execute in User mode. The non-user modes - known as privileged modes - are entered in order to service interrupts or exceptions, or to access protected resources. Each operating mode has dedicated banked registers for fast exception handling. The FIQ mode has 5 additional banked working registers, r8_fiq to r12_fig, to enhance interrupt processing speed.Registers ARM7TDMI has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannot all be seen at once. The processor state and operating mode dictate which registers are available to the program- mer. Figure 4. Register Organization in ARM State The ARM State Register Set In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (non- User) modes, mode-specific banked registers are switched in. Figure 4 shows which registers are available in each mode: the banked registers are marked with a shaded tri- angle. The ARM state register set contains 16 directly accessible registers: RO to R15. All of these except R15 are general- purpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register used to store status information. ARM State General Registers and Program Counter System & User FIQ Supervisor Abort IRQ Undefined RO R1 R2 R3 R4 R5 R6 R7 R8& Rg R10 R14 R12 R13 R14 RO R1 R2 R3 R4 R5 R6 R7 RO R1 R2 R3 R4 R5 R6 R7 R8 RQ R10 R14 Ri2 R13 sve R14 sve R15 (PC) RO A R2 R3 R4 R5 R6 R7 R8& Rg R11 R12 R13_abt R14_abt R15 (PC) RO Ri R2 R3 R4 R5 R6 R7 R8 Rg R11 R12 R13_irq R14_irq R15 (PC) ARM State Program Status Registers RO R1 R2 R3 R4 R5 R6 R7 R8& Rg CPSR CPSR CPSR CPSR CPSR CPSR SPSR_fiq SPSR_sve SPSR_abt SPSR_irq , = banked register AIMELANIME The THUMB State Register Set The THUMB state register set is a subset of the ARM state CPSR. There are banked Stack Pointers, Link Registers set. The programmer has direct access to eight general and Saved Process Status Registers (SPSRs) for each registers, RO-R7, as well as the Program Counter (PC), a privileged mode. stack pointer register (SP), a link register (LR), and the Figure 5. Register Organization in Thumb State THUMB State General Registers and Program Counter System & User FIQ Supervisor Abort IRQ Undefined Ro Ro Ro Ro Ro Ro R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R38 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 sP LR PC THUMB State Program Status Registers CPSR CPSR CPSR CPSR SPSR_fiq SPSR_abt SPSR_irq = banked registerARM7TDMI Architecture The ARM7TDMI is a 3-stage pipeline, 32-bit RISC proces- sor. The processor architecture is Von Neumann load/store architecture, which is characterized by a single data and address bus for instructions and data. The CPU has two instruction sets, the ARM and the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and provides maximum performance. Thumb instructions are 16-bits wide and give maximum code-density. Instructions operate on 8-, 16-, and 32-bit data types. The THUMB Concept The ARM7TDMI processor employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or appli- cations where code density is an issue. The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI processor has two instruction sets: * the standard 32-bit ARM set * a 16-bit THUMB set The THUMB sets 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARMs performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32- bit register set as ARM code. THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system. THUMBs Advantages THUMB instructions operate with the standard ARM regis- ter configuration, allowing excellent interoperability between ARM and THUMB states. Each 16-bit THUMB Figure 6. Flexible Selection of ARM or Thumb Instruction Set Phase 1 instruction has a corresponding 32-bit ARM instruction with the same effect on the processor model. The major advantage of a 32-bit (ARM) architecture over a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions, and to address a large address space efficiently. When processing 32-bit data, a 16-bit architecture will take at least two instructions to perform the same task as a single ARM instruction. However, not all the code in a program will process 32-bit data (for example, code that performs character string han- dling), and some instructions, like Branches, do not process any data at all. If a 16-bit architecture only has 16-bit instructions, and a 32-bit architecture only has 32-bit instructions, then overall the 16-bit architecture will have better code density, and better than one half the performance of the 32-bit architec- ture. Clearly 32-bit performance comes at the cost of code density. THUMB breaks this constraint by implementing a 16-bit instruction length on a 32-bit architecture, making the pro- cessing of 32-bit data efficient with a compact instruction coding. This provides far better performance than a 16-bit architecture, with better code density than a 32-bit architecture. THUMB also has a major advantage over other 32-bit architectures with 16-bit instructions. This is the ability to switch back to full ARM code and execute at full speed. Thus critical loops for applications such as * fast interrupts * DSP algorithms can be coded using the full ARM instruction set, and linked with THUMB code. The overhead of switching from THUMB code to ARM code is folded into sub-routine entry time. Various portions of a system can be optimized for speed or for code density by switching between THUMB and ARM execution as appropriate. Phase 2 Thumb State AIMEL 7ANIME Software Development Toolkit The ARM7TDMI has a complete software development Supported platforms: environment including: * IBM PC, 486 or above, having, at a minimum, 16M bytes * ARM and Thumb C compilers RAM, 18M bytes hard disc space running: * ARM and Thumb Assemblers Windows 95 + Linker Windows NT (Intel x86) * Symbolic debugger with ARM and Thumb instruction set Windows 3.1 or 3.11 emulation * Sun/SPARC running SunOS v4.1.3_u1 * Object file librarian * HP running HP-UX v9.03 * C run-time library kernel (includes FP library) The Toolkit is distriouted on CD-ROM media. The Windows * ANSI X3UII C library platform Toolkit features a graphical user interface. * Several utilities Sun/SPARC and HP platforms are based on a command line interface. Figure 7. Windows User Interface of the ARM Software Development Kit Polat iis te slot me Re ate a subeq .vl0.rl,asr andeq rQ.,rl,lsl #6 adegt 275, #0235 streq _[rd,-r0] andeq .T0,r0.lsl #14 andeq .ro,4rd0 subpl vl. #0 stmyeda 5 .f{r0.r2.r3,r6.r13} ldrvebt r6,[r5].#-0"365 strveb r6,[rl2,#-0x261]! hSrvs eper_ cef.r0.lser #18 andeq r6,r0,r?.ror #10 ldmvedb r5! f{r0.r2.rg.r5.r7, Nerves: cpsr_,rl2.,ror #8 ; ? strvst ro, [r0)], #-Ondbe ldrveh r6,[r5,-r5.ror #4]! rebos rh.rld 20. ler te . Tracer, 46B, Dummy MMU. Soft Angel 1.4 [Angel SWIs]. FPE. Profiler. Pagetables, Little endian.Hardware Development Toolkit A number of development boards are available from ARM, Atmel, and third parties. These platforms allow an application developer to prototype hardware and software working together in near real-time. AEB-1 Evaluation Board (ARM) FCM Development Board * ARM7TDMI processor core (Europe Technology / Atmel) * 256K byte Flash memory * ARM7TDMI device * 128K byte SRAM * 2 ASICs with peripherals: * 4 programmable output LEDs and a power-on LED (USART, SPIO, PIO, TIMER, SPI, AD/DA Converters...) * 9-pin D-Sub serial connector * 2 large Xilinx FPGAs (100K gates or more) ATO! Development Board (Atmel) Reset switch and Interrupt switches FCC and CE EMC Class A compliant JTAG socket 24 MHz clock HSDT100 Development Board (SIDSA) * ARM7TDMI device * 2 SRAM devices (256K byte - 15nsec access time) * 1 FLASH device (1M byte - 120 nsec access time) * 1 ALTERA EPLD (decoding and bus management) AT91M40400-DEV microcontroller * 2 ALTERA FPGAs for hardware prototyping: EPF10K50 and EPF10K100, with logic capacities ranging from Sata storage and 4M-bit Flash memory for program and 50000 to 100000 equivalent gates, and memory from 12K to 32K bits. 32K byte 8-bit boot EPROM 2 serial ports, one for host debugger communication 32 MHz master clock oscillator, with 16 MHz, 8 MHz and 4 MHz options All microcontroller signals are available on monitor points LEDs connected to I/O pins Reset and interrupt buttons 3.3V operation, 5V for Flash, battery and external power connector Angel debug monitor firmware AIMEL ANMEL ey Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686677 FAX (44) 1276-686697 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon, Hong Kong TEL (852) 27219778 FAX (852) 27221369 Japan Atmel Japan K.K. Tonetsu Shinkawa Bldg., 9F 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Min. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4 42 53 60 00 FAX (33) 4 42 53 60 01 Atmel Corporation 1999. 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