DSPIC30F6014A-30I/PT - Microchip Technology, Inc.

dsPIC30F6011A/6012A/6013A/6014A

Data Sheet

High-Performance, 16-bit

Digital Signal Controllers

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PRO MATE, rfPIC and SmartShunt are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

dsPIC30F6011A/6012A/6013A/6014A

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set architecture

• Flexible addressing modes

• 83 base instructions

• 24-bit wide instructions, 16-bit wide data path

• Up to 144 Kbytes on-chip Flash program space

• Up to 48K instruction words

• Up to 8 Kbytes of on-chip data RAM

• Up to 4 Kbytes of nonvolatile data EEPROM

• 16 x 16-bit working register array

• Up to 30 MIPS operation:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with PLL

active (4x, 8x, 16x)

• Up to 41 interrupt sources:

- 8 user-selectable priority levels

- 5 external interrupt sources

- 4 processor traps

DSP Features:

• Dual data fetch

• Modulo and Bit-Reversed modes

• Two 40-bit wide accumulators with optional

saturation logic

• 17-bit x 17-bit single-cycle hardware fractional/

integer multiplier

• All DSP instructions are single cycle:

- Multiply-Accumulate (MAC) operation

• Single-cycle ±16 shift

Peripheral Features:

• High-current sink/source I/O pins: 25 mA/25 mA

• Five 16-bit timers/counters; optionally pair up

16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

• 16-bit Compare/PWM output functions:

• Data Converter Interface (DCI) supports common

audio Codec protocols, including I2S and AC’97

• 3-wire SPI modules (supports 4 Frame modes)

•I

2C™ module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• Two addressable UART modules with FIFO

buffers

• Two CAN bus modules compliant with CAN 2.0B

standard

Analog Features:

• 12-bit Analog-to-Digital Converter (ADC) with:

- 200 Ksps conversion rate

- Up to 16 input channels

- Conversion available during Sleep and Idle

• Programmable Low-Voltage Detection (PLVD)

• Programmable Brown-out Reset

Special Microcontroller Features:

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for

industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/write cycle (min.) for

industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip

low-power RC oscillator for reliable operation

• Fail-Safe Clock Monitor operation:

- Detects clock failure and switches to on-chip

low-power RC oscillator

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157).

High-Performance, 16-bit Digital Signal Controllers

dsPIC30F6011A/6012A/6013A/6014A

CMOS Technology:

• Low-power, high-speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption

dsPIC30F6011A/6012A/6013A/6014A Controller Families

Device Pins

Program Memory SRAM

Bytes

EEPROM

Bytes

Timer

16-bit

Input

Cap

Output

Comp/Std

PWM

Codec

Interface

ADC

12-bit

100 Ksps

UART

SPI

I2C™

CAN

Bytes Instructions

dsPIC30F6011A 64 132K 44K 6144 2048 5 8 8 — 16 ch 2 2 1 2

dsPIC30F6012A 64 144K 48K 8192 4096 5 8 8 AC’97, I2S16 ch 2212

dsPIC30F6013A 80 132K 44K 6144 2048 5 8 8 — 16 ch 2 2 1 2

dsPIC30F6014A 80 144K 48K 8192 4096 5 8 8 AC’97, I2S16 ch 2212

dsPIC30F6011A/6012A/6013A/6014A

Pin Diagrams

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

13 36

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/T4CK/CN1/RC13

EMUC2/OC1/RD0

IC4/INT4/RD11

IC2/INT2/RD9

IC1/INT1/RD8

VSS

OSC2/CLKO/RC15

OSC1/CLKI

VDD

SCL/RG2

EMUC3/SCK1/INT0/RF6

U1RX/SDI1/RF2

EMUD3/U1TX/SDO1/RF3

RG15

T2CK/RC1

T3CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS

VDD

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

AN1/VREF-/CN3/RB1

AN0/VREF+/CN2/RB0

OC8/CN16/RD7

RG13

RG12

RG14

VSS

C2TX/RG1

C1TX/RF1

C2RX/RG0

EMUD2/OC2/RD1

OC3/RD2

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

AVDD

AVSS

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

VSS

VDD

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

U2TX/CN18/RF5

U2RX/CN17/RF4

SDA/RG3

SS2/CN11/RG9

AN5/IC8/CN7/RB5

AN4/IC7/CN6/RB4

IC3/INT3/RD10

VDD

C1RX/RF0

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

64-Pin TQFP

dsPIC30F6011A

dsPIC30F6011A/6012A/6013A/6014A

Pin Diagrams (Continued)

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

13 36

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/T4CK/CN1/RC13

EMUC2/OC1/RD0

IC4/INT4/RD11

IC2/INT2/RD9

IC1/INT1/RD8

VSS

OSC2/CLKO/RC15

OSC1/CLKI

VDD

SCL/RG2

EMUC3/SCK1/INT0/RF6

U1RX/SDI1/RF2

EMUD3/U1TX/SDO1/RF3

COFS/RG15

T2CK/RC1

T3CK/RC2

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS

VDD

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

AN1/VREF-/CN3/RB1

AN0/VREF+/CN2/RB0

OC8/CN16/RD7

CSDO/RG13

CSDI/RG12

CSCK/RG14

VSS

C2TX/RG1

C1TX/RF1

C2RX/RG0

EMUD2/OC2/RD1

OC3/RD2

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

AVDD

AVSS

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

VSS

VDD

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

U2TX/CN18/RF5

U2RX/CN17/RF4

SDA/RG3

SS2/CN11/RG9

AN5/IC8/CN7/RB5

AN4/IC7/CN6/RB4

IC3/INT3/RD10

VDD

C1RX/RF0

OC4/RD3

OC7/CN15/RD6

OC6/IC6/CN14/RD5

OC5/IC5/CN13/RD4

64-Pin TQFP

dsPIC30F6012A

dsPIC30F6011A/6012A/6013A/6014A

Pin Diagrams (Continued)

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

22 80

IC5/RD12

OC4/RD3

OC3/RD2

EMUD2/OC2/RD1

RG14

CN23/RA7

CN22/RA6

C2RX/RG0

C2TX/RG1

C1TX/RF1

C1RX/RF0

RG13

RG12

OC8/CN16/RD7

OC6/CN14/RD5

EMUC2/OC1/RD0

IC4/RD11

IC2/RD9

IC1/RD8

INT4/RA15

IC3/RD10

INT3/RA14

VSS

OSC1/CLKI

VDD

SCL/RG2

U1RX/RF2

U1TX/RF3

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/CN1/RC13

VREF+/RA10

VREF-/RA9

AVDD

AVSS

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

VDD

U2RX/CN17/RF4

IC8/CN21/RD15

U2TX/CN18/RF5

AN6/OCFA/RB6

AN7/RB7

T3CK/RC2

T4CK/RC3

T5CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

PGC/EMUC/AN1/CN3/RB1

PGD/EMUD/AN0/CN2/RB0

VSS

VDD

RG15

T2CK/RC1

INT2/RA13

INT1/RA12

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

VDD

VSS

OC5/CN13/RD4

IC6/CN19/RD13

SDA/RG3

SDI1/RF7

EMUD3/SDO1/RF8

AN5/CN7/RB5

VSS

OSC2/CLKO/RC15

OC7/CN15/RD6

EMUC3/SCK1/INT0/RF6

IC7/CN20/RD14

80-Pin TQFP

dsPIC30F6013A

dsPIC30F6011A/6012A/6013A/6014A

Pin Diagrams (Continued)

Note: For descriptions of individual pins, see Section 1.0 “Device Overview”.

22 80

IC5/RD12

OC4/RD3

OC3/RD2

EMUD2/OC2/RD1

CSCK/RG14

C2RX/RG0

C2TX/RG1

C1TX/RF1

C1RX/RF0

CSDO/RG13

CSDI/RG12

OC8/CN16/RD7

OC6/CN14/RD5

EMUC2/OC1/RD0

IC4/RD11

IC2/RD9

IC1/RD8

INT4/RA15

IC3/RD10

INT3/RA14

VSS

OSC1/CLKI

VDD

SCL/RG2

U1RX/RF2

U1TX/RF3

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/CN1/RC13

VREF+/RA10

VREF-/RA9

AVDD

AVSS

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

VDD

U2RX/CN17/RF4

IC8/CN21/RD15

U2TX/CN18/RF5

AN6/OCFA/RB6

AN7/RB7

T3CK/RC2

T4CK/RC3

T5CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1/LVDIN/CN4/RB2

PGC/EMUC/AN1/CN3/RB1

PGD/EMUD/AN0/CN2/RB0

VSS

VDD

COFS/RG15

T2CK/RC1

INT2/RA13

INT1/RA12

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

VDD

VSS

OC5/CN13/RD4

IC6/CN19/RD13

SDA/RG3

SDI1/RF7

EMUD3/SDO1/RF8

AN5/CN7/RB5

VSS

OSC2/CLKO/RC15

OC7/CN15/RD6

EMUC3/SCK1/INT0/RF6

IC7/CN20/RD14

80-Pin TQFP

dsPIC30F6014A

CN23/RA7

CN22/RA6

dsPIC30F6011A/6012A/6013A/6014A

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 11

2.0 CPU Architecture Overview........................................................................................................................................................ 17

3.0 Memory Organization................................................................................................................................................................. 27

4.0 Address Generator Units............................................................................................................................................................ 41

5.0 Interrupts .................................................................................................................................................................................... 47

6.0 Flash Program Memory.............................................................................................................................................................. 53

7.0 I/O Ports ..................................................................................................................................................................................... 59

8.0 Data EEPROM Memory ............................................................................................................................................................. 65

9.0 Timer1 Module ........................................................................................................................................................................... 71

10.0 Timer2/3 Module ........................................................................................................................................................................ 75

11.0 Timer4/5 Module ....................................................................................................................................................................... 81

12.0 Input Capture Module................................................................................................................................................................. 85

13.0 Output Compare Module ............................................................................................................................................................ 89

14.0 SPI Module................................................................................................................................................................................. 93

15.0 I2C™ Module ............................................................................................................................................................................. 97

16.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 105

17.0 CAN Module ............................................................................................................................................................................. 113

18.0 Data Converter Interface (DCI) Module.................................................................................................................................... 125

19.0 12-bit Analog-to-Digital Converter (ADC) Module .................................................................................................................... 135

20.0 System Integration ................................................................................................................................................................... 145

21.0 Instruction Set Summary .......................................................................................................................................................... 165

22.0 Development Support............................................................................................................................................................... 173

23.0 Electrical Characteristics .......................................................................................................................................................... 177

24.0 Packaging Information.............................................................................................................................................................. 215

Appendix A: Appendix A: ................................................................................................................................................................... 225

Index .................................................................................................................................................................................................. 227

The Microchip Web Site ..................................................................................................................................................................... 233

Customer Change Notification Service .............................................................................................................................................. 233

Customer Support.............................................................................................................................................................................. 233

Reader Response .............................................................................................................................................................................. 234

Product Identification System ............................................................................................................................................................ 235

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Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

dsPIC30F6011A/6012A/6013A/6014A

NOTES:

dsPIC30F6011A/6012A/6013A/6014A

1.0 DEVICE OVERVIEW

This document contains specific information for the

dsPIC30F6011A/6012A/6013A/6014A Digital Signal

Controller (DSC) devices. The dsPIC30F devices

contain extensive Digital Signal Processor (DSP)

functionality within a high-performance 16-bit

microcontroller (MCU) architecture. Figure 1-1 and

Figure 1-2 show device block diagrams for

dsPIC30F6011A/6012A and dsPIC30F6013A/6014A,

respectively.

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and gen-

eral device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157).

dsPIC30F6011A/6012A/6013A/6014A

FIGURE 1-1: dsPIC30F6011A/6012A BLOCK DIAGRAM

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

MCLR

, V

AN4/IC7/CN6/RB4

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

Low-Voltage

Detect

UART1,

CAN2

Timing

Generation

CAN1,

AN5/IC8/CN7/RB5

PCH PCL

Program Counter

ALU<16>

X Data Bus

C™

DCI

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

PCU

12-bit ADC

Timers

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

SS2/CN11/RG9

Input

Capture

Module

Output

Compare

Module

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/T4CK/CN1/RC13

T2CK/RC1

PORTB

C2RX/RG0

C2TX/RG1

SCL/RG2

SDA/RG3

PORTG

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective Address

X RAGU

X WAGU

Y AGU

AN0/V

REF

+/CN2/RB0

AN1/V

REF

-/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

OSC2/CLKO/RC15

, AV

UART2

SPI2

PORTC

Interrupt

Controller

PSV & Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

RAM

X Data

RAM

Address

Latch

Address

Latch

Control Signals

to Various Blocks

EMUC2/OC1/RD0

EMUD2/OC2/RD1

OC3/RD2

OC4/RD3

OC5/IC5/CN13/RD4

OC6/IC6/CN14/RD5

OC7/CN15/RD6

OC8/CN16/RD7

IC1/INT1/RD8

IC2/INT2/RD9

IC3/INT3/RD10

IC4/INT4/RD11

*CSDI/RG12

*CSDO/RG13

*CSCK/RG14

*COFS/RG15

T3CK/RC2

SPI1,

Address Latch

Program Memory

(Up to 144 Kbytes)

Data Latch

Data EEPROM

(Up to 4 Kbytes)

U2TX/CN18/RF5

EMUC3/SCK1/INT0/RF6

C1RX/RF0

C1TX/RF1

U1RX/SDI1/RF2

EMUD3/U1TX/SDO1/RF3

U2RX/CN17/RF4

PORTF

* CSDI, CSDO, CSCK, and COFS are codec functions on dsPIC30F6012A only

dsPIC30F6011A/6012A/6013A/6014A

FIGURE 1-2: dsPIC30F6013A/6014A BLOCK DIAGRAM

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

MCLR

, V

AN4/CN6/RB4

AN12/RB12

AN13/RB13

AN14/RB14

AN15/OCFB/CN12/RB15

Low-Voltage

Detect

UART1,

INT4/RA15

INT3/RA14

REF

+/RA10

REF

-/RA9

CAN2

Timing

Generation

CAN1,

AN5/CN7/RB5

PCH PCL

Program Counter

ALU<16>

X Data Bus

C™

DCI

AN6/OCFA/RB6

AN7/RB7

PCU

12-bit ADC

Timers

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

SS2/CN11/RG9

U2TX/CN18/RF5

EMUC3/SCK1/INT0/RF6

SDI1/RF7

EMUD3/SDO1/RF8

Input

Capture

Module

Output

Compare

Module

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/CN1/RC13

T4CK/RC3

T2CK/RC1

PORTB

C1RX/RF0

C1TX/RF1

U1RX/RF2

U1TX/RF3

C2RX/RG0

C2TX/RG1

SCL/RG2

SDA/RG3

PORTG

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective Address

X RAGU

X WAGU

Y AGU

PGD/EMUD/AN0/CN2/RB0

PGC/EMUC/AN1/CN3/RB1

AN2/SS1/LVDIN/CN4/RB2

AN3/CN5/RB3

OSC2/CLKO/RC15

U2RX/CN17/RF4

, AV

UART2

SPI2

16 PORTA

PORTC

PORTF

Interrupt

Controller

PSV & Table

Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

RAM

X Data

RAM

Address

Latch

Address

Latch

Control Signals

to Various Blocks

EMUC2/OC1/RD0

EMUD2/OC2/RD1

OC3/RD2

OC4/RD3

OC5/CN13/RD4

OC6/CN14/RD5

OC7/CN15/RD6

OC8/CN16/RD7

IC1/RD8

IC2/RD9

IC3/RD10

IC4/RD11

IC5/RD12

IC6/CN19/RD13

IC7/CN20/RD14

IC8/CN21/RD15

*CSDI/RG12

*CSDO/RG13

*CSCK/RG14

*COFS/RG15

T3CK/RC2

SPI1,

INT1/RA12

INT2/RA13

CN23/RA7

CN22/RA6

T5CK/RC4

Address Latch

Program Memory

(Up to 144 Kbytes)

Data Latch

Data EEPROM

(Up to 4 Kbytes)

* CSDI, CSDO, CSCK, and COFS are codec functions on dsPIC30F6014A only

dsPIC30F6011A/6012A/6013A/6014A

Table 1-1 provides a brief description of device I/O

pinouts and the functions that may be multiplexed to a

port pin. Multiple functions may exist on one port pin.

When multiplexing occurs, the peripheral module’s

functional requirements may force an override of the

data direction of the port pin.

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin

Type

Buffer

Type Description

AN0-AN15 I Analog Analog input channels.

AN0 and AN1 are also used for device programming data and

clock inputs, respectively.

AVDD P P Positive supply for analog module. This pin must be connected

at all times.

AVSS P P Ground reference for analog module.

CLKI

CLKO

ST/CMOS

—

External clock source input. Always associated with OSC1 pin

function.

Oscillator crystal output. Connects to crystal or resonator in

Crystal Oscillator mode. Optionally functions as CLKO in RC

and EC modes. Always associated with OSC2 pin function.

CN0-CN23 I ST Input change notification inputs.

Can be software programmed for internal weak pull-ups on all

inputs.

COFS

CSCK

CSDI

CSDO

I/O

—

Data Converter Interface frame synchronization pin.

Data Converter Interface serial clock input/output pin.

Data Converter Interface serial data input pin.

Data Converter Interface serial data output pin.

C1RX

C1TX

C2RX

C2TX

—

CAN1 bus receive pin.

CAN1 bus transmit pin.

CAN2 bus receive pin.

CAN2 bus transmit pin

EMUD

EMUC

EMUD1

EMUC1

EMUD2

EMUC2

EMUD3

EMUC3

I/O

ICD Primary Communication Channel data input/output pin.

ICD Primary Communication Channel clock input/output pin.

ICD Secondary Communication Channel data

input/output pin.

ICD Secondary Communication Channel clock input/output pin.

ICD Tertiary Communication Channel data input/output pin.

ICD Tertiary Communication Channel clock input/output pin.

ICD Quaternary Communication Channel data

input/output pin.

ICD Quaternary Communication Channel clock input/output pin.

IC1-IC8 I ST Capture inputs 1 through 8.

INT0

INT1

INT2

INT3

INT4

External interrupt 0.

External interrupt 1.

External interrupt 2.

External interrupt 3.

External interrupt 4.

LVDIN I Analog Low-Voltage Detect Reference Voltage input pin.

MCLR I/P ST Master Clear (Reset) input or programming voltage input. This

pin is an active low Reset to the device.

OCFA

OCFB

OC1-OC8

—

Compare Fault A input (for Compare channels 1, 2, 3 and 4).

Compare Fault B input (for Compare channels 5, 6, 7 and 8).

Compare outputs 1 through 8.

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F6011A/6012A/6013A/6014A

OSC1

OSC2

I/O

ST/CMOS

—

Oscillator crystal input. ST buffer when configured in RC mode;

CMOS otherwise.

Oscillator crystal output. Connects to crystal or resonator in

Crystal Oscillator mode. Optionally functions as CLKO in RC

and EC modes.

PGD

PGC

I/O

In-Circuit Serial Programming™ data input/output pin.

In-Circuit Serial Programming clock input pin.

RA6-RA7

RA9-RA10

RA12-RA15

I/O

PORTA is a bidirectional I/O port.

RB0-RB15 I/O ST PORTB is a bidirectional I/O port.

RC1-RC4

RC13-RC15

I/O

PORTC is a bidirectional I/O port.

RD0-RD15 I/O ST PORTD is a bidirectional I/O port.

RF0-RF8 I/O ST PORTF is a bidirectional I/O port.

RG0-RG3

RG6-RG9

RG12-RG15

I/O

PORTG is a bidirectional I/O port.

SCK1

SDI1

SDO1

SS1

SCK2

SDI2

SDO2

SS2

I/O

—

Synchronous serial clock input/output for SPI1.

SPI1 Data In.

SPI1 Data Out.

SPI1 Slave Synchronization.

Synchronous serial clock input/output for SPI2.

SPI2 Data In.

SPI2 Data Out.

SPI2 Slave Synchronization.

SCL

SDA

I/O

Synchronous serial clock input/output for I2C™.

Synchronous serial data input/output for I2C.

SOSCO

SOSCI

—

ST/CMOS

32 kHz low-power oscillator crystal output.

32 kHz low-power oscillator crystal input. ST buffer when config-

ured in RC mode; CMOS otherwise.

T1CK

T2CK

T3CK

T4CK

T5CK

Timer1 external clock input.

Timer2 external clock input.

Timer3 external clock input.

Timer4 external clock input.

Timer5 external clock input.

U1RX

U1TX

U1ARX

U1ATX

U2RX

U2TX

—

UART1 Receive.

UART1 Transmit.

UART1 Alternate Receive.

UART1 Alternate Transmit.

UART2 Receive.

UART2 Transmit.

VDD P — Positive supply for logic and I/O pins.

VSS P — Ground reference for logic and I/O pins.

VREF+ I Analog Analog Voltage Reference (High) input.

VREF- I Analog Analog Voltage Reference (Low) input.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin

Type

Buffer

Type Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F6011A/6012A/6013A/6014A

NOTES:

dsPIC30F6011A/6012A/6013A/6014A

2.0 CPU ARCHITECTURE

OVERVIEW

2.1 Core Overview

This section contains a brief overview of the CPU

architecture of the dsPIC30F. For additional

hard-ware and programming information, please refer

to the “dsPIC30F Family Reference Manual”

(DS70046) and the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157) respectively.

The core has a 24-bit instruction word. The Program

Counter (PC) is 23-bits wide with the Least Significant

bit (LSb) always clear (refer to Section 3.1 “Program

Address Space”), and the Most Significant bit (MSb)

is ignored during normal program execution, except for

certain specialized instructions. Thus, the PC can

address up to 4M instruction words of user program

space. An instruction prefetch mechanism is used to

help maintain throughput. Program loop constructs,

free from loop count management overhead, are

supported using the DO and REPEAT instructions, both

of which are interruptible at any point.

The working register array consists of 16 x 16-bit

registers, each of which can act as data, address or

offset registers. One working register (W15) operates

as a software Stack Pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split

into two blocks, referred to as X and Y data memory.

Each block has its own independent Address

Generation Unit (AGU). Most instructions operate

solely through the X memory, AGU, which provides the

appearance of a single unified data space. The

Multiply-Accumulate (MAC) class of dual source DSP

instructions operate through both the X and Y AGUs,

splitting the data address space into two parts (see

Section 3.2 “Data Address Space”). The X and Y

data space boundary is device specific and cannot be

altered by the user. Each data word consists of 2 bytes,

and most instructions can address data either as words

or bytes.

There are two methods of accessing data stored in

program memory:

• The upper 32 Kbytes of data space memory can

be mapped into the lower half (user space) of

program space at any 16K program word

boundary, defined by the 8-bit Program Space

Visibility Page (PSVPAG) register. This lets any

instruction access program space as if it were

data space, with a limitation that the access

requires an additional cycle. Moreover, only the

lower 16 bits of each instruction word can be

accessed using this method.

• Linear indirect access of 32K word pages within

program space is also possible using any working

Table read and write instructions can be used to

access all 24 bits of an instruction word.

Overhead-free circular buffers (Modulo Addressing)

are supported in both X and Y address spaces. This is

primarily intended to remove the loop overhead for

DSP algorithms.

The X AGU also supports Bit-Reversed Addressing on

destination effective addresses to greatly simplify input

or output data reordering for radix-2 FFT algorithms.

Refer to Section 4.0 “Address Generator Units” for

details on modulo and Bit-Reversed Addressing.

The core supports Inherent (no operand), Relative,

Literal, Memory Direct, Register Direct, Register

Indirect, Register Offset and Literal Offset Addressing

modes. Instructions are associated with predefined

addressing modes, depending upon their functional

requirements.

For most instructions, the core is capable of executing

a data (or program data) memory read, a working

program (instruction) memory read per instruction

cycle. As a result, 3-operand instructions are

supported, allowing C = A + B operations to be

executed in a single cycle.

A DSP engine has been included to significantly

enhance the core arithmetic capability and throughput.

It features a high-speed 17-bit by 17-bit multiplier, a

40-bit ALU, two 40-bit saturating accumulators and a

40-bit bidirectional barrel shifter. Data in the

accumulator or any working register can be shifted up

to 16 bits right, or 16 bits left in a single cycle. The DSP

instructions operate seamlessly with all other

instructions and have been designed for optimal

real-time performance. The MAC class of instructions

can concurrently fetch two data operands from memory

while multiplying two W registers. To enable this

concurrent fetching of data operands, the data space

has been split for these instructions and linear for all

others. This has been achieved in a transparent and

flexible manner, by dedicating certain working registers

to each address space for the MAC class of

instructions.

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157).

dsPIC30F6011A/6012A/6013A/6014A

The core does not support a multi-stage instruction

pipeline. However, a single stage instruction prefetch

mechanism is used, which accesses and partially

decodes instructions a cycle ahead of execution, in

order to maximize available execution time. Most

instructions execute in a single cycle with certain

exceptions.

The core features a vectored exception processing

structure for traps and interrupts, with 62 independent

vectors. The exceptions consist of up to 8 traps (of

which 4 are reserved) and 54 interrupts. Each interrupt

is prioritized based on a user-assigned priority between

1 and 7 (1 being the lowest priority and 7 being the

highest), in conjunction with a predetermined ‘natural

order’. Traps have fixed priorities ranging from 8 to 15.

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and

consists of 16 x 16-bit working registers (W0 through

W15), 2 x 40-bit accumulators (ACCA and ACCB),

STATUS register (SR), Data Table Page register

(TBLPAG), Program Space Visibility Page register

(PSVPAG), DO and REPEAT registers (DOSTART,

DOEND, DCOUNT and RCOUNT) and Program Coun-

ter (PC). The working registers can act as data,

address or offset registers. All registers are memory

mapped. W0 acts as the W register for file register

addressing.

Some of these registers have a shadow register

associated with each of them, as shown in Figure 2-1.

The shadow register is used as a temporary holding

shadow registers are accessible directly. The following

rules apply for transfer of registers into and out of

shadows.

•PUSH.S and POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits

only) are transferred.

•DO instruction

DOSTART, DOEND, DCOUNT shadows are

pushed on loop start, and popped on loop end.

When a byte operation is performed on a working

target register is affected. However, a benefit of

memory mapped working registers is that both the

Least and Most Significant Bytes can be manipulated

through byte wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/

FRAME POINTER

The dsPIC® DSC devices contain a software stack.

W15 is the dedicated software Stack Pointer (SP), and

will be automatically modified by exception processing

and subroutine calls and returns. However, W15 can be

referenced by any instruction in the same manner as all

other W registers. This simplifies the reading, writing

and manipulation of the Stack Pointer (e.g.,

creating stack frames).

W15 is initialized to 0x0800 during a Reset. The user

may reprogram the SP during initialization to any

location within data space.

W14 has been dedicated as a Stack Frame Pointer as

defined by the LNK and ULNK instructions. However,

W14 can be referenced by any instruction in the same

manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS register

(SR), the LSB of which is referred to as the SR Low

byte (SRL) and the Most Significant Byte (MSB) as the

SR High byte (SRH). See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags

(including the Z bit), as well as the CPU Interrupt

Priority Level status bits, IPL<2:0> and the Repeat

Active status bit, RA. During exception processing,

SRL is concatenated with the MSB of the PC to form a

complete word value which is then stacked.

The upper byte of the STATUS register contains the

DSP Adder/Subtracter status bits, the DO Loop Active

bit (DA) and the Digit Carry (DC) status bit.

2.2.3 PROGRAM COUNTER

The Program Counter is 23-bits wide; bit 0 is always

clear. Therefore, the PC can address up to 4M

instruction words.

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

dsPIC30F6011A/6012A/6013A/6014A

FIGURE 2-1: PROGRAMMER’S MODEL

TABPAG

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP Operand

Registers

W10

W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

DSP Address

Registers

AD39 AD0AD31

DSP

Accumulators

ACCA

ACCB

PSVPAG

7 0

Program Space Visibility Page Address

OA OB SA SB

RCOUNT

15 0

REPEAT Loop Counter

DCOUNT

15 0

DO Loop Counter

DOSTART

22 0

DO Loop Start Address

IPL2 IPL1

SPLIM Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

15 0

Core Configuration Register

Legend

CORCON

DA DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End Address

DOEND

dsPIC30F6011A/6012A/6013A/6014A

2.3 Divide Support

The dsPIC DSC devices feature a 16/16-bit signed

fractional divide operation, as well as 32/16-bit and

16/16-bit signed and unsigned integer divide

operations, in the form of single instruction iterative

divides. The

following instructions and data sizes are supported:

•DIVF - 16/16 signed fractional divide

•DIV.sd - 32/16 signed divide

•DIV.ud - 32/16 unsigned divide

•DIV.sw - 16/16 signed divide

•DIV.uw - 16/16 unsigned divide

The 16/16 divides are similar to the 32/16 (same number

of iterations), but the dividend is either zero-extended or

sign-extended during the first iteration.

The divide instructions must be executed within a

REPEAT loop. Any other form of execution (e.g., a

series of discrete divide instructions) will not function

correctly because the instruction flow depends on

RCOUNT. The divide instruction does not automatically

set up the RCOUNT value and it must, therefore, be

explicitly and correctly specified in the REPEAT

instruction as shown in Table 2-1 (REPEAT will execute

the target instruction {operand value + 1} times). The

REPEAT loop count must be setup for 18 iterations of

the DIV/DIVF instruction. Thus, a complete divide

operation requires 19 cycles.

TABLE 2-1: DIVIDE INSTRUCTIONS

Note: The divide flow is interruptible. However,

the user needs to save the context as

appropriate.

Instruction Function

DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1

DIV.sd Signed divide: (Wm + 1:Wm)/Wn → W0; Rem → W1

DIV.ud Unsigned divide: (Wm + 1:Wm)/Wn → W0; Rem → W1

DIV.sw Signed divide: Wm/Wn → W0; Rem → W1

DIV.uw Unsigned divide: Wm/Wn → W0; Rem → W1

dsPIC30F6011A/6012A/6013A/6014A

2.4 DSP Engine

The DSP engine consists of a high-speed 17-bit x

17-bit multiplier, a barrel shifter and a 40-bit

adder/subtracter (with two target accumulators, round

and saturation logic).

The dsPIC30F is a single-cycle instruction flow

architecture; therefore, concurrent operation of the

DSP engine with MCU instruction flow is not possible.

However, some MCU ALU and DSP engine resources

may be used concurrently by the same instruction

(e.g., ED, EDAC).

The DSP engine also has the capability to perform

inherent accumulator-to-accumulator operations,

which require no additional data. These instructions are

ADD, SUB and NEG.

The DSP engine has various options selected through

various bits in the CPU Core Configuration register

(CORCON), as listed below:

• Fractional or integer DSP multiply (IF).

• Signed or unsigned DSP multiply (US).

• Conventional or convergent rounding (RND).

• Automatic saturation on/off for ACCA (SATA).

• Automatic saturation on/off for ACCB (SATB).

• Automatic saturation on/off for writes to data

memory (SATDW).

• Accumulator Saturation mode selection

(ACCSAT).

A block diagram of the DSP engine is shown in

Figure 2-2.

Note: For CORCON layout, see Table 3-3.

TABLE 2-2: DSP INSTRUCTIONS SUMMARY

Instruction Algebraic Operation ACC Write Back

CLR A = 0 Yes

ED A = (x - y)2No

EDAC A = A + (x - y)2No

MAC A = A + (x * y) Yes

MAC A = A + x2No

MOVSAC No change in A Yes

MPY A = x * y No

MPY A = x 2No

MPY.N A = - x * y No

MSC A = A - x * y Yes

dsPIC30F6011A/6012A/6013A/6014A

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

Zero Backfill

Sign-Extend

Barrel

Shifter

40-bit Accumulator A

40-bit Accumulator B Round

Logic

X Data Bus

To/From W Array

Adder

Saturate

Negate

16 16

40 40

Y Data Bus

Carry/Borrow Out

Carry/Borrow In

Multiplier/Scaler

17-bit

dsPIC30F6011A/6012A/6013A/6014A

2.4.1 MULTIPLIER

The 17 x 17-bit multiplier is capable of signed or

unsigned operation and can multiplex its output using a

scaler to support either 1.31 fractional (Q31) or 32-bit

integer results. Unsigned operands are zero-extended

into the 17th bit of the multiplier input value. Signed

operands are sign-extended into the 17th bit of the

multiplier input value. The output of the 17 x 17-bit

multiplier/scaler is a 33-bit value which is

sign-extended to 40 bits. Integer data is inherently

represented as a signed two’s complement value,

where the MSB is defined as a sign bit. Generally

speaking, the range of an N-bit two’s complement

integer is -2N-1 to 2N-1 - 1. For a 16-bit integer, the data

range is -32768 (0x8000) to 32767 (0x7FFF) including

‘0’. For a 32-bit integer, the data range is

-2,147,483,648 (0x8000 0000) to 2,147,483,647

(0x7FFF FFFF).

When the multiplier is configured for fractional

multiplication, the data is represented as a two’s

complement fraction, where the MSB is defined as a

sign bit and the radix point is implied to lie just after the

sign bit (QX format). The range of an N-bit two’s

complement fraction with this implied radix point is -1.0

to (1 – 21-N). For a 16-bit fraction, the Q15 data range

is -1.0 (0x8000) to 0.999969482 (0x7FFF) including ‘0’

and has a precision of 3.01518x10-5. In Fractional

mode, the 16x16 multiply operation generates a 1.31

product which has a precision of 4.65661 x 10-10.

The same multiplier is used to support the MCU

multiply instructions which include integer 16-bit

signed, unsigned and mixed sign multiplies.

The MUL instruction may be directed to use byte or

word sized operands. Byte operands will direct a 16-bit

result, and word operands will direct a 32-bit result to

the specified register(s) in the W array.

2.4.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTER

The data accumulator consists of a 40-bit

adder/subtracter with automatic sign extension logic. It

can select one of two accumulators (A or B) as its

pre-accumulation source and post-accumulation

destination. For the ADD and LAC instructions, the data

to be accumulated or loaded can be optionally scaled

via the barrel shifter, prior to accumulation.

2.4.2.1 Adder/Subtracter, Overflow and

Saturation

The adder/subtracter is a 40-bit adder with an optional

zero input into one side and either true, or complement

data into the other input. In the case of addition, the

carry/borrow input is active high and the other input is

true data (not complemented), whereas in the case of

subtraction, the carry/borrow input is active low and the

other input is complemented. The adder/subtracter

generates overflow status bits SA/SB and OA/OB,

which are latched and reflected in the STATUS

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is

destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all

the guard bits are not identical to each other.

The adder has an additional saturation block which

controls accumulator data saturation, if selected. It

uses the result of the adder, the overflow status bits

described above, and the SATA/B (CORCON<7:6>)

and ACCSAT (CORCON<4>) mode control bits to

determine when and to what value to saturate.

Six STATUS register bits have been provided to

support saturation and overflow; they are:

•OA:

ACCA overflowed into guard bits

•OB:

ACCB overflowed into guard bits

• SA:

ACCA saturated (bit 31 overflow and saturation)

ACCA overflowed into guard bits and saturated

(bit 39 overflow and saturation)

• SB:

ACCB saturated (bit 31 overflow and saturation)

ACCB overflowed into guard bits and saturated

(bit 39 overflow and saturation)

•OAB:

Logical OR of OA and OB

• SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data

passes through the adder/subtracter. When set, they

indicate that the most recent operation has overflowed

into the accumulator guard bits (bits 32 through 39).

The OA and OB bits can also optionally generate an

arithmetic warning trap when set and the

corresponding overflow trap flag enable bit (OVATE,

OVBTE) in the INTCON1 register (refer to Section 5.0

“Interrupts”) is set. This allows the user to take

immediate action, for example, to correct system gain.

dsPIC30F6011A/6012A/6013A/6014A

The SA and SB bits are modified each time data

passes through the adder/subtracter but can only be

cleared by the user. When set, they indicate that the

accumulator has overflowed its maximum range (bit 31

for 32-bit saturation, or bit 39 for 40-bit saturation) and

will be saturated (if saturation is enabled). When

saturation is not enabled, SA and SB default to bit 39

overflow and thus indicate that a catastrophic overflow

has occurred. If the COVTE bit in the INTCON1 register

is set, SA and SB bits will generate an arithmetic

warning trap when saturation is disabled.

The overflow and saturation status bits can optionally

be viewed in the STATUS register (SR) as the logical

OR of OA and OB (in bit OAB) and the logical OR of SA

and SB (in bit SAB). This allows programmers to check

one bit in the STATUS register to determine if either

accumulator has overflowed, or one bit to determine if

either accumulator has saturated. This would be useful

for complex number arithmetic which typically uses

both the accumulators.

The device supports three saturation and overflow

modes:

• Bit 39 Overflow and Saturation:

When bit 39 overflow and saturation occurs, the

saturation logic loads the maximally positive 9.31

(0x7FFFFFFFFF), or maximally negative 9.31

value (0x8000000000) into the target accumulator.

The SA or SB bit is set and remains set until

cleared by the user. This is referred to as ‘super

saturation’ and provides protection against errone-

ous data, or unexpected algorithm problems (e.g.,

gain calculations).

• Bit 31 Overflow and Saturation:

When bit 31 overflow and saturation occurs, the

saturation logic then loads the maximally positive

1.31 value (0x007FFFFFFF), or maximally

negative 1.31 value (0x0080000000) into the

target accumulator. The SA or SB bit is set and

remains set until cleared by the user. When this

Saturation mode is in effect, the guard bits are not

used (so the OA, OB or OAB bits are never set).

• Bit 39 Catastrophic Overflow:

The bit 39 overflow status bit from the adder is

used to set the SA or SB bit which remain set until

cleared by the user. No saturation operation is

performed and the accumulator is allowed to

overflow (destroying its sign). If the COVTE bit in

the INTCON1 register is set, a catastrophic over-

flow can initiate a trap exception.

2.4.2.2 Accumulator ‘Write Back’

The MAC class of instructions (with the exception of

MPY, MPY.N, ED and EDAC) can optionally write a

rounded version of the high word (bits 31 through 16)

of the accumulator that is not targeted by the instruction

into data space memory. The write is performed across

the X bus into combined X and Y address space. The

following addressing modes are supported:

• W13, Register Direct:

The rounded contents of the non-target

accumulator are written into W13 as a 1.15

fraction.

• [W13] + = 2, Register Indirect with Post-Increment:

The rounded contents of the non-target

accumulator are written into the address pointed

to by W13 as a 1.15 fraction. W13 is then

incremented by 2 (for a word write).

2.4.2.3 Round Logic

The round logic is a combinational block which

performs a conventional (biased) or convergent

(unbiased) round function during an accumulator write

(store). The Round mode is determined by the state of

the RND bit in the CORCON register. It generates a

16-bit, 1.15 data value which is passed to the data

space write saturation logic. If rounding is not indicated

by the instruction, a truncated 1.15 data value is stored

and the least significant word (lsw) is simply discarded.

Conventional rounding takes bit 15 of the accumulator,

zero-extends it and adds it to the ACCxH word (bits 16

through 31 of the accumulator). If the ACCxL word

(bits 0 through 15 of the accumulator) is between

0x8000 and 0xFFFF (0x8000 included), ACCxH is

incremented. If ACCxL is between 0x0000 and 0x7FFF,

ACCxH is left unchanged. A consequence of this

algorithm is that over a succession of random rounding

operations, the value will tend to be biased slightly

positive.

Convergent (or unbiased) rounding operates in the

same manner as conventional rounding, except when

ACCxL equals 0x8000. If this is the case, the LSb

(bit 16 of the accumulator) of ACCxH is examined. If it

is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not

modified. Assuming that bit 16 is effectively random in

nature, this scheme will remove any rounding bias that

may accumulate.

The SAC and SAC.R instructions store either a

truncated (SAC) or rounded (SAC.R) version of the

contents of the target accumulator to data memory via

the X bus (subject to data saturation, see

Section 2.4.2.4 “Data Space Write Saturation”).

Note that for the MAC class of instructions, the

accumulator write back operation will function in the

same manner, addressing combined MCU (X and Y)

data space though the X bus. For this class of

instructions, the data is always subject to rounding.

dsPIC30F6011A/6012A/6013A/6014A

2.4.2.4 Data Space Write Saturation

In addition to adder/subtracter saturation, writes to data

space may also be saturated but without affecting the

contents of the source accumulator. The data space

write saturation logic block accepts a 16-bit, 1.15

fractional value from the round logic block as its input,

together with overflow status from the original source

(accumulator) and the 16-bit round adder. These are

combined and used to select the appropriate 1.15

fractional value as output to write to data space

memory.

If the SATDW bit in the CORCON register is set, data

(after rounding or truncation) is tested for overflow and

adjusted accordingly, For input data greater than

0x007FFF, data written to memory is forced to the

maximum positive 1.15 value, 0x7FFF. For input data

less than 0xFF8000, data written to memory is forced

to the maximum negative 1.15 value, 0x8000. The MSb

of the source (bit 39) is used to determine the sign of

the operand being tested.

If the SATDW bit in the CORCON register is not set, the

input data is always passed through unmodified under

all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 16-bit

arithmetic or logic right shifts, or up to 16-bit left shifts

in a single cycle. The source can be either of the two

DSP accumulators, or the X bus (to support multi-bit

shifts of register or memory data).

The shifter requires a signed binary value to determine

both the magnitude (number of bits) and direction of the

shift operation. A positive value will shift the operand

right. A negative value will shift the operand left. A

value of ‘0’ will not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a

40-bit result for DSP shift operations and a 16-bit result

for MCU shift operations. Data from the X bus is

presented to the barrel shifter between bit positions 16

to 31 for right shifts, and bit positions 0 to 16 for left

shifts.

dsPIC30F6011A/6012A/6013A/6014A

NOTES:

dsPIC30F6011A/6012A/6013A/6014A

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

The program address space is 4M instruction words. It

is addressable by a 24-bit value from either the 23-bit

PC, table instruction Effective Address (EA), or data

space EA, when program space is mapped into data

space as defined by Table 3-1. Note that the program

space address is incremented by two between

successive program words in order to provide

compatibility with data space addressing.

User program space access is restricted to the lower

4M instruction word address range (0x000000 to

0x7FFFFE) for all accesses other than TBLRD/TBLWT,

which use TBLPAG<7> to determine user or

configuration space access. In Table 3-1, Program

Space Address Construction, bit 23 allows access to

the Device ID, the Unit ID and the configuration bits.

Otherwise, bit 23 is always clear.

Note: This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals, register descriptions and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046). For more information on the

device instruction set and programming,

refer to the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157).

Note: The address map shown in Figure 3-1 and

Figure 3-2 is conceptual, and the actual

memory configuration may vary across

individual devices depending on available

memory.

dsPIC30F6011A/6012A/6013A/6014A

FIGURE 3-1:

PROGRAM SPACE MEMORY

MAP FOR

dsPIC30F6011A/6013A

FIGURE 3-2:

PROGRAM SPACE MEMORY

MAP FOR

dsPIC30F6012A/6014

Reset – Target Address

User Memory

Space

000000

00007E

000002

000080

Device Configuration

User Flash

Program Memory

016000

015FFE

Configuration Memory

Space

Data EEPROM

(44K instructions)

(2 Kbytes)

800000

F80000

Registers F8000E

F80010

DEVID (2)

FEFFFE

FF0000

FFFFFE

Reserved

F7FFFE

Reserved

7FF800

7FF7FE

(Read ‘0’s)

8005FE

800600

UNITID (32 instr.)

Vector Tables

8005BE

8005C0

Reset – GOTO Instruction

000004

Reserved

7FFFFE

Reserved

000100

0000FE

000084

Alternate Vector Table

Reserved

Interrupt Vector Table

Reset – Target Address

User Memory

Space

000000

00007E

000002

000080

Device Configuration

User Flash

Program Memory

018000

017FFE

Configuration Memory

Space

Data EEPROM

(48K instructions)

(4 Kbytes)

800000

F80000

Registers F8000E

F80010

DEVID (2)

FEFFFE

FF0000

FFFFFE

Reserved

F7FFFE

Reserved

7FF000

7FEFFE

(Read ‘0’s)

8005FE

800600

UNITID (32 instr.)

Vector Tables

8005BE

8005C0

Reset – GOTO Instruction

000004

Reserved

7FFFFE

Reserved

000100

0000FE

000084

Alternate Vector Table

Reserved

Interrupt Vector Table