N
CLC522
Wideband Variable-Gain Amplifier
General Description
The CLC522 variable gain amplifier (VGA) is a dc-coupled, two-
quadrant multiplier with differential voltage inputs and a single-ended
voltage output. Two input buffers and an output operational amplifer
are integrated with the multiplier core to make the CLC522 a complete
VGA system that does not require external buffering.
The CLC522 provides the flexibility of externally setting the maximum
gain with only two external resistors. Greater than 40dB gain control
is easily achieved through a single high impedance voltage input. The
CLC522 provides a linear (in Volts per Volt) relationship between the
amplifier's gain and the gain-control input voltage.
The CLC522's maximum gain may be set anywhere over a nominal
range of 2V/V to 100V/V. The gain control input then provides
attenuation from the maximum setting. For example, set for a
maximum gain of 100V/V, the CLC522 will provide a 100V/V to 1V/V
gain control range by sweeping the gain control input voltage from +1
to -0.98V.
Set at a maximum gain of 10V/V, the CLC522 provides a 165MHz
signal channel bandwidth and a 165MHz gain control bandwidth. Gain
nonlinearity over a 40dB gain range is 0.5% and gain accuracy at
AVmax = 10V/V is typically ±0.3%.
June 1999
CLC522
Wideband Variable-Gain Amplifier
Features
■330MHz signal bandwidth: Avmax = 2
■165MHz gain-control bandwidth
■0.3° to 60MHz linear phase deviation
■0.04% (-68dB) signal-channel non-linearity
■>40dB gain-adjustment range
■Differential or single-end voltage inputs
■Single-ended voltage output
Applications
■Variable attenuators
■Pulse amplitude equalizers
■HF modulators
■Automatic gain control & leveling loops
■Video production switching
■Differential line receivers
■Voltage controlled filters
1999 National Semiconductor Corporation http://www.national.com
Printed in the U.S.A.
Gain (V/V)
Gain vs. Gain Control Voltage (V
g
)
-1.1 Gain Control Voltage, V
g
(Volts) 1.1
10
0
V
Vn
sCR
ss
CR k
CR
kR
RQk
R
Rk
CR
o
in
b
by
f
g
b
yoy
=−
++
===
11
1
185
222
., ,
ω
TT
TT
Typical Applicationypical Application
ypical Applicationypical Application
ypical Application
2nd Order Tuneable Bandpass Filter Pinout
DIP & SOIC
CLC522 Electrical Characteristics
(VCC = ±5V; AVmax = +10; Rf =1kΩΩ
ΩΩ
Ω; Rg =182W; RL = 100ΩΩ
ΩΩ
Ω; Vg=+1.1V)
Ordering Information
supply voltage ±7V
short circuit current 80mA
common-mode input voltage ±Vcc
maximum junction temperature +150°C
storage temperature -65°C to+150°C
lead temperature (soldering 10 sec) +300°C
transistor count 74
Absolute Maximum Ratings
Notes
1 )AJE (SOIC) is tested/guaranteed with Rf=866Ω and Rg= 165Ω.
2)J-level, spec is 100% tested at +25°C.
3)Specified with Vin = 0.2V and Vg < 0.5Vpp.
4) Feedtrough is specified at max. attenuation (i.e Vg =-1.1V)
http://www.national.com 2
Model Temperature Range Description
CLC522AJP -40°C to +85°C 14-pin PDIP
CLC522AJE -40°C to +85°C 14-pin SOIC
CLC522ALC -40°C to +85°C dice
CLC522AMC -55°C to +125°C dice, MIL-STD-883
PARAMETERS CONDITIONS TYP MIN/MAX RATINGS UNITS NOTES
Ambient Temperature AJ +25 +25 0 to +70 -40 to +85 °C 1
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth Vout < 0.5Vpp 165 120 115 110 MHz
Vout < 5.0Vpp 150 100 95 90 MHz
gain control bandwidth Vout < 0.5Vpp 165 120 115 110 MHz 3
gain flatness Vout < 0.5Vpp
peaking DC to 30MHz 0 0.1 0.1 0.1 dB
rolloff DC to 30MHz 0.05 0.25 0.25 0.4 dB
linear phase deviation DC to 60MHz 0.3 1.0 1.1 1.2 °
feedthrough 30MHz - 62 - 57 - 57 -57 dB 4
TIME DOMAIN RESPONSE
rise and fall time 0.5V step 2.2 2.9 3.0 3.2 n s
5.0V step 3 .0 5 .0 5. 0 5.0 n s
settling time 2.0V step to 0.1% 12 18 18 18 ns
overshoot 0.5V step 2 15 15 15 %
slew rate 4.0V step 2000 1400 1400 1400 V/µs
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion 2Vpp, 20MHz - 5 0 - 4 4 - 4 4 -44 dBc
3rd harmonic distortion 2Vpp, 20MHz -65 - 5 8 - 5 6 -54 dBc
equivalent input noise 1 to 200MHz 5.8 6 . 2 6.5 6. 8 n V/√Hz
noise floor 1 to 200MHz - 152 - 150 - 149 - 149 dBm 1Hz
GAIN ACCURACY
signal channel nonlinearity (SGNL)V
out = ±2Vpp 0.04 0.1 0.1 0.1 % 2
gain control nonlinearity (GCNL) full range 0.5 2.0 2.2 3.0 % 2
gain error (GACCU)A
Vmax=+10 ±0.0 ±0.5 ± 0.5 ±1.0 dB 2
Vghigh +990 +990±60 + 990±60 + 990±60 mV
low -9 75 -975±80 - 975±80 - 975±80 mV
STATIC DC PERFORMANCE
Vin voltage range common mode ± 2.2 ± 1.2 ± 1.2 ± 1.4 V
bias current 9 21 26 45 µA2
average drift 65 --- 175 275 nA/°C
offset current 0.2 2.0 3.0 4.0 µA
average drift 5 --- 30 40 nA/°C
resistance 1500 650 450 175 kΩ
capacitance 1.0 2.0 2.0 2.0 pF
Vgbias current 15 3 8 47 82 µA
average drift 125 --- 300 600 nA/°C
resistance 100 38 30 15 kΩ
capacitance 1.0 2.0 2.0 2.0 pF
output voltage range RL= ∞± 4.0 ± 3.7 ± 3.6 ± 3.5 V
current ± 70 ± 47 ± 40 ± 25 mA
offset voltage AVmax=+10 25 85 95 120 mV 2
average drift 100 --- 350 400 µV/°C
resistance 0.1 0.2 0.3 0.6 Ω
IRgmax 1.8 1.37 1.26 1.15 mA
power supply sensitivity output referred 10 40 40 40 mV/V
common-mode rejection ratio input referred 70 59 59 59 dB
supply current RL= ∞46 61 62 63 mA 2
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Package Thermal Resistance
Package θJC θJA
Plastic (AJP) 55°C/W 100°C/W
Surface Mount (AJE) 35°C/W 105°C/W
CerDIP 40°C/W 95°C/W
CLC522TypicalPerformance
(T
A
=+25°C, V
cc
=±5V, A
v
=+10, V
g
=1.1V, R
L
=100Ω; unless noted)
0
-45
-90
-135
-180
-270
V
out
= 500m V
pp
R
g
=182Ω
R
f
= 1kΩ
A
V
=A
Vmax
(V
g
=1.0V)
A
V
=1
(V
g
=-0.8V)
Gain
Phase
1 Frequency (MHz) 200
Normalized Magnitude (1dB/div)
Phase (45°/div)
Frequency Response (A
Vmax
=10)
V
in
= 25mV
pp
R
g
=10.2Ω
R
f
= 715Ω
A
V
=A
Vmax
(V
g
=1.0V)
Gain
Phase
1Frequency (MHz) 100
Normalized Magnitude (1dB/div)
Phase (45°/div)
Frequency Response (A
Vmax
=100)
0
-45
-90
-135
-180
-270
A
V
=1
(V
g
=-0.98V)
V
out
= 2V
pp
R
g
=2kΩ
R
f
= 2.2kΩ
A
V
=A
Vmax
(V
g
=1.0V)
Gain
Phase
1 Frequency (MHz) 500
Normalized Magnitude (1dB/div)
Phase (45°/div)
Frequency Response (A
Vmax
=2)
0
-45
-90
-135
-180
-270
A
V
=1
(V
g
=0V)
100
90
80
70
60
50
40
30
20
10
0
Frequency (Hz)
PSRR/CMRR (dB)
PSRR and CMRR (Input Referred)
CMRR
PSRR
10
4
10
5
10
6
10
7
10
8
Phase
Gain
A
vmax
+ 10
V
o
= 2V
pp
R
f
= 1k
V
g
= 1.1V
Magnitude (0.1dB/div)
Deviation from Linear Phase(0.1°/div)
Gain Flatness & Linear Phase Deviation
0Frequency (3MHz/div) 30MHz
V
g
(Volts)
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
10
0
Full Scale Non-linearity (%)
Gain (V/V)
SGNL vs. V
g
, Gain
0.9 0.7 0.5 0.3 0.1 -0.1 -0.3 -0.5 -0.7 -0.9
Frequency (25MHz/div)
0
-45
-90
-135
-180
-225
Magnitude (1dB/div)
Large Signal Frequency Response
Magnitude
Phase
Gain
SGNL
V
o
= 5V
pp
V
g
= 1.1V
A
vmax
= +100
R
f
= 806Ω
A
vmax
= +2
R
f
= 2kΩ
A
vmax
= +10
R
f
= 1kΩ
0 250
Phase (deg)
R
f
= 1kΩ
V
out
= 0.5V
pp
V
out
=5V
pp
A
vmax
= +10
V
g
=1.0V
Large signal (Volts)
Small Signal (Volts)
Large & Small Signal Pulse Response
Time (5ns/div)
3
2
1
0
-1
-2
-3
+.75
+.50
+.25
0
-.25
-.50
-.75
V
out
V
g
V
g
= 1.0V
V
g
= -1.0V
A
vmax
= + 10
V
in
= 0.25V DC
2.5
Vout (0.5V/div.)
Gain Control Settling Time & Delay
Time (5ns/div)
0
100mV/div
Gain Control Channel Feedthrough
Time (5ns/div)
+1V
0
-1V
V
g
Input
Output
V
in
= 0 A
Vmax
= + 10
2V output step
V
g
= 1.0V
.2
.15
0.1
.05
0
-.05
-.1
-.15
-.2
Settling Error (%)
Short Term Settling Time
0100
Time (10ns/div)
A
Vmax
= + 10
2V output step
V
g
= 1.0V
.20
.15
.10
.05
0
-.05
-.10
-.15
-.20
Settling Error (%)
Long Term Settling Time
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
Time (sec)
Rs
Ts
A
vmax
= +10
Load Capacitance, C
L
(pF)
Settling Time, TS, (ns), to 0.1%
Rs (ohms)
Settling Time vs. Capacitive Load
10 100 1000
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
R
s
C
L
Vg=1.0Volt
50Ω
182Ω
1kΩ
1kΩ
CLC522
Frequency (MHz)
V
g
=+1.1V V
g
=-1.1V
55
40
25
10
-5
-20
-35
-50
-65
-80
-95
Gain (dB)
Feed-through Isolation
1 10 100
A
Vmax
=+2
R
f
=2kΩ
A
Vmax
=+10
R
f
=1kΩ
A
Vmax
=+100
R
f
=750Ω
V
o
=2.5V
pp
50
45
40
35
30
25
20
15
10
5
002 4 68101214
Settling Time to 0.1% (ns)
Settling Time vs. Gain
Attenuation From Maximum Gain (dB)
R
f
= 2kΩ
V
o
= 1V
pp
A
vmax
=5
A
vmax
= 10
A
vmax
= 20
3http://www.national.com
Theory of Operation
The CLC522 is a linear wideband variable-gain amplifier
as illustrated in Fig 1. A voltage input signal may be
applied differentially between the two inputs (+Vin, -Vin),
or single-endedly by grounding one of the unused inputs.
The CLC522 input buffers convert the input voltage to a
current (IRg) that is a function of the differential input
voltage (Vinput =+Vin - -Vin) and the value of the gain-
setting resistor (Rg). This current (IRg) is then mirrored to
a gain stage with a current gain of 1.85. The voltage-
controlled two-quadrant multiplier attenuates this current
which is then converted to a voltage via the output
amplifier. This output amplifier is a current-feedback op
amp configured as a transimpedance amplifier. It's tran-
simpedance gain is the feedback resistor (Rf). The input
signal, output, and gain control are all voltages. The
output voltage can easily be calculated as seen in Eq. 1.
Eq. 1
Fig. 1
Phase
Negative Sync Phase
Positive Sync
Gain
Positive Sync
Gain
Negative Sync
4.43 MHz
Avmax = +10
Vg= 1.0V
Number of 150ΩLoads
Differential Gain (%)
DifferentialPhase (degrees)
Differential Gain and Phase
1234
.25
.20
.15
.10
.05
0
.25
.20
.15
.10
.05
0
50MHz
20MHz
10MHz
5MHz
-4 -2 0246810
Output Power (Pout, dBm)
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
Distortion Level (dBc)
2nd Harmonic Distortion vs. P
out
1.1V
50Ω
P
o
1kΩ50Ω
50Ω
50Ω
20Ω
182Ω
R
f
V
g
522
50MHz
20MHz
10MHz
5MHz
-4 -2 0 2 4 6 8 10
Output Power (Pout, dBm)
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
Distortion Level (dBc)
3rd Harmonic Distortion vs. P
out
1.1V
50Ω
50Ω
1kΩ
50Ω
50Ω
20Ω
182Ω
R
f
V
g
522 P
o
Input
Limited
R
f
= 900Ω
Output
Limited
R
f
= 1.4kΩ
0 100
Frequency (MHz)
20
19
18
17
16
15
14
13
12
11
10
-1dB Compression (dBm)
-1dB Compression at Maximum Gain
P
o
P
i
R
g
R
f
50
Ω
50
Ω
50
Ω
20
Ω
50
Ω
522
CLC522TypicalPerformance
(T
A
=+25°C, V
cc
=±5V, A
v
=+10, V
g
=1.1V, R
L
=100Ω; unless noted)
Phase, Vg= 0.0V
Phase, Vg= 1.0V
Gain, Vg= 0.0V
Gain, Vg= 1.0V
4.43 MHz
Positive Sync
Avmax = +2
Number of 150ΩLoads
Differential Gain (%)
DifferentialPhase (degrees)
Differential Gain and Phase
1234
.10
.08
.06
.04
.02
0
.10
.08
.06
.04
.02
0
0 102030405060708090100
Maximum Gain Setting, AVmax (V/V)
100
10
1
Voltage Noise (nV/√Hz)
Input Referred Voltage Noise vs A
Vmax
VI VR
out R gf
g
=∗∗ +
∗185 1
2
.
sin
.
ce I V
R
AR
R
V
Rinput
g
vf
g
g
g=
=∗∗+
185 1
2
Eq. 2
The gain of the CLC522 is therefore a function of three
external variables; Rg, Rf and Vg as expressed in Eq. 2.
The gain-control voltage (Vg) has a ideal input range of
-1V≤Vg≤+1V. At Vg=+1V, the gain of the CLC522 is at
its maximum as expressed in Eq. 3.
AR
R
Vf
g
max .
=185 Eq. 3
Notice also that Eq. 3 holds for both differential and
single-ended operation.
Choosing Rf and Rg
Rg is calculated from Eq.4. Vinputmax is the maximum peak
RV
I
ginput
Rg
=max
max Eq. 4
input voltage (Vpk) determined by the application. IRgmax
is the maximum allowable current through Rg and is
typically 1.8mA. Once AVmax is determined from the
minimum input and desired output voltages, Rf is then
determined using Eq. 5. These values of Rf and Rg are
RRA
fgV
=∗∗
1
185.max Eq. 5
the minimum possible values that meet the input voltage
and maximum gain constraints. Scaling the resistor
values will decrease bandwidth and improve stability.
Application Discussion
http://www.national.com 4
Fig. 2 illustrates the resulting CLC522 bandwidths as a
function of the maximum and minimum input voltages
when Vout is held constant at 1V pp.
Adjusting Offsets
Treating the offsets introduced by the input and output
stages of the CLC522 is easily accomplished with a two
step process. The offset voltage of the output stage is
treated by first applying -1.1Volts on Vg, which effectively
isolates the input stage and multiplier core from the
output stage. As illustrated in Fig. 3, the trim pot located
at R14 on the CLC522 Evaluation Board should then be
adjusted in order to null the offset voltage seen at the
CLC522's output (pin 10). Once this is accomplished, the
offset errors introduced by the input stage and multiplier
core can then be treated. The second step requires the
absence of an input signal and matched source imped-
ances on the two input pins in order to cancel the bias
current errors. This done then +1.1Volts should be
applied to Vg and the trim pot located at R10 adjusted in
order to null the offset voltage seen at the CLC522's
output. If a more limited gain range is anticipated, the
above adjustments should be made at these operating
points.
Gain Errors
The CLC522's gain equation as theoretically expressed
in Eq. 2 must include the device's error terms in order to
yield the actual gain equation. Each of the gain error
Fig. 2
Fig. 3
terms are specified in the Electrical Characteristics table
and are defined below and illustrated in Fig. 4.
GACCU : error of AVmax , expressed as ±dB.
GCNL : deviation from theoretical expressed as ±%.
Vghigh : voltage on Vg producing AVmax .
Vglow : voltage on Vg producing AVmin = 0V/V.
∆Vghigh ,∆Vglow : error of Vghigh ,Vglow expresed as ±mV.
Combining these error terms with Eq. 2 gives the "gain
envelope" equation and is expressed in Eq. 7. From the
Electrical Characteristics table, the nominal endpoint
values of V g are: Vghigh =+990mV and Vglow = -975mV.
Signal-Channel Nonlinearity
Signal-channel nonlinearity, SGNL, also known as integral
endpoint linearity, measures the non-linearity of an
amplifier’s voltage transfer function. The CLC522's SGNL,
as it is specified in the Electrical Characteristics table, is
measured while the gain is set at its maximum (i.e.
Vg=+1.1V). The Typical Performance Characteristics
plot labled "SGNL & Gain vs Vg" illustrates the CLC522's
SGNL as Vg is swept through its full range. As can be
seen in this plot, when the gain as reduced from AVmax ,
SGNL improves to < 0.02%(-74dB) at Vg=0 and then
degrades somewhat at the lowest gains.
Noise
Fig. 5 describes the CLC522's input-refered spot noise
density as a function of AVmax . The plot includes all the
noise contributing terms. At AVmax = 10V/V, the CLC522
has a typical input-referred spot noise density (eni) of
5.8nV/√Hz. The input RMS voltage noise can be deter-
mined from the following single-pole model:
Eq. 8
Further discussion and plots of noise and the noise model
is provided in Application Note OA-23. Comlinear also
provides SPICE models that model internal noise and
other parameters for a typical part.
AVmax
AV
AVmin
Vglow Vghigh
Vg
±GCNL
±GACCU
±∆Vghigh
±∆Vglow
Fig. 4
Eq . 7
AA VV V
VVVV V GCNL
VV
GACCU
gg g
gggg g
low low
high high low low
=−±
()
±−±
()
±−
()
±
max
10 1
20 2
∆
∆∆
V e dB bandwidth
RMS in
=∗ ∗−
()
157 3.
5http://www.national.com
Component parasitics also influence high frequency
results, therefore it is recommended to use metal film
resistors such as RN55D or leadless components such
as surface mount devices. High profile sockets are not
recommended. If socketing is necessary, it is recom-
mended to use low impedance flush mount connector
jacks such as Cambion (P/N 450-2598).
Application Circuits
Four-Quadrant Multiplier
Applications requiring multiplication, squaring or other
non-linear functions can be implemented with four-quad-
rant multipliers. The CLC522 implements a four-quad-
rant multiplier as illustrated in figure 8.
Frequency Shaping
Frequency shaping and bandwidth extension of the
CLC522 can be accomplished using parallel networks
connected across the Rg ports. The network shown in the
Fig. 9 schematic will effectively extend the CLC522's
bandwidth.
2nd Order Tuneable Bandpass Filter
The CLC522 Variable-Gain Amplifier placed into feed-
back loops provide signal processing functions such as
2nd order tuneable bandpass filters. The center fre-
quency of the 2nd order bandpass illustrated on the front
page is adjusted through the use of the CLC522's gain-
control voltage, Vg. The integrators implemented with
two CLC420s, provide the coefficients for the transfer
function.
Voltage Noise (nV/√Hz)
Input Referred Voltage Noise vs A
Vmax
0 102030405060708090100
Maximum Gain Setting, A
Vmax
(V/V)
100
10
1
Circuit Layout Considerations
Please refer to the CLC522 Evaluation Board Literature
for precise layout guidelines. Good high-frequency op-
eration requires all of the de-coupling capcitors shown in
Fig. 6 to be placed as close as possible to the power
supply pins in order to insure a proper high-frequency
low-impedance bypass. Adequate ground plane and low-
inductive power returns are also required of the layout.
Minimizing the parasitic capacitances at pins 3, 4, 5, 6, 9,
10 and 12 as shown in Fig. 7 will assure best high
frequency performance. Vref (pin 9) to ground should
include a small resistor value of 25 ohms or greater to
buffer the internal voltage follower. The parasitic induc-
tance of component leads or traces to pins 4, 5 and 9
should also be kept to a minimum. Parasitic or load
capacitance, CL, on the output (pin 10) degrades phase
margin and can lead to frequency response peaking or
circuit oscillation. This should be treated with a small
series resistor between output (pin 10) and CL (see the
plot “Settling Time vs. Capacitive Load" for a recom-
mended series resistance).
Fig. 5
Fig. 6
Fig. 7
R
f
R
g
R
T
50Ω
50Ω
50Ω
V
baseband
V
out
V
carrier
25Ω
10
12
3
42
9
5
6
CLC522
R
m
=
2R
g
1.85
R
1
= R
T
|| R
m
|| R
s
R
1
R
s
R
T
=
R
m
R
s
R
m
-R
s
Fig. 8
Fig. 9
http://www.national.com 6
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7 http://www.national.com
CLC522
Wideband Variable-Gain Amplifier
http://www.national.com
8
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of the president of National Semiconductor Corporation. As used herein:
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sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
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Tel: 1(800) 272-9959 Deutsch Tel: (+49) 0-180-530 85 85 Tsimshatsui, Kowloon
Fax: 1(800) 737-7018 English Tel: (+49) 0-180-532 78 32 Hong Kong
Francais Tel: (+49) 0-180-532 93 58 Tel: (852) 2737-1600
Italiano Tel: (+49) 0-180-534 16 80 Fax: (852) 2736-9960
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.
