CLC5602IMX - National Semiconductor

CLC5602

Dual, High Output, Video Amplifier

General Description

The National CLC5602 has a new output stage that delivers

high output drive current (130mA), but consumes minimal

quiescent supply current (1.5mA/ch) from a single 5V supply.

Its current feedback architecture, fabricated in an advanced

complementary bipolar process, maintains consistent

performance over a wide range of gains and signal levels,

and has a linear phase response up to one half of the −3dB

frequency.

The CLC5602 offers a 0.1dB gain flatness to 22MHz and

differential gain and phase errors of 0.06

and 0.02%. These features are ideal for professional and

consumer video applications.

The CLC5602 offers superior dynamic performance with a

135MHz small-signal bandwidth, 300V/µs slew rate and a

5.7ns rise/fall times (2V

STEP

). The combination of low

quiescent power, high output current drive, and high speed

performance make the CLC5602 well suited for many

battery powered personal communication/computing sys-

tems.

The ability to drive low impedance, highly capacitive loads,

makes the CLC5602 ideal for single ended cable

applications. It also drives low impedance loads with

minimum distortion. The CLC5602 will drive a 100Ωload

with only −86/−85dBc second/third harmonic distortion (A

+2, V

OUT

=2V

, f = 1MHz). With a 25Ωload, and the same

conditions, it produces only −86/−72dBc second/third

harmonic distortion.

The CLC5602 can also be used for driving differential-input

step-up transformers for applications such as Asynchronous

Digital Subscriber Lines (ADSL) or High-Bit-Rate Digital

Subscriber Lines (HDSL).

When driving the input of high resolution A/D converters, the

CLC5602 provides excellent −87/−95dBc second/third

harmonic distortion (A

=+ 2, V

OUT

=2 V

, f =1 MHz, R

1kΩ) and fast settling time.

Features

n130mA output current

n0.06%, 0.02˚ differential gain, phase

n1.5mA/ch supply current

n135MHz bandwidth (A

=+2)

n−87/−95dBc HD2/HD3 (1MHz)

n15ns settling to 0.05%

n300V/µs slew rate

nStable for capacitive loads up to 1000pf

nSingle 5V or ±5V supplies

Applications

nVideo line driver

nADSL/HDSL driver

nCoaxial cable driver

nUTP differential line driver

nTransformer/coil driver

nHigh capacitive load driver

nPortable/battery powered applications

nDifferential A/D driver

Connection Diagram

Maximum Output Voltage vs. R

DS015000-1

DS015000-3

Pinout

DIP & SOIC

January 2001

CLC5602 Dual, High Output, Video Amplifier

Typical Application

Ordering Information

Package Temperature Range

Industrial Part Number Package

Marking NSC

Drawing

8-pin plastic DIP −40˚C to +85˚C CLC5602IN CLC5602IN N08E

8-pin plastic SOIC −40˚C to +85˚C CLC5602IM CLC5602IM M08A

CLC5602IMX CLC5602IM

DS015000-2

Recommended Inverting Gain Configuration

CLC5602

www.national.com 2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (V

-V

) +14V

Output Current (Note 4) 140mA

Common-Mode Input Voltage V

to V

Maximum Junction Temperature +150˚C

Storage Temperature Range −65˚C to +150˚C

Lead Temperature (soldering 10 sec) +300˚C

ESD (human body model) 1000V

Operating Ratings

Thermal Resistance

Package (θ

)(θ

)

MDIP 65˚C/W 130˚C/W

SOIC 50˚C/W 145˚C/W

+5V Electrical Characteristics

= +2, R

= 750Ω,R

= 100Ω,V

= +5V(Note 5), V

+(V

/2), R

tied to V

; unless specified

Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units

Ambient Temperature CLC5602IN/IM +25˚C +25˚C 0 to

70˚C −40 to

85˚C

Frequency Domain Response

-3dB Bandwidth V

= 0.5V

100 85 75 70 MHz

= 2.0V

65 60 55 50 MHz

−0.1dB Bandwidth V

= 0.5V

22 20 17 15 MHz

Gain Peaking <200MHz, V

= 0.5V

0 0.5 0.9 1.0 dB

Gain Rolloff <30MHz, V

= 0.5V

0.1 0.3 0.4 0.5 dB

Linear Phase Deviation <30MHz, V

= 0.5V

0.3 0.5 0.6 0.6 deg

Differential Gain NTSC, R

= 150Ωto −1V 0.04 – – – %

Differential Phase NTSC, R

= 150Ωto −1V 0.09 – – – deg

Time Domain Response

Rise and Fall Time 2V Step 6.1 8.5 9.2 10.0 ns

Settling Time to 0.05% 1V Step 25 35 50 80 ns

Overshoot 2V Step 10 20 22 22 %

Slew Rate 2V Step 220 190 165 150 V/µs

Distortion And Noise Response

2nd Harmonic Distortion 2V

,1MHz −77 −74 −71 −71 dBc

, 1MHz; R

=1KΩ−80 −77 −75 −70 dBc

, 5MHz −63 −59 −57 −57 dBc

3rd Harmonic Distortion 2V

,1MHz −85 −81 −78 −78 dBc

,1MHz; R

=1KΩ−82 −79 −76 −76 dBc

, 5MHz −62 −57 −54 −54 dBc

Equivalent Input Noise

Voltage (e

)>1MHz 3.4 4.4 4.9 4.9 nV/

Non-Inverting Current (i

)>1MHz 6.3 8.2 9.0 9.0 pA/

Inverting Current (i

)>1MHz 8.7 11.3 12.4 12.4 pA/

Crosstalk (Input Referred) 10MHz, 1V

−72 – – – dB

Static, DC Performance

Input Offset Voltage (Note 3) 1456mV

Average Drift 7 – 15 15 µV/˚C

Input Bias Current

(Non-Inverting) (Note 3) 5 121516µA

Average Drift 25 – 60 60 nA/˚C

Input Bias Current (Inverting)

(Note 3) 3 101213µA

Average Drift 10 – 20 20 nA/˚C

CLC5602

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+5V Electrical Characteristics (Continued)

= +2, R

= 750Ω,R

= 100Ω,V

= +5V(Note 5), V

+(V

/2), R

tied to V

; unless specified

Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units

Static, DC Performance

Power Supply Rejection Ratio DC 48 45 43 43 dB

Common Mode Rejection Ratio DC 49 47 45 45 dB

Supply Current Per Channel

(Note 3) R

=∞1.5 1.7 1.8 1.8 mA

Miscellaneous Performance

Input Resistance (Non-Inverting) 0.46 0.36 0.32 0.32 MΩ

Input Capacitance

(Non-Inverting) 1.8 2.75 2.75 2.75 pF

Input Voltage Range, High 4.2 4.1 4.1 4.0 V

Input Voltage Range, Low 0.8 0.9 0.9 1.0 V

Output Voltage Range, High R

= 100Ω4.0 3.9 3.9 3.8 V

Output Voltage Fange, Low R

= 100Ω1.0 1.1 1.1 1.2 V

Output Voltage Range, High R

=∞4.1 4.0 4.0 3.9 V

Output Voltage Range, Low R

=∞0.9 1.0 1.0 1.1 V

Output Current (Note 4) 100 80 65 40 mA

Output Resistance, Closed Loop DC 55 90 90 120 mΩ

±5V Electrical Characteristics

= +2, R

= 750Ω,R

= 100Ω,V

=±5V, unless specified.

Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units

Ambient Temperature CLC5602IN/IM +25˚C +25˚C 0 to

70˚C −40 to

85˚C

Frequency Domain Response

-3dB Bandwidth V

=1.0V

135 115 105 100 MHz

=4.0V

48 45 42 40 MHz

−0.1dB Bandwidth V

=1.0V

20 18 15 12 MHz

Gain Peaking <200MHz, V

=1.0V

0 0.5 0.9 1.0 dB

Gain Rolloff <30MHz, V

=1.0V

0.1 0.3 0.4 0.5 dB

Linear Phase Deviation <30MHz, V

= 1.0V

0.15 0.3 0.4 0.4 deg

Differential Gain NTSC, R

= 150Ω0.06 0.18 - - %

Differential Phase NTSC, R

= 150Ω0.02 0.04 - - deg

Time Domain Response

Rise and Fall Time 2V Step 5.7 6.2 6.8 7.3 ns

Settling Time to 0.05% 2V Step 15 25 40 60 ns

Overshoot 2V Step 18 20 22 22 %

Slew Rate 2V Step 300 225 190 175 V/µs

Distortion And Noise Response

2nd Harmonic Distortion 2V

, 1MHz −86 −82 −79 −79 dBc

, 1MHz; R

=1KΩ−87 −83 −80 −80 dBc

, 5MHz −70 −64 −61 −60 dBc

3rd Harmonic Distortion 2V

, 1MHz −85 −81 −78 −78 dBc

,1MHz; R

=1KΩ−95 −90 −87 −87 dBc

, 5MHz −66 −64 −61 −60 dBc

Equivalent Input Noise

CLC5602

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±5V Electrical Characteristics (Continued)

= +2, R

= 750Ω,R

= 100Ω,V

=±5V, unless specified.

Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units

Distortion And Noise Response

Voltage (e

)>1MHz 3.4 4.4 4.9 4.9 nV/

Non-Inverting Current (i

)>1MHz 6.3 8.2 9.0 9.0 pA/

Inverting Current (i

)>1MHz 8.7 11.3 12.4 12.4 pA/

Crosstalk (Input Referred) 10MHz, 1V

−72 - - - dB

Static, DC Performance

Input Offset Voltage 2678mV

Average Drift 8 - - - µV/˚C

Input Bias Current

(Non-Inverting) 5 121617µA

Average Drift 40 - - - nA/˚C

Input Bias Current (Inverting) 8 24 28 28 µA

Average Drift 20 - 45 45 nA/˚C

Power Supply Rejection Ratio DC 48 45 43 43 dB

Common Mode Rejection Ratio DC 51 49 47 47 dB

Supply Current (Per Channel) R

=∞1.6 1.9 2.0 2.0 mA

Miscellaneous Performance

Input Resistance (Non-Inverting) 0.59 0.47 0.43 0.43 MΩ

Input Capacitance

(Non-Inverting) 1.45 2.15 2.15 2.15 pF

Common Mode Input Range ±4.2 ±4.1 ±4.1 ±4.0 V

Output Voltage Range R

= 100Ω±3.8 ±3.6 ±3.6 ±3.5 V

Output Voltage Range R

=∞±4.0 ±3.8 ±3.8 ±3.7 V

Output Current 130 100 80 50 mA

Output Resistance, Closed Loop DC 40 70 70 90 mΩ

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined

from tested parameters.

Note 3: AJ-level: spec. is 100% tested at +25˚C.

Note 4: The short circuit current can exceed the maximum safe output current

Note 5: VS=V

CC −V

CLC5602

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Typical Performance Characteristics (A

= +2, R

= 750Ω,R

= 100Ω,V

= +5V

M=V

/2), R

tied to V

, unless specified)

Non-Inverting Frequency Response

Normalized Magnitude (1dB/div)

Frequency (Hz)

1M 10M 100M

Phase (deg)

-90

-180

-450

-270

-360

Gain

Phase

Vo = 0.5Vpp

Av = +1

Rf = 1.0kΩ

Av = +2

Rf = 649Ω

Av = +5

Rf = 301Ω

Av = +10

Rf = 200Ω

DS015000-4

Inverting Frequency Response

Normalized Magnitude (1dB/div)

Frequency (Hz)

1M 10M 100M

Phase (deg)

135

180

-45

Gain

Phase

Vo = 0.5Vpp

Av = -2

Rf = 649Ω

Av = -1

Rf = 649Ω

Av = -5

Rf = 649Ω

Av = -10

Rf = 500Ω

DS015000-5

Frequency Response vs. R

Magnitude (1dB/div)

Frequency (Hz)

1M 10M 100M

Phase (deg)

-90

-180

-450

-270

-360

Gain

Phase

Vo = 0.5Vpp

RL = 25Ω

RL = 100Ω

RL = 1kΩ

DS015000-6

Frequency Response vs. V

Magnitude (1dB/div)

Frequency (Hz)

1M 10M 100M

Vo = 2Vpp

Vo = 1Vpp

Vo = 0.1Vpp

DS015000-7

Gain Flatness & Linear Phase

Magnitude (0.05dB/div)

Frequency (MHz)

10 20 30

Phase (deg)

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

Gain

Phase

DS015000-8

Open Loop Transimpedance Gain Z(s)

Magnitude (dBΩ)

Frequency (Hz)

1k 10k 100k 1M 10M 100M

Gain

Phase (deg)

135

180

225

100

120

Phase

DS015000-9

CLC5602

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Typical Performance Characteristics (A

= +2, R

= 750Ω,R

= 100Ω,V

= +5V

M=V

(VS/2), R

tied to V

, unless specified) (Continued)

PSRR & CMRR

PSRR & CMRR (dB)

Frequency (Hz)

1k 10k 100M

100k 1M 10M

PSRR

CMRR

DS015000-10

Equivalent Input Noise

Noise Voltage (nV/√Hz)

Frequency (Hz)

3.6

3.5

3.4

10k 100k 1M 10M

3.3

3.2

Non-Inverting Current 7pA/√Hz

Inverting Current 8.7pA/√Hz

Voltage 3.35nV/√Hz

Noise Current (pA/√Hz)

12.5

7.5

2.5

DS015000-11

2nd & 3rd Harmonic Distortion

Distortion (dBc)

Frequency (Hz)

1M 10M

-100

-90

-80

-70

-60

-50

-40

-30

2nd

RL = 1kΩ

2nd

RL = 100Ω

3rd

RL = 100Ω

3rd

RL = 1kΩ

Vo = 2Vpp

DS015000-12

2nd & 3rd Harmonic Distortion, R

=25Ω

Distortion (dBc)

Output Amplitude (Vpp)

0 0.5 1 1.5 2 2.5

-90

-80

-70

-60

-50

-40

-30

-20

3rd, 10MHz

2nd, 1MHz

2nd, 10MHz

3rd, 1MHz

DS015000-13

2nd & 3rd Harmonic Distortion, R

=100Ω

Distortion (dBc)

Output Amplitude (Vpp)

0 0.5 1 1.5 2 2.5

-100

-90

-80

-70

-60

-50

-40

3rd, 10MHz

2nd, 1MHz

2nd, 10MHz

3rd, 1MHz

DS015000-14

2nd & 3rd Harmonic Distortion, R

=1kΩ

Distortion (dBc)

Output Amplitude (Vpp)

0 0.5 1 1.5 2 2.5

-100

-90

-80

-70

-60

-50

3rd, 10MHz

2nd, 1MHz

2nd, 10MHz

3rd, 1MHz

DS015000-15

CLC5602

www.national.com7

Typical Performance Characteristics (A

= +2, R

= 750Ω,R

= 100Ω,V

= +5V

M=V

(VS/2), R

tied to V

, unless specified) (Continued)

Large & Small Signal Pulse Response

Output Voltage (0.5V/div)

Time (10ns/div)

Large Signal

Small Signal

DS015000-16

Closed Loop Output Resistance

Output Resistance (Ω)

Frequency (Hz)

10k 100k 1M 10M 100M

0.01

0.1

100

VCC = ±5V

DS015000-17

vs. Temperature

Offset Voltage VIO (mV)

Temperature (ϒC)

-60 -20 20 60 100 140

-1.5

IBI, IBN (µA)

-3

-1.0 -2

-0.5 -1

0.5 1

1.0 2

-1.5 3

IBN

IBI

VIO

DS015000-18

Frequency Response

Normalized Magnitude (1dB/div)

Frequency (Hz)

1M 10M 100M

Phase (deg)

-45

-90

-225

-135

-180

Gain

Phase

Vo = 1.0Vpp

Av = +1

Rf = 1.0kΩ

Av = +2

Rf = 649Ω

Av = +5

Rf = 301Ω

Av = +10

Rf = 200Ω

DS015000-19

Inverting Frequency Response

Normalized Magnitude (1dB/div)

Frequency (Hz)

1M 10M 100M

Phase (deg)

135

180

-45

Gain

Phase Av = -1

Rf = 649Ω

Av = -2

Rf = 649Ω

Av = -5

Rf = 649Ω

Av = -10

Rf = 500Ω

Vo = 1.0Vpp

DS015000-20

Frequency Response vs. R

Magnitude (1dB/div)

Frequency (Hz)

1M 10M 100M

Phase (deg)

-90

-180

-450

-270

-360

Gain

Phase

Vo = 1.0Vpp

RL = 1kΩ

RL = 100Ω

RL = 25Ω

DS015000-21

CLC5602

www.national.com 8

Typical Performance Characteristics (A

= +2, R

= 750Ω,R

= 100Ω,V

= +5V

M=V

(VS/2), R

tied to V

, unless specified) (Continued)

Frequency Response vs. V

Magnitude (1dB/div)

Frequency (Hz)

1M 10M 100M

Vo = 2Vpp

Vo = 0.1Vpp

Vo = 1Vpp

Vo = 5Vpp

DS015000-22

Gain Flatness & Linear Phase

Magnitude (0.1dB/div)

Frequency (MHz)

0525

0.3

0.4

0.2

-0.1

0.1

Gain

Phase

10 15 20 30

DS015000-23

Small Signal Pulse Response

Amplitude (200mV/div)

Time (10ns/div)

Av = +2

Av = -2

DS015000-24

Large Signal Pulse Response

Amplitude (0.5V/div)

Time (20ns/div)

Av = +2

Av = -2

DS015000-25

Differential Gain and Phase

Gain (%)

Number of 150 Ω Loads

1234

Phase (deg)

-0.2

-0.16

-0.12

-0.08

-0.04

-0.2

-0.16

-0.12

-0.08

-0.04

Phase Neg Sync

Phase Pos Sync

Gain Pos Sync

Gain Neg Sync

DS015000-26

2nd & 3rd Harmonic Distortion vs. Frequency

DS015000-27

CLC5602

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Typical Performance Characteristics (A

= +2, R

= 750Ω,R

= 100Ω,V

= +5V

M=V

(VS/2), R

tied to V

, unless specified) (Continued)

2nd & 3rd Harmonic Distortion, R

=25Ω

Distortion (dBc)

Output Amplitude (Vpp)

01234

-100

-90

-80

-70

-60

-50

-40

-30

3rd, 10MHz

2nd, 1MHz

2nd, 10MHz

3rd, 1MHz

DS015000-28

2nd & 3rd Harmonic Distortion, R

=100Ω

Distortion (dBc)

Output Amplitude (Vpp)

0 0.5 1 1.5 2 2.5

-110

-100

-90

-80

-70

-60

-50

-40

3rd, 10MHz

2nd, 1MHz

2nd, 10MHz

3rd, 1MHz

DS015000-29

2nd & 3rd Harmonic Distortion, R

=1kΩ

Distortion (dBc)

Output Amplitude (Vpp)

012345

-110

-100

-90

-80

-70

-60

-50

3rd, 10MHz

2nd, 1MHz

2nd, 10MHz

3rd, 1MHz

DS015000-30

Short Term Settling Time

Vo (% Output Step)

Time (ns)

1 10 100 1000 10000

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

DS015000-31

Long Term Settling Time

Vo (% Output Step)

Time (s)

100

1m 100m

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

10m

DS015000-32

vs. Temperature

Offset Voltage VOS(mV)

Temperature (ϒC)

-60 -20 20 60 100 140

0.8

IBI, IBN (µA)

-3

0.9 -2

1- 1

1.1 0

1.2 1

1.3 2

1.4 3

IBN

IBI

VOS

DS015000-33

CLC5602

www.national.com 10

Typical Performance Characteristics (A

= +2, R

= 750Ω,R

= 100Ω,V

= +5V

M=V

(VS/2), R

tied to V

, unless specified) (Continued)

Application Division

The CLC5602 is a current feedback amplifier fabricated in an

advanced complementary bipolar process. The CLC5602

operates from a single 5V supply or dual ±5V supplies.

Operating from a single supply, the CLC5602 has the

following features:

•Provides 100mA of output current while consuming

7.5mW of power

•Offers low −80/−82dB 2nd and 3rd harmonic distortion

•Provides BW60MHz and 1MHz distortion <−65dBc at V

= 2.0V

The CLC5602 performance is further enhanced in ±5V

supply applications as indicated in the ±5V Electrical

Characteristics table and ±5V Typical Performance plots.

Current Feedback Amplifiers

Some of the key features of current feedback technology

are:

•Independence of AC bandwidth and voltage gain

•Inherently stable at unity gain

•Adjustable frequency response with feedback resistor

•High slew rate

•Fast settling

Current feedback operation can be described using a simple

equation. The voltage gain for a non-inverting or inverting

current feedback amplifier is approximately by Equation 1.

Z(j )

=+ω(1)

where:

•A

is the closed loop DC voltage gain

•R

is the feedback resistor

•Z(jω) is the CLC5602’s open loop transimpedance gain

•Z(jω)/R

is the loop gain

The denominator of Equation 1 is approximately equal to 1 at

low frequencies. Near the −3dB corner frequency, the

interaction between R

and Z(jω) dominates the circuit

performance. The value of the feedback resistor has a large

affect on the circuits performance. Increasing R

has the

following affects:

•Decreases loop gain

•Decreases bandwidth

•Reduces gain peaking

Channel Matching

Magnitude (0.5dB/div)

Frequency (Hz)

1M 10M 100M

Channel 1

Channel 2

DS015000-34

Input Referred Crosstalk

Magnitude (dB)

Frequency (Hz)

1M 10M 100M

-90

-80

-70

-60

-50

-40

-20

-30

Vo = 1Vpp

DS015000-35

Pulse Crosstalk

Active Channel

Amplitude (0.2V/div)

Time (10ns/div)

Inactive Channel

Amplitude (20mV/div)

Active Output

Channel

Inactive Output

Channel

DS015000-36

CLC5602

www.national.com11

Application Division (Continued)

•Lowers pulse response overshoot

•Affects frequency response phase linearity

Refer to the Feedback Resistor Selection section for more

details on selecting a feedback resistor value.

CLC5602 Design Information

Single Supply Operation (V

=+5V, V

=GND) The

specifications given in the +5V Electrical Characteristics

table for single supply operation are measured with a

common mode voltage (V

) of 2.5V. V

is the voltage

around which the inputs are applied and the output voltages

are specified.

Operating from a single +5V supply, the Common Mode

Input Range (CMIR) of the CLC5602 is typically +0.8V to

+4.2V. The typical output range with R

=100Ωis +1.0V to

+4.0V.

For single supply DC coupled operation, keep input signal

levels above 0.8V DC. For input signals that drop below 0.8V

DC, AC coupling and level shifting the signal are

recommended. The non-inverting and inverting configura-

tions for both input conditions are illustrated in the following

2 sections.

DC Coupled Single Supply Operation

Figure 1

and

Figure

show the recommended non-inverting and inverting

configurations for input signals that remain above 0.8V DC.

AC Coupled Single Supply Operation

Figure 3

and

Figure 4

show possible non-inverting and

inverting configurations for input signals that go below 0.8V

DC. The input is AC coupled to prevent the need for level

shifting the input signal at the source. The resistive voltage

divider biases the non-inverting input to V

÷ 2 = 2.5V (For

= +5V).

Dual Supply Operation

The CLC5602 operates on dual supplies as well as single

supplies. The non-inverting and inverting configurations are

shown in

Figure 5

and

Figure 6

1/2

CLC5602

0.1µF

6.8µF

Vin

VA1

in vf

==+

VCC

Vcm

Note: Rt, RL and Rg are tied

to Vcm for minimum power

consumption and maximum

output swing.

Vcm DS015000-39

FIGURE 1. Non-Inverting Configuration

-Rf

0.1µF

6.8µF

Vin

Rb4

VAR

in vf

==−

VCC

Vcm

Note: Rb, provides DC bias

for non-inverting input.

Rb, RL and Rt are tied

to Vcm for minimum power

consumption and maximum

output swing.

Vcm

Select Rt to yield

desired Rin = Rt || Rg

1/2

CLC5602

DS015000-40

FIGURE 2. Inverting Configuration

-Rf

0.1µF

6.8µF

Vin

CcR

VV1

R2.5

oin f











low frequency cutoff 1

2RC,where: R R

in cin

πRR

source

VCC

1/2

CLC5602

DS015000-41

FIGURE 3. AC Coupled Non-Inverting Configuration

-Rf

0.1µF

6.8µF

Vin

VV R

R2.5

oin f

=−











low frequency cutoff 1

2RC

=π

VCC

1/2

CLC5602

DS015000-42

FIGURE 4. AC Coupled Inverting Configuration

-Rf

0.1µF

6.8µF

Vin

VCC

0.1µF

6.8µF

VEE

VA1

in vf

==+

1/2

CLC5602

DS015000-43

FIGURE 5. Dual Supply Non-Inverting Configuration

CLC5602

www.national.com 12

Application Division (Continued)

Feedback Resistor Selection

The feedback resistor, R

, affects the loop gain and

frequency response of a current feedback amplifier.

Optimum performance of the CLC5602, at a gain of +2V/V, is

achieved with R

equal to 750Ω. The frequency response

plots in the Typical Performance sections illustrate the

recommended R

for several gains. These recommended

values of R

provide the maximum bandwidth with minimal

peaking. Within limits, R

can be adjusted to optimize the

frequency response.

•Decrease R

to peak frequency response and extend

bandwidth

•Increase R

to roll off frequency response and compress

bandwidth

As a rule of thumb, if the recommended R

is doubled, then

the bandwidth will be cut in half.

Unity Gain Operation

The recommended R

for unity gain (+1V/V) operation is

1kΩ.R

is left open. Parasitic capacitance at the inverting

node may require a slight increase in R

to maintain a flat

frequency response.

Load Termination

The CLC5602 can source and sink near equal amounts of

current. For optimum performance, the load should be tied to

Driving Cables and Capacitive Loads

When driving cables, double termination is used to prevent

reflections. For capacitive load applications, a small series

resistor at the output of the CLC5602 will improve stability

and settling performance. The Frequency Response vs. C

plot, shown below in

Figure 7

, gives the recommended

series resistance value for optimum flatness at various

capacitive loads.

Transmission Line Matching

One method for matching the characteristic impedance (z

)

of a transmission line or cable is to place the appropriate

resistor at the input or output of the amplifier.

Figure 8

shows typical inverting and non-inverting circuit

configurations for matching transmission lines.

Non-inverting gain applications:

•Connect R

directly to ground.

•Make R

, and R

equal to Z

•Use R

to isolate the amplifier from reactive loading

caused by the transmission line, or by parasitics.

Inverting gain applications:

•Connect R

directly to ground.

•Make R

, and R

equal to Z

•Make R

,IIR

The input and output matching resistors attenuate the signal

by a factor of 2, therefore additional gain is needed. Use C

to match the output transmission line over a greater

frequency range. C

compensates for the increase of the

amplifier’s output impedance with frequency.

Power Dissipation

Follow these steps to determine the power consumption of

the CLC5602:

1. Calculate the quiescent (no-load) power: P

amp

)

2. Calculate the RMS power at the output stage:

=(V

-V

load

)(I

load

), where V

load

and I

load

are the RMS

voltage and current across the external load.

3. Calculate the total RMS power: P

amp

-Rf

0.1µF

6.8µF

Vin

VCC

0.1µF

6.8µF

VEE

Rb3

Note: Rb provides DC bias

for the non-inverting input.

Select Rt to yield desired

Rin = Rt || Rg.

VAR

in vf

==−

1/2

CLC5602

DS015000-44

FIGURE 6. Dual Supply Inverting Configuration

Magnitude (1dB/div)

Frequency (Hz)

1M 10M 100M

Vo = 1Vpp CL = 10pF

Rs = 46.4Ω

CL = 100pF

Rs = 20Ω

CL = 1000pF

Rs = 6.7Ω

CL1k

-1k

DS015000-45

FIGURE 7. Frequency Response vs. C

R3Z0

V2+

1/2

CLC5602

DS015000-46

FIGURE 8. Transmission Line Matching

CLC5602

www.national.com13

Application Division (Continued)

The maximum power that the DIP and SOIC packages can

dissipate at a given temperature is illustrated in

Figure 9

The power derating curve for any CLC5602 package can be

derived by utilizing the following equation:

where T

amb

= Ambient temperature (˚C)

= Thermal resistance, from junction to ambient, for a

given package (˚C/W)

Layout Considerations

A proper printed circuit layout is essential for achieving high

frequency performance. National provides evaluation boards

for the CLC5602 (CLC730038-DIP, CLC730036-SOIC) and

suggests their use as a guide for high frequency layout and

as an aid for device testing and characterization.

General layout and supply bypassing play major roles in high

frequency performance. Follow the steps below as a basis

for high frequency layout:

•Include 6.8µF tantalum and 0.1µF ceramic capacitors on

both supplies.

•Place the 6.8µF capacitors within 0.75 inches of the

power pins.

•Place the 0.1µF capacitors less than 0.1 inches from the

power pins.

•Remove the ground plane under and around the part,

especially near the input and output pins to reduce

parasitic capacitance.

•Minimize all trace lengths to reduce series inductances.

•Use flush-mount printed circuit board pins for prototyping,

never use high profile DIP sockets.

Evaluation Board Information

A data sheet is available for the CLC730038/CLC730036

evaluation boards. The evaluation board data sheet

provides:

•Evaluation board schematics

•Evaluation board layouts

•General information about the boards

The evaluation boards are designed to accommodate dual

supplies. The boards can be modified to provide single

supply operation. For best performance; 1) do not connect

the unused supply, 2) ground the unused supply pin.

SPICE Models

SPICE models provide a means to evaluate amplifier

designs. Free SPICE models are available for National’s

monolithic amplifiers that:

•Support Berkeley SPICE 2G and its many derivatives

•Reproduce typical DC, AC, Transient, and Noise

performance

•Support room temperature simulations

The readme file that accompanies the diskette lists released

models, and provides a list of modeled parameters. The

application note OA-18, Simulation SPICE Models for

National’s Op Amps, contains schematics and a

reproduction of the readme file.

Application Circuits

Single Supply Cable Driver

The typical application shown below shows one of the

CLC5602 amplifiers driving 10m of 75Ωcoaxial cable. The

CLC5602 is set for a gain of +2V/V to compensate for the

divide-by-two voltage drop at V

Single Supply Lowpass Filter

Figure 12

and

Figure 13

illustrate a lowpass filter and design

equations. The circuit operates from a single supply of +5V.

The voltage divider biases the non-inverting input to 2.5V.

And the input is AC coupled to prevent the need for level

shifting the input signal at the source. Use the design

equations to determine R

, and C

based on the

desired Q and corner frequency.

DS015000-48

FIGURE 9. Power Derating Curves

1/2

CLC5602

1kΩ

0.1µF

6.8µF

Vin

+5V

1kΩ

5kΩ

0.1µF

10m of 75Ω

Coaxial Cable

75Ω

0.1µF75Ω

0.1µF

DS015000-49

FIGURE 10. Single Supply Cable Driver

100mV/div

20ns/div

Vin = 10MHz, 0.5Vpp

DS015000-50

FIGURE 11. Response After 10m of Cable

CLC5602

www.national.com 14

Application Division (Continued)

This example illustrates a lowpass filter with Q = 0.707 and

corner frequency f

= 10MHz. A Q of 0.707 was chosen to

achieve a maximally flat, Butterworth response.

Figure 14

indicates the filter response.

Differential Line Driver with Load Impedance Conver-

sion

The circuit shown in the Typical Application schematic on

the front page and in

Figure 15

, operates as a differential line

driver. The transformer converts the load impedance to a

value that best matches the CLC5602’s output capabilities.

The single-ended input signal is converted to a differential

signal by the CLC5602. The line’s characteristic impedance

is matched at both the input and the output. The schematic

shows Unshielded Twisted Pair for the transmission line;

other types of lines can also be driven.

Set up the CLC5602 as a difference amplifier:

V21

=⋅+











=⋅

Make the best use of the CLC5602’s output drive capability

as follows:

RR 2V

meq max

max

⋅

where R

is the transformed value of the load impedance,

max

is the Output Voltage Range, and I

max

is the maximum

Output Current.

Match the line’s characteristic impedance:

meq

Select the transformer so that it loads the line with a value

very near Z

over frequency range. The output impedance of

the CLC5602 also affects the match. With an ideal

transformer we obtain:

ReturnLoss 20 log nZ j

Z,dB

2o 5602

=− ⋅ ⋅

()

where Z

O(5602)

(jω) is the output impedance of the CLC5602

and |Z

O(5602)

(jω)| << R

The load voltage and current will fall in the ranges:

-Rf

1kΩ

0.1µF

C1Vo

Vin

5kΩ4

0.1µF

0.1µF5kΩ

+5V

0.1µF

100Ω

1.698kΩ

158ΩR2

158Ω

100pF

1/2

CLC5602

DS015000-51

FIGURE 12. Lowpass Filter Topology

Gain K 1 R

Corner frequency 1

RR CC

RC RC

RC (1 K) RC

For R R R and C C C

(3 K)

c1212

12 12

==+

=++−

== ==

−

DS015000-52

FIGURE 13. Design Equations

Magnitude (dB)

Frequency (Hz)

-21

-15

-9

-3

1M 10M 100M

DS015000-53

FIGURE 14. Lowpass Response

1/2

CLC5602

Rg2

Rt2

Rf2

Rf1

Rg1

1/2

CLC5602

Vin

Rt1 Rm/2

Rm/2

UTP

Req

1:n

Vd/2

-Vd/2

DS015000-54

FIGURE 15. Differential Line Driver with Load

Impedance Conversion

CLC5602

www.national.com15

Application Division (Continued)

VnV

≤⋅

≤

max

The CLC5602’s high output drive current and low distortion

make it a good choice for the application.

Full Duplex Cable Driver

The circuit shown in Fig 16 below, operates as a full duplex

cable driver which allows simultaneous transmission and

reception of signals on one transmission line. The circuit on

either side of the transmission line uses are CLC5602 as a

cable driver, and the second CLC5602 as a receiver. V

an attenuated version of Vi

, while V

is an attenuated of

inB

is used to match the transmission line. R

and R

set

the DC gain of the CLC5602, which is used in a difference

mode. R

provides good CMRR and DC offset. The

transmitting CLC5602’s are shown in a unity gain

configuration because they consume the least power of any

gain, for a given load. For proper operation we need R

The receiver output voltage are:

VVA

Z(j)

outA(B) inA(B) inB(A) f2

o(5602)

≈⋅+⋅−+











where A is the attenuation of the cable, Z

O(5602)

(jω)isthe

output impedance of the CLC5602 (see the

Close-Loop

Output Resistance

plot), and |Z

O(5602)

(jω)| << R

We selected the component values as follows:

•R

= 1.0kΩ, the recommended value for the CLC5602 at

unity gain

•R

=50Ω, the characteristic impedance of the

transmission line

•R

= 750Ω≥R

, the recommended value for the

CLC5602 at A

R(R||R)±

225

t2 f2 g2 m1

==Ω

These values give excellent isolation from the other input:

V38dB, f 5.0MHz

oA(B)

inB(A) ≈− =

The CLC5602 provides large output current drive, while

consuming little supply current, at the nominal bias point. It

also produces low distortion with large signal swings and

heavy loads. These features make the CLC5602 an

excellent choice for driving transmission lines.

Rf1

Rt1

Rf2

1/2

CLC5602

VinA

Rg2

Rt2

Rm1

VoB

Rf1

Rt1

Rf2

VinB

Rg2

Rt2

Rm1

VoA

1/2

CLC5602

1/2

CLC5602

1/2

CLC5602

DS015000-60

Full Duplex Cable Driver

CLC5602

www.national.com 16

Physical Dimensions inches (millimeters) unless otherwise noted

8-Pin SOIC

NS Package Number M08A

8-Pin MDIP

NS Package Number N08E

CLC5602

www.national.com17

Notes

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe Fax: +49 (0) 180-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

Email: ap.support@nsc.com

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

www.national.com

CLC5602 Dual, High Output, Video Amplifier

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.