PD - 91257D IRLML2402 HEXFET(R) Power MOSFET l l l l l l l Generation V Technology Ultra Low On-Resistance N-Channel MOSFET SOT-23 Footprint Low Profile (<1.1mm) Available in Tape and Reel Fast Switching D VDSS = 20V G RDS(on) = 0.25 S Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. A customized leadframe has been incorporated into the standard SOT-23 package to produce a HEXFET Power MOSFET with the industry's smallest footprint. This package, dubbed the Micro3, is ideal for applications where printed circuit board space is at a premium. The low profile (<1.1mm) of the Micro3 allows it to fit easily into extremely thin application environments such as portable electronics and PCMCIA cards. Micro3 Absolute Maximum Ratings Parameter I D @ TA = 25C I D @ TA = 70C IDM PD @TA = 25C VGS dv/dt TJ, TSTG Max. Continuous Drain Current, V GS @ 4.5V Continuous Drain Current, V GS @ 4.5V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Junction and Storage Temperature Range Units 1.2 0.95 7.4 540 4.3 12 5.0 -55 to + 150 A mW mW/C V V/ns C Thermal Resistance Parameter RJA Maximum Junction-to-Ambient Typ. Max. Units 230 C/W 01/15/03 http://store.iiic.cc/ IRLML2402 Electrical Characteristics @ TJ = 25C (unless otherwise specified) V(BR)DSS/TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) g fs Gate Threshold Voltage Forward Transconductance IDSS Drain-to-Source Leakage Current V(BR)DSS IGSS Qg Qgs Qgd t d(on) tr t d(off) tf Ciss Coss Crss Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. 20 0.70 1.3 Typ. 0.024 2.6 0.41 1.1 2.5 9.5 9.7 4.8 110 51 25 Max. Units Conditions V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 1mA 0.25 VGS = 4.5V, ID = 0.93A 0.35 VGS = 2.7V, ID = 0.47A V VDS = VGS, ID = 250A S VDS = 10V, ID = 0.47A 1.0 VDS = 16V, VGS = 0V A 25 VDS = 16V, VGS = 0V, TJ = 125C -100 VGS = -12V nA 100 VGS = 12V 3.9 ID = 0.93A 0.62 nC VDS = 16V 1.7 VGS = 4.5V, See Fig. 6 and 9 VDD = 10V ID = 0.93A ns RG = 6.2 RD = 11, See Fig. 10 VGS = 0V pF VDS = 15V = 1.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics IS I SM VSD t rr Q rr Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Min. Typ. Max. Units 0.54 7.4 25 16 1.2 38 24 A V ns nC Conditions MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 0.93A, VGS = 0V TJ = 25C, IF = 0.93A di/dt = 100A/s Notes: Repetitive rating; pulse width limited by Pulse width 300s; duty cycle 2%. ISD 0.93A, di/dt 90A/s, VDD V(BR)DSS, Surface mounted on FR-4 board, t 5sec. max. junction temperature. ( See fig. 11 ) TJ 150C http://store.iiic.cc/ D G S IRLML2402 100 100 VGS 7.5V 5.0V 4.0V 3.5V 3.0V 2.5V 2.0V BOTTOM 1.5V 10 1 0.1 1.5V 20s PULSE WIDTH TJ = 25C A 0.01 0.1 1 10 1 1.5V 0.1 R DS(on) , Drain-to-Source On Resistance (Normalized) 2.0 I D , Drain-to-Source Current (A) TJ = 25C TJ = 150C 1 0.1 V DS = 10V 20s PULSE WIDTH 2.5 3.0 3.5 10 Fig 2. Typical Output Characteristics 10 2.0 1 VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 0.01 20s PULSE WIDTH TJ = 150C A 0.01 0.1 10 VDS , Drain-to-Source Voltage (V) 1.5 VGS 7.5V 5.0V 4.0V 3.5V 3.0V 2.5V 2.0V BOTTOM 1.5V TOP I , Drain-to-Source Current (A) D I , Drain-to-Source Current (A) D TOP A 4.0 VGS , Gate-to-Source Voltage (V) I D = 0.93A 1.5 1.0 0.5 0.0 -60 -40 -20 VGS = 4.5V 0 20 40 60 TJ , Junction Temperature (C) Fig 4. Normalized On-Resistance Vs. Temperature Fig 3. Typical Transfer Characteristics http://store.iiic.cc/ A 80 100 120 140 160 IRLML2402 200 V GS, Gate-to-Source Voltage (V) 160 C, Capacitance (pF) 10 V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd Ciss 120 Coss 80 Crss 40 0 10 8 6 4 2 0 0.0 A 1 I D = 0.93A VDS = 16V 100 1.0 2.0 3.0 A 4.0 Q G , Total Gate Charge (nC) VDS , Drain-to-Source Voltage (V) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 10 100 OPERATION IN THIS AREA LIMITED BY R DS(on) TJ = 150C I D , Drain Current (A) ISD , Reverse Drain Current (A) FOR TEST CIRCUIT SEE FIGURE 9 1 TJ = 25C 0.1 VGS = 0V 0.01 0.2 0.4 0.6 0.8 1.0 1.2 A 1.4 10 100s 1 1ms TA = 25C TJ = 150C Single Pulse 0.1 1 10ms A 10 VDS , Drain-to-Source Voltage (V) VSD , Source-to-Drain Voltage (V) Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage http://store.iiic.cc/ 100 IRLML2402 4.5V RD V DS QG VGS QGS QGD D.U.T. RG VG + - VDD 4.5V Pulse Width 1 s Duty Factor 0.1 % Charge Fig 9a. Basic Gate Charge Waveform Fig 10a. Switching Time Test Circuit Current Regulator Same Type as D.U.T. VDS 50K 90% .2F 12V .3F + V - DS D.U.T. 10% VGS VGS 3mA td(on) IG tr t d(off) tf ID Current Sampling Resistors Fig 9b. Gate Charge Test Circuit Fig 10b. Switching Time Waveforms Thermal Response (Z thJA ) 1000 100 D = 0.50 0.20 0.10 0.05 10 0.02 PDM 0.01 t1 SINGLE PULSE (THERMAL RESPONSE) 1 0.1 0.00001 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJA + TA 0.0001 0.001 0.01 0.1 1 10 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient http://store.iiic.cc/ 100 IRLML2402 Peak Diode Recovery dv/dt Test Circuit Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + D.U.T + - - + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test Driver Gate Drive P.W. Period D= + - VDD P.W. Period VGS=10V D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple 5% * VGS = 5V for Logic Level Devices Fig 12. For N-Channel HEXFETS http://store.iiic.cc/ ISD * IRLML2402 Package Outline Micro3 (SOT-23 / TO-236AB) Dimensions are shown in millimeters (inches) D -B- 3 E -A- LEAD ASSIGNMENTS 1 - GATE 2 - SOURCE 3 - DRAIN 3 3 DIM A H 1 0.20 ( .008 ) 2 M A M e e1 A -CB 0.10 (.004) 0.008 (.003) A1 3X M C 3X L 3X C AS B S INCHES MIN .032 MILLIMETERS MAX .044 MIN 0.82 MAX 1.11 A1 .001 .004 0.02 0.10 B .015 .021 0.38 0.54 C .004 .006 0.10 0.15 D .105 .120 2.67 3.05 e .0750 BASIC 1.90 BASIC e1 .0375 BASIC 0.95 BASIC E .047 .055 1.20 1.40 H .083 .098 2.10 2.50 L .005 .010 0.13 0.25 0 8 0 8 MINIMUM RECOMMENDED FOOTPRINT 0.80 ( .031 ) 3X 0.90 ( .035 ) 3X 2.00 ( .079 ) NOTES: 1. DIMENSIONING & TOLERANCING PER ANSI Y14.5M-1982. 2. CONTROLLING DIMENSION : INCH. 3 DIMENSIONS DO NOT INCLUDE MOLD FLASH. 0.95 ( .037 ) 2X Part Marking Information Micro3 (SOT-23 / TO-236AB) 1RWHV7KLVSDUWPDUNLQJLQIRUPDWLRQDSSOLHVWRGHYLFHVSURGXFHGDIWHU 1RWHV7KLVSDUWPDUNLQJLQIRUPDWLRQDSSOLHVWRGHYLFHVSURGXFHGEHIRUH :: ,)35(&('('%