Preliminary Data Sheet V2.2 - Infineon Technologies

ICs for Communications

PC I I nt er face f or Telephony/Data Appl icat i on s

PITA-2

PSB 4610 Ver sion 2.2

Prel im i nar y Dat a Sheet 01.00 DS 1

For questions on technology, deliv ery and prices please contact the Infineon Technologies Offices

in Germany or the Infi neon Technologies Companies and Representatives worldwide:

see our webpage at http://www.infineon.com

PSB 4610

Revision History: Current Version: 01.00

Previous V ersion: PSB 4610 Version 2.1 (12.99)

Page

(i n previous

Version)

Page

(i n current

Version)

Subjects (major changes since last revision)

181 default value (40h) 1221 0001 changed to 1222 0001

ABM®, AO P®, A RCO FI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EP IC®-1, EPI C ®-S, ELIC®, FAL C®54,

FALC®56, F ALC ®-E1, F ALC ®-LH, IDEC®, IOM®, IO M®-1, IOM®-2, I PAT ®-2 , ISA C®-P, I SAC ®-S, ISAC®-S TE,

ISAC®-P TE , ITAC®, IWE®, M U SAC®-A, OC T AT ®-P, QUAT®-S, SI C AT ®, SICO FI®, SICOFI®-2, SICOFI®-4,

SICOFI®-4µC, SLI C OF I® are regis t ered t radem ark s of I nf ineon T ec hnologies AG.

ACE™, ASM™, ASP™, PO TSWIRE™, QuadF ALC™, SCO UT ™ are t rademark s of Inf ineon T echnologies AG.

dition 0 1.00

P ublis hed by Inf ineon Tec hnologies AG

TR,

B al anstr aß e 73,

81541 M ü n ch en

A ll Rig hts Re ser ve d.

At t ent ion plea se !

As f ar as pat ents or ot her rights of t hird part ies are c onc erned, liabilit y is only as sum ed for c om ponent s , not f or

applicat ions, proc es s es and c ircuit s im plem ent ed w it hin c om ponents or as s em blies .

T he inf ormat ion des c ribes t he t y pe of com ponent and s hall not be c ons idered as ass ured charac t erist ic s .

T erm s of deliv ery and right s t o c hange des ign res erv ed.

Due to technical requirements components may contain dangerous substances. For information on the types in

ques t ion pleas e c ont ac t y our neares t I nfineon T ec hnologies Of f ic e.

I nf ineon T ec hnologies AG is an approved C EC C manuf ac t urer.

Packing

Pleas e us e t he rec y c ling operators k now n to you. W e c an als o help y ou – get in t ouc h with your neares t s ales

of f ic e. By agreem ent w e w ill t ak e pac k ing mat erial bac k , if it is s orted. You m us t bear t he c os ts of t rans port.

For pac king material that is returned t o us unsorted or which we are not obliged to accept , we shall have t o invoic e

you for an y co sts incu rre d.

Com ponents us ed in life- support dev ic es or sy st em s m ust be e xpres sly aut horized for suc h purpos e!

Critical components 1 of t he I nf ineon Tec hnologies AG, may only be used in lif e-support devices or sy stems2 wi th

t he expres s w ritt en approv al of t he I nf ineon T ec hnologies AG.

1 A critica l co mpo ne nt is a co mpo ne nt used i n a life- supp or t de vice or system wh ose fail ure ca n re ason ab ly b e

ex pec t ed t o c aus e t he f ailure of t hat lif e-s upport dev ic e or sy s t em, or to aff ect its s af et y or eff ec tiv eness of t hat

de vice or system.

2 Life su ppo rt devi ce s o r syste ms a re i nten ded (a) to b e imp lan te d in the human b ody, or (b ) to sup por t a nd/o r

maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en-

dangered.

PSB 4610

Preliminary Data Sheet III 01.00

Organizat ion of thi s Data Sheet

•Chap ter 1, Feat ures

Descr ibes t he general feat ures of the PIT A- 2.

•Chap ter 2, Typical Applications with the PITA-2

Des c ribes ty pic al applic ations that c an be r ealiz ed with the PITA -2.

•Chap ter 3, Con stru c ti on of th e PIT A-2

S hows a block diagr am and des c ribes the interfac es and their func tions .

•Chap ter 4, Communicatio n w ith the P IT A-2

Des c ribes the P CI bus inter face of the P ITA- 2.

•Chap ter 5, Communicatio n w ith Ext ern al Co mponen ts

Giv es a general des cription of the loc al bus interfaces of the PITA -2.

•Chapter 6, Power Management

Descr ibes t he power managem ent functions ( inc luding D3cold) of the PIT A- 2.

•Chapt er 7, Reset and Int errupt s

Des c ribes the r equir ement s for r eset and the behaviour of the PIT A-2.

•C ha pt e r 8 , Pi nning

Descr ibes t he pins, types of pins and the charac teristics of the interfaces.

•Chap ter 9, Electrical Characterist ics

Des c ribes elec tr ic al maxim um ratings and elec tr ic al c haracteristic s.

•Chap ter 10, Package O utlines

Des c ribes the pac kage outlines.

•Chapt er 11, Co nfigu rat ion S pace Register of the P IT A- 2

Contains descr iptions of the C onfiguration Space Registers of the PIT A -2.

•Chap ter 12, Internal Register of th e P ITA

Contains descr iptions of the I nternal Registers of the P ITA- 2.

•Chap ter 13, Abbreviatio ns

Des c ribes abbr eviations occur ing in this dat a s heet.

•Chap ter 14, Index

PSB 4610

Preliminary Data Sheet IV 01.00

Im portant Notes about this Data Sheet

________________________________________

Wha t’s New?

The organization of the struc tur e follows the guidelines of Inform ation Mapping®.

________________________________________

What is Information Mapping®?

This is a res ear c h bas ed method for the

– analysis

– structure

– presentation

of us er -orientated manuals.

________________________________________

Major Changes

Instead of the used chapter s with mono caus al desc riptions you now get

– all inform ation

– for a s cope

– under the corres ponding heading.

________________________________________

The Intention

This Data Sheet is intended to be

– easily survey ed

– increas ingly readable

– c ustomized applic able

– practice-orientated

– offering the quic kest poss ible way to the required informat ion.

________________________________________

PSB 4610
Table of  Content s Page
Semiconductor Group  V Preliminary Data Sheet 01.00
1F eatu res   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2Ty pic a l A pplic a tions with t he  PITA-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3C ons truc tion of  the PITA-2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4Co mmu n ica t io n w ith  the PI T A-2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0
.1 PC I C o n fi g u r a t i o n  Sp a ce   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1
1.1 Inform ation about t he P CI Configur ation Spac e   .  . . .  . . . . . . . . . . . . . . .12
.1 .2 Access  to  th e  PCI C o n fi g u rati o n  Spa ce . . . . . . . . . . . . . . . . . . . . . . . . . .15
.1 .3 Ba s e  Ad d r e ss R e g i ste r  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6
1.4 Other  Regis ters  of t he P CI Configur ation Spac e .  . . .  . . . . . . . . . . . . . . .20
.2 PC I M a ste r/Ta rg e t C o n tr o l l e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2
2.1 S upported PCI Commands   . . . . . . . . . . . . . . . . . . . . . .  .  . . . . . . . . .  . . .23
2.2 Trans action Ty pe Bur st Read  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
.2 .3 Tr a n sa cti o n  Typ e  Bu rst Wr i te   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 7
2.4 Transaction Type Fast Back to Back . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3 Interr upt Contr ol Register - Retry  Counter  . . .  . .  . .  . .  . . .  . . . . . . . . . . . . . .31
5Communicat ion with  External Component s . . . . . . . . . . . . . . . . . . . . . .3 3
.1 Se r i a l D MA In te rfa c e   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .3 4
.1 .1 D MA  C o n tro ll e r  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 6
1.2 Infor mation about the DMA  Cont roller . . . . . . . . . . . . . . . . . . . . . . . . .  . .37
.1 .3 In te rn a l Re g i ste rs o f th e  DMA  C o n tro ll e r  . . . . . . . . . . . . . . . . . . . . . . . . .4 1
1.4 IOM-2 Mode 1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
1.5 IOM-2 Mode 2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
1.6 IOM-2 Mode 3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
1.7 IOM - 2 M odes -  S upplem entar y  Des cr iption . .  . .  . . .  . .  . . . . . . . . . . . . . .56
1.8 S ingle Modem  M ode V 2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
1.9 S ingle Modem  M ode A LIS  V3.X  . . . . . . . . . . . . . . . . . .  .  . . . . . . . . . . . .65
1.10 Dual Modem /M odem+V oice M ode  . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .73
1.11 Loop Bac k M ode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .76
.2 Pa r a l le l  In te rfa ce   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 8
.2 .1 AL E  a ft e r  Syste m R e se t  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1
2.2 ALE after internal Software Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.3 ALE  after  set ting t he P ar allel Interface M ode Bit .  . .  . .  . . . . . . . . . . . . . .83
2.4 Non Multiplexed Mode ( Write Trans action)  .  . .  . .  . .  . . . . . . . . . . . . . . . .84
2.5 Non Multiplexed Mode ( Read Trans ac tion) . . .  . .  . .  . . . . . . . . . . . . . . . .86
2.6 Multiplexed Mode (Wr ite Transaction) .  . . .  . .  . .  . . .  . .  . . . . . . . . . . . . . .87
2.7 Multiplexed Mode (Read Tr ans act ion)  . .  . . .  . .  . .  . .  . . . . . . . . . . . . . . . .88
2.8 Tr ansaction Disc onnec t with Tar get A bort . .  . .  . . .  . .  . . . . . . . . . . . . . . .89
2.9 Transaction Termination with Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
.2 .1 0 Ti m i n g  o f th e  Pa r a l l e l  I n te r fa ce   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4
3 General Purpose I/O I nterf ace . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . .97

PSB 4610
Table of  Content s Page
Semiconductor Group  VI Preliminary Data Sheet 01.00
3.1 Infor mation about the GP I /O  Int erfac e  . . . . . . . . . . . . .  . . . . . .  . . . . . . .98
.3 .2 Ti m i n g  o f th e  GP I/O In t e r fa ce  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 0 0
.3 .3 In te rn a l Re g i ste rs o f th e  GP I/O In te rfa ce  . . . . . . . . . . . . . . . . . . . . . . .10 1
3.4 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
3.5 Output Mode   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .109
3.6 Inter rupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . .111
3.7 Usage of the GP  I /O Inter fac e as ALIS V2. 1 Control Inter face  . . . . . . .113
.4 SP I  EEP R O M In te r f a c e  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 5
4.1 Inform ation about t he S PI E E PROM Inter face   . .  . . .  . . . . . . . . . . . . . .116
.4 .2 Ti m i n g  o f th e  SP I  EEPR OM In te rfa ce   . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 9
.4 .3 In te rn a l Re g i ste rs fo r th e  SP I EE PROM Inte rfa ce  . . . . . . . . . . . . . . . . .12 1
6Powe r  M a n a ge me nt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 3
1 Infor mation about the Power Supply Concept  . . . . . . . . . .  .  . . . . . . . . . . .124
1.1 Inform ation about t he P ower  Management  S tates   .  . .  . . . . . . . . . . . . .126
1.2 Considerations about Power  Cons umpt ion and Repor ting  . . . . . . . . . .128
1.3 Configur ation Spac e Regis ters of the Power  M anagement . . . . . . . . . .131
.1 .4 El e c trica l C h a ra c t e r i stics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 6
.1 .5 D e si g n  H i n ts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 7
1.6 Com patibility Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . .148
7Reset and  Int errupt s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 9
.1 R e se t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4 9
.2 In te rru p ts   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5 2
8Pinning  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5 6
9E lectrical Ch aract eristi cs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6 6
.1 Ab s o l u te  Ma ximu m R a ti n g s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6 7
.2 D C C h a r a cte ri sti cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6 8
P ackage O ut lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7 2
Conf iguration Sp ace Regist er o f the PITA- 2 . . . . . . . . . . . . . . . . . . . . .1 7 3
1 .1 D e sc ri p ti o n  o f th e  R e g i s te r Ty p e s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7 4
1 .2 C o n fi g u r a ti o n  Sp a c e  R e g i ste rs   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7 5
3 Regis ter s  which do not occur els ewher e in the Data S heet   . . . . . . . . . . .185
Int ernal Regist er of  th e P ITA   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 9 3
2 .1 D e sc ri p ti o n  o f th e  R e g i s te r Ty p e s  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 9 4
2 .2 In te rn a l R e g i ste r  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 9 5
3 Regis ter s  which do not occur els ewher e in the Data S heet   . . . . . . . . . . .202
Ab b reviatio ns  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 0 5
I n dex  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 0 6

PSB 4610

Preliminary Data Sheet 1 01.00

Introduction

________________________________________

What is the PITA-2?

The PITA-2 is a cost-effective PCI bridge for industrial and communication

applications. I t support s dual cards and D3cold power m anagement.

________________________________________

The PITA-2 can b e used in

•PCI ISDN cards.

•P CI hardware modem s.

•P CI software m odem s.

•Industrial PCI bridge applicat ions.

________________________________________

Inter faces of t he PITA-2

The P ITA-2 off ers the following interfac es:

Interfaces to fin d i n

P CI Mast er/Tar get Controller see chapter 4. 2 on page 22

Ser ial DM A Int erf ac e s ee chapter 5.1 on page 34

P arallel Int erfac e see chapter 5. 2 on page 78

PSB 4610

Preliminary Data Sheet 2 01.00

Gener al Purpos e I/O Interfac e s ee chapter 5.3 on page 97

SP I EEP ROM Int er face s ee chapter 5.4 on page 115

The P ITA-2 off ers the following interfac es:

Interfaces to fin d i n

PSB 4610

Features

Preliminary Data Sheet 3 01.00

1 Features

________________________________________

Comp lia nt with

•P C 99 (P CI r equir ement s)

•PCI B us Specific ation Version 2.2

•PCI P ower Managem ent Specific ation V ersion 1.1

________________________________________

Highlights

•Dual Car d suppor t (3.3V and 5V signaling environment )

•E xtensive Power Management Feat ures ( including D3c old)

•Automatic Configuration with Customer Specific V alues

________________________________________

Interfaces

•P CI Master Target Interface

–PCI 2.2 compliant

–32 bit

–33 MHz

•Ser ial Int erfac e

–Suppor ts IO M -2 M odes

–S upports s er ial inter face to the ALIS chip- set fam ily

–DMA Control le r for seri al communica ti on

–16 word F IF Os for each dir ection

•Para llel Inte rface

with chip select logic s upport ing up to t hree ex ter nal com ponents

•General P urpose I/ O Interface

with interr upt capability

•SPITM Interface

for optional E EP ROM

________________________________________

PSB 4610

Features

Preliminary Data Sheet 4 01.00

________________________________________

Compatibility

•ALI S V2.1 P SB 4596

•ALI S V3.X PSB 4596

•IS DN IOM -2 Component s , e.g.:

–IEC-Q famil y

–S BCX, SB CX- X

•Com ponents consis ting of a parallel multiplexed or non m ultiplex ed Intel/

Infineon Inter fac e, e.g:

–IPA C , IPAC -X

–ISAC-S, I SAC-SX, ISAC-SX TE

________________________________________

PSB 4610

Typ ical Applications wi th the PITA- 2

Preliminary Data Sheet 5 01.00

2 Typical Applications with the PITA-2

________________________________________

Overview

Besides all the applications that require only a simple PCI interface there are

s ome applic ations which the PITA -2 is es pec ially suited for.

Simple applications benefit from the easy configuration of the PITA-2, the

ext ensive power managem ent support and the st andar d interfaces on the loc al

bus side.

Telecommunication applications (e.g modems) benefit from the integrated

mas ter DMA controller as well as the IOM- 2/GCI bus interface.

This allows for easy connection of most telecommunications transceivers and

subs tant ially reduces t he CPU work load.

Fur therm or e the PIT A-2 fully suppor ts D3c old state.

This allows the PC to enter a deep sleep state and still be able to react to an

inc oming c all at the same time.

________________________________________

ISDN-S Inte rf ace Ap plicatio n with the IPAC

PSB 2115

IPAC

PSB 4610

PTA-2

EEPROM

S0-Interface

PC I B u s

u C In terface

SPI

PSB 4610

Typ ical Applications wi th the PITA- 2

Preliminary Data Sheet 6 01.00

________________________________________

IS DN-U Int erface App lication with th e 3PAC and IE C-Q TE

________________________________________

PSB 2113

3PAC

PSB 4610

PTA-2

PC I B u s

uC Interface

EEPROM

SPI

U-Interface

PSB21911

IE C- Q TE

PSB 4610

Construction of the PITA- 2

Preliminary Data Sheet 7 01.00

3 Construction of the PITA-2

________________________________________

Overview

The PITA-2 provides a Peripheral Component Interconnect (PCI) bus interface

which acts as a bridge between the PCI bus and the different controllers and

interfaces:

•The Parallel Inter face Contr ol s upport s up to three ex ternal devic es .

•The S erial Int erface is cont rolled by the internal DMA Controller; s erial

c omm unic ation uses tr ans mit and r ec eiv e FI FOs .

•The EEP ROM for conf igur ation of the PITA - 2 and cust omer spec ific dat a

storage.

•The Gener al Purpos e I/O Int er face.

________________________________________

Block Diagram of the PITA-2

________________________________________

PITA-2

PCI

Controller

EEPROM

Control

Parallel

Interface

Control

Serial

Interface

Control

DMA

Controller

TX FIFO

RX FI FO

SPI-

Interface

Parallel

Microcontroller

Interface

General

Purpose

Interface

Serial

Interface

PCI-Bus

PSB 4610

Construction of the PITA- 2

Preliminary Data Sheet 8 01.00

________________________________________

Descrip tion of t he single Blocks

Name provides supports Notes

PCI Bus

Control •a 32 bit inter fac e

at speeds up to

33 MHz

•Bus Master D MA

capabi lity for data

pass ing through

the Serial

Interface

•Tar get c apability

for data passing

thr ough the

Pa ral le l Int e rfa c e

•D0

•D1

•D2

•D3hot and D3c old

•5V environm ent

•3.3V environm ent

•V aux supply

Parallel

Interface

Control

Chips with a Infineon/

Intel Standard Parallel

Interface, including:

•ISDN devices

•Modem s DSP s

•Industrial devices

Three pr ede-

coded chip s el-

ec t lines

Can be used

for pinst rap-

ping the subsy -

stem/

subsyst em

vendor ID

Serial

Interface

Control

Chips with a serial

interfac e, including:

•Analog v oic e

codecs

•Analog modem

codecs

•IOM-2 devices .

Transmit and

receive data

are held in

separate 16

word FIFOs.

PSB 4610

Construction of the PITA- 2

Preliminary Data Sheet 9 01.00

________________________________________

EEPROM

Control •additional

informati on, such

–the Subsystem

Vendor ID

–extensiv e pow-

er manage-

ment

information

Al l EEPRO Ms wi th

SPI in te rface This is an

optional

feature that

can be used to

customize the

PITA-2

configuration

at s tar t up.

General

Purpose

I/O

Interface

•GP output s

•GP inputs

•GP interrupt

inputs

It can be

configured to

ac t as

•Input pins

•Output pins

•I nterr upt

pins.

Can be used

for

pinst rapping

the s ubsys tem

Descrip tion of t he single Blocks (cont’d)

Name provides supports Notes

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 10 01.00

4 Communication with the PITA- 2

________________________________________

For communication with the PITA-2 the followin g blocks are u sed:

Components Page

P CI Configuration S pace 11

P CI Mas ter/T arget Controller 22

Inter rupt Contr ol Register - Retr y Counter 31

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 11 01.00

4. 1 PCI Configur at ion Space

________________________________________

Overview

Overview Page

Infor mat ion about the PCI Conf iguration Space 12

Ac c ess to the PCI Configur ation Space 15

B ase Address Register 16

Other Regist er s of the P CI Configuration S pac e 20

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 12 01.00

4.1.1 Inf ormat ion abo ut th e PCI Con f igu ratio n Space

________________________________________

Description

The PCI Configuration Space c ontains infor m ation about

•the P CI device

•the r eques ted address s pac e in the mem or y s pace of the P CI system.

The address s pac e includes 64 32-bit r egis ters where the firs t 16 r egis ter s build

the c onfigur ation s pac e header ( 00h- 3Ch, refer to “Conf igur ation Space Register

of the P ITA- 2” on page 173)

________________________________________

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 13 01.00

________________________________________

Construction of the PCI C onfiguration Space

De vice ID

31 23 15 7

Vendor ID

Status Command

Class Code Revision ID

BIST H eader Ty pe Latency Timer Cac h Line Size

Bas e Address R egi s ter 0 (Int er nal R egist ers)

Bas e Address R egister 1 (Paral lel Interface)

Bas e Address R egi s ter 2 (unused)

Bas e Address R egi s ter 3 (unused)

Bas e Address R egi s ter 4 (unused)

Bas e Address R egi s ter 5 (unused)

C ardBus CIS Pointer

Subsystem ID Subsys tem Vendor ID

Ex pansion R OM Bas e Address

Reserved Cap_Ptr

Reserved

Max_Lat Min_Gnt Interrupt Pin In te r r up t Lin e

Pow er M anagem ent Capabili ties Ca pab il ity IDNe xt Ite m P o i nt er

PMCSRBridge SupportData

P ower Data Register 1

P ower Data Register 2

P ower Data Register 3

U nused C onfigurat i on Spac e Regist er s

shaded fields l oaded duri ng

init ializ at ion if EEPROM is connec t ed

58h

54h

50h

4Ch

48h

44h

40h

3Ch

38h

34h

30h

2Ch

28h

24h

20h

1Ch

18h

14h

10h

0Ch

08h

04h

00h

081624

CardB us CI S

5Ch

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 14 01.00

________________________________________

Descrip tion of Register Types

Type Description

PE •r ead only via P CI

•thes e bits ar e initialized by pins trapping dur ing PCI r eset

or by the optional E EPROM

H•r ead only via P CI

•hardwired

RC •read clear via P CI

•thes e bits are set by the internal logic

•thes e bits c an be r ead out and r eset by writing logical “1”

to th e m

•wri ting logical “0” does n’t influence the stat es of these bits

RW •read write via PCI

•these bits can be read out and written via t he P CI bus

E•r ead only via P CI

•thes e bits are initialized to a default value dur ing PCI

r eset or by the optional E E PROM

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 15 01.00

4.1.2 Access to th e PCI Configu ration Space

________________________________________

Description

The PITA-2 supports single 32 bit data transactions for the access to the PCI

Configurat ion Space.

________________________________________

Spe c ial Qualities

Name Description

Subsystem ID •lower 4 bit s c an be set via pins tr apping if no

EEPR O M is u sed

•with external E EPROM the c omplet e 16 bit

v alue can be loaded for the Subsyst em ID

Subs y stem Vendor ID •16 bit ID of the car d manuf ac turer

•has to be applied for at the PCI Spec ial Interes t

Group

•c an be set via pins tr apping dur ing r es et if no

EEPR O M is u sed

•c an be loaded fr om ex ternal EEPROM

CardBus CIS Pointer is not supported by the PITA-2, although it is

implemented in the PCI Configuration Space

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 16 01.00

4.1.3 Base Addr ess Register

________________________________________

Base Add ress Reg isters 0 - 5

Base Ad dress Reg ister Description

B ase Address Register 0 •the lower 12 bits are hardwired t o “0”

•occ upies an address space of 4K

•allows acc es s to the internal r egis ter s of

the PIT A-2

B ase Address Register 1 •the lower 12 bits are hardwired t o “0”

•allows continuous r ead and write

oper ations for acces s to the par allel

interface

•occ upies an address space of 4K

•addr es s s pace is logically s egmented in

4x 1K addr ess blocks

B ase Address Register 2 - 5 not used

Structure of the Add ress Space o f Base Add ress Register 1

Ad dress Space Access to

3FFh - 000h device 1 on the parallel interface ( CS0)

7FFh - 400h device 2 on the parallel interface ( CS1)

BFF h - 800h device 3 on the parallel interface ( CS2)

FFFh - C00h not us ed

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 17 01.00

________________________________________

Co nfig urat io n Sp ace Register: 04h

Bit 1 Memory_Access_Enable

Type RW

Defau lt Val ue 0b

Description Only if thi s bit is set to ‘1’, the PCI interface will react on

trans ac tions to the bas e addres s r egis ter s BAR ( all Bas e

Addres s Registers are defined as m emor y m apped).

Co nfig urat io n Sp ace Register: 10h

Bit 31:12 B ase A ddres s Regis ter 0

Type RW

Defau lt Val ue 0000h

Bit 11:00 B ase A ddres s Regis ter 0

Type H

Value 000h

Description BAR0 c ontains the base addr es s of an addr es s s pac e in the

P CI m ain m emory through whic h the inter nal r egis ter s of t he

PI TA -2 can be acces sed.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 18 01.00

________________________________________

Co nfig urat io n Sp ace Register: 14h

Bit 31:12 B ase A ddres s Regis ter 1

Type RW

Defau lt Val ue 0000h

Bit 11:00 B ase A ddres s Regis ter 1

Type H

Value 000h

Description BA R1 c ontains the base addr ess of a 4-k ilobyte addr ess

s pac e in the PCI main mem ory through which the parallel

m ic ro c ontroller interface of the P ITA- 2 c an be acces s ed.

Co nfig urat io n Sp ace Register: 18h

Bit 31:0 B ase A ddres s Regis ter 2

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 2 is not support ed.

Co nfig urat io n Sp ace Register: 1Ch

Bit 31:0 B ase A ddres s Regis ter 3

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 3 is not support ed.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 19 01.00

________________________________________

Co nfig urat io n Sp ace Register: 20h

Bit 31:0 B ase A ddres s Regis ter 4

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 4 is not support ed.

Co nfig urat io n Sp ace Register: 24h

Bit 31:0 B ase A ddres s Regis ter 5

Type H

Value 0000 0000h

Description Base A ddres s Regis ter 5 is not support ed.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 20 01.00

4.1.4 Oth er Registers of th e PCI Conf igu ration Space

________________________________________

Co nfig urat io n Sp ace Register: 28h

Bit 31:0 Car dBus CIS P ointer

Type H

Value 0000 002C0h

Description Unused

Bit 31:28 ROM_Image_Number

Type H

Value 0000b

Description Unused

Bit 27:3 Address_Space_Offset

Type H

Value 000054h

Description Unused

Bit 2:0 Address_Space_Indicator

Type H

Value 000b

Description Unused

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 21 01.00

________________________________________

Note T he CardB us function is not support ed in this version of the PI TA -2.

________________________________________

Co nfig urat io n Sp ace Register: 2Ch

Bit 31:20 Subs yst em ID

Type E

Defau lt Val ue 000h

Bit 19:16 Subs yst em ID

Type PE

Value Pinstrap value or EE PROM value

Description Ident ifies a spec ific board of a manufacturer on which the

PI TA -2 is used.

The 4 LSBs will be set by pins trapping GP 0-3 during PCI

r es et if no EEPRO M is us ed and the c om plete 16 bit register

c an be loaded if the optional EEP ROM is used.

Bit 15:0 Subs ystem Vendor ID

Type PE

Value Pinstrap value or EE PROM value

Description Mar ks of the Vendor of the board on which the P IT A- 2 is

us ed. This register will be set by pins trapping PA D0- 7 and

P A0- 7 dur ing PCI reset if no E EPROM is used or configur ed

from a connected EEPROM. This ID is alloc ated by the P CI

SIG.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 22 01.00

4. 2 PCI Master/ Target Cont roller

________________________________________

Introduction

The inter face of the PCI bus is repr esented by t he P CI Mas ter/Tar get Controller.

This cont r oller is par t of the PITA- 2.

The PCI M as ter /Target Cont r oller s uppor ts

•sev eral t ypes of trans actions,

•B ase Addr es s Registers 0 and 1.

The PCI M as ter /Target Cont r oller

•has a “Med iu m De vice Sel ect ” behavior,

•tr unc ates bur st tr ansac tions at the end of t he firs t dataphase.

________________________________________

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 23 01.00

4.2.1 Supported PCI Co mman ds

________________________________________

PCI Ma s te r Controller:

P CI Co mmand Transact ion Type

Mem ory Read s ingle t ransfer

Mem ory Wr ite single trans fer

PCI Targ e t Co ntroller:

P CI Co mmand Transact ion Type

Mem ory Read s ingle t ransfer

Mem ory Read Multiple m apped on Mem or y Read

Mem ory Read Line m apped on Mem or y Read

Mem ory Wr ite single trans fer

Mem ory Wr ite and

Invalidate mapped on Memor y Wr ite

Configuration Read single tr ansfer

Configuration Write single tr ansfer

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 24 01.00

________________________________________

Note T he following timing diagrams ar e m eant as an exam ple and s how trans actions

to and from the PCI c onfigur ation s pace.

________________________________________

Overview

Overview Page

Trans action Ty pe B urst Read 25

Trans action Ty pe B urst W rite 27

Trans action Ty pe Fast Bac k to Back 29

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 25 01.00

4.2.2 Tr ansaction T ype Burst Read

________________________________________

Description

•As serting IRDY and STO P at the firs t dataphase leads t o the disc onnection

(Disc onnect- B) of the burst read tr ansact ion by the PI TA -2.

•STOP is asser ted until F RAM E is deas s erted.

•Deass ertion of FRA ME means that STOP and DE VSE L together are

deasserted.

________________________________________

Timing Diagram

________________________________________

ADR DATA

1010

12345678910111213

IDSEL

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 26 01.00

________________________________________

Co nfig urat io n Sp ace Register: 04h

Bit 26:25 DEVSEL_Timing

Type H

Value 01b

Description ‘01’ = medium tim ing, i. e. the DEV SE L signal will be

as s erted f rom the PCI interface with t he s ec ond pos itive PCI

c loc k edge aft er FRA ME was as serted on the PCI bus by a

master.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 27 01.00

4.2.3 Tr ansaction T ype Burst Write

________________________________________

Description

•As serting IRDY and STO P at the firs t dataphase leads t o the disc onnection

( Dis connec t-B ) of the burs t write trans ac tion by the P ITA- 2.

•STOP is asser ted until F RAM E is deas s erted.

•Deass ertion of FRA ME means that STOP and DE VSE L together are

deasserted.

________________________________________

Timing Diagram

________________________________________

ADR DATA1 DATA2

1010

BE1 BE2

12345678910111213

IDSEL

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 28 01.00

________________________________________

Co nfig urat io n Sp ace Register: 04h

Bit 26:25 DEVSEL_Timing

Type H

Value 01b

Description ‘01’ = medium tim ing, i. e. the DEV SE L signal will be

as s erted f rom the PCI interface with t he s ec ond pos itive PCI

c loc k edge aft er FRA ME was as serted on the PCI bus by a

master.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 29 01.00

4.2.4 Tr ansaction T ype Fast Back to Back

________________________________________

Description

With the fast bac k to back trans action a P CI Mast er Controller can per form

•s ever al wr ite tr ans ac tions

•a read trans ac tion as las t tr ans ac tion

without setting the PCI bus to IDLE state in between or releasing the bus to

another master.

A t the end of a trans action:

•The Master as s erts t he FRAM E signal and at the s ame time the TRDY signal

is deasserted.

The transact ion is answered with a RE TRY s ignal by the PITA- 2

•if the parallel interf ace is included in the fas t back to back trans action

•and the par allel int erface is still busy.

________________________________________

Timing Diagram

________________________________________

ADR DATA1 ADR2 DATA2

1011

BE1 1011

BE2

12345678910111213

IDSEL

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 30 01.00

________________________________________

Co nfig urat io n Sp ace Register: 04h

Bit 23 Fast_Back_To_Back_Capability

Type H

Value 1b

Description The P ITA - 2 s uppor ts fas t back- to-bac k .

Bit 9 Fast_Back_To_Back_Enable

Type H

Value 0b

Description The P ITA - 2 its elf gener ates no fast bac k -to-back

transactions.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 31 01.00

4.3 Interr upt Cont rol Register - Ret r y Count er

________________________________________

Description

•Par t of the PCI M aster Target Controller

•Functionality:

1. Disconnec tion of the PCI M aster transac tion wit h Retry by the addres sed PCI

Slave.

2. Dec rement of the c ounter .

3. The Retry _Counter_Int bit is set.

4. An interr upt will be generated if the Ret ry_Counter_Enable bit is set.

5. The P CI Master star ts the tr ansaction again.

________________________________________

Inter nal Register: 00h

Bit 27 RETRY_Counter_Down_Int_En

Type RW

Defau lt Val ue 0b

Description Enable for the Retry _Counter _Down inter rupt bit

Bit 11 Retry_Counter_Int

Type RC

Defau lt Val ue 0b

Description I f a P CI Mas ter initiated tr ans ac tion is r etried f rom a PCI

Slave with the number of retries def ined in the

Retry _Counter r egis ter, this interr upt bit is set by the PCI

interface.

PSB 4610

Communication with the PITA- 2

Preliminary Data Sheet 32 01.00

________________________________________

Inter nal Register:1Ch

Bit 23:16 Retry Count Register

Type RW

Defau lt Val ue 00h

Description Hold the number of retries for a single PCI master

transaction before the PITA-2 will assert an interrupt (if

enabled).

A s an ex ample, if this r egis ter is progr amm ed with the value

4, the PITA-2 will retry a single PCI transaction up to four

tim es as a mas ter befor e it asser ts an interrupt . The PITA-2

will c ontinue to r etry the t ransact ion until it suc ceeds or the

sof tware decides to abort the whole transac tion.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 33 01.00

5 Communication with External Com ponents

________________________________________

Introduction

This c hapter descr ibes the interfaces for communication wit h dev ic es on the local

bus side ( i. e. not the PCI bus side).

________________________________________

Interfaces

Interfaces Page

Serial DMA I nterface 34

Pa ral le l Int e rf ace 78

Gener al P ur pose I/ O Int er face 97

SPI EEPROM Interface 1 1 5

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 34 01.00

5.1 Se ria l DMA Inte rfa ce

________________________________________

Introduction

The s er ial DMA interface is us ed in differ ent modes to tr ans mit and rec eiv e 16 bit/

32 bit data fr am es. These data fram es have differ ent content and s tr uc tur es :

•Data

•Data/V oice and Com mand

•Data/V oice and Com mand for two codec s

•Differ ent time slots on IOM- 2.

________________________________________

Usage of the Serial DMA In terface

The s er ial DMA interface is c loc ked by default with t he internally gener ated cloc k

(DCL = PCI cloc k divided by 40) .

The S er_Clock _S et bit m ust be s et in the Ser ial Clock Select register to ’1’ when

the inter fac e s hall work in ALIS V3. X or IOM -2 mode

Reset ting this bit can result in an unknown behavior of t he FI FOs and the s erial

controller.

The s erial DM A interface is f ully controlled by the DMA c ontroller .

________________________________________

PSB 4610
Communication with External Com ponent s
Preliminary  Data Sheet  35 01.00
 
________________________________________
________________________________________
Overview
Overview Page
DMA Contr oller 36
IOM-2 Mode 1 47
IOM-2 Mode 2 50
IOM-2 Mode 3 53
IOM-2 Modes  - Supplementary Desc ription 56
Single M odem Mode V2.1 61
Single M odem Mode ALIS V3.X 65
Dual Modem /M odem+ Voice Mode 73
Loop Bac k M ode 76

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 36 01.00

5.1.1 DMA Controller

________________________________________

Overview

Overview Page

Infor mat ion about the DMA Cont roller 37

Inter nal Regist ers of the DMA Cont roller 41

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 37 01.00

5.1.2 Inform ation about the DMA Controller

________________________________________

Description

For the control of the DMA Controller, three register are implemented in the

internal registers:

•The Cir cular B uffer S tart Addr es s is a 4- k byte aligned PCI address which

points to a 4-kby te c ir c ular buffer in the PCI main m emory . All DMA r ead/wr ite

transactions between host and PITA will be processed via this 4-kbyte address

space.

•The DM A Control register includes the 6-bit parameter DMA Selec t whic h is

us ed to define the mode for the next DMA t r ansfer. With the DMA _St ar t bit the

DM A t ransfer can be st arted and s topped.

•The c ontents of the DM A Wr ite Count Register is inter pr eted as a thr es hold for

the wr ite trans fers from the DMA c ontroller .

________________________________________

Function of the DMA Controller

Phase Function

1 DMA _Start bit is s et in the DMA Cont rol Register and a DMA

transf er is st art ed as defined in the DM A S elect Register.

2 T he DMA controller loads the Circular Buf fer Start Addres s t o its

A ct ual Circular Buffer Pointer .

3 T he DMA cont roller fills the T X FIFO by r eading 15 t imes thr ough

the PCI interface ( P CI mas ter mode) fr om the c ir cular buff er .

4 The DM A controller signals the end of the initial sequenc e.

5 The DMA controll er increments the Actual Circular Buffer Pointer by

4 each read t ransfer.

6 T he DMA cont roller loads the contents of the 12 bit DM A Wr it e

Count Regis ter to its internal 12 bit DMA wr it e c ounter.

7 After the fir s t 15 r ead tr ans fer s in the beginning of the 16th read

tr ans fer the DMA controller st ar ts the norm al DM A algorithm.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 38 01.00

________________________________________

DMA Write Coun ter

A fter each wr ite tr ans ac tion fr om t he RX FI FO t o the buf fer the int er nal DMA wr ite

count er is inc rement ed by 1. If this counter reaches ’0’ an inter rupt is generat ed

and the counter is loaded again with the contents of the DMA Write Counter

The internal DM A writ e counter is decrem ented ev ery t wo write transac tions as

long as two 16 bit values per FS C frame ar e t ransferr ed in t he following modes :

•32 bit frame mode

•dual modem m ode

•mode m+vo ice mo de

•IOM- 2 mode 2 and 3.

________________________________________

Function of the DMA Algorithm

Phase Function

1 The DM A controller reads the 16th data wor d from t he c ur r ent

addr ess in the cir c ular buffer (A c tual Circ ular B uffer Pointer) t o the

i n te rna l TX FIFO.

2 The DM A controller writes the f ir s t r eceived 16-bit data word from

the RX FI FO to the same addr es s in the c ir cular buff er .

3 The DM A controller incr ement s the Actual Buff er P ointer by 4.

4 The DM A controller reads the 17th data wor d from t he c ur r ent

addr ess in the cir c ular buffer (A c tual Circ ular B uffer Pointer) t o the

i n te rna l TX FIFO.

5 The DMA controller writes the second received 16-bit data word

from the RX FIFO t o the sam e addr ess in the circular buffer.

6 The DM A controller incr ement s the Actual Buff er P ointer by 4.

7 and so on

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 39 01.00

________________________________________

DMA_ Start bit

•The r eset of t he DM A_S tart bit st ops the DMA trans fer imm ediately.

•The ass ertion of the DMA _Start bit reset s the TX and RX FIFO’s.

This means that all FIFO data is los t when the DM A t rans fer is s topped.

________________________________________

Da ta in t he Circular Buffer

Since no data is written from the RX FIFO to the circular buffer for the first 15

addresses, the first interrupt after the DMA_Start assertion means that the

r eceived data is available in the c ir cular buffer on address

•003Ch to 003Ch + [DMA W rite Count]: 16 bit f rame modes

•003Ch t o 0003Ch + 2 x [DMA Write Count]: 32 bit fr ame modes.

Dur ing nor mal data transfer ev er y inter r upt m eans that received data is av ailable

in the circ ular buffer on addres s

•[end addr es s from las t interrupt ] to [end addr ess from last int err upt] + [DMA

Write Count] : 16 bit frame modes

•[end addr ess fr om last int er rupt] to [end addr es s fr om las t inter r upt] + 2 x [DMA

Write Count] : 32 bit frame modes

________________________________________

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 40 01.00

________________________________________

Example fo r DMA con t rolled Data Transfer via Circu lar Buf f er

The s tatus of the DMA c ontroller :

16 bit frame access mode (ALIS V2.1 mode/IOM-2 mode 1) when three data

frames are already wr it ten to the T X line.

________________________________________

RX data 1

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 4

TX data 3

TX data 2

TX data 1

RX data 4

RX data 3

RX data 2

TX data 23

TX data 22

TX data 21

TX data 20

don't care

1531

16 0

Circular Buffer

Memory

0000h

0004h

0008h

0038h

003Ch

RX data 8

RX data 9

RX data 10

RX data 11

RX data 12

RX data 13

RX data 14

RX data 15

RX data 16

RX data 17

RX data 18

RX data 19

RX data 5

RX data 6

RX data 7

RX data 20

TX data 16

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 19

TX data 18

TX data 17

TX data 4

Serial Control

DMA

Controller PITA

Actual_Circular_-

Buffer_Pointer

TX FIFO RX FIFO

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 41 01.00

5.1.3 Int ernal Registers of the DMA Con t roller

________________________________________

Inter nal Registers: 00h

Bit 26 FIFO_Overflow_Empty_Int_En

Type RW

Defau lt Val ue 0b

Description Enable for the FIFO_Over flow_Em pty inter rupt bit

Bit 25 DMA_Write_Counter_Overflow_Int_En

Type RW

Defau lt Val ue 0b

Description Enable for the DMA _Write_Counter_Overflow interr upt bit .

Bit 24 DMA_Write_Counter_Int_En

Type RW

Defau lt Val ue 0b

Description Enable for the DMA _Write_Counter interrupt bit.

Bit 10 FIFO_Overflow_Empty_Int

Type RC

Defau lt Val ue 0b

Description During a DM A trans fer the ser ial c ontroller was unable to

write received data to the RX FI FO because is was already

full or the ser ial c ontroller was unable t o send data after the

rising F SC edge because of empty T X F IFO.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 42 01.00

________________________________________

Bit 9 DMA_Write_Counter_Overflow_Int

Type RC

Defau lt Val ue 0b

Description T his bit is s et if the int ernal DM A write counter is count ed

down while the DMA_W rite_Counter_Int bit is st ill ac tive.

This m eans t hat the interr upt gener ated by t he

DM A_Write_Counter_Int bit is not y et pr ocess ed.

Bit 8 DMA_Write_Counter_Int

Type RC

Defau lt Val ue 0b

Description This bit is s et if the num ber of data, defined in the DM A Wr ite

Count Register is wr itten thr ough t he P CI interface. In the

32-bit modes (dual modem , modem+ voice, I OM -2 mode 2,

IOM- 2 mode 3) this bit is set if the number of dat a pairs

defined in the DMA Write Count Register is transf erred

through the PCI interface.

Inter nal Registers: 00h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 43 01.00

________________________________________

Inter nal Registers: 04h

Bit 31:0 DM A Control Register

Bit 31:9 Reserved

Type H

Value 0000000h

Description Reserved

Bit 8 DMA_Start

Type RW

Defau lt Val ue 0b

Description By ass erting this bit a DM A transf er between the circular

buffer and the s erial DM A int er face us ing inter nal RX/ TX

FIFOs is s tar ted. This bit is res et by the host if the DMA

tr ansfer is to be finished.

Bit 7:6 Reserved

Type H

Value 00b

Description Reserved

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 44 01.00

________________________________________

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description Used to define the m ode for the next DMA transfer:

–Mode 1 ( ’000001’): Single M odem Mode V2. 1

–Mode 2 ( ’000010’): Single M odem Mode V3. X

–Mode 3 ( ’000100’): Dual M odem/ Modem+ Voice Mode

V3.X

–Mode 4 ( ’001000’): I OM-2 Mode 1

–Mode 5 ( ’010000’): I OM-2 Mode 2

–Mode 6 ( ’100000’): I OM-2 Mode 3

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

Inter nal Registers: 04h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 45 01.00

________________________________________

Inter nal Registers: 08h

Bit 31:12 Circular Buffer St art Addres s

Type RW

Defau lt Val ue 000000h

Bit 11:0 Circular Buffer St art Addres s

Type H

Value 000h

Description •4-k byte aligned PCI address which points to a 4-k by te

circular buff er in the PCI m ain memory .

•A ll DM A read/write trans actions between the hos t and the

P ITA are proc ess ed via this 4- kby te addres s space.

Inter nal Register: 0Ch

Bit 31:02 A ctual Circular Buf fer Pointer

Type R

Value 31-12 equal to 31-12 of Regis ter 08, 11-02 ac tual address

Bit 1:0 A ctual Circular Buf fer Pointer

Type H

Value 00b

Description By r eading t his r egis ter the s oft ware has ac c ess to the PCI

address in t he DM A circular buffer address pointer.

The bits 31-12 are equal the cont ents of the Circular Buffer

St art Addr ess Regis ter. The bits 11-0 r epresent the act ual

dwor d addres s in the c ir cular buff er .

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 46 01.00

________________________________________

Inter nal Register: 1Ch

Bit 11:0 DM A Write Count Regis ter

Type RW

Defau lt Val ue 000h

Description

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 47 01.00

5.1.4 IOM-2 Mode 1

________________________________________

T ransmissio n and Recep tion of Data in the Circular Buf fer

________________________________________

Don´t care B1

31 B2

RX data 1

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 4

TX data 3

TX data 2

TX data 1

RX data 4

RX data 3

RX data 2

TX data 23

TX data 22

TX data 21

TX data 20

don't care

1531

16 0

Circular Buffer

Memory

0000h

0004h

0008h

0038h

003Ch

15 716 8 0

Data in Circu lar Buff er and on Serial DMA In terface

Direction Dat a in Circu lar Bu ffer Data o n Serial DMA

Interface

Tr ansmit Bits fr om circ ular buff er:

[31:16] = don’t care

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Wr ite to s er ial DM A inter face:

B1 [7:0]

B2 [7:0]

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 48 01.00

________________________________________

Timing Diagram

________________________________________

Receive B its to circular buff er:

[31:16] = don’t care

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Read from s erial DMA

interface:

B1 [7:0]

B2 [7:0]

Data in Circu lar Buff er and on Serial DMA In terface (cont’d)

Direction Dat a in Circu lar Bu ffer Data o n Serial DMA

Interface

8 bit B1 channel DU 8 bit B2 channel DU

8 bit B1 channel DD 8 bit B2 channel DD

125 us

16 bit B1, B2 frame, double clock

FSC (i)

DCL (i)

TXD (o)

RXD (i)

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Cont r ol Register includes the 6 bit par am eter DM A

Select.

Used to define the m ode for the next DMA transf er:

Mode 4 (’001000’): IOM-2 Mode 1

With the DMA_S tar t bit t he DM A trans fer can be started or

stopped.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 49 01.00

________________________________________

Inter nal Register: 20h

Bit 1 DCL_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 1=’0’: The DCL signal is configur ed as input, i.e. not

dr iv en by the PITA .

Bit 0 Serial_Clock_Select

Type RW

Defau lt Val ue 0b

Description Bit 0=’1’: The s er ial c ontr oller is dr iven with the exter nal DCL

input clock.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 50 01.00

5.1.5 IOM-2 Mode 2

________________________________________

T ransmissio n and Recep tion of Data in the Circular Buf fer

________________________________________

Don´t care B1

31 B2

RX data 1

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 4

TX data 3

TX data 2

TX data 1

RX data 4

RX data 3

RX data 2

TX data 23

TX data 22

TX data 21

TX data 20

don't care

1531

16 0

Circular Buffer

Memory

0000h

0004h

0008h

0038h

003Ch

15 716 8 0

Don´t care Monitor 0

31 D, C/I, MR, MX

15 716 8 0

Data in Circu lar Buff er and on Serial DMA In terface

Direction Buffer

Offset Dat a in Circu lar Buff er Data on Serial DMA

Interface

Trans mit 0, 2, 4,

... Bits f rom circular buff er:

[31:16] = don’t ca re

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Wr ite to ser ial DM A

interface:

B1 [7:0]

B2 [7:0]

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 51 01.00

________________________________________

Timing Diagram

________________________________________

Trans mit 1, 3, 5,

... Bits f rom circular buff er:

[31:16] = don’t ca re

[15:8] = Monitor 0 [7:0]

[7:0] =

D,C/I0,M R,M X [7:0]

Wr ite to ser ial DM A

interface:

M onitor 0 [ 7:0]

D,C/I0,M R,M X [7: 0]

Receive 0, 2, 4,

... Bits to c ir cular buff er :

[31:16] = don’t ca re

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Read from s erial DM A

interface:

B1 [7:0]

B2 [7:0]

1, 3, 5,

... Bits to c ir cular buff er :

[31:16] = don’t ca re

[15:8] = Monitor 0 [7:0]

[7:0] =

D,C/I0,M R,M X [7:0]

Read from s erial DM A

interface:

M onitor 0 [ 7:0]

D,C/I0,M R,M X [7: 0]

Data in Circu lar Buff er and on Serial DMA In terface (cont’d)

Direction Buffer

Offset Dat a in Circu lar Buff er Data on Serial DMA

Interface

8 bit B1 channel DU 8 bit B2 channel DU

8 bit B1 channel DD 8 bit B2 channel DD

125 us

16 bit B1, B2 frame, double clock

FSC (i)

DCL (i)

TXD (o)

RXD (i)

8 bit Monitor 0 channel DU

8 bit Monitor 0 channel DD

2 bit D

4 bit C/I 0 MR

MR4 bit C/I 0

16 bit MON0, D, C/I0, MR, MX frame

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 52 01.00

________________________________________

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Control Regist er inc ludes the 6 bit parameter DMA

Select.

Used to define the m ode for the next DMA transf er:

Mode 5 (’010000’): IOM-2 Mode 2

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

Inter nal Register: 20h

Bit 1 DCL_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 1=’0’: The DCL signal is configur ed as input, i.e. not

dr iv en by the PITA .

Bit 0 Serial_Clock_Select

Type RW

Defau lt Val ue 0b

Description Bit 0=’1’: The s er ial c ontr oller is dr iven with the exter nal DCL

input clock.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 53 01.00

5.1.6 IOM-2 Mode 3

________________________________________

T ransmissio n and Recep tion of Data in the Circular Buf fer

________________________________________

Don´t care B1

31 B2

RX data 1

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 4

TX data 3

TX data 2

TX data 1

RX data 4

RX data 3

RX data 2

TX data 23

TX data 22

TX data 21

TX data 20

don't care

1531

16 0

Circular Buffer

Memory

0000h

0004h

0008h

0038h

003Ch

15 716 8 0

Don´t care IC1

31 IC2

15 716 8 0

Data in Circu lar Buff er and on Serial DMA In terface

Directio n Bu ffer

Offset Dat a in Circular Buf f er Data o n Serial DMA

Interface

Transmit 0, 2, 4,

... Bits from circular buff er:

[31:16] = don’t ca re

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Bits to serial DMA

interface:

B1 [7:0]

B2 [7:0]

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 54 01.00

________________________________________

Timing Diagram

________________________________________

Transmit 1, 3, 5,

... Bits from circular buff er:

[31:16] = don’t ca re

[15:8] = IC1 [7:0]

[7 :0 ] = IC2 [7 :0]

Write to serial DMA

interface:

IC 1 [7 :0 ]

IC 2 [7 :0 ]

Receive 0, 2, 4,

... B its to c ir cular buffer :

[31:16] = don’t care

[15:8] = B1 [7: 0]

[7:0] = B2 [7:0]

Read from s erial DMA

interface:

B1 [7:0]

B2 [7:0]

1, 3, 5,

... Write to circ ular buff er:

[31:16] = don’t care

[15:8] = IC1 [7:0]

[7 :0 ] = IC2 [7 :0]

Read from s erial DMA

interface:

IC 1 [7 :0 ]

IC 2 [7 :0 ]

Data in Circu lar Buff er and on Serial DMA In terface (cont’d)

Directio n Bu ffer

Offset Dat a in Circular Buf f er Data o n Serial DMA

Interface

8 bit B1 channel DU 8 bit B2 channel DU

8 bit B1 channel DD 8 bit B2 channel DD

125 us

16 bit B1, B2 frame, double clock

FSC (i)

DCL (i)

TXD (o)

RXD (i)

8 bit IC1 channel DU

8 bit IC1 channel DD

16 bit IC1, IC2 frame

8 bit IC2 channel DU

8 bit IC2 channel DD

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 55 01.00

________________________________________

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Control Regist er inc ludes the 6 bit parameter DMA

Select.

Used to define the m ode for the next DMA transf er:

Mode 6 (’100000’): IOM-2 Mode 3

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

Inter nal Register: 20h

Bit 1 DCL_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 1=’0’: The DCL signal is configur ed as input, i.e. not

dr iv en by the PITA .

Bit 0 Serial_Clock_Select

Type RW

Defau lt Val ue 0b

Description Bit 0=’1’: The s er ial c ontr oller is dr iven with the exter nal DCL

input clock.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 56 01.00

5.1.7 IOM-2 Modes - Supplementary Descrip tion

________________________________________

Selection of IOM-2 Time Slots

The MI SC regis ter contains four bit s . They ar e used for mas k ing the tim e slot on

IOM-2.

If Bx_MSK (x := [1,4]) is set:

•The cor responding v alue fr om the TX FIFO is not writ ten to the DU line.

•FFh is written to th is time slo t.

•In IOM -2 m ode 1 the bits B3_M SK and B4_MS K have no effect .

•Data is alway s transferr ed from the IOM -2 time slot to the RX- FIFO.

________________________________________

T iming Diagram f or all IOM-2 Modes

________________________________________

FSS

FSH

FSW

FSH

CYC

IOD

FSC (i)

DCL (i)

RXD (i)

TXD (o)

FSS

IIH

IIS

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 57 01.00

________________________________________

Figu re of the M ISC Register B1 - B4 Mask Bits

________________________________________

Ab breviation s fo r the T iming Diag ram

Parameter Symbol Limit Values Unit

min. max.

FSC pulse width tFSW 40 ns

FSC setup time tFSS 40 ns

FSC hold time tFSH 40 ns

DCL cycle time t CYC 244 ns

DCL HIGH ti me tWH 100 ns

DCL LOW tim e tWL 100 ns

IOM output data

delay tIOD 100 ns

IOM input data

setup tIIS 20 ns

IOM input data hold tIIH 20 ns

IOM-2

Mode 1

IOM-2

Mode 2

B2 Monitor 0

D,C/I0,MR,MX

IOM-2

Mode 3

B2 IC1

IC2

MISC

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 58 01.00

________________________________________

Ma s king of IOM -2 Time slot s ( Example for IOM-2 Mode 2 )

________________________________________

RXD (i)

TXD (0)

B2 Monitor 0

Previous IOM-2 frame

Don't care B1 B2

Don't care Monitor 0 D,C/I0,MR,MX

D,C/I0,MR,MX

Next IOM-2 frame

MON0

D,C/I0,

MR,MX

MON0

D,C/I0,

MR,MX

'FFh' 'FFh''FFh' 'FFh'

RX FIFO

TX FIFO

IOM-2 DD line

IOM-2 DU line

B1_MSK B3_MSK B4_MSK B2_MSK

Data 1

Data 2

Data 3

Circular Buffer

Memory

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 59 01.00

________________________________________

Inter nal Register: 1Ch

Bit 31:0 MI SC (Mis cellaneous Register)

Bit 31 IOM_B1_masking

Type RW

Defau lt Val ue 0b

Description Bit 31=’0’: B yt e B 1 is gener ated out of the circular buffer.

B it 31= ’1’: FFh is t ransm itt ed on the B1 time slot.

Bit 30 IOM_B3_masking

Type RW

Defau lt Val ue 0b

Description Bit 30=’0’: B yt e B 2 is gener ated out of the circular buffer.

B it 30= ’1’: FFh is t ransm itt ed on the B2 time slot.

Bit 29 IOM_M onitor_0 / IC1_m as king

Type RW

Defau lt Val ue 0b

Description Bit 29=’0’: B yt e M onitor 0 or IC1 is generated out of the

circular buff er.

B it 29= ’1’: FFh is t ransm itt ed on the Monitor /I C1 tim e s lot.

Monit or is used in IO M -2 m ode 2.

IC1 is used in IOM- 2 m ode 3.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 60 01.00

________________________________________

Bit 28 IOM_S upl_m asking / IC2_m as king

Type RW

Defau lt Val ue 0b

Description Address:=’0’: Byte D, C/I0, M R, M X or IC2 is generated out

of the circular buff er.

Address:=’1’: FFh is trans mitt ed on the D, C/ I0, MR, MX or

IC 2 ti me s l o t .

D, C/I 0, MR, MX : Us ed in I OM-2 mode 2.

IC2: Used in IOM -2 mode 3

Inter nal Register: 1Ch (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 61 01.00

5.1.8 Sin gle Modem Mode V2.1

________________________________________

Timing diagrams

________________________________________

Da ta in Circular Buffer and on Seri al DMA Interfac e

Direction Dat a in Circu lar Buff er Data o n Serial DMA

Interface

Trans mit B its fr om circular buffer:

[31:16] = don’t c a re

[15:0] = data fr ame [15: 0]

Write to serial DMA

interface:

data fr am e [15:0]

Receive B its to circular buff er:

[31:16] = don’t c a re

[15:0] = data fr ame [15: 0]

Read from s erial DMA

interface:

data fr am e [15:0]

16 bit data

125 us

16 bit data frame

FSC (i)

DCL (o)

TXD (o)

RXD (i)

FSW

DCD

CYC

DCI

ISU

IHO

high-Z

FSC (i)

DCL (o)

RXD (i)

TXD (o)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 62 01.00

________________________________________

Configuration of the Single Modem Mode V2.1 aft e r a Sys te m/Soft Rese t

•The configuration of the PS B4596 V 2.1 in single m odem mode is r ealized by

sof twar e using the 4-bit Gener al Purpos e I/O Inter face of the PIT A ( See

“Gener al Purpos e I/O Interface” on page 97.).

•After a system/soft reset the FSC is an input pin both for

–the P ITA

–th e ALIS V2 .1

•Af ter a syst em re set t h e D CL_Out _ En b it must be se t t o ’1’ by the host.

________________________________________

Ab breviation s fo r the T iming Diag ram

Parameter Symbol PCI

Clo ck

Cycles

Limit Values Unit

min. typ. max.

FSC pulse width tFSW 40 ns

DCL delay tDCD 16 480 ns

DCL idle time tDCI 105 µs

DCL cycle time t CYC 40 1200 ns

DCL HIGH ti me tWH 20 600 ns

DCL LOW tim e tWL 20 600 ns

DCL duty cy c le 45 50 55 %

Input data setup t ISU 10 ns

Input data hold tIHO 10 ns

Output data delay tOD 10 ns

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 63 01.00

________________________________________

Note A Pull Down res is tor is requir ed on the board to avoid a floating FS C signal in t his

situation.

________________________________________

PITA Conf igu ration for ALIS V2.1 after a Syst em Reset

Seri al DMA Interface

Mode Ser_Clock_S el ( clock

i n pu t to Se ri a l D MA

interface)

DCL_Out_E n (DCL

Direction)

ALI S V2.1 0 PCI clock/

40 1 DCL

output

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Control Regist er inc ludes the 6 bit parameter DMA

Select.

Used to define the m ode for the next DMA transf er:

Mode 1 (’000001’): Si ng l e Mo d e m Mo de V2 . 1

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 64 01.00

________________________________________

Inter nal Register: 20h

Bit 1 DCL_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 1=’1’: The DCL signal is output (open drain) and driven

by the PITA .

Bit 0 Serial_Clock_Select

Type RW

Defau lt Val ue 0b

Description Bit 0=’0’: The ser ial controller is driv en wit h the clock s ignal

generat ed by the internal clock div ider.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 65 01.00

5.1.9 Sin gle Modem Mode AL IS V3.X

________________________________________

5.1.9.1 Infor mation about the S ingle Modem Mode ALIS V3.X

________________________________________

Timing Diagram

________________________________________

Overview

Overview Page

Inform ation about t he S ingle Modem Mode ALIS V3.X 65

Inter nal Registers of the Single Modem M ode V 3.X 67

Da ta in Circular Buffers, on Se rial DMA Interface

Direction Dat a i n Circular Buf f er Dat a on Seri al DMA In terface

Tr ansmit Read fr om c ir cular buffer :

[31:16]= don’t ca re

[15:0] = data fr ame [15:0]

Write to serial DMA interface:

data fr am e [15:0]

Receive Write to circular buffer:

[31:16]= don’t ca re

[15:0] = data fr ame [15:0]

Read from s erial DMA interfac e:

data fr am e [15:0]

FSC (i)

16 bit data

DCL (i)

TXD (o) 8 bit CMD 8 bit write data

16 bit data 8 bit read dataRXD (i)

125 us

32 bit data / command frame

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 66 01.00

________________________________________

Note The timing characteristics of the serial DMA interface in Single modem mode

V3.X mode are identical to the IOM-2 modes with the only difference that the DCL

signal is not a double bit clock, but a single bit clock, similar to Single Modem

mode V2.1.

________________________________________

Configuration of the Single Modem Mode V3.X a fter a Syst e m/Soft Reset

•Realiz ed by starting the DMA trans fer.

– S eparate from this transf er the command by te and comm and data by te are

writ ten to the ALIS Com mand Registers in the PITA on address es 10h.

•After a system/soft reset the single modem mode V3.X is in the multiplexed

m ode becaus e t he non multiplexed mode is not suppor ted.

•The A LIS V3.X needs some tim e af ter an ex ternal r eset until it has st abiliz ed

FS C and DCL. Fur ther m ore as the PIT A-2 does not autom atically as serts

S RST as a respons e to a P CI r es et the following proc edur e is r ecom mended

to start the com municat ion with the ALI S V3.X:

–Assert SRST by r eset ting bit 25 of internal regis ter 025h

–Deass ert SRS T by setting bit 25 of int ernal regis ter 025h

–Wait 500ms

•A fter this pr ocedur e the ALIS V 3.X is ready for r ec eiv ing the fir s t command

________________________________________

PITA Configurat ion for ALIS V3.X afte r a System Rese t

Seri al DMA Interface

Mode Ser_Clock_S el ( clock

i n pu t to Se ri a l D MA

interface

DCL_Out_E n (DCL

Direction)

ALIS V3.X 1 DCL input

clock

0DCL_Out

_En

2×ALIS V3.X 1 0

A LIS V3.X + second

codec 10

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 67 01.00

5.1.9.2 Internal Registers of the Single Modem Mode V3.X

________________________________________

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Control Regist er inc ludes the 6 bit parameter DMA

Select.

Used to define the m ode for the next DMA transf er:

Mode 2 (’000010’): Si ng l e Mo d e m Mo de V3 . X

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

Inter nal Register: 10h

Bit 31:0 ALIS Comm and Register 1

Description T his com mand register is used for the firs t comm and

st ructure in the FS C t ime slot by t he serial controller .

Bit 31:25 Reserved

Type H

Value 0b

Description Reserved

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 68 01.00

Bit 24 New_ALIS_Command_1

Type RW

Defau lt Val ue 0b

Description Bit 24=’1’: The host has wr itt en a new c ommand to the ALIS

Com mand Resister 1.

Bit 24=’0’: Last command written to the ALIS Command

Regis ter 1 by t he hos t is pr oces s ed and t he receiv ed data is

av ailable in the ALI S Received Data 1 r egis t er.

This bit is set by soft ware if there is a new com mand in the

ALIS Command 1 Register. After the serial DMA interface

has tr ansmitted the new com mand and t he received data is

wr itten to the ALIS_Rec eiv ed_Data_1 bits , this bit is r es et by

the serial DMA interface.

Bit 23:16 ALIS_Received_Data_1

Type RW

Defau lt Val ue 00h

Description During a DMA transfer in mode 2 or 3 every time a new

command is transferred through the serial DMA interface,

the received data is fetc hed and saved in t his regist er.

New c omm and means : The comm and was written through

the PCI interface to the A LIS c omm and r egis ter.

Tr ans fer r ing a NOP c ommand ( FFh or 00h) leads to skipping

of the received data.

Inter nal Register: 10h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 69 01.00

________________________________________

Bit 15:8 ALIS_Command_1

Type RW

Defau lt Val ue 00h

Description During a DMA transfer in mode 2 or 3 the contents of this

r egis ter ar e trans ferr ed as c omm and through the s erial DMA

interface.

After tr ans ferr ing the new com mand through the serial DM A

interface, the r egis ter is s et to NOP ( FFh).

Bit 7:0 ALIS_Transmit_Data_2

Type RW

Defau lt Val ue 00h

Description During a DMA tr ans fer in A LIS V 3.x m ode 2 or 3 the c ontents

of this register are transferred as data through the serial

DM A interface.

Inter nal Register: 10h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 70 01.00

________________________________________

Inter nal Register: 14h

Bit 31:0 ALIS Comm and Register 2

Defau lt Val ue 00000000h

Bit 31:25 Reserved

Type H

Defau lt Val ue 000h

Description Reserved

Bit 24 New_ALIS_Command_2

Type RW

Defau lt Val ue 0b

Description Bit 24=’1’: The hos t has wr itten a new c om mand t o the ALIS

Com mand 2 Regis ter .

B it 24= ’0’: Last c ommand written to the ALIS Com mand 2

Regist er by the host is proces sed and the received data is

av ailable in the ALI S Received Data 2 Register .

This bit is s et by soft ware if there is a new c ommand in t he

ALIS Comm and 2 Register . Aft er the serial controller has

trans m itted the new command and the receiv ed data is

wr itten in the A LIS Rec eiv ed Data 2 Register, this bit is res et

by the serial controller.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 71 01.00

________________________________________

Bit 23:16 ALIS_Received_Data_2

Type RW

Defau lt Val ue 00h

Description During a DMA transfer in mode 3 ev ery time a new

com mand is t ransferred through the serial DM A interface,

the received data is fetc hed and saved in t his regist er.

New com mand means : The comm and was wr itten thr ough

the PCI interface to the A LIS V 3.X c ommand regist er .

If only a N OP com mand (F Fh or 00h) is tr ansfer red t he

received data is s kipped.

Bit 15:8 ALIS_Command_2

Type RW

Defau lt Val ue 00h

Description During a DMA transfer in mode 3 the c ontents of this r egis ter

are trans ferred as comm and through the serial DM A

interface.

A fter tr ans fer r ing the new com mand t hrough t he s erial DMA

interface, the r egis ter is s et to NOP ( FFh).

Bit 7:0 ALIS_Transmit_Data_2

Type RW

Defau lt Val ue 00h

Description During a DMA transfer in mode 3 the c ontents of this r egis ter

are trans ferred as data through the serial interfac e.

Inter nal Register: 14h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 72 01.00

________________________________________

Inter nal Register: 20h

Bit 1 DCL_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 1=’0’: The DCL signal is input and driven by the PIT A .

Bit 0 Serial_Clock_Select

Type RW

Defau lt Val ue 0b

Description Bit 0=’1’: The s er ial c ontr oller is dr iven with the exter nal DCL

input clock.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 73 01.00

5.1.10 Dual Mod em/Modem+Voice Mod e

________________________________________

Description

•The PI TA transm its and r ece ives two 32 bit fr ames per FSC tim e slot.

•E ach 32 bit fr ames cons is ts of 16 bit data and 16 bit command/ data

information.

•For each of the 32 bit fr ames the 16 bit t r ansmitted data is r ead out of t he TX

FIFO.

•The 16 bit tr ans mit ted data is wr itten to the RX FIFO.

•The command read/write dat a for the f ir s t 32 bit frame is r ead out/ wr itt en to the

ALIS Comm and Register 1 (10h)

•The command read/write data for the sec ond 32 bit frame is read out/ written to

the A LIS Com mand Regis ter 2 ( 14h).

•The internal DM A write counter is inc rem ented every second write tr ans fer to

the c ir cular buff er .

•A new fr ame trans miss ion starts if the FSC is sam pled ’1’ at a negat iv e edge

of the DCL s ignal.

•The P ITA s tarts dr iv ing the TX D line with the fir st bit of the tr ans mitted dat a at

the nex t positiv e DCL edge.

•Dur ing the tr ans miss ion the ris ing DCL edge indicates the star t of a bit on t he

TXD while the falling edge of the DCL is used to lat ch the RXD signal.

•The P ITA s tops dr iv ing the TX D signal with t he positiv e DCL edge when bit 32

of the firs t or s econd transm itt ed f rame is on the T XD line.

________________________________________

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 74 01.00

________________________________________

Data Organization in the Circular Buffer

________________________________________

Timin g Diagram for the Du al Modem M ode

________________________________________

RX data 1

TX data 15

TX data 14

TX data 13

TX data 12

TX data 11

TX data 10

TX data 9

TX data 8

TX data 7

TX data 6

TX data 5

TX data 4

TX data 3

TX data 2

TX data 1

RX data 4

RX data 3

RX data 2

TX data 23

TX data 22

TX data 21

TX data 20

don't care

1531

16 0

Circular Buffer

Memory

0000h

0004h

0008h

0038h

003Ch

Don´t care TX Data 1 Modem 1

31 15 716 8 0

Don´t care TX Data 1 Modem 2

31 15 716 8 0

16 bit data 8 bit CMD 8 bit write data 16 bit data 8 bit CMD 8 bit write data

16 bit data 8 bit read data 16 bit data 8 bit read data

125 us

32 bit data / command frame 32 bit data / command frame

FSC (i)

DCL (i)

TXD (o)

RXD (i)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 75 01.00

________________________________________

Timin g Diagram for the Du al Modem+Voice M ode

________________________________________

Descrip tion of t he T iming Diagram

•The sec ond 32 bit fram e only consists of the 16 bit voice data.

•The v oice data is r ead out the TX FI FO.

•The v oice data is tr ansm itted thr ough t he s er ial DMA inter fac e ( MSB fir s t) .

•Dur ing this tr ans m ission the rec eiv ed 16 bit v oic e data ( MSB firs t) is wr itten to

th e R X FIFO.

________________________________________

16 bit data 8 bit CMD 8 bit write data 16 bit data stuffing pattern 'FFh'

16 bit data 8 bit read data 16 bit data

125 us

32 bit data / command frame 32 bit data frame

FSC (i)

DCL (i)

TXD (o)

RXD (i)

16 bit stuffing 'FFh'

Inter nal Registers: 04h

Bit 5:0 DMA Se lect

Type RW

Defau lt Val ue 000000b

Description The DMA Control Regist er inc ludes the 6 bit parameter DMA

Select.

Used to define the m ode for the next DMA transf er:

Mode 3 (’000100’): Single Dual Modem/Modem + Voice

Mode V3 .X

With the DMA _St art bit the DMA tr ansfer can be s tarted or

stopped.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 76 01.00

5.1.11 Lo op Back M ode

________________________________________

Description

If Loop_Back_Mode is set to ’1’ transmit data is transferred from the TX FIFO

bac k to the RX FI FO.

________________________________________

Mode Diagram

________________________________________

PITA

DMA

Controller

TX FIFO

RX FIFO

Loop

closed

Data 1

Data 2

Data 3

Circular Buffer

Memory

Serial Controller

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 77 01.00

________________________________________

Inter nal Register: 28h

Bit 0 Loop_Back_Mode

Type RW

Defau lt Val ue 0b

Description •Bit 0=’0’: The s er ial c ontroller tr ans mits and r ec eiv es data/

c omm ands through the serial DM A int erf ac e ( nor mal

operat ion mode).

•Bit 0=’1’: T he ser ial contr oller is in loop back m ode.

–The ser ial DMA inter face reads the data in t he

trans m itting FIFO and writes them in the r eceiving

FIFO.

–No data/com mand tr ans mission will take place on the

s er ial DMA inter fac e.

–The s erial DM A interface is clock ed with the defined

Ser_Clock_ Sel bit .

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 78 01.00

5.2 Pa ra lle l In te rfac e

________________________________________

Description

The PI TA has an 8 bit par allel inter face to suppor t three ex ternal c omponents .

This par allel inter face is implem ented in mult iplex ed and non multiplexed m ode.

It works in I nfineon/I ntel bus m ode.

The par allel inter face is by default in t he non mult iplex ed m ode.

________________________________________

Inter nal Register: 1Ch

Bit 26 Parallel_interface_mode

Type RW

Defau lt Val ue 0b

Description 0: non mult iplex ed mode

1: multiplexed mode

Bit 24 Softreset_parallel_mode

Type RW

Defau lt Val ue 0b

Description 0: Deactivates the res et signal PRS T to the application.

1: Activates the high active reset signal PRST to the

application.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 79 01.00

________________________________________

Mapp ing bet ween PCI Data and Parallel Interface Data

Data on the

P CI b us AD31-0 PCI B yte

Enables

C/BE3-0

Data on the

Parall el Interface Data bu s

PAD7-0

AD[31-8] = Don’t C a re

AD[7 -0] = Para llel

Inter face Data

“XXX0”PAD[7-0] = AD[7-0]

AD[31-8] = Don’t C a re

AD[7 -0] = Para llel

Inter face Data

“XXX1”No tr ans act ion, PCI interface

disc onnec ts with Tar get Abor t.

Ad dress M apping of the 4-kbyte PCI Add ress Space to th e Parallel

Interface

Address on

the

PCI ad dress

bus A D 1 1 -0

Chip Sel ect on

the

parallel in terface

Address on th e

parallel in terface address bus

PAD7-0 = AD9-2 (mux mode)

PA7-0 = AD9-2 ( non-mux mod e)

3FFh - 000h CS0 FFh - 00h

7FFh - 400h CS1 FFh - 00h

B FFh - 800h CS2 F Fh - 00h

FFFh - C00h none ( not used)

PSB 4610
Communication with External Com ponent s
Preliminary  Data Sheet  80 01.00
 
________________________________________
________________________________________
Modes an d T iming of the Parallel Interf ace
M odes and  Ti ming Page
AL E aft er Syst em Re set 81
ALE after  inter nal Sof tware Reset 82
A LE aft er s ett ing the Par allel I nter face Mode Bit 83
Non Multiplexed Mode ( Write Trans action) 84
Non Multiplexed Mode ( Read Tr ans ac tion) 86
M ultiplexed Mode (Write Trans act ion) 87
M ultiplexed Mode (Read Transac tion) 88
Tr ansaction Dis c onnec t with Target Abor t 89
Trans action Ter mination wit h R etry 92
Timing of the Parallel Interf ace 94

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 81 01.00

5.2.1 ALE af t er System Reset

________________________________________

Timing Diagram

________________________________________

Description

Both ALE and PRS T are high during RST and rem ain high for a m aximum of 4

cycles after RST goes deasserted.

________________________________________

12345678910111213

RST

PRST

ALE

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 82 01.00

5.2.2 ALE af t er internal Sof t ware Reset

________________________________________

Timing Diagram

________________________________________

Description

•A fter the inter nal Sof t Reset is deasser ted t he s am e behavior as in „ALE after

System Reset “ gener ated.

•The s oft reset bit in the int e rnal regis ters c an only be set or res et if the parallel

interface is in idle st ate.

•If A LE is high before PA R_RS T is ass er ted, it goes to low one cy c le after PRST

and tak es the new v alue depending on the PAR_MOD bit in the 6th cy c le aft er

P RST is deas s er ted.

________________________________________

PRST

ALE

12345678910111213

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 83 01.00

5.2.3 ALE af t er setting th e Parallel Interface Mode Bit

________________________________________

Timing Diagram

________________________________________

Description

•The par allel inter face is in non multiplexed mode by default .

•To s et the parallel interface into multiplexed mode:

The Parallel_Int er face_Mode bit has t o be s et to ’1’ after reset.

•Two P CI clocks after finishing this data phase t he A LE signal is asserted.

________________________________________

123456789101112

ADR DATAADR1 DATA

CMD1 0000 CMD 0000

______

FRAME

____

IRDY

_____

TRDY

_______

DEVSEL

AD31-0

_______

C/BE3-0

_____

STOP

ALE

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 84 01.00

5.2.4 Non M ultiplexed Mode ( Write Transact io n)

________________________________________

Timing Diagram

________________________________________

Description

•A fter the addres s phase on the P CI bus ( clock 3) and the C/B E0=0 veri ficati on

the address dec oding phase of the target (c locks 3 to 4) is act ive.

•The by te addr ess for the t rans ac tion on the par allel int er face is gener ated out

of the P CI addres s AD9- 2 by mapping it to the par allel inter face addres s bus

PA7-0.

•One PCI c loc k af ter the PCI data phase is finished the data fr om t he P CI bus

is plac ed on the data bus P AD7-0 (cloc k 5) and t he write trans action star ts.

•The data is plac ed fr om t he P CI bus on P AD7-0 asser ting the WR signal and

a CS 2- 0 signal.

•A new acc es s to the par allel interfac e could be ac cepted with an addres s

phase at clock 9. Any acc ess before would be cancelled wit h Retry because

the PCI Inter face is process ing the last acc es s.

________________________________________

ADR DATA

CMD XXX0

XXXX PCI-ADR[9-2] XXXX

PCI-DATA[7-0]

12345678910111213

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PA7-0

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 85 01.00

________________________________________

Example

As an example the value 0A4h shall be written at address 005h of the device

connected to CS1. In this example the Base Address Register 1 (BAR1) shall

c ontain the addr ess 20004000h.

•CS1 is activated for the address space 400h to 7FFh. Ther efore the device’s

addr es s space starts at PCI address BA R1+400h= 20004400h.

•Only the lower by te of eac h 32bit word trans ferr ed to and f rom the PITA - 2 ov er

the P CI bus is us ed for the parallel interface. Therefore the r elative PCI

addr es s is four times the relativ e dev ic e addr es s: r el. PCI address = four times

005h = 014h.

•The abs olute PCI addr es s for the data trans fer is

BAR1+400h+014h=20004414h.

•Only the low by te of a 32 bit dat a wor d matt er s , the upper thr ee byt es ar e

ignor ed by the PITA - 2. In order to write the value 0A 4h the data word

000000A4 can be written to PCI addres s 20004414h.

________________________________________

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 86 01.00

5.2.5 Non M ultiplexed Mode ( Read Transaction)

________________________________________

Timing Diagram

________________________________________

Description

•A fter the addres s phase on the P CI bus ( clock 3) and the C/B E0=0 veri ficati on

the address dec oding phase of the target (c locks 3 to 4) is act ive.

•The by te addr ess for the t rans ac tion on the par allel int er face is gener ated out

of the P CI addres s AD9- 2 by mapping it to the par allel inter face addres s bus

P A7- 0 (c lock 5) .

•The following P CI c loc k ass er ts the signals RD and CS 2-0.

•A fter 5 c loc k s the RD signal is deassert ed.

•The data from P AD7- 0 is fetc hed.

•With t he nex t cloc k the data is placed on t he P CI bus and the data phase is

finished by deasserting the TRDY signal.

•The 8 bit data fr om the par allel interfac e is placed an the last s ignific ant by te

of the P CI data bus AD7-0.

________________________________________

ADR DATA

CMD XXX0

XXXX PCI-ADR[9-2] XXXX

DATA[7-0]

12345678910111213

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PA7-0

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 87 01.00

5.2.6 Multiplexed Mo de ( Write Tran saction)

________________________________________

Timing Diagram

________________________________________

Description

•A fter the addres s phase on the PCI bus (cloc k 3) and the C/ BE0=0 verification

the address dec oding phase of the target (c locks 3 to 4) is act ive.

•The by te address for t he trans ac tion on the parallel interface addr ess is

gener ated out of the PCI address A D9- 2 by mapping it t o the parallel interface

addr es s bus PA7- 0.

•One PCI c loc k af ter the PCI data phase is finished the data fr om t he P CI bus

is plac ed on the data bus P AD7-0 (cloc k 5) and t he write trans action star ts.

•The data is plac ed fr om t he P CI bus on P AD7-0 asser ting the CS2- 0 signal.

•The ALE signal is deasser ted.

•With the following P CI clock the data from t he P CI bus is placed on P AD7-0

(clock5).

•The WR signal is asserted.

•A new acc es s to the par allel interfac e could be ac cepted with an addres s

phas e at clock 11. Any ac ces s bef or e would be c ancelled with Retr y bec aus e

the PCI Inter face is process ing the last acc es s.

________________________________________

ADR DATA1

CMD XXX0

PCI-ADR[9-2] PCI-DATA1[7-0]

12345678910111213

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 88 01.00

5.2.7 Multiplexed Mo de ( Read Transactio n)

________________________________________

Timing Diagram

________________________________________

Description

•A fter the addres s phase on the PCI bus (cloc k 3) and the C/ BE0=0 verification

the address dec oding phase of the target (c locks 3 to 4) is act ive.

•The by te addr ess for the t rans ac tion on the par allel int er face is gener ated out

of the P CI addres s AD9- 2 by mapping it to the par allel inter face addres s bus

P A7- 0 (c lock 5) .

•The following P CI c loc k ass er ts the ALE s ignal.

•A fter 2 c loc k s the ALE signal is deasser ted.

•The addr ess is held for one m ore c lock.

•A fter 5 c loc k s the RD signal is deassert ed.

•At the s ame time the data is lat ched in die P CI output regist ers.

•TRDY is as sert ed on the PCI bus to finish the data phase.

•At the nex t clock the CS2-0 and ALE s ignals are deas ser t ed.

________________________________________

ADR(00)

DATA1

CMD XXX0

PCI-ADR[9-2] DATA1[23-16]

1 2 3 4 5 6 7 8 9 10 11 12 13 14

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 89 01.00

5.2.8 Tr ansaction Discon nect with Targ et Abor t

________________________________________

Timing Diagram

________________________________________

ADR DATA ADR DATA

CMD XXX1 CMD XXX1

12345678910111213

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 90 01.00

________________________________________

Description

C/BE0 = 1: No transaction is started on selected parallel interface, due to the

wr ong by te enable. The P CI M ast er Target Controller disc onnec ts the trans ac tion

with tar get abort.

________________________________________

Co nfig urat io n Sp ace Register: 04h

Bit 30 System_Error_Signaled

Type RC

Defau lt Val ue 0b

Description This bit is set by the PITA’s PCI M ast er , if t he m ast er as s ert s

the sy st em error signal on the P CI bus . This oc curs if a

trans ac tion initiated by the PIT A is disc onnec ted wit h target

abort.

Bit 29 Master_Abort_Detected

Type RC

Defau lt Val ue 0b

Description I f no fast /m edium /slow or subtrac tive s lav e reacts to a P CI

tr ansact ion initiated by the PCI Mas ter, the m aster will

discard the tr ansaction and s et this bit.

Bit 28 Master_Abort_Detected

Type RC

Defau lt Val ue 0b

Description I f a P CI trans act ion initiated by the P CI Master is

dis c onnected with Tar get A bort , t he P CI master will set this

bit. The PCI M aster is not allowed to st ar t a new PCI

trans ac tion, until this bit is deasser ted.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 91 01.00

________________________________________

Bit 27 Target_Abort_Signaled

Type RC

Defau lt Val ue 0b

Description T his bit is s et by the PCI interface if a t ransaction was

dis c onnected with Tar get Abor t. The PI TA will disc onnect

trans ac tions with Tar get A bor t if illegal by te enables ar e

detected.

Bit 8 System_Error_Enable

Type RW

Defau lt Val ue 0b

Description I f this bit is ass erted, the P CI M as ter will ass er t the Sy s tem

Error Sig nal (SERR) if it rec eiv es a t arget abort during a

tr ansact ion initiated by it self.

Bit 2 Master_Enable

Type RW

Defau lt Val ue 0b

Description If this bi t is set to ’0’ the PCI Master is not allowed to start any

trans ac tion on the PCI B us.

Co nfig urat io n Sp ace Register: 04h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 92 01.00

5.2.9 Transact ion Terminat ion with Retry

________________________________________

Description’

Retry means that the PITA finishes a transaction without a data transfer by

asserting the signal STOP, because the parallel interface processes another

transaction.

The PCI Master Target Controller has to repeat the transaction until a slave

accepts the transaction with data transfer or target abort. This sequence is

inv is ible for the sof tware.

________________________________________

Timing Diagram

________________________________________

ADR1 DATA1 ADR2 DATA2

CMD1 XXX0 CMD2 XXX0

PCI-ADR[9-2] PCI-DATA1[7-0]

12345678910111213

FRAME

IRDY

TRDY

DEVSEL

AD31-0

C/BE3-0

STOP

CS2-0

ALE

PAD7-0

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 93 01.00

________________________________________

Expl anati on of ADR/CMD and ADR2/CMD2

A DR/ CMD: The PCI Mas ter Tar get Controller acc epts the wr ite trans ac tion

ADR2/CM D2: The second tr ansaction is retried.

________________________________________

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 94 01.00

5.2.10 Timing of the Pa rallel In te rfa c e

________________________________________

Read Tim ing

________________________________________

W rite Timing

________________________________________

Mu lt ip lexed Address Timing

________________________________________

RD x CS

AD0-AD7

Data

WR x CS

AD0-AD7

Data

ALE

WR x CS or

RD x CS

AD0-AD7

ALS

Address

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 95 01.00

________________________________________

Non M ultiplex e d Addre ss Timing

________________________________________

Appl ication Re set and Int err u pt T im ing

________________________________________

Address

A0-A7

WR x CS or

RD x CS

valid state

PRST, SRST

Host wri te

access to

the register

ROD

previous state

IN T O (i)

IO D

INTA (o)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 96 01.00

________________________________________

Ab breviation s of th e Timin g Diagrams

Parameter Sym-

bol PCI

Clo ck

Cycles

Lim it

Values Unit

min. max

A LE puls e widt h tAA 5 150 ns

Addr es s setup tim e t o A LE tAL 130 ns

Addr es s hold tim e f r om ALE tLA 130 ns

Address latch setup time to WR,

RD tALS 130 ns

Addr es s setup tim e tAS 130 ns

Addr es s hold tim e tAH 130 ns

A LE guard t ime tAD 130 ns

RD pulse width t RR 5 150 ns

Data output delay from RD tRD 5 150 ns

Data float from RD tDF 130ns

RD control interv al tRI 5 150 ns

W pulse widt h tWW 390 ns

Data setup time to W x CS tDW 260 ns

Data hold time W x CS tWD 130 ns

W cont rol inter val tWI 390 ns

Re se t Ou tp u t D e l a y tROD 390ns

Inter rupt O utput Delay tIOD 260ns

PSB 4610
Communication with External Com ponent s
Preliminary  Data Sheet  97 01.00
 
5 .3 Gene ra l Purpo se I/O Inte rfac e
________________________________________
________________________________________
Overview
Overview Page
Infor mat ion about the GP I/ O Interfac e 98
Timing of the GP  I/O Interfac e 100
Inter nal Regist ers of the GP  I/O Interface 101
Input Mode 107
Output Mode 109
Inter rupt Mode 111
Usage of the GP  I /O Inter fac e as ALIS V2. 1 Control Inter face 113

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 98 01.00

5.3.1 Inf ormat ion abo ut th e GP I/O Interface

________________________________________

Description

For additional ac cess to ext ernal devices with a slow int erfac e behavior a 4 bit

General P urpose I/ O interface is im plem ented in the PITA.

________________________________________

Appl ication Interr up t

•The PCI inter fac e supports a separ ate int errupt input with progr am mable

polarity.

•The four pins of t he gener al purpos e I/ O inter fac e can be us ed as additional

interr upt input s.

•E ach of thes e fiv e interr upts has an I nterr upt_Enable bit and an

Interrupt_Contr ol_S tat us bit .

•For the separate input t he enable an polarity bits are located in t he Inter r upt

Contr ol Regis ter .

•For the Gener al P ur pose I/ O the enable bit s ar e located in t he Interface Control

________________________________________

Pinning

Pin Pi n N am e Ge ne r a l P u r pos e I/O

Function SPI EEPR O M

Function

2 GP0 I/O/Int. SO

3 GP1 I/O/Int. SI

4 GP2 I/O/Int. SCK

5 GP3 I/O/Int. –

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 99 01.00

________________________________________

Co ntrol Registers fo r GPx Pins

Interrupt Control Register

- ICR GPx_I NT GP Int errupt Status

GP I/O In te rface C o n trol

GPx_INT_En GP Interrupt Enable

GPx_OUT_En GP Output Enable

GPx_OUT GP Output Value

GPx_I N GP Input V alue

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 100 01.00

5.3.2 Timing of the GP I/O Interfac e

________________________________________

Timing Diagram

________________________________________

valid state

Host write

access

GP0-3 (o)

GPx configured

as output

ISU

IHO

valid state

Host read

access

GP0-3 (i)

GPx configured

as input

IOD

GPx configured

as interrupt input

GP0-3 (i)

INTA (o)

Ab breviation s of th e Timin g Diagram

Parameter Symbol Limit Values Unit

min. max.

GPx Output Data Delay tOD 90 ns

GP x Input Data Setup tISU 30 ns

GP x Input Data Hold tIHO 30 ns

GPx In te rru p t Ou tp u t

Delay tIOD 90 ns

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 101 01.00

5.3.3 Int e rnal Regist e rs of the GP I/O Int erf ace

________________________________________

Inter nal Register: 00h

Bit 5 GP3_INT

Type RC

Defau lt Val ue 0b

Description T he G P3 pin can be us ed as ’active lo w’ inter rupt input if

GP3_Int_En=’1’ and GP 3_Out_En= ’0’.

Th e b it i s set to ’1’ if bot h ar e tr ue and low is detec ted at this

pin.

Bit 4 GP2_INT

Type RC

Defau lt Val ue 0b

Description T he G P2 pin can be us ed as ’active lo w’ inter rupt input if

GP2_Int_En=’1’ and GP 2_Out_En= ’0’.

Th e b it i s set to ’1’ if bot h ar e tr ue and low is detec ted at this

pin.

Bit 3 GP1_INT

Type RC

Defau lt Val ue 0b

Description T he G P1 pin can be us ed as ’active lo w’ inter rupt input if

GP1_Int_En=’1’ and GP 1_Out_En= ’0’.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 102 01.00

________________________________________

Bit 2 GP0_INT

Type RC

Defau lt Val ue 0b

Description T he G P0 pin can be us ed as ’active lo w’ inter rupt input if

GP0_Int_En=’1’ and GP 0_Out_En= ’0’.

Inter nal Register: 00h (cont’d)

Inter nal Register: 18h

Bit 27 GP3_Int_En

Type RW

Defau lt Val ue 0b

Description Bit 27=’1’: GP 3 is conf igured as input, the pin is used as an

interr upt input with GP 3_Int _en as corres ponding bit in the

Inter r upt Contr ol Regis ter.

B it 27= ’1’: GP3 is not used as an interrupt pin.

Bit 26 GP2_Int_En

Type RW

Defau lt Val ue 0b

Description Bit 26=’1’: GP 2 is conf igured as input, the pin is used as an

interr upt input with GP 2_Int _en as corres ponding bit in the

Inter r upt Contr ol Regis ter.

B it 26= ’0’: GP2 is not used as an interrupt pin.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 103 01.00

Bit 25 GP1_Int_En

Type RW

Defau lt Val ue 0b

Description Bit 25=’1’: GP 1 is conf igured as input, the pin is used as an

interr upt input with GP 1_Int _en as corres ponding bit in the

Inter r upt Contr ol Regis ter.

B it 25= ’0’: GP1 is not used as an interrupt pin.

Bit 24 GP0_Int_En

Type RW

Defau lt Val ue 0b

Description Bit 24=’1’: GP 0 is conf igured as input, the pin is used as an

interr upt input with GP 0_Int _en as corres ponding bit in the

Inter r upt Contr ol Regis ter.

B it 24= ’0’: GP0 is not used as an interrupt pin.

Bit 19 GP3_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 19=’1’: GP _3 is configured as output pin.

B it 19= ’0’: GP _3 is configur ed as input pin.

Bit 18 GP2_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 18=’1’: GP _2 is configured as output pin.

B it 18= ’0’: GP _2 is configur ed as input pin.

Inter nal Register: 18h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 104 01.00

Bit 17 GP1_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 17=’1’: GP _1 is configured as output pin.

B it 17= ’0’: GP _1 is configur ed as input pin.

Bit 16 GP0_Out_En

Type RW

Defau lt Val ue 0b

Description Bit 16=’1’: GP _0 is configured as output pin.

B it 16= ’0’: GP _0 is configur ed as input pin.

Bit 11 GP3_IN

Type R

Description Actual Value on the GP3 pin (pin f eedback)

Bit 10 GP2_IN

Type R

Description Actual Value on the GP2 pin (pin f eedback)

Bit 9 GP1_IN

Type R

Description Actual Value on the GP1 pin (pin f eedback)

Inter nal Register: 18h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 105 01.00

Bit 8 GP0_IN

Type R

Description Actual Value on the GP0 pin (pin f eedback)

Bit 3 GP3_OUT

Type RW

Defau lt Val ue 0b

Description The GP3 pin is driven with the value written to this output

r egis ter if the GP3_OUT_E n is set to ’1’.

Bit 2 GP2_OUT

Type RW

Defau lt Val ue 0b

Description The GP2 pin is driven with the value written to this output

r egis ter if the GP2_OUT_E n is set to ’1’.

Bit 1 GP1_OUT

Type RW

Defau lt Val ue 0b

Description The GP1 pin is driven with the value written to this output

r egis ter if the GP1_OUT_E n is set to ’1’.

Inter nal Register: 18h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 106 01.00

________________________________________

Bit 0 GP0_OUT

Type RW

Defau lt Val ue 0b

Description The GP0 pin is driven with the value written to this output

r egis ter if the GP0_OUT_E n is set to ’1’.

Inter nal Register: 18h (cont’d)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 107 01.00

5.3.4 Input Mode

________________________________________

Description

For using a general purpose I/O pin as input pin, the control register must be

c onfigur ed as follows:

GPx_OUT_En = ‘0’(Out put disabled)

GPx_INT_En = ‘0’(Interr upt dis abled)

(x := [0, 3 ])

Des cr iption of the inter nal r egis ter 18h on page 102.

The GP x_O UT and GPx _INT bit s can be tr eated as don’t care in this mode. The

cur rent signal value at the pin G Px can be read from r egis ter bit GP x_IN.

________________________________________

Inter nal Structure of a GPx Inp ut Pin

________________________________________

Timing Diagram

________________________________________

GPx_IN

GPx

ISU

IHO

valid state

Host read

access

GP0-3 (i)

GPx configured

as input

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 108 01.00

________________________________________

Ab breviation s of th e Timin g Diagram

Parameter Symbol Limit Values Unit

min. max.

GP x Input Data Setup tISU 30 ns

GP x Input Data Hold tIHO 30 ns

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 109 01.00

5.3.5 Output Mode

________________________________________

Description

For us ing a general purpos e I/O pin as output pin, the contr ol register mus t be

c onfigur ed as follows:

GPx_OUT_En = ‘1’(Out put enabled)

GPx_INT_En = ‘don’t c a re ’

(x := [0, 3 ])

Des cr iption of the inter nal r egis ter 18h on page 102.

The GPx _IN and G Px_INT regist er bits c an be treated as don’t car e in this m ode.

The GPx pin will drive the connected signal line with the value defined in the

GP x _OUT r egis ter bit, whic h is progr am med by the hos t.

________________________________________

Inter nal Structure of a GPx Output Pin

________________________________________

GPx_Out

GPx

GPx_Out_En

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 110 01.00

________________________________________

Timing Diagram

________________________________________

valid state

Host write

access

GP0-3 (o)

GPx configured

as output

Ab breviation of t he Timing Diagram

Parameter Symbol Limit Values Unit

min. max.

GPx Output Data Delay tOD 90 ns

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 111 01.00

5.3.6 Int errupt M ode

________________________________________

Description

For us ing a general purpos e I/O pin as output pin, the contr ol register mus t be

c onfigur ed as follows:

GPx_OUT_En = ‘1’(Out put disabled)

GPx_INT_En = ‘1’(Interr upt enabled)

(x := [0, 3 ])

Des cr iption of the inter nal r egis ter 18h on page 102.

The GPx _OUT regis ter bit c an be tr eated as don’t car e in this m ode. The GPx pin

ac ts as an active low inter r upt input pin.

If the dev ice detects ’0’ at the G P x pin

•the GP x _INT register is set to ’1’

•an interrupt on the PCI bus is gener ated

•the curr ent state of the GP x pin c an be read from GPx _IN bit or c an be treated

as don’t ca re.

________________________________________

Inter nal Structure of a GPx Inter rupt Inp ut pin

________________________________________

Timing Diagram

________________________________________

GPx_IN

GPx

>=1

INTA

IOD

GPx configured

as interrupt input

GP0-3 (i)

INTA (o)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 112 01.00

________________________________________

Ab breviation of t he Timing Diagram

Parameter Symbol Limit Values Unit

min. max.

GPx In te rru p t Ou tp u t

Delay tIOD 90 ns

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 113 01.00

5.3.7 Usag e of th e GP I/O Interface as ALIS V2.1 Con trol Interface

________________________________________

The serial cont r ol inter fac e of the ALI S V2.1 can be r ealiz ed by s oft war e us ing the

General P urpose I/ O pins.

The GP3 pin is used as CS pin while the other three GPx pins ar e shared with the

SPI EE PR O M In t erf a ce.

The INT0 pin of the PITA can be pr ogr amm ed to be active on a H lev el. Ther efore

this pin c an be connect ed direct ly to the INT pin of the ALIS .

The GP3 pin is dr iv en high during the autom atic E EPR OM configuration phas e

after a system r es et to disable the ALIS V2. 1 c ontr ol int er face.

Pin description on page 162.

________________________________________

Description

PIT A Si gn a ls ALIS Signals Description

GP3 Out CS Chip s elec t ( ac tive low) , for enabling

the P SB4596 Contr ol Int erf ace.

GP2 Out DCLK Clock signal for the Cont r ol

Interface.

(P SB 4596 acc epts 1 k Hz to 1024

kHz)

GP1 In DOUT Data input for PITA, data output from

PSB4596.

Data input is latched at the negat ive

DCLK edge.

GP0 Out DIN Data output from PITA, data input for

PSB4596.

Data output changes with the rising

DCLK edge.

INT0 In INT Interr upt signal (high ac tive)

S RST Out RE SE T Res et signal (low ac tive)

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 114 01.00

________________________________________

Timin g Diagram for a Write T ransactio n with two Dat a Bytes transmitted

________________________________________

Timin g Diagram fo r a Read Access with one Data Byte received via DOUT

________________________________________

GP3 (o) / CS (i)

GP2 (o) / DCLK (i)

GP1 (i) / DOUT (o)

GP0 (o) / DIN (i)

High `Z´

Control Data Byte 1 Data Byte 2

Control Frame

6 1237 45 0 6 1237 45 0 6 1237 45 0

GP3 (o) / CS (i)

GP2 (o) / DCLK (i)

GP1 (i) / DOUT (o)

GP0 (o) / DIN (i)

High `Z´

Control Identification Data Byte 1

Control Frame

6 1237 45 0

6 1237 45 0 6 1237 45 0

High `Z´

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 115 01.00

5 .4 SPI EEPROM Int erf ac e

________________________________________

Overview

Overview Page

Infor mat ion about the SP I EEP ROM Interfac e 116

Timing of the SPI E EP ROM I nter face 119

Inter nal Regist ers for the SPI E EP ROM Inter face 121

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 116 01.00

5.4. 1 Informati on about the SPI EEPROM Interface

________________________________________

Description

Three pins are us ed to provide an SP ITM- c ompatible serial inter face to a 256 x 8

bit EEPROM. These pins also do double-duty as part of the General Purpose

Inter fac e. Two other pins are also us ed to s elec t the E E PROM c hip and to enable/

dis able the aut omatic r ec onfiguration of the conf igur ation s pace by the EE PROM .

This would occur after a sy stem r eset.

The EEP ROM can be us ed for :

•A utom atic reconfiguration of the PITA.

•Cust omer spec ific pur poses (e.g. s torage of serial boar d num bers).

________________________________________

Au t omat ic reconfig uration of t he PITA

Parts of the PCI Configuration Space can be configured with data from this

ext ernal EE PROM aft er s ystem reset . The following sequence is processed by

the P ITA:

•The PI TA c hec ks :

–Whether the ELD ( EEP ROM_Load) pin is clamped to ’1’.

–Whether the firs t byte in the EE PRO M (addr es s loc at ion 00h) is A Ah.

•If t he fir s t step was succ essful, the PITA s tarts:

–Reading out four by tes s tarting wit h addr es s 01h.

–Wr iting t he r ead values in the configur ation s pace address 00h.

–Reading out the next four bytes.

–Wr iting t he r ead values in the configur ation s pace address 04h.

–And so on.

________________________________________

Note

Dur ing the c onfigur ation phas e, all ac ces s to t he PCI interface are ans wer ed with

’Retry’ by the PIT A.

________________________________________

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 117 01.00

________________________________________

Using t he EEPROM for customer specific pu rposes

The c ontents of the EE PRO M can be programm ed by wr iting a com mand to the

EEPROM Control Register and initiating a read/write transaction to the

EEPROM.

________________________________________

Note If the aut omatic r econfiguration of the PIT A is us ed ( ELD pin c lam ped t o ’1’) , only

those addresses in the EEPROM not mapped to the PCI configuration space

should be used.

________________________________________

Starting a read or write tr ansaction

The c ontents of the EE PRO M can be programm ed by wr iting a com mand to the

EEPROM Control Register and initiating a read/write transaction to the

EEPROM.

•The hos t wr ites

–The EEPRO M Command value before the nex t EE P ROM tr ansfer is s tarted.

–The EEP ROM Byte Address v alue for read or wr ite ac c ess.

–The E EPROM Data v alue for the ’W rite St atus Register ’ and ’W rite Data to

Me mory Array’.

•The hos t set s the E EPROM_S tart bit.

•If the EEP RO M interface detects t he as serted EE PROM _St art bit; it

–Interprets the EEP RO M Comm and.

•Start s t he r ead or write trans action to the connect ed E EP ROM .

•If t he tr ans actions are s tar ted via the EEP ROM Control r egis ter, then the

EE PROM interface does not check for a connect ed E EPROM .

________________________________________

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 118 01.00

________________________________________

Aft er fin ishing t he t ransaction:

•The EEP ROM cont r ol module:

–Deas ser ts the EEP ROM_S tar t bit .

–Generates an interrupt in the EEP ROM Control Int Register, if the

EE PRO M _Control_Int_en bit is set t o ’1’.

•If T he E E PROM Com mand Register is s et to RDSR or REA D, then t he v alue

of the E EPROM is av ailable in the EEP ROM Data Register.

________________________________________

Co nnectio n of an ALIS V2.1 device to the Serial Con trol Interface

For the c onnection of an ALIS V2. 1 device to t he Ser ial Control Int erfac e of t he

PITA the G P3 pin is additionally used as low act ive chip select s ignal CS to t he

ALIS V2.1.

The GP3 pin is always driven ’high’ and therefore the ALIS V2.1 interface is

inactive during the phase of automatic initialization of the PCI Configuration

Space.

________________________________________

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 119 01.00

5.4.2 Timing of the SPI EEPROM Int erf ace

________________________________________

Timing Diagram

________________________________________

CSS

CYC

CLH

CLL

ISU

IHO

CSI

CSH

OSU

OHO

LSB out

LSB in

high-Z

EPCS (o)

SCK (o)

SO (i)

SI (o)

Ab breviation s of th e Timin g Diagram

Parameter Symbol Limit Values Unit

min. max.

Chip Select S etup Tim e tCSS 500 ns

Chip Select Hold Tim e tCSH 500 ns

C hip Select Inactive tCSI 500 ns

Cl ock Cycle Time t CYC 1000 ns

Clo ck H IGH Ti me tCLH 410 ns

Clock LOW Time tCLL 410 ns

Clock Output Ris e Tim e tOR 2µs

Clock Output Fall Tim e tOF 2µs

Input Data Setup T ime tISU 100 ns

Input Data Hold T ime tIHO 100 ns

Output Data Setup Time tOSU 500 ns

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 120 01.00

________________________________________

Note T he S CK is a s trobed clock signal (i. e. it is only ac tive as long as valid data is

tr ans ferr ed on SI /SO line) and output data is wr itten on the falling edge and input

data is lat ched on the ris ing edge. Although t he fir st SCK edge is pos it ive, t he

PITA drives the firs t valid bit on S I (output) with the falling edge of EP CS, so the

m inim um setup tim e with respec t to the first S CK rising edge is guar anteed.

________________________________________

Output Data Hold T ime t OHO 0 500 ns

Output Disable T ime tOD 500 ns

Wr ite Cycle Time tWC 10 ms

Ab breviation s of th e Timin g Diagram (cont’d)

Parameter Symbol Limit Values Unit

min. max.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 121 01.00

5.4.3 Int ernal Registers f or the SPI EEPROM Interface

________________________________________

Inter nal Register: 00h

Bit 28 EEPROM_Control_Int_En

Type RW

Defau lt Val ue 0b

Description Enable for the EEP ROM_Control_Int interrupt bit

Bit 12 EEPROM_Control_Int

Type RC

Defau lt Val ue 0b

Description The E EP ROM_Control_Int_E n bit and the E EPROM ar e set

to ’1’ if the trans action is finis hed.

Inter nal Register: 24h

Bit 31:0 EE PRO M Contr ol Regist er

Defau lt Val ue 00000000h

Bit 24 EEPROM_Start

Type RW

Defau lt Val ue 0b

Description Bit 24=’1’: An EEPROM transaction is started with the

EEPROM Command, EEPROM Data and EEPROM Byte

Address.

BI T 24=’0’: An EE PROM trans act ion can be started.

PSB 4610

Communication with External Com ponent s

Preliminary Data Sheet 122 01.00

________________________________________

Bit 23:16 EEPR O M Co mm a nd

Type RW

Defau lt Val ue 00h

Description The following SP I com mands ar e s uppor ted:

’00000110’: W RE N S et Write Enable Latch

’00000100’: W RDI Res et Write Enable Lat ch

’00000101’: RDSR Read St atus Register

’00000001’: WRSR W rite Status Regist er

’00000011’: READ Read Data from M emor y A rray

’00000010’: WRIT E W rite Dat a to Me m o ry Ar ra y

’OTHERS’: No action

Bit 15:8 EEPR O M By te Ad dre ss

Type RW

Defau lt Val ue 00h

Description Byte Address for the next EEPROM read or write

transaction.

Bit 7:0 EEPR O M Da ta

Type RW

Defau lt Val ue 00h

Description •Tr ans ac tion with a read c omm and:

Af ter the tr ansact ion has been finis hed this regist er

cont ains t he byte that has been read fr om the EEP ROM.

•Tr ans ac tion with a write c om mand:

The c ontents of this regis ter will be writt en to t he

EE PRO M By te Address if t he connec ted EEP RO M aft er

the EEPROM_Start bit is s et.

Inter nal Register: 24h (cont’d)

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 123 01.00

6 Pow er Management

________________________________________

Overview

Overview Page

Infor mat ion about the Power Supply Concept 124

Infor mat ion about the Power Management States 126

Configuration Space Regist ers of the Power Managem ent 131

E lectr ical Charac teristics 146

Compatibility Is sues 147

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 124 01.00

6.1 Inform at ion about t he Pow er S u ppl y Concept

________________________________________

Three different P ower Supplies

The PITA -2 has three dif fer ent power s upplies. It may be helpful for t he sys tem

des ign t o under s tand the scope of eac h of these s upplies .

•VIO

This supply is internally connec ted to all s ignals intended for the PCI bus ( pin

num bers 8-12, 16- 60 and 64) .

V IO can be either 3.3V or 5V and is der iv ed from the VIO s upply of the PCI bus.

This supply has an eff ect on the thres holds of t he input st r uct ur e in or der to

c omply with the PCI bus spec ification. Ther efor e t he P ITA -2 can be operated

in either 5V or 3.3V signaling environm ent as s pec ified in the PCI Loc al Bus

Spec if icat ion Revision 2.2

•VDD3

This supply power s the same pins as listed f or V IO. It is used for the out put

dr iv er s of the PCI bus s ignals and m us t be limited t o 3.3V at all times ( ev en

when VIO is 5V). This supply does not power the internal logic of the PITA -2.

It does, howev er , power t he loc al bus signals ( pin number s 1- 7, 65- 74, 76-87

and 90- 100). If this supply is pr esent the input signals on the local bus s ignals

c an be as high as 5V.

•VAUX

This supply als o powers the local bus signals ( pin number s 1- 7, 65-74, 76-87

and 90- 100) as well as the internal logic . This power supply is 3.3V only. If this

s upply is not pres ent, the PI TA-2 can not generate a PME event, the output

v oltage on any of the above mentioned signals is undefined and t he input

v oltage at any of t hese pins m us t not exc eed VA UX by more than 0.3V.

If this s upply is pr es ent, then t he PI TA is fully oper ational and the input signals

on the loc al bus signals c an be as high as 5V .

________________________________________

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 125 01.00

________________________________________

Summary Information

Supply Voltage Comment

VIO 3.3V or 5V For P CI bus only , affec ts input thr es hold, alm ost no

cur r ent. S hould be pres ent at all tim es .

VDD3 3.3V For P CI and local bus , decouples internal logic from

P CI bus. S hould be pres ent at all tim es ex cept

D3c old. If present, the local bus signals can tolerate

5V.

V AUX 3.3V S upplies inter nal logic , mus t be present for 5V

toler anc e of loc al (non P CI s ignals) input signals. Can

be swit ched of f when D3c old is not supported.

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 126 01.00

6.1.1 Inform ation about the Power Management States

________________________________________

Description

The PITA-2 supports the Power Management states D0, D1, D2, D3hot and

D3cold.

The P ITA- 2 c an ass er t t he PME s ignal even if the PCI cloc k (CLK) is not running.

Furthermore the PITA-2 has a separate power supply (Vaux) which meets the

power c onstraints ( 20 m A) for the PCI Vaux supply (dis abled slots) . T heref or e the

PITA-2 fully supports the D3c old st ate.

A separate Application Note describes a power supply circuitry for a D3cold

enabled PITA- 2.

Please note t hat bits 8 (PM E_E n) and 15 ( PME _Status ) of configuration spac e

r egis ter 44h are not af fected by a P CI r eset . This behav ior allows the PCI device

dr iv er t o determ ine the PCI dev ic e( s) that s ignalled the P ME ev ent.

________________________________________

D0 •The D0 state represents the default state of the internal logic aft er a sys tem

reset.

•After a system reset the PCI interface has t o be init ialized before being used.

•The PI TA- 2 r es ponds only to configuration access es while not com pletely

initialized.

•After initialization the PI TA -2 is fully operational.

________________________________________

D1 •D1 is a light s leep st ate.

•The P ITA-2 supports the D1 st ate by default if this state is not disabled by an

E EP ROM c onfigur ation.

•The PI TA- 2 P CI func tion can be s et to the D1 state by software.

•The P ITA-2 PCI f unction only r esponds to PCI configuration acces ses.

•All accesses to the memory spaces defined by the Base Address Registers are

disabled.

•The only PCI bus operation the PCI int erfac e is allowed to initiate is t he

ass ertion of the PME signal.

•Tr ans ition t o D0 by soft ware is pos s ible.

________________________________________

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 127 01.00

________________________________________

D2 •B y default the suppor t of t he D2 state is dis abled in the PI TA-2.

•D2 can be enabled by configuration by an E EPROM.

•Sam e s tat e behavior as described for the state D1.

________________________________________

D3 •Sam e s tat e behavior as described for the state D1.

•The only legal state trans it ions f rom D3 to D0 are:

–by sof tware reset; the software has to perfor m a fully reinitialization of the

P CI func tion inc luding the PCI Configur ation S pace.

–by sys tem rese t

________________________________________

D3hot•P ower and c loc k are s till av ailable to the PI TA- 2.

•P ower and c loc k can be r etur ned to D0 by soft war e.

•State behavior as des cribed f or the stat e D3.

________________________________________

D3cold (Stan dby)

•D3cold is a “power off ” st ate.

•The P CI clock is turned off .

•The PCI bus power V cc has been disconnec ted.

•A s long as the PI TA-2 is s upplied with power on the V aux pins it can s till ass er t

PME.

•The P ITA-2 can assert P ME even if the PCI cloc k is not available.

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PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 128 01.00

6.1.2 Con siderat ion s abou t Power Con sumpt ion and Reporting

________________________________________

Definitions

First of all it is important to distinguish between a PCI component and a PCI

device.

T he PCI component is the circ uitry that is interfacing the P CI bus. A s an example

the P ITA- 2 is a P CI bus component .

T he PCI device is the circuitry designed to perform a specific function (e.g. a

m odem ) inc luding the PCI c omponent.

Ther efore for all power c ons umpt ion c alc ulations or m easurem ents it is im portant

to add up the power r equir em ents of all t he circ uitry that is act iv e in a giv en s tat e.

Fur therm or e it is impor tant to dist inguis h between PCI slots that are disabled and

thos e that ar e enabled.

________________________________________

Power Consumption

A disabled PCI slot may draw up to 20 mA from power supply VAUX. A PCI

dev ic e which occ upies a disabled slot does not have to suppor t D3cold state. A s

the P ITA-2 draws a max imum of 19 m A it can be left connect ed to VA UX all the

time provided that the external circuitry is switched off (by using the PME_En

signal).

An enabled PCI slot may consume up to 375 mA when in D3cold state. This

leav es enough headroom (356 m A) for ext er nal c ir c uitry to trigger the PITA - 2 f or

a PME ev ent.

________________________________________

Reporting

The P CI Bus Power Managem ent Inter face S pecification s pec ifies two ways that

allow the operating system or ot her soft ware to det ermi ne the power consumption

of a PCI device:

•Coar se r epor ting by r egis ter 40h:8- 6 ( A ux _Curr ent)

•Ex tended reporting by using t he dat a selec t mechanism

The P ITA- 2 s upports both ways. It is up to the P CI dev ic e designer to choos e the

r epor ting mechanis m and also whic h v alues are r eported.

Ex tended reporting overrides coar se r eporting.

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PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 129 01.00

________________________________________

Co arse Repo rting

This mechanis m is implemented by the Aux Curr ent field ( r egister 40h) . I t is only

pos sible t o r eport a single range for the m ax . c ur r ent drawn by the P CI device and

this range only applied for state D3cold.

________________________________________

Assignments

________________________________________

Exte nd e d Re porting

This mechanis m allows a detailed power cons umpt ion repor ting. It is poss ible to

report individual power limits for each power state. Furthermore there is no

pr edefined range which m ay fit m ore or less but all values c an be specified by the

P CI designers as needed.

The actual data is retrieved by first selecting a specific item (e.g. D2 Power

Consumed) by writing a select code into the Data Select field in register 44h.

Then the PIT A-2 mir ror s the selec ted v alues t o the Data and the Data S c ale field

of regist er 44h. The softwar e can then read thes e two values. The t able below

s hows the way the Data S c ale f ield should be interpr eted for single f unct ion P CI

devices.

8 76M ax. Curren t ( mA)

1 1 1 375

1 1 0 320

1 0 1 270

1 0 0 220

0 1 1 160

0 1 0 100

0 0155

0 0 0 0 (self powered)

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 130 01.00

________________________________________

Data Selected — Data Reported

________________________________________

Note The unit for all values is Watts .

________________________________________

The Data Scale field modifies the value of th e Data field as fo llows:

The act ual data c an be s tor ed in the ext er nal E EPROM. A t res et the PITA -2 loads

the data into the appropriate regist ers.

Data Select Data Reported

0 D0 P ower Consum ed

1 D1 P ower Consum ed

2 D2 P ower Consum ed

3 D3 P ower Consum ed

4 D0 P ower Dis sipated

5 D1 P ower Dis sipated

6 D2 P ower Dis sipated

7 D3 P ower Dis sipated

Data Scale Modifier

0 Unknown

1x 0.1

2 x 0.01

3 x 0.001

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 131 01.00

6.1.3 Con f igu ration Space Registers o f the Power Managemen t

________________________________________

Configur ation Register related to Power Management

There are basically two types of configuration registers related to power

management:

•Contr ol Regis ter s

•Data Regis ter s

The c ontrol regis ter s ( 40h and 44h) define the capabilities and the behav ior of the

P ITA - 2. As an ex am ple bit 26 in regis ter 40h defines whether the PITA -2 supports

D2 or not .

The data registers (48h, 4Ch and 50h) reflect the power consumption of the

whole P CI device for eight diff er ent configurations. A c onfiguration is s elected by

a value in t he data s elect f ield of regis ter 44h. The corres ponding value is then

plac ed into the data field of r egis ter 44h.

The actual v alues have no eff ect on the operation or power cons umption of the

PITA-2. These values are calculated or measured by the PCI device designer

and can be stored in the external EEPROM. Please note that the PCI device

includes all external circ uit ry and us ually cons is ts not only of the P IT A- 2.

Regist er 34h is m erely a pointer to the fir st regist er of the power management

conf iguration space and hardwired to 40h.

________________________________________

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 132 01.00

________________________________________

Co nfig urat io n Sp ace Register: 34h

Bit 31:8 Reserved

Type H

Value 000000h

Description Reserved

Bit 7:0 Cap_Ptr

Type H

Value 40h

Description T he Capabilities Pointer points to the firs t Power

M anagement Regis ter in the PCI Configur ation Space.

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 133 01.00

________________________________________

Co nfig urat io n Sp ace Register: 40h

Bit 31:0 P ower M anagement Capabilities (PMC)

Bit 31 PME_Support_D3cold

Type E

Defau lt Val ue 0b

Description 0: P ME c annot be ass er ted in st ate D3cold

1: PM E can be asser ted in state D3cold

Bit 30 PME_Support_D3hot

Type E

Defau lt Val ue 0b

Description 0: P ME c annot be ass er ted in st ate D3hot

1: PM E can be asser ted in state D3hot

Bit 29 PME_Support_D2

Type E

Defau lt Val ue 0b

Description 0: P ME c annot be ass er ted in st ate D2

1: PM E can be asser ted in state D2

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 134 01.00

Bit 28 PME_Support_D1

Type E

Defau lt Val ue 1b

Description 0: P ME c annot be ass er ted in st ate D1

1: PM E can be asser ted in state D1

Bit 27 PME_Support_D0

Type E

Defau lt Val ue 0b

Description 0: P ME c annot be ass er ted in st ate D0

1: PM E can be asser ted in state D0

Bit 26 D2_Support

Type E

Defau lt Val ue 0b

Description •Not s uppor ted from the P ITA - 2 by default.

•Support c an be enabled by EE PROM.

Bit 25 D1_Support

Type E

Defau lt Val ue 1b

Description •The P ITA - 2 s uppor ts the D1 P ower s tat e by def ault.

•Can be disabled by E EP ROM.

Co nfig urat io n Sp ace Register: 40h (cont’d)

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 135 01.00

Bit 24:22 A ux Cur r ent

Type E

Defau lt Val ue 000b

Description This field can be us ed to r eport the VA UX curr ent dr awn by

the PCI device if t he Data Regis ter in r egis ter 44h is not

us ed. If the Data Register is used, this field m us t r ead 000b.

Otherwise the following as signments apply :

001: up to 55mA

010: up to 100mA

011: up to 160 m A

100: up to 220 m A

101: up to 270 m A

110: up to 320 m A

111: up to 375 m A

Bit 21 DS I (Devic e Specific Initializ ation)

Type E

Value 1b

Description Indicates that the P ITA-2 requires a s pecific init ialization

s equenc e f ollowing the tr ans ition t o D0 st ate (uninitializ ed) .

Bit 20 Reserved

Type H

Value 0b

Description Reserved

Co nfig urat io n Sp ace Register: 40h (cont’d)

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 136 01.00

Bit 19 PME_Clock

Type E

Defau lt Val ue 0b

Description The P ITA - 2 c an ass er t PM E without a running clock .

Whether this bit mus t be set is ther efore dependant on t he

ext ernal circ uitry that triggers the PITA -2 for a P ME event.

0: no c loc k requir ed

1: clock required

Bit 18:16 Version

Type E

Defau lt Val ue 010b

Description T he value 010b indicates t hat the device complies with the

Revision 1.1 of the PCI Pow er M anagement Interface

Specification.

Bit 15:8 Next_Item_Ptr

Type H

Value 00h

Description No next it em

Bit 7:0 Capabiltity_ID

Type H

Value 01h

Description Indicates that the data st ructure is cur rently pointed to the

P CI Power Management data struct ur e.

Co nfig urat io n Sp ace Register: 40h (cont’d)

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 137 01.00

________________________________________

Co nfig urat io n Sp ace Register: 44h

Bit 31:24 DATA_Register

Type H

Value 00h

Description Depending on the Data_S elec t field (B it 12:9) parts of the

P ower Data regis ter ( 48h) are mapped to this regis ter.

Bit 23:16 P MCS R_BS E (Bridge s uppor t extension)

Type H

Value 00h

Description not used

Bit 15 PME_Status

Type RC

Defau lt Val ue none (s ticky bit)

Description This bit is set when t he P CI int er face as s erts the PM E signal

independent of the stat e of the P ME _EN bit .

Bit 14:13 Data_Scale

Type H

Value 00b

Description Depending on the Data_S elec t field (B it 12:9) parts of the

Power _Data register are mapped to this register.

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 138 01.00

Bit 12:9 Data_Select

Type RW

Defau lt Val ue 0h

Description •Values from 0 - 7 ar e s uppor ted: Parts of the P ower_Data

Data_Sc ale field.

•V alues fr om 8 - 15: Z ero values ar e m apped to the DATA

Bit 8 PME_En

Type RW

Defau lt Val ue none (s ticky bit)

Description Enables or dis ables the P IT A-2 to asser t the PME signal.

PME_En=’0’: As s ert ion of the PM E s ignal is disabled.

PME_En=’1’: The devic e is enabled to ass er t the PME

signal.

Bit 7:2 Reserved

Type H

Value 00h

Description Reserved

Co nfig urat io n Sp ace Register: 44h (cont’d)

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 139 01.00

________________________________________

Bit 1:0 Power_State

Type RW

Defau lt Val ue 00b

Description Power_State=’00’: D0 s tate (s upported by the PIT A -2)

Power_State=’01’: D1 s tate (s upported by the PITA -2)

Power_State=’10’: D2 st ate (not suppor ted by default )

Power_State=’11’: D3hot state (supported by the PITA-2).

Co nfig urat io n Sp ace Register: 44h (cont’d)

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 140 01.00

________________________________________

Co nfig urat io n Sp ace Register: 48h

Bit 31:30 Reserved

Type H

Value 00b

Bit 29:28 D a ta Sca le fo r D a ta Se le ct = 2

Type E

Defau lt Val ue 00b

Description This v alue is mapped to t he Data Sc ale field of register 44h

when Dat a S elec t (als o in r egis ter 44h) is s et to 2.

Bit 27:20 Data for Data Sel ect = 2

Type E

Defau lt Val ue 00h

Description This v alue is mapped to the Data field of r egis ter 44h when

Data Selec t (also in register 44h) is s et to 2.

Bit 19:18 D a ta Sca le fo r D a ta Se le ct = 1

Type E

Defau lt Val ue 00b

Description This v alue is mapped to t he Data Sc ale field of register 44h

when Dat a S elec t (als o in r egis ter 44h) is s et to 1.

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 141 01.00

________________________________________

Bit 17:10 Data for Data Sel ect = 1

Type E

Defau lt Val ue 00h

Description This v alue is mapped to the Data field of r egis ter 44h when

Data Selec t (also in register 44h) is s et to 1.

Bit 9:8 D a ta Sca le fo r D a ta Se le ct = 0

Type E

Defau lt Val ue 00b

Description This v alue is mapped to t he Data Sc ale field of register 44h

when Dat a S elec t (als o in r egis ter 44h) is s et to 0.

Bit 7:0 Data for Data Sel ect = 0

Type E

Defau lt Val ue 00h

Description This v alue is mapped to the Data field of r egis ter 44h when

Data Selec t (also in register 44h) is s et to 0.

Co nfig urat io n Sp ace Register: 48h (cont’d)

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 142 01.00

________________________________________

Co nfig urat io n Sp ace Register: 4Ch

Bit 31:30 Reserved

Type H

Value 00h

Bit 29:28 D a ta Sca le fo r D a ta Se le ct = 5

Type E

Defau lt Val ue 00b

Description This v alue is mapped to t he Data Sc ale field of register 44h

when Dat a S elec t (als o in r egis ter 44h) is s et to 5.

Bit 27:20 Data for Data Sel ect = 5

Type E

Defau lt Val ue 00h

Description This v alue is mapped to the Data field of r egis ter 40h when

Data Selec t (also in register 44h) is s et to 5.

Bit 19:18 D a ta Sca le fo r D a ta Se le ct = 4

Type E

Defau lt Val ue 00b

Description This v alue is mapped to t he Data Sc ale field of register 44h

when Dat a S elec t (als o in r egis ter 44h) is s et to 4.

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 143 01.00

________________________________________

Bit 17:10 Data for Data Sel ect = 4

Type E

Defau lt Val ue 00h

Description This v alue is mapped to the Data field of r egis ter 44h when

Data Selec t (also in register 44h) is s et to 4.

Bit 9:8 D a ta Sca le fo r D a ta Se le ct = 3

Type E

Defau lt Val ue 00b

Description This v alue is mapped to t he Data Sc ale field of register 44h

when Dat a S elec t (als o in r egis ter 44h) is s et to 3.

Bit 7:0 Data for Data Sel ect = 3

Type E

Defau lt Val ue 00h

Description This v alue is mapped to the Data field of r egis ter 44h when

Data Selec t (also in register 44h) is s et to 3.

Co nfig urat io n Sp ace Register: 4Ch (cont’d)

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 144 01.00

________________________________________

Co nfig urat io n Sp ace Register: 50h

Bit 31:20 Reserved

Type H

Value 00b

Bit 19:18 D a ta Sca le fo r D a ta Se le ct = 7

Type E

Defau lt Val ue 00b

Description This v alue is mapped to t he Data Sc ale field of register 44h

when Dat a S elec t (als o in r egis ter 44h) is s et to 7.

Bit 17:10 Data for Data Sel ect = 7

Type E

Defau lt Val ue 00h

Description This v alue is mapped to the Data field of r egis ter 44h when

Data Selec t (also in register 44h) is s et to 7.

Bit 9:8 D a ta Sca le fo r D a ta Se le ct = 6

Type E

Defau lt Val ue 00b

Description This v alue is mapped to t he Data Sc ale field of register 44h

when Dat a S elec t (als o in r egis ter 44h) is s et to 6.

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 145 01.00

________________________________________

Bit 7:0 Data for Data Sel ect = 6

Type E

Defau lt Val ue 00h

Description This v alue is mapped to the Data field of r egis ter 44h when

Data Selec t (also in register 44h) is s et to 6.

Co nfig urat io n Sp ace Register: 50h (cont’d)

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 146 01.00

6.1.4 Electrical Ch aract eristics

________________________________________

Descrip tion of t he T able

The table above shows the curr ent drawn by the Vaux power supply in different

power managem ent modes . The PITA -2 m eets the 20mA lim it defined f or D3cold

dis abled PCI s lots.

________________________________________

Vaux Power Supply in different Power Managem ent Modes

State Typ Max

D0 19 mA

D1 19 mA

D2 19 mA

D3hot 19 mA

D3c old 19 mA

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 147 01.00

6.1.5 Design Hints

________________________________________

D3cold

For a design that suppor ts D3cold it is important to check all s ignals on the loc al

bus side of the PITA -2 that m ay be affected by a m is sing Vdd3.

A s dur ing D3c old Vdd3 will drop to zer o all pins that ar e strapped to V dd3 eit her

dir ec tly or by a pullup will als o drop to zer o.

Therefor e it is strongly rec omm ended to str ap pins on t he local bus side of t he

PITA-2 to Vaux instead.

This is espec ially impor tant f or the test pin (pin 1) of the PITA -2. If this pin is not

kept at a high lev el during D3cold the P IT A- 2 will not be able to reliably as sert

PME#.

Pins that can cause an int errupt (I NT0 and GP0- GP3) s hould als o be chec ked to

avoid unwanted PM E# ev ents.

________________________________________

PSB 4610

Powe r M a n a ge me nt

Preliminary Data Sheet 148 01.00

6.1.6 Compat ibility Issues

________________________________________

Supported Designs by PITA

The PITA-2 supports designs which are compliant to the PCI Local Bus

Specification Revision 2.2 and the PCI Bus Power Management Interface

Sp ecificatio n Revision 1.1.

________________________________________

Potential Comp a tibility Prob lem

The only potential com patibility problem arises if the PIT A -2 is used in a des ign

which:

•us es the PME signal

•does not support D3c old

In this case it m ay be tem pting to connect the Vaux power supply of t he P ITA- 2

directly to the 3.3V s ignal of the PCI connector and likewise directly c onnect t he

PME signal of the P ITA-2 to the PM E# signal of the PCI c onnector .

Howev er, s uc h a design may affec t a PCI sy s tem , which:

•supports Vaux

•has at least one dev ic e wit h D3cold support connec ted

Under t hese c ircum s tanc es t he following unwanted behavior may happen:

The PCI s y stem enters D3cold and the PCI bus enter s s tat e B 3. In this state the

supply power 3.3V is disabled while Vaux remains active. As the PITA-2 is

c onnected to the 3.3V s upply its own supply V aux will also float . The P ME signal

of the P ITA- 2 has an internal clam p diode which will lim it the volt age on PM E to

about V aux+0.7V.

Ther efore it is likely that the PITA - 2 will pull down the PM E # s ignal and ther efore

block all other D3c old com pliant devic es on the bus.

This behavior c an be easily av oided by implem enting Vaux detec tion and power

swit ching as the PITA -2 meets t he power supply requirements for P CI slots that

do not support D3cold but have V aux power s upply .

If the P CI device c annot generate a PM E event at all it is best to leave the PM E#

s ignal of the PCI c onnec tor not connec ted.

________________________________________

PSB 4610

Reset an d In terrupt s

Preliminary Data Sheet 149 01.00

7 Reset and I nterrupts

________________________________________

7.1 Reset

________________________________________

Introduction

After each power up the PITA-2 must be reset. This reset is necessary to

establish a well defined state for all subsequent actions. This chapter informs

about:

•r eset phases

•ex ter nal signals affec ted by res et

•internal registers affected by reset

•pinstrapping

•autom atic r econf igur ation

________________________________________

Reset Phases

The P ITA- 2 c an be only reset by pulling the RS T signal low and t hen high while

the PITA-2 is powered up. There is no provision for a power on reset.

Further more t he PITA -2 requires sev en clock c ycles after the rising edge of the

RST signal.

After t he rising edge the PIT A -2 may start t he autom atic reconfiguration. D uring

this proc ess it c opies the c ontents of an ex ternal E EPROM into select ed fields of

the configuration space registers. Automatic reconfiguration is entered when

s ignal ELD is s tr apped to H. Other wis e t he P ITA-2 will s kip this phas e.

________________________________________

PSB 4610

Reset an d In terrupt s

Preliminary Data Sheet 150 01.00

________________________________________

Exter nal Signals

All PCI signals are f loated as long as the RST signal is low.

Signific ant input signals ( GP IO0-GPIO3, PA 0-PA 7, PA D0-PA D7 and ELD) m ust

r emain s table at leas t six c loc k c ycles after the r ising edge of the RST signal.

The s ignal P RST is forc ed to low (inac tive state) at the rising edge of RST .

The s ignal S RS T is forc ed to high (inac tive st ate) at the rising edge of RST.

Usually both signals have not been active before the RST signal has been

asserted. Therefore no signal change will usually happen at both SRST and

PSRT. As a consequence components which are connected to one of these

signals are not automatically reset by a PCI reset. This behavior is desirable

when these c omponent s rem ain activ e during D3cold bec ause after a wake up

the SW driver can obtain valuable information from these devices about the

reason for a wake up.

On the other hand, for a com plet e initialization of the P CI device the SW driver

m ust perform a reset for t hese devices by specif ically program ming the internal

registers of the PI TA -2.

________________________________________

Inter nal Registers

All internal register fields that are affected by an ex ternal reset are mark ed by a

default value in t he r egis ter des cription. This default value m ay be over r idden by

the optional autom atic reconfigur ation pr ocess.

After an external reset the PITA-2 allows only configuration space accesses.

Furthermore the PITA-2 will abort configuration space accesses until it has

com pleted t he reset sequenc e (including the opt ional autom atic rec onfiguration

pr oc ess ) . Therefore the S W dr iv er will not be able t o read any incor r ec t tr ans ient

value from any configuration space register .

For the power management the following bits are not affected by an external

reset (s tick y b its ):

•conf iguration space 44h:8

•conf iguration space 44h:15

•internal register 18h:24-27

The reason for this behavior is that the P ITA - 2 s uppor ts the D3c old s tate and thus

m ust be able to assert a PM E signal even while RST is low.

________________________________________

PSB 4610

Reset an d In terrupt s

Preliminary Data Sheet 151 01.00

________________________________________

Pinstrapping

P ins tr apping is used for:

•Loading the Subsy st em V endor ID.

•Loading the leas t signific ant 4 bits of the Subs y st em ID to the PCI

Configurat ion Space.

Several output pins from the parallel micro controller interface and the general

pur pos e I /O inter face ar e implem ented as tr istate output pins .

During PCI reset they are driven in tristate mode and the external logic v alue is

latched in the S ubs y st em ID (4 LSBs ) and the Subs ys tem V endor ID. This m eans

that the signals on board, connect ed to thes e pins, must be forc ed with pullup/

pulldown r esistors to the des ir ed v alue if they ar e not driven by the PIT A-2.

________________________________________

Au t omat ic reconfig uration of t he PITA-2 with t he serial EEPROM

The P ITA- 2 can also be c onfigur ed by the EE P ROM af ter sys tem r es et. Pins trap

values are over written by this proc ess if the procedure described in “Automatic

rec onf iguration of the PITA” on page 116 was succ essful.

The PITA-2 will abort PCI configuration accesses during automatic

reconfiguration.

________________________________________

Signal Name Usage duri ng P CI Reset (pi nstrappi ng)

P AD(7:0) Subs ystem Vendor ID( 15:8)

P A(7:0) Subs yst em Vendor ID( 7:0)

GP 3 Subs ystem ID(3)

GP 2 Subs ystem ID(2)

GP 1 Subs ystem ID(1)

GP 0 Subs ystem ID(0)

PSB 4610

Reset an d In terrupt s

Preliminary Data Sheet 152 01.00

7.2 Interrupts

________________________________________

Introduction

The P ITA-2 can generate an interrupt on the P CI signal I NTA

•ext ernal, async hronous event (e.g. an incom ing call)

•internal, sy nc hr onous event (e.g. an EE PROM acc es s finished) )

________________________________________

Genera l Not es

The P ITA-2 can only as sert INTA if the f ollowing requirem ents ar e m et:

•PITA-2 is in D0 or D1 s tate

•the interr upt s our ce is enabled by s etting the cor r es ponding inter r upt enable bit

in inter nal r egis ter 00h ( ICR) .

•the ev ent has occur r ed

Once INTA has been asserted by the PITA-2 it will stay active until a write

transaction to the internal register ICR occurs. After this write transaction has

oc cur r ed the PITA -2 deas serts the s ignal INTA.

The P ITA-2 will im mediat ely aft er this wr ite tr ans ac tion ass er t I NTA again if eit her

of the following conditions holds:

•not all inter rupt reporting bits have been c leared

•the r equir ement s for as serting an interr upt still hold

The former condition usually arises when more than one source has been

ac tiv ated and the inter r upt handler reacts to the ev ents sequentially.

The latter c ondition us ually ar is es if an ex ter nal ev ent has oc cur r ed a second time

while the inter rupt handler is still process ing the firs t occurr ence of this ev ent.

Report ing bits w it hin the int ernal r egis ter ICR c an only be cleared by writing a

logical 1 at t he bits that s hall be cleared. A read acc ess to t his r egis ter does not

clear any bit nor does it affect any signal.

________________________________________

PSB 4610

Reset an d In terrupt s

Preliminary Data Sheet 153 01.00

________________________________________

Exter nal Events

For ext er nal event s either the dedicated INT0 pin or one of the General Purpos e

IO pins (GP0-G P 3) can be us ed. T he following table shows how t o pr ogram t he

PITA-2 in order to activ ate one or mor e of thes e pins for inter rupts.

________________________________________

Programming of the P ITA-2

Source Enabled by R e por ted by Act ive Level

INT0 00h:INT0_EN=1

00h:INT0_POL=1 00h:INT0=1 H

INT0 00h:INT0_EN=1

00h:INT0_POL=0 00h:INT0=1 L

GP0 00h:GP0_INT=1

18h:GP0_INT_EN= 1

18h:GP0_OUT _EN = 0

00h:GP0_INT=1 L

GP1 00h:GP1_INT=1

18h:GP1_INT_EN= 1

18h:GP1_OUT _EN = 0

00h:GP1_INT=1 L

GP2 00h:GP2_INT=1

18h:GP2_INT_EN= 1

18h:GP2_OUT _EN = 0

00h:GP2_INT=1 L

GP3 00h:GP3_INT=1

18h:GP3_INT_EN= 1

18h:GP3_OUT _EN = 0

00h:GP3_INT=1 L

PSB 4610

Reset an d In terrupt s

Preliminary Data Sheet 154 01.00

________________________________________

Inter nal Events

The following internal ev ents can trigger an int errupt when enabled:

•an EEP RO M comm and has f inished

•the pr ogr ammed num ber of wr ites to the DMA buf fer has occ ur r ed

•FIFO over flow (receive failure)

•FIFO under flow (trans mit failur e)

•the P CI ret r y c ounter has expired ( too many r etr ies for a s ingle tr ans fer )

________________________________________

EEPROM Command f inished & DMA Wat erm ark reach ed

The E E PROM c omm and finis hed and the DMA waterm ark r eac hed interr upts are

norm al events.

________________________________________

FIFO Over flow & FIFO Underflow

The FIF O overf low and FI FO under flow event s indicate a fat al error whic h may

r esult in a c ommunic ation failure. The actual impac t of t hese events depends on

the error detection and error correction capabilities of the communi cation protocol

of the applic ation.

________________________________________

Summatio n o f th e used Bits in Register ICR

Event Enabled by Reported by

EE P ROM command finished 00h:28=1 00h:12=1

DM A waterm ark reached 00h: 24=1 00h:8= 1

FIFO overflow 00h:25= 0 00h:9=1

FIFO underf low 00h:26= 1 00h:10=1

P CI retr ies expired 00h:27=1 00h:11= 1

PSB 4610

Reset an d In terrupt s

Preliminary Data Sheet 155 01.00

________________________________________

PCI Ret ries exp ired

The P CI ret ries ex pired ev ent is not a norm al ev ent but is not necessar ily a fat al

event . If the P ITA-2 report s this event the following has happened:

•The DM A contr oller has requested a data word t ransfer to/ from the FIFO.

•The P ITA-2 has requested the PCI bus for the transfer.

•The PI TA- 2 has been granted the PCI bus.

•The P ITA- 2 has initiated the trans fer < n> times but t he PCI target has abor ted

the tr ans fer eac h t ime. < n> is the number pr ogr ammed in int er nal register

1Ch:23:16.

A t this point the PITA -2 r eleases the P CI bus and reports the event. Howev er, as

the DM A dat a trans fer r eques t is not sat is fied the PITA - 2 will r eques t the PCI bus

again for the same dat a transfer until the reques t is sat isfied. Depending on t he

P CI tar get this may either have no effec t (data deliv er ed in tim e finally) or a fatal

ev ent may happen ( FIFO overflow/underflow).

________________________________________

Caution

It is import ant t o bear in m ind that in D3cold state Vdd3 will v anis h. F or devices

that support D3cold it is therefore strongly recommended to strap low active

interr upt sources (e. g. G P0-GP3) not to V dd3 but to Vaux instead.

________________________________________

PSB 4610

Pinning

Preliminary Data Sheet 156 01.00

8Pinning

________________________________________

PITA-2 Pinout

This illustr ation s hows the numbered pins and their respec tive signals :

________________________________________

PITA-2

T-QFP-100-10

100

25 51

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

CS1

CS2

INTA

VAUX

VSS

VIO

VDD3

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

C/BE0

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

C/BE1

PAR

SERR

PERR

STOP

DEVSEL

TRDY

IRDY

FRAME

C/BE2

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

PRST

PAD7

PAD6

PAD5

PAD4

PAD3

PAD2

PAD1

PAD0

CS0

VAUX

VSS

PME_EN

ALE

INT0

SRST

DCL

RXD

TXD

FSC

VAUX_PR

ELD

ECS

GP3

TES T

GP2

GP1

GP0

CLKRUN

PME

RST

CLK

GNT

REQ

VAUX

VSS

VIO

VDD3

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

C/BE3

IDSEL

PSB 4610

Pinning

Preliminary Data Sheet 157 01.00

________________________________________

Overview

The following table list s the interfaces and t heir res pective pins:

________________________________________

Interface Total In Out I/O Page

P CI bus 52 4 5 43 158

P ar allel Inter fac e 23 3 14 8 159

Ser ial Int er face 5 2 2 1 161

GP I/O In te rfa ce 4 0 0 4 1 6 2

Special EEP ROM

Signals 2 1 1 0 163

Power Managem ent 2 1 1

Description of PI N Types

Type Description

O/P S Output Pin/ P in S tr ap Pin

I Input Pin

IO B idir ectional Input /O utput P in

OD Open Drain

PSB 4610

Pinning

Preliminary Data Sheet 158 01.00

________________________________________

This table lists the Pins Characteristics of t he PCI Bu s

Pin No. Signal

Name Pin C ount Type Function

9 CLK 1 I PCI - Clock (m ax. 33

MHz)

8RST1IPCI - Reset

16 - 23,

26 - 33,

44 - 51,

53 - 60

AD( 31:0) 32 IO PC I - A ddress- /Data

bus

24, 34,

43, 52 C/BE(3:0) 4 IO PCI - Com mand/Byt e

E nable Bus

(B yte Enables are low

active)

42 PAR 1 I O PCI - Parit y

64 INTA 1 OD PC I - Interr upt Signal

25 IDSEL 1 I PCI - Initializ ation

Device Select Signal

For Car dBus boards

this signal m us t s et to

‘1’

35 FRAME 1IOPCI - Frame

36 IRDY 1 IO PCI - Initiator Ready

37 TRDY 1 IO PCI -Target Ready

38 DEVSEL 1 I O PCI - Device Sel ect

39 STOP 1IOPCI - Stop

11 REQ 1 OTS PCI - Bus Request

10 GNT 1 I PCI - Bus Gr ant

PSB 4610

Pinning

Preliminary Data Sheet 159 01.00

________________________________________

40 PERR 1 I O PCI - Parit y Error

41 SERR 1 O D PCI - Syst em Error

7PME1 O D PCI - Power

M anagement Event

12 CLKRUN 1 I Clock Run

This table lists the Pins Characteristics of t he PCI Bu s (cont’d)

Pin No. Signal

Name Pin C ount Type Function

This table lists the Pins Characteristics of t he Parallel In terfaces

Pin No. Signal

Name Pin C ount Type Function

76 P RST 1 O Ac tive high reset

66, 67,

87 CS(2:0) 3 O Chip Select S ignals for

thr ee dev ic es

connec ted to the

par allel m ic ro c ontr oller

interface.

84 - 77 P AD(7: 0) 8 IO - Mult iplexed B us

Mode:

Addr ess/ Data bus for

the par allel int er face.

- Non-M ult iplexed B us

Mode:

Data bus for the

parallel interface.

PSB 4610

Pinning

Preliminary Data Sheet 160 01.00

________________________________________

74 - 68, 65 PA (7:0) 8 O /P S - Multiplexed B us

Mode:

Not us ed; pins c an be

left not connected.

- Non-M ult iplexed B us

Mode:

A ddres s bus for the

parallel interface.

91 A LE 1 O Addr ess Latch Enable

S ignal, ac tiv e high.

In non- multiplexed

mode the ALE input of

peripheral devic es

mus t be connec ted to

VSS.

86 WR 1 O Wr ite Signal, ac tiv e low

85 RD 1 O Read Signal, act iv e low

92 INT0 1 I Standard active low

inter rupt input for

connec ted dev ic es,

whic h is forwar ded to

the P CI inter fac e

(INTA).

This table lists the Pins Characteristics of t he Parallel In terfaces (cont’d)

Pin No. Signal

Name Pin C ount Type Function

PSB 4610

Pinning

Preliminary Data Sheet 161 01.00

________________________________________

This table list the Pins Char acteristics of t he Serial Interface

Pin No. Signal

Name Pin C ount Type Function

93 SRST 1 O Ac tive low reset output.

97 FSC 1 I Frame Synchronization

Clock signal, 8 kHz.

94DCL1I

O (OD ) Ser ial Data Clock

Signal.

The direction of this pin

c an be contr olled by

the DCL_Out_En bit in

the internal r egis ters .

B y default this pin is

input.

For P SB4596 V 2.1

mode, this pin mus t

c onfigur ed as output

(open drain), for all

other modes this pin

mus t be input.

95 RX D 1 I S erial Data Input Signal

96 TX D 1 O (O D) Ser ial Data Output

Signal

PSB 4610

Pinning

Preliminary Data Sheet 162 01.00

________________________________________

This table lists the Pins Characteristics of t he Gen eral Pu rpose I/O

Interface

Pin No. Signal

Name Pin C ount Type Function

2 GP3 1 IO Gener al Pur pos e I/O

Pin 3

This pin is driven high

during the autom atic

EEPROM configuration

if ELD = ‘1’.

3 GP2 1 IO Gener al Pur pos e I/O

Pin 2

Serial EEPR O M

I nterfac e : SCK - Se ria l

Clock Signal.

4 GP1 1 IO Gener al Pur pos e I/O

Pin 1

Serial EEPR O M

Inter face: SO - S erial

D a ta Ou tp u t from

EE PROM (input to th e

PITA-2).

5 GP0 1 IO Gener al Pur pos e I/O

Pin 0

Serial EEPR O M

I nterfac e : SI - Seria l

Data Input to the

EE PROM (out put fr o m

the PITA-2).

PSB 4610

Pinning

Preliminary Data Sheet 163 01.00

________________________________________

This table lists the Pins Characteristics of t he Special EEPROM Sig nals

Pin No. Signal

Name Pin C ount Type Function

99 ELD 1 I EE PRO M Load

’1’ -> EEPROM

Configur ation is

enabled.

’0’ -> EEPROM

Configur ation is

disabled.

100 ECS 1 O EE PR O M Ch ip Select

( SP I Signal)

PSB 4610

Pinning

Preliminary Data Sheet 164 01.00

________________________________________

This table lists the Pins Characteristics of t he Power Management

Pin No. Signal

Name Pin C ount Type Function

90 PME_EN 1 O Reflects the state of the

P ME _EN bit. Can be

us ed t o power down all

external logic that is not

needed in st ate D3.

98 VA UX_PR 1 I Indic ates that Vaux is

present.

PSB 4610

Pinning

Preliminary Data Sheet 165 01.00

________________________________________

This table lists the Pins Characteristics of t he Power Supp ly

Pin No. Signal

Name Pin C ount Type Function

15, 61 V DD3 5 I Positive Power Supply

3.3V ± 10%

6, 75, 88 Vaux 3 I P os itive Power Supply

3.3V ± 10%

14, 62 VIO 2 I IO Voltage Supply

( either 3.3V or 5V)

13, 63, 89 V SS 3 I Ground 0V

PSB 4610

E lectrical Characteristics

Preliminary Data Sheet 166 01.00

9 Electri cal Characteristics

________________________________________

Pin Groups

The P ITA-2 has two differ ent kind of pins:

•PCI Pi ns (8-12, 16-60 and 64)

Thes e pins ar e powered by VDD3 and V IO and ar e intended for c onnect ion to

the P CI bus.

•Loc a l Pins ( 1-5, 7, 65-74, 76-87 and 90-100)

Thes e pins are power ed by VA UX or V DD3 (one power supply is s uffic ient)

and are intended for c onnect ion to the local s ignal of the PCI dev ic e.

The A C and DC s pecification for thes e t wo groups are may be dif ferent and ar e

therefore lis ted in separ at e t ables for each group.

________________________________________

Overview:

Overview Page

A bsolute Max im um Ratings 167

DC Characteris tics 168

PSB 4610

E lectrical Characteristics

Preliminary Data Sheet 167 01.00

9. 1 Absol ut e Maximum Rat ings

________________________________________

Note: Stresses above those listed under ’Absolute Maximum Ratings’ may cause

perm anent damage to the device.

Ex posure to conditions beyond thos e indicated in t he rec omm ended operational

c onditions of this specification may affect devic e reliabilit y .

This is a stress rating only and functional operation of the device under these

conditions or at any other condition beyond those indicated in the operational

c onditions of this specification is not implied.

________________________________________

This T able shows t he Parameters for the Ab solu te Maximum Ratings

Parameter Limit Values Unit

V oltage on PC I pins

with respec t to gr ound VS1 –0.5 to VIO + 0.5 V

Voltage on loc al pins

with respec t to gr ound VS2 –0.3 to 5.5 V

Am bient tem perature under bias TA0 to 70 °C

S tor age tem perature Tstg –65 to 150 °C

Max im um voltage on VIO V DD 7V

Max im um voltage on VDD3 and

VAUX VDD 4.6 V

PSB 4610

E lectrical Characteristics

Preliminary Data Sheet 168 01.00

9.2 D C C har acteri st ics

________________________________________

Description

The DC charac teristics of the PITA -2 ar e given in thr ee separ ate tables:

•PCI pins , 5V s ignaling environment ( VIO = 5V)

•P CI pins, 3.3V signaling env ir onment ( V IO = 3.3V )

•Local pins

________________________________________

Conditions

5V Si gn aling Environment

TA = 0 t o 70 °C; VIO = 4.75V t o 5.25V , Vaux and VDD3 = 3. 0V to 3.6V , VSS = 0 V

3.3V Si gnal in g E nvi ronment

TA = 0 t o 70 °C; VIO, Vaux and V DD3 = 3.0V to 3.6V , VSS = 0 V

________________________________________

PSB 4610

E lectrical Characteristics

Preliminary Data Sheet 169 01.00

________________________________________

DC Characteristics PCI Pins (5V Signaling Envir onment)

Parameter Sym Limit Values Unit Tes t Condit i on Rem.

min max

Input High

Voltage VIH 2.0 VIO+

0.5 V

Input Low

Voltage VIL –0.5 0.8 V

Input High

Leakage

Current

IIH 70 uA Vin = 2.7V 1)

Input Low

Leakage

Current

IIL -70 uA Vin = 0.5V 2)

Output High

Voltage VOH 2.4 V IOH = –2mA

L-out put

voltage VOL 0.55 V IOL = 3/6mA 3)

Input Pin

Capacitance CIN 10 if

Inductance LPIN 20 nH

PM E# Input

Leakage IOFF 1 uA V out below 5.25V

VDD3 off/floating

1) exce pt fo r CLK RUN w hic h is internally pulled dow n (I LIh = 500 uA

2) exce pt fo r CLK RUN w hic h is internally pulled dow n (I LIh = 500 uA

3) 6mA f or F R AM E, TRDY, IRDY, D EVSEL, S TOP, S ERR, PE RR, LO CK and I N T A

PSB 4610

E lectrical Characteristics

Preliminary Data Sheet 170 01.00

________________________________________

DC Characte ris tics PCI Pin s (3.3V Sig nal ing Environ men t)

Parameter Sym Limit Values Unit T est

Condition Rem.

min max

Input High

Voltage VIH 0.5VIO VIO+0.5 V

Input Low

Voltage VIL –0.5 0.3VIO V

I nput

Leakage

Current

IIL -10 10 uA 0 < Vin < VIO 1)

Output High

Voltage VOH 0.9VIO VI

OH =

–0.5 mA

L-out put

voltage VOL 0.1VIO VI

OL =

1.5mA

Input Pin

Capacitance CIN 10 pF

Inductance LPIN 20 nH

PM E# Input

Leakage IOFF 1 uA V out below

3.6V

VDD3 off /

floating

1) exce pt fo r CLK RUN w hic h is internally pulled dow n (I LIh = 500 uA

PSB 4610

E lectrical Characteristics

Preliminary Data Sheet 171 01.00

________________________________________

DC Characte ris tics Loc al Pins

Parameter Sym Limit Values Unit T est

Condition Rem.

min max

Input High

Voltage VIH 2.4 5.25 V

Input Low

Voltage VIL –0.3 0.8 V

I nput

Leakage

Current

IIL -10 10 uA

Output High

Voltage VOH 2.4 V IOH =

–2 mA

L-out put

voltage VOL 0.4 V IOL =

2 mA

PSB 4610

P ackage Outlines

Preliminary Data Sheet 172 01.00

10 Package Outlines

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 173 01.00

11 Configuration Space Register of the PITA-2

________________________________________

Overview

Page

Description of the Register Types 174

Configuration Space Regist ers 175

Registers whic h do not occur els ewhere in the Data S heet 185

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 174 01.00

11.1 Descr iption of the Register Types

________________________________________

Descrip tion of t he Register T ypes

Type Description

PE •r ead only via P CI

•thes e bits ar e initialized by pins trapping dur ing PCI r eset

or by the optional E EPROM

H•r ead only via P CI

•hardwired

RC •read clear via P CI

•thes e bits are set by the internal logic

•thes e bits c an be r ead out and r eset by writing logical “1”

to th e m

•wri ting logical “0” does n’t influence the stat es of these bits

RW •read write via PCI

•these bits can be read out and written via t he P CI bus

E•r ead only via P CI

•thes e bits are initialized to a default value dur ing PCI

r eset or by the optional E E PROM

PSB 4610
Conf igurat ion Space Register of  t he PIT A-2
Preliminary  Data Sheet  175 01.00
 
11.2 C onf igur at ion Space Regi st er s
________________________________________
________________________________________
00h
Ad. Bit Type Default 
Value Regist er Name Page
00h 31:16 E 2104h Devic e ID 185
15:0 E 110A h Vendor  ID of S iem ens AG. 185
04h 
Ad. Bit Type Default 
Value Regist er Name Page
04h 31:0 0290 
0000h P CI Status Register 185
31 RC 0b Parit y Error Detected 185
30 RC 0b S ystem Err or S ignaled 90
29 RC 0b Master Abor t  Detect ed 90
28 RC 0b Target Abor t Detected 90
27 RC 0b Target Abor t S ignaled 90
26:25 H 01b DEV SE L Timing 26
28
24 RC 0b Data Parit y Error 
Reported 185
23 H 1b Fast Back-to-Back 
Capability 30
22 H 0b User Defined Func tions 185
21 H 0b 66 MHz  Capability 185

PSB 4610
Conf igurat ion Space Register of  t he PIT A-2
Preliminary  Data Sheet  176 01.00
 
________________________________________
20 E 1b Capabilities 185
19:16 H 0000b Reserved 185
15:0 Com mand Register 185
15:10 H 000000b Reserved 185
9 H 0b Fast Bac k - to- Back  E nable 30
8 RW 0b S yst em Err or E nable 90
7 H 0b Addr ess /Data S tepping 
Enable ( not used) 185
6 RW 0b Parity E rr or  Res pons e 185
5:3 H 000b The PIT A- 2 does not 
s upport the Special Cy cle 
Command.
185
2 RW 0b Master Enable 90
1 RW 0b Memor y Ac c ess Enable 17
0 H 0b I/O  Acc ess Enable 185
04h  (cont’d)
Ad. Bit Type Default 
Value Regist er Name Page
08h
Ad. Bit Type Default 
Value Regist er Name Page
08h 31:8 E 028000h Class  Code/PCI network  
device 188
7:0 E 02h Revis ion ID 188

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 177 01.00

________________________________________

0Ch

Ad. Bit Type Default

Value Regist er Name Page

0Ch 31:24 H 00h BIST 189

23:16 H 00h Header Ty pe 189

15:8 H 00h Mas ter Latenc y Timer 189

7:0 H 00h Cache Line Size 189

10h

Ad. Bit Type Default

Value Regist er Name Page

10h 31:0

31:12

11:0 RW

00000000h B ase Regis ter 0 17

14h

Ad. Bit Type Default

Value Regist er Name Page

14h 31:0

31:12

11:0 RW

00000000h B ase Regis ter 1 18

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 178 01.00

________________________________________

18h

Ad. Bit Type Default

Value Regist er Name Page

18h 31:0 H 00000000h B ase Address Register 2

( not used) 18

1Ch

Ad. Bit Type Default

Value Regist er Name Page

1Ch 31:0 H 00000000h B ase Address Regist er 3

( not used) 18

20h

Ad. Bit Type Default

Value Regist er Name Page

20h 31:0 H 00000000h B ase Address Register 4

( not used) 19

24h

Ad. Bit Type Default

Value Regist er Name Page

24h 31:0 H 00000000h B ase Address Register 5

( not used) 19

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 179 01.00

________________________________________

28h

Ad. Bit Type Default

Value Regist er Name Page

28h 31: 0 0000 02C0 CardB us CI S Pointer 20

31:28 H 0000b ROM Image Num ber 20

27:3 H 000054h A ddress Space O ff set 20

2:0 H 000b A ddress Spac e Indic ator 21

2Ch

Ad. Bit Type Default

Value Regist er Name Page

2Ch 31:20

19:16

000h

pinstrap

v alue or

EEPROM-

value

Subs y stem ID 21

15:0 PE pinstrap

value

EEPROM-

value

Subs y stem V endor ID 21

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 180 01.00

________________________________________

30h

Ad. Bit Type Default

Value Regist er Name Page

30h

31:0 H 00000000h Reserved 190

34h

Ad. Bit Type Default

Value Regist er Name Page

34h 31:8 H 00h Reserved 132

7:0 H 40h Capabilities Pointer 132

38h

Ad. Bit Type Default

Value Regist er Name Page

38h 31:0 H 00000000h Reserved 190

3Ch

Ad. Bit Type Default

Value Regist er Name Page

3Ch 31:24 E 00h Max_Lat 191

23:16 E 00h Min_Gnt 191

15:8 H 01h I nter rupt pin 191

PSB 4610
Conf igurat ion Space Register of  t he PIT A-2
Preliminary  Data Sheet  181 01.00
 
________________________________________
7:0 RW FF h Inter rupt Line 191
3Ch   (cont’d)
Ad. Bit Type Default 
Value Regist er Name Page
40h 
Ad. Bit Type Default 
Value Regist er Name Page
40h 31:0 1222 0001 Power  Managem ent 
Capabilities (PM C) 133
31:30
29:28
27
E
E
E
00b
01b
0b
PME_Support 133
26 E 0b D2_Support 133
25 E 1b D1_Support 133
24:22 E 000b A ux Current 133
21 E 1b DSI 133
20 H 0b Reserved 133
19 E 0b PME Clock 133
18:16 E 010b Version
The value 010b indicates 
that the device complies 
with the Rev ision 1. 1 of the 
P CI Power Managem ent 
Inter face Specification.
133
15:8 H 00h Nex t Item Pt r 133
7:0 H 01h Capability ID 133

PSB 4610
Conf igurat ion Space Register of  t he PIT A-2
Preliminary  Data Sheet  182 01.00
 
________________________________________
________________________________________
44h
Ad. Bit Type Default 
Value Regist er Name Page
44h 31:24 H 00h DATA  Regist er 137
23:16 H 00h PM CSR_B SE  Br idge 
S upport Ex tensions 137
15 RC 0b PME Stat us 137
14:13 H 00b Data Sc ale 137
12:9 RW 0h Data Select 137
8 RW 0b PME_En 137
7:2 H 00h Reserved 137
1:0 RW 00b P ower State 137
48h 
Ad. Bit Type Default 
Value Regist er Name1 Page
48h 31:0 P ower Data Regis ter 1 140
31:30 H 00b Reserved 140
29:28 H/E W 00b Data_Sc ale in 
Data_S elec t = 2 140
27:20 H/E W 00h DA TA in Data_S elec t = 2 140
19:18 H/E W 00b Data_Sc ale in 
Data_S elec t = 1 140
17:10 H/E W 00h DA TA in Data_S elec t = 1 140

PSB 4610
Conf igurat ion Space Register of  t he PIT A-2
Preliminary  Data Sheet  183 01.00
 
________________________________________
________________________________________
9:8 H/E W 00b Dat a_Sc ale in 
Data_S elec t = 0 140
7:0 H/E W 00h DA T A in Data_S elec t = 0 140
48h  (cont’d)
Ad. Bit Type Default 
Value Regist er Name1 Page
4Ch  
Ad. Bit Type Default 
Value Regist er Name Page
4Ch 31:0 P ower Data Regis ter 2 142
31:30 H 00b Reserved 142
29:28 E 00b Dat a_Sc ale in 
Data_S elec t = 5 142
27:20 E 00h DA T A in Data_S elec t = 5 142
19:18 E 00b Dat a_Sc ale in 
Data_S elec t = 4 142
17:10 E 00h DA T A in Data_S elec t = 4 142
9:8 E 00b Dat a_Sc ale in 
Data_S elec t = 3 142
7:0 E 00h DA T A in Data_S elec t = 3 142

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 184 01.00

________________________________________

50h

Ad. Bit Type Default

Value Regist er Name Page

50h 31:0 P ower Data Regis ter 3 144

31:20 H 000h Reserved 144

19:18 E 00b Dat a_Sc ale in

Data_S elec t = 7 144

17:10 E 00h Dat a_Value in

Data_S elec t = 7 144

9:8 E 00b Dat a_Sc ale in

Data_S elec t = 6 144

7:0 E 00h Dat a_Value in

Data_S elec t = 6 144

54h

Ad. Bit Type Default

Value Regist er Name Page

54h 31:0 H 00h Car dBus CIS 192

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 185 01.00

11.3 Registers which do not occur elsewhere in the Data

Sheet

________________________________________

00h

Bit 31:16 Devi ce ID

Type E

Defau lt Val ue 2104h

Description Ident ifies the PITA -2 within all PCI devices from S iemens

Semiconductors.

Bit 15:0 Vendor ID

Type E

Defau lt Val ue 110Ah

Description 110A is the Vendor ID of Siem ens A G.

04h

Bit 31:0 P CI St atus Register

Defau lt Val ue 02900000h

Bit 31 Parity_Error_Detected

Type RC

Defau lt Val ue 0b

Description This bit is set, if a parity error is detected during a transaction

with t he PI TA-2. This is done independently from the stat us

of the ‘Par ity Err or Res pons e’ bit.

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 186 01.00

Bit 24 Data_Parity_Error_Reported

Type RC

Defau lt Val ue 0b

Description The P CI M ast er as s er ts this bit if it detects the PERR s ignal

on the PCI bus asserted during a PCI transaction initiated by

itself.

Bit 22 User_Defined_Functions

Type H

Value 0b

Description T he PIT A-2 has no user defined functions.

Bit 21 66_MHz_Capability

Type H

Value 0b

Description The P ITA - 2 is not a 66 MHz device (0 - 33 MHz suppor ted.)

Bit 20 Capabilities

Type E

Defau lt Val ue 1b

Description If this bit is set , the PCI device has addit ional capabilities

defined in the PCI Configuration Space Header. A dditional

c apabilities can be found in the Cap_Ptr under addres s 34h.

04h (cont’d)

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 187 01.00

Bit 19:16 Reserved

Type H

Defau lt Val ue 0000b

Description

Bit 15:0 Com mand Register

Bit 15:10 Reserved

Type H

Defau lt Val ue 000000b

Description

Bit 7 Address/Data_Stepping_Enable

Type H

Defau lt Val ue 0b

Description not used

Bit 6 Parity_Error_Response

Type RW

Defau lt Val ue 0b

Description If thi s bi t i s s e t to ‘1’, the PCI inter face reports data par it y

errors by ass erting the PERR signal.

04h (cont’d)

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 188 01.00

________________________________________

Bit 5:3

Type H

Value 000b

Description T he PIT A-2 does not support the Spec ial Cycle Comm and.

The P ITA-2 does not generat e Memor y W rite and inv alidate

transactions.

The PITA-2 does not s upport VG A Palette snooping.

Bit 0 I/O_Access_Enable

Type H

Defau lt Val ue 0b

Description The P CI inter face does not s upport I/O commands .

04h (cont’d)

08h

Bit 31:8 Class_Code

Type H or EW

Defau lt Val ue 028 000h

Description PCI networ k devic e

Bit 7:0 Revi sion ID

Type H

Defau lt Val ue 02h

Description Revision of the PCI device

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 189 01.00

________________________________________

0Ch

Bit 31:24 BIST

Type H

Defau lt Val ue 00h

Description T he PIT A-2 has no built-in self test.

Bit 23:16 Header_Type

Type H

Defau lt Val ue 00h

Description

Bit 15:8 Master_Latency_Timer

Type H

Defau lt Val ue 00h

Description Unused

Bit 7:0 Cache_Line_Size

Type H

Defau lt Val ue 00h

Description T he PIT A-2 does not support the cache line size regist er

bec aus e it s uppor ts only single data trans actions.

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 190 01.00

________________________________________

30h

Bit 31:0 Reserved

Type H

Defau lt Val ue 0000 0000h

Description Reserved

38h

Bit 31:0 Reserved

Type H

Defau lt Val ue 0000 0000h

Description

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 191 01.00

________________________________________

3Ch

Bit 31:24 Max_Lat

Type E

Defau lt Val ue 00h

Description S e t to ’0’ becaus e only single data trans act ions ar e

supported.

Bit 23:16 Mint_Gnt

Type E

Defau lt Val ue 00h

Description S e t to ’0’ becaus e only single data trans act ions ar e

supported.

Bit 15:8 Interrupt_Pin

Type H

Defau lt Val ue 01h

Description As a single function device, t he P ITA- 2 us es the INTA s ignal.

Bit 7:0 Interrupt_Line

Type RW

Defau lt Val ue FFh

Description Thes e Bits s how t he inter r upt line which is us ed by this

s y stem. F or a x 86 sys tem the v alue FF means unknown.

Thes e registers ar e written dur ing the initializ ation of the

operat ing sys tem .

PSB 4610

Conf igurat ion Space Register of t he PIT A-2

Preliminary Data Sheet 192 01.00

________________________________________

54h

Bit 31:0 Cardbus_CIS

Type H

Value 00h

Description Not s uppor ted by PITA - 2

PSB 4610

Internal Regist er of th e P ITA

Preliminary Data Sheet 193 01.00

12 I n ternal Register of the PITA

________________________________________

Overview

Page

Description of the Register Types 194

Inter nal Regist er 195

Registers which do not oc c ur els ewhere in the Dat a S heet 202

PSB 4610

Internal Regist er of th e P ITA

Preliminary Data Sheet 194 01.00

12.1 Descr iption of the Register Types

________________________________________

Descrip tion of t he Register T ypes

Type Description

Rread only

RC read clear

•thes e bits are set by the internal logic

•thes e bits c an be r ead out and r es et by writing logical “1”

to th e m

•wr iting logic al “0” doesn’t influenc e the s tates of these bits

RW read write

•thes e bits can be read out and wr itten via the PCI bus

PSB 4610
Internal Regist er of  th e P ITA
Preliminary  Data Sheet  195 01.00
 
12.2 Internal Register
________________________________________
00h 
Ad. Bit Type Default 
Value Regist er Name Page
00h 31:0 00000000h ICR - Interr upt Control 
Register 202
31:29 R 000b Reserved 202
28 RW 0b EEPROM_Control_Int_En 121
27 RW 0b Retry_Counter_Down_
Int_En 31
26 RW 0b FIFO_Overflow_Empty_
Int_En 41
25 RW 0b DMA_Write_Counter_
Overflow_Int_En 41
24 RW 0b DMA_Write_Counter_Int_
En 41
23:18 R 000000b Reserved 202
17 RW 0b INT0_En 202
16 RW 0b INT0_Pol 202
15:13 R 000b Reserved 202
12 RC 0b EEPROM_Control_Int 121
11 RC 0b Retry_Counter_Int 31
10 RC 0b FIFO_Overflow_Empty_
Int 41
9 RC 0b DMA_Write_Counter_
Overflow_Int 41
8 RC 0b DMA_Write_Counter_Int 41

PSB 4610
Internal Regist er of  th e P ITA
Preliminary  Data Sheet  196 01.00
 
________________________________________
________________________________________
7:6 R 0b Reserved 202
5 RC 0b GP3_INT 101
4 RC 0b GP2_INT 101
3 RC 0b GP1_INT 101
2 RC 0b GP0_INT 101
1RC0b INT0 202
00h  (cont’d)
Ad. Bit Type Default 
Value Regist er Name Page
04h 
Ad. Bit Type Default 
Value Register Name Page
04h 31:0 00000000h DMA Contr ol Regis ter 43
31:09 R 0000000h Reserved 43
8RW0b DMA Start 43
7:6 R 00b Reserved 43
5:0 RW 000000b DM A Select  -  all modes
IOM- 2 Mode 1
IOM- 2 Mode 2
IOM- 2 Mode 3
Single M odem Mode V2.1
Single M odem Mode V3.X
Dual Modem + Voic e Mode
43
48
52
55
63
67
75

PSB 4610

Internal Regist er of th e P ITA

Preliminary Data Sheet 197 01.00

________________________________________

08h

Ad. Bit Type Default

Value Regist er Name Page

08h 31:12

11:0

00000h

000h

Ci rcu lar Buffer Start

Address 45

0Ch

Ad. Bit Type Default

Value Regist er Name Page

0Ch 31:00 R 00000000h A ct ual Circular Buf fer

Pointer 45

10h

Ad. Bit Type Default

Value Regist er Name Page

10h 31:0 00000000h ALIS Com mand Regis ter 1 67

31:25 R 00h Reserved 67

24 RW 0b New_ALIS_Command_1 67

23:16 RW 00h ALIS_Received_Data_1 67

15:8 RW 00h ALIS_Command_1 67

7:0 RW 0b ALIS_Transmit_Data_1 67

PSB 4610
Internal Regist er of  th e P ITA
Preliminary  Data Sheet  198 01.00
 
________________________________________
________________________________________
14h
Ad. Bit Type Default 
Value Regist er Name Page
14h 31:0 00000000h ALIS Com mand Regis ter 2 70
32:25 R 000h Reserved 70
24 RW 0b New_ALIS_Command_2 70
23:16 RW 00h ALIS_Received_Data_2 70
15:8 RW 00h ALIS_Command_2 70
7:0 RW 00h ALIS_Transmit_Data_2 70
18h 
Ad. Bit Type Default 
Value Regist er Name Page
18h 31:0 00000000h GP I/ O Interface Control 
Register 102
31:28 R 0h Reserved 102
27 RW 0b GP3_Int_En 102
26 RW 0b GP2_Int_En 102
25 RW 0b GP1_Int_En 102
24 RW 0b GP0_Int_En 102
23:20 R 0000b Reserved 102
19 RW 0b GP3_Out_En 102
18 RW 0b GP2_Out_En 102

PSB 4610
Internal Regist er of  th e P ITA
Preliminary  Data Sheet  199 01.00
 
________________________________________
 
17 RW 0b GP1_Out_En 102
16 RW 0b GP0_Out_En 102
15:12 R 0000b Reserved 102
11 R - GP3_IN 102
10 R - GP2_IN 102
9 R - GP1_IN 102
8 R - GP0_IN 102
7:4 R 0000b Reserved 102
3 RW 0b GP3_OUT 102
2 RW 0b GP2_OUT 102
1 RW 0b GP1_OUT 102
0 RW 0b GP0_OUT 102
18h  (cont’d)
Ad. Bit Type Default 
Value Regist er Name Page
1Ch  
Ad. Bit Type Default 
Value Regist er Name Page
1Ch 31:0 00000000h MISC - M isc ellaneous 
Register 59
31 RW 0b IO M B1 M ask ing 59
30 RW 0b IO M B2 M ask ing 59
29 RW 0b IO M MON0/IC1 Mask ing 59
28 RW 0b IO M D+C/I0+M R+M X / 
IC2 Mask ing 59

PSB 4610
Internal Regist er of  th e P ITA
Preliminary  Data Sheet  200 01.00
 
________________________________________
27 RW 1b Serial Interface Buffer  
Mode 204
26 RW 0b P arallel Int erfac e M ode 78
25 RW 1b Soft reset Serial Interface 204
24 RW 0b Sof t reset P ar allel 
Interface 78
23:16 RW 00h Retry Count Regist er 32
15:12 R 0000b Reserved 204
11:0 RW 0000h DMA  Wr ite Count Register 46
1Ch   (cont’d)
Ad. Bit Type Default 
Value Regist er Name Page
20h 
Ad. Bit Type Default 
Value Regist er Name Page
20h 31:0 00000000h Ser ial Cloc k  S elec t 
Register
31:2 R 00000000h Reserved
1 RW 0b DCL_Out_En 49
52
55
64
72
0 RW 0b Serial_Clock_Sel 49
52
55
64
72

PSB 4610
Internal Regist er of  th e P ITA
Preliminary  Data Sheet  201 01.00
 
________________________________________
________________________________________
________________________________________
24h
Ad. Bit Type Default 
Value Regist er Name Page
24h 31:0 00000000h EE PROM Contr ol Regis ter 121
31:25 R 0000h Reserved 121
24 RW 0b EEPRO M Start 121
23:16 RW 00h EEPROM Command 121
15:8 RW 00h EE PRO M By te Address 121
7:0 RW 00h EE PRO M Data 121
28h
Ad. Bit Type Default 
Value Regist er Name Page
28h 31:0 00000000h DM A TE ST Regis ter 204
31:01 R 00000000h Reserved 204
0 RW 0b Loop_Back_Mode 77

PSB 4610

Internal Regist er of th e P ITA

Preliminary Data Sheet 202 01.00

12.3 Registers which do not occur elsewhere in the Data

Sheet

________________________________________

00h

Bit 31:0 ICR - Inter r upt Contr ol Regis ter

Defau lt Val ue 00000000h

Description The inter r upt enable bits f or GP3- 0 ar e plac ed in the GP I/ O

Inter fac e Contr ol Regist er .

All int errupt enables are high active:

Int_En=’0’ -> corres ponding interr upt (bit) is disabled

Int_En=’1’ -> corres ponding interr upt (bit) is enables

Bit 31:29 Reserved

Type R

Value 000b

Bit 23:18 Reserved

Type R

Value 000000b

Bit 17 INT0_En

Type RW

Defau lt Val ue RW

Description Enable for the INT0 interrupt bit.

PSB 4610

Internal Regist er of th e P ITA

Preliminary Data Sheet 203 01.00

________________________________________

Bit 16 INT0_POL

Type RW

Defau lt Val ue 0b

Description P o l a rity of IN T0 a cti ve le vel

0: L-Level

1: H-level

Bit 23:18 Reserved

Type R

Value 000000b

Bit 1 INT0

Type RC

Defau lt Val ue 0b

Description An interrupt is detec ted on pin INT0 .

Bit 0 Reserved

Type R

Value 0b

00h (cont’d)

PSB 4610

Internal Regist er of th e P ITA

Preliminary Data Sheet 204 01.00

________________________________________

1Ch

Bit 27 Serial Int erface Buf fer Mode

Type RW

Value 1b

Description 0: T he TXD pin is configured as PUSH /PU LL output pin.

1: T he T XD pin is configured as OP EN DRAIN out put pin.

Bit 25 Soft Reset Serial Interfac e

Type RW

Defau lt Val ue 1b

Description 0: Ac tivates t he low active res et signal SRS T to the

application.

1: Deactivates t he res et signal SRS T to the application.

Before as sert ing this bit the DMA _Start bit has to be reset .

28h

Bit 31:0 DM A Test Register

Defau lt Val ue 00000000h

Bit 31:1 Reserved

Type R

Defau lt Val ue 00000000h

PSB 4610

Abbreviations

Preliminary Data Sheet 205 01.00

13 Abbreviations

A C A lternating Current.

A /D A nalog to digit al.

A DC Analog to digit al c onv er ter.

A LE A ddr es s latch enable.

A LIS Analog Line Int er face S olution. Chip set consis ting of PS B4595 and

PSB4596.

DC Dir ect Current .

DCL Double Bit Clock . (In this context, only in the IOM -2 modes of the

serial inter face of the PITA , single bit in all other m odes).

DMA D ire ct Me m o ry Ac ce ss.

DD Data Downst ream.

DU Data Upstr eam.

EEPR O M =

E2PROM Elect rically eras able program mable read only mem ory.

FIFO

R X FIFO

TX FIFO

Fi rst in fi r st o u t.

FSC Frame Sync.

I/O In/out.

IOM ISDN Or iented M odular .

ISD N Integrated Serv ic es Digital Network.

M S B M os t Signific ant Bit.

P ITA P CI Int er face for Telephony/Dat a A pplic ations.

P CI Per ipher al Component Inter c onnect.

RX D Receiv e Direction.

TX D Trans mit Direction.

PSB 4610
Index
Semiconductor Group 206 Preliminary Data Sheet 01.00
 
14 Index
A
Ab s o l u te  Ma ximu m R a ti n g s    1 6 7
ALIS V2.1
Configuration aft er Reset     63
Connection to the PI TA -2     118
ALIS V3.X
Configuration aft er Reset     66
B
B ase Address  Register    16
BAR 0    1 7
BAR 1    1 8
S truc ture of the Addres s  Spac e    16
C
Configuration Space Register
Power Managem ent
34h    132
40h    133
44h    137, 140, 142, 144
Reference Table    175
D
DC Characteris tics     168
DM A Algorithm     38
DM A Contr oller    36
Dual Modem/Modem + Voice Mode    73
G
General Purpose I/O I nterf ace    97
Input Mode    107
Int errupt Mode    111
Out put Mode     109
I
Interfaces
General Pur pose I/O Interf ac e    97
Paral le l Int erf ace    78
S er ial DMA  Inter face    34
SPI EEPROM Interface    115
Inter nal Register
00h    195
20h    200
24h    201
DM A Controller
00h    41
04h    43, 45, 63, 67, 69, 75
08h    45
0Ch    45, 46, 77, 78, 102
1Ch    46
GP I/O Inte rfa ce
00h    101
18h    102
Loopback Mode
28h    77
P ar allel Inter fac e
1Ch    78
Reference Table    195
Retry Counter
00h    31
1Ch    32
S ingle Modem  Mode V2.1
20h    49, 52, 55, 64, 72
SPI EEPROM Interface
00h    67,  70, 121
24h    121
Inter rupt Control Register     31
IOM-2 Mode 1    47
IOM-2 Mode 2    50
IOM-2 Mode 3    53
IOM-2 Modes
Gener al Descr iption    56
Mask ing of IOM -2 T imes lots     58
Select ion of IO M -2 T imes lots     56
L
Loopback  Mode    76
M
Multiplexed Mode

PSB 4610
Index
Semiconductor Group 207 Preliminary Data Sheet 01.00
 
Read Tr ans act ion    88
Write Transaction    87
N
Non Mult iplex ed M ode
Read Tr ans act ion    86
Write Transaction    84
P
Parallel I nterface    78
PCI Bus
P inning    158
P CI Comm ands    23
PCI Configur ation Space    11
Acce ss to  th e    1 5
Constr uction of     13
P CI Mas ter Contr oller    23
P CI T ar get Controller    23
Pinning
Descript ion of PIN Types     157
GP I/O In te rfa c e    1 6 2
Parallel Interfaces     159
Power Supply     164, 165
S er ial Inter fac e    161
S pec ial EE P ROM Signals    163
P instr apping    151
Power  Managem ent    123
Power  Management States     126
R
R e se t    1 4 9
S
Ser ial DMA  Interfac e    34
Single M odem Mode V2.1    61
Configuration aft er Reset     62
Single M odem Mode V3.X     65
Configuration aft er Reset     66
SPI EEPROM Interface     1 1 5
T
Timing    89
Timing Diagr am
ALE after internal Softreset    82
A LE  after s ett ing the Par allel I nterface
Mode Bit    83
ALE aft er Syst em Reset    81
B ur s t Read    25
Burs t Write    2 7
Dual Modem/Modem+Voice Mode
74
Fast Back to Back    29
GP I/O Inte rfa ce
Input Mode    107
Inter r upt Mode    111
Output Mode    110
IOM -2 all Modes    56
IOM -2 Mode 1    48
IOM -2 Mode 2    51
IOM -2 Mode 3    54
Loopback Mode    76
P ar allel Inter fac e
Mult iplexed Addres s    94
Non Mulitplexed Addr es s     95
Read    94
Write    94
S ingle Modem  Mode V2.1    61
S ingle Modem  Mode V3.X    65
SPI EEPROM Interface    119
Trans act ion Disconnec t     89
Trans act ion Ter mination    92
V
Vendor  ID    151