NHS3100 Temperature logger Rev. 6.03 -- 15 June 2018 1 Product data sheet General description The NHS3100 is an IC optimized for temperature monitoring and logging. It has an embedded NFC interface, an internal temperature sensor and a direct battery connection. These features support an effective system solution with a minimal number of external components and a single layer foil implementation for temperature monitoring. The NHS3100 works either battery-powered or NFC-powered. The embedded ARM Cortex-M0+ offers flexibility to the users of this IC to implement their own dedicated solution. The NHS3100 contains multiple features, including multiple Power-down modes and a selectable CPU frequency of up to 8 MHz, for ultra low power consumption. Users can program this NHS3100 with the industry-wide standard solutions for ARM Cortex-M0+ processors. As of September 22, 2017, this device has been certified by the NFC forum (certification ID: 58516). CAUTION Semiconductors are light sensitive. Exposure to light sources can cause the IC to malfunction. The IC must be protected against light. The protection must be applied to all sides of the IC. CAUTION msc896 This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. NHS3100 NXP Semiconductors Temperature logger 2 Features and benefits 2.1 System * * * * * ARM Cortex-M0+ processor running at frequencies of up to 8 MHz ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC) ARM Serial Wire Debug (SWD) System tick timer IC reset input 2.2 Memory * 32 kB on-chip flash programming memory * 4 kB on-chip EEPROM of which 320 bytes are write-protected * 8 kB SRAM 2.3 Digital peripherals * Up to 12 General Purpose Input Output (GPIO) pins with configurable pull-up/pull-down resistors and repeater mode * GPIO pins which can be used as edge and level sensitive interrupt sources * High-current drivers (sink only; 20 mA) on four GPIO pins 2 * High-current drivers (sink only; 20 mA) on two I C-bus pins * Programmable WatchDog Timer (WDT) 2.4 Analog peripherals * Temperature sensor with 0.3 C absolute temperature accuracy between 0 C and 40 C and 0.5 C in the range -40 C and +85 C 2.5 Communication interfaces * NFC/RFID ISO 14443 type A interface; NFC forum type 2 compatible 2 2 * I C-bus interface supporting full I C-bus specification and Fast-mode with a data rate of 400 kbit/s, with multiple-address recognitions and Monitor mode 2.6 Clock generation * 8 MHz internal RC oscillator, trimmed to 2 % accuracy, which is used for the system clock * Timer oscillator operating at 32 kHz linked to the RTC timer unit NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 2 / 45 NHS3100 NXP Semiconductors Temperature logger 2.7 Power control * * * * * Support for 1.72 V to 3.6 V external voltages The NHS3100 can also be powered from the NFC field. Activation via NFC possible Integrated Power Management Unit (PMU) for versatile control of power consumption Four reduced power modes for ARM Cortex-M0+: Sleep, Deep-sleep, Deep powerdown and Battery-off * Power gating for each analog peripheral for ultra-low power operation * < 50 nA IC current consumption in Battery-off mode at 3.0 V * Power-On Reset (POR) 2.8 General * Unique device serial number for identification 3 Applications * Temperature measurement * Temperature logging * Cold chain validation 4 Ordering information Table 1. Ordering information Type number Package Name Description Version NHS3100 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm SOT616-3 NHS3100UK WLCSP25 wafer level chip-scale package; 25 balls; 2.51 x 2.51 x 0.5 mm SOT1401-1 NHS3100W8 bumped die bumped die with 8 functional bumps; 2.51 x 2.51 x 0.16 mm SOT1870-1 5 Marking Table 2. Marking codes NHS3100 Product data sheet Type number Marking code NHS3100 NHS3100 NHS3100UK NHS3100 NHS3100W8 no marking code All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 3 / 45 NHS3100 NXP Semiconductors Temperature logger 6 Block diagram The internal block diagram of the NHS3100 is shown in Figure 1. It consists of a Power Management Unit (PMU), clocks, timers, a digital computation, and a control cluster (ARM Cortex-M0+ and memories) and AHB-APB slave modules. PADS POWER PADS DIGITAL SWITCH MATRIX 32 kHz FRO 8 MHz FRO WAKE-UP TIMER CLOCK SHOP I2C-BUS LDO (1.2 V) INTERNAL POWER SWITCHES LDO (1.6 V) POR 8 kB SRAM 32 kB FLASH SPI TIMERS WATCHDOG SYSCONFIG GPIO 4 kB EEPROM IOCONFIG MFIO (DIGITAL) I2C-BUS EXTERNAL POWER SWITCH EEPROM CONTROL FLASH CONTROL PMU ARM M0+ AHB-APB BRIDGE TEMPERATURE SENSOR NFC/RFID HIGH DRIVE aaa-015348 Figure 1. NHS3100 block diagram NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 4 / 45 NHS3100 NXP Semiconductors Temperature logger 7 Pinning information 7.1 Pinning 7.1.1 HVQFN24 package 19 LB 20 LA 21 (reserved) 22 (reserved) terminal 1 index area 23 (reserved) 24 (reserved) Figure 2 shows the pad layout of the NHS3100 in the HVQFN24 package. PIO0_0/WAKEUP 1 18 (reserved) PIO0_1/CLKOUT 2 17 (reserved) PIO0_2/SSEL 3 16 PIO0_11/CT32B_M1/SWDIO PIO0_6/SCLK 4 PIO0_8/MISO 5 PIO0_9/MOSI 6 15 PIO0_10/CT32B_M0/SWCLK 25 VSS 14 PIO0_3/CT16B_M0 PIO0_5/SDA 12 9 RESETN PIO0_4/SCL 11 8 VSS (reserved) 10 7 VDDBAT 13 PIO0_7/CT16B_M1 aaa-015349 Transparent top view Figure 2. Pad configuration HVQFN24 Table 3. Pad allocation table of the HVQFN24 package Pad 1 2 3 4 5 PIO0_0/WAKEUP PIO0_1/CLKOUT PIO0_2/SSEL PIO0_6/SCLK PIO0_8/MISO 13 PIO0_7/CT16B_M1 14 [1] PIO0_3/CT16B_M0 15 [1] PIO0_10/CT32B_M0/SWCLK 16 [1] PIO0_11/CT32B_M1/SWDIO 17 [2] (reserved) [2] (reserved) 18 7 VDDBAT 19 8 VSS 20 11 12 [1] [2] RESETN (reserved) PIO0_4/SCL PIO0_5/SDA Symbol [1] PIO0_9/MOSI 10 Product data sheet Pad 6 9 NHS3100 Symbol LB LA 21 [2] (reserved) 22 [2] (reserved) 23 [2] (reserved) 24 [2] (reserved) High source current pads. See Section 8.6.3. These pads must be tied to ground. All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 5 / 45 NHS3100 NXP Semiconductors Temperature logger Table 4. Pad description of the HVQFN24 package Pad Symbol Type Description 7 VDDBAT supply positive supply voltage 8 VSS supply ground PIO0_0 I/O GPIO WAKEUP I Deep power-down mode wake-up pin PIO0_1 I/O GPIO CLKOUT O clock output PIO0_2 I/O GPIO SSEL I SPI/SSP serial select line PIO0_3 I/O GPIO Supply [1] GPIO 1 2 3 14 11 12 4 13 5 6 15 16 CT16B_M0 O 16-bit timer match output 0 PIO0_4 I/O GPIO SCL I/O I C-bus SCL clock line PIO0_5 I/O GPIO SDA I/O I C-bus SDA data line PIO0_6 I/O GPIO SCLK I/O SPI/SSP serial clock line PIO0_7 I/O GPIO [2] 2 2 CT16B_M1 O 16-bit timer match output 1 PIO0_8 I/O GPIO MISO O SPI/SSP master-in slave-out line PIO0_9 I/O GPIO MOSI I SPI/SSP master-out slave-in line PIO0_10 I/O GPIO CT32B_M0 O 32-bit timer match output 0 SWCLK I ARM SWD clock PIO0_11 I/O GPIO CT32B_M1 O 32-bit timer match output 1 SWDIO I/O ARM SWD I/O 20 LA A NFC antenna/coil terminal A 19 LB A NFC antenna/coil terminal B RESETN I external reset input Radio Reset 9 [1] NHS3100 Product data sheet [3] The GPIO port is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pads depends on the function selected through the IOCONFIG register block. All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 6 / 45 NHS3100 NXP Semiconductors Temperature logger [2] If external wake-up is enabled on this pad, it must be pulled HIGH before entering Deep power-down mode and pulled LOW for a minimum of 100 s to exit Deep power-down mode. It has weak pull-up to VBAT or internal NFC voltage (whichever is highest). A LOW on this pad resets the device. This reset causes I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. It has weak pull-up to VDDBAT. [3] 7.1.2 WLCSP25 package Figure 3 shows the ball layout of the NHS3100 in the WLCSP25 package. ball A1 index area NHS3100UK 1 2 3 4 5 A B C D E aaa-024187 Transparent top view Figure 3. Ball configuration WLCSP25 Table 5. Ball allocation table of the WLCSP25 package Ball A1 Symbol [1] PIO0_7/CT16B_M1 [1] C4 A2 VSS C5 PIO0_11/CT32B_M1/SWDIO A3 RESETN D1 PIO0_0/WAKEUP A4 PIO0_4/SCL D2 PIO0_1/CLKOUT [2] (reserved) [2] (reserved) [2] (reserved) E1 [2] (reserved) E2 [2] (reserved) PIO0_10/CT32B_M0/SWCLK E3 [2] (reserved) C1 PIO0_2/SSEL E4 LA C2 PIO0_6/SCLK E5 LB C3 VSS - - PIO0_5/SDA B1 D4 PIO0_9/MOSI B3 D5 (reserved) B4 [1] B5 [1] [1] [2] D3 PIO0_8/MISO B2 Product data sheet Ball VDDBAT A5 NHS3100 Symbol PIO0_3/CT16B_M0 High source current balls. See Section 8.6.3. These balls must be tied to ground. All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 7 / 45 NHS3100 NXP Semiconductors Temperature logger Table 6. Ball description of the WLCSP25 package Ball Symbol Type Description VDDBAT supply positive supply voltage Supply A1 A2, C3 VSS supply ground [1] GPIO D1 D2 C1 B4 A4 A5 C2 C4 B1 B2 B5 C5 PIO0_0 I/O GPIO WAKEUP I Deep power-down mode wake-up pin PIO0_1 I/O GPIO CLKOUT O clock output PIO0_2 I/O GPIO SSEL I SPI/SSP serial select line PIO0_3 I/O GPIO CT16B_M0 O 16-bit timer match output 0 PIO0_4 I/O GPIO SCL I/O I C-bus SCL clock line PIO0_5 I/O GPIO SDA I/O I C-bus SDA data line PIO0_6 I/O GPIO SCLK I/O SPI/SSP serial clock line PIO0_7 I/O GPIO [2] 2 2 CT16B_M1 O 16-bit timer match output 1 PIO0_8 I/O GPIO MISO O SPI/SSP master-in slave-out line PIO0_9 I/O GPIO MOSI I SPI/SSP master-out slave-in line PIO0_10 I/O GPIO CT32B_M0 O 32-bit timer match output 0 SWCLK I ARM SWD clock PIO0_11 I/O GPIO CT32B_M1 O 32-bit timer match output 1 SWDIO I/O ARM SWD I/O E4 LA A NFC antenna/coil terminal A E5 LB A NFC antenna/coil terminal B RESETN I external reset input Radio Reset A3 [1] NHS3100 Product data sheet [3] The GPIO port is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depend on the function selected through the IOCONFIG register block. All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 8 / 45 NHS3100 NXP Semiconductors Temperature logger [2] [3] If external wake-up is enabled on this pin, it must be pulled HIGH before entering Deep power-down mode and pulled LOW for a minimum of 100 s to exit Deep power-down mode. A LOW on this pin resets the device. This reset causes I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. It has weak pull-up to VDDBAT or internal NFC voltage (whichever is highest). 7.1.3 NHS3100W8 gold bump version Figure 4 shows the bump layout of the NHS3100W8. 2 3 4 1 12 11 10 5 6 9 8 7 pin numbering aaa-025706 Figure 4. Bump configuration Bump die: Top view, bumps up NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 9 / 45 NHS3100 NXP Semiconductors Temperature logger Table 7. Bump allocation table of the NHS3100W8 package Bump Symbol Bump Symbol 1 PIO0_0/WAKEUP 7 TP1 2 TP0 8 VSS 3 LA 9 VDDBAT 4 LB 10 PIO0_6 5 PIO0_11/CT32B_M1/SWDIO 11 TP2 6 PIO0_10/CT32B_M0/SWCLK 12 TP3 Table 8. Bump description of the NHS3100W8 package Bump Symbol Type Description VDDBAT supply positive supply voltage VSS supply ground PIO0_0 I/O GPIO WAKEUP I Deep power-down mode wake-up pin 10 PIO0_6 I/O GPIO 6 PIO0_10 I/O GPIO Supply 9 8 [1] GPIO 1 5 CT32B_M0 O 32-bit timer match output 0 SWCLK I ARM SWD clock PIO0_11 I/O GPIO CT32B_M1 O 32-bit timer match output 1 SWDIO I/O ARM SWD I/O 3 LA A NFC antenna/coil terminal A 4 LB A NFC antenna/coil terminal B [2] Radio Test pins 2 TP0 - test pin - do not connect 7 TP1 - test pin - do not connect, or connect to ground 11 TP2 - test pin - do not connect 12 TP3 - test pin - do not connect [1] [2] NHS3100 Product data sheet The GPIO port is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 balls depends on the function selected through the IOCONFIG register block. If external wake-up is enabled on this ball, it must be pulled HIGH before entering Deep power-down mode and pulled LOW for a minimum of 100 s to exit Deep power-down mode. All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 10 / 45 NHS3100 NXP Semiconductors Temperature logger 8 Functional description 8.1 ARM Cortex-M0+ core Refer to the Cortex-M0+ Devices Technical Reference Manual (Ref. 1) for a detailed description of the ARM Cortex-M0+ processor. The NHS3100 ARM Cortex-M0+ core has the following configuration: * System options - Nested Vectored Interrupt Controller (NVIC) - Fast (single-cycle) multiplier - System tick timer - Support for wake-up interrupt controller - Vector table remapping register - Reset of all registers * Debug options - Serial Wire Debug (SWD) with two watchpoint comparators and four breakpoint comparators - Halting debug is supported 8.2 Memory map Figure 5 shows the memory and peripheral address space of the NHS3100. The only AHB peripheral device on the NHS3100 is the GPIO module. The APB peripheral area is 512 kB in size. Each peripheral is allocated 16 kB of space. All peripheral register addresses are 32-bit word aligned. Byte and halfword addressing is not possible. All reading and writing are done per full word. NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 11 / 45 NHS3100 NXP Semiconductors Temperature logger 0xFFFF FFFF (reserved) 0xE020 0000 0xE01F FFFF 0x501F FFFF (reserved) private peripheral bus 0x5001 0000 0x5000 FFFF 0xE000 0000 0xDFFF FFFF GPIO PIO0 (reserved) 0x5000 0000 0x5020 0000 0x501F FFFF AHB peripherals AHB peripherals 0x5000 0000 0x4FFF FFFF (reserved) 0x4008 0000 0x4007 FFFF (reserved) APB peripherals 0x4000 0000 0x3FFF FFFF 0x4006 0000 temperature sensor 0x4005 8000 RFID/NFC 0x4005 4000 RTC timer 0x4004 8000 system configuration 0x4004 4000 IOCONFIG (reserved) (reserved) 0x3000 1000 0x3000 0FFF (reserved) 4 kB EEPROM 0x3000 0000 0x2FFF FFFF (reserved) 0x1000 2000 0x1000 1FFF 0x4004 0000 SPI/SSP 0x4003 C000 flash controller 0x4003 8000 PMU 0x4003 4000 EEPROM controller 0x4001 4000 32-bit timer 0x4000 C000 16-bit timer 0x4000 4000 watchdog timer 0x4000 0000 l2C-bus (reserved) 8 kB SRAM 0x1000 0000 0x0FFF FFFF (reserved) (reserved) (reserved) 0x0000 8000 0x0000 7FFF 32 kB on-chip flash 0x0000 0000 APB peripherals aaa-017231 Figure 5. NHS3100 memory map 8.3 System configuration The system configuration APB block controls oscillators, start logic, and clock generation of the NHS3100. Also included in this block is a register for remapping the interrupt vector table. 8.3.1 Clock generation The NHS3100 Clock Generator Unit (CGU) includes two independent RC oscillators. These oscillators are the System Free-Running Oscillator (SFRO) and the Timer FreeRunning Oscillator (TFRO). NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 12 / 45 NHS3100 NXP Semiconductors Temperature logger The SFRO runs at 8 MHz. The system clock is derived from it and can be set to 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, or 62.5 kHz (Note: Some features are not available when using the lower clock speeds). The TFRO runs at 32.768 kHz and is the clock source for the timer unit. The TFRO cannot be disabled. Following reset, the NHS3100 starts operating at the default 500 kHz system clock frequency to minimize dynamic current consumption during the boot cycle. The SYSAHBCLKCTRL register gates the system clock to the various peripherals and memories. The temperature sensor receives a fixed clock frequency, irrespective of the system clock divider settings, while the digital part uses the system clock (AHB clock 0). SYSCLKDIV[2:0] system clock (AHB clock 0) SYSTEM CLOCK DIVIDER SYSTEM FRO (8 MHz) peripheral clocks SYSAHBCLKCTRL SYSCLKTRIM fixed-frequency taps analog peripheral clocks SSPCLKDIV SPI/SSP CLOCK DIVIDER WATCHDOG CLOCK DIVIDER 0 WDTSEL SPI/SSP WDT_PCLK WDTCLKDIV PMU/always-on-domain TIMER FRO (32 kHz) wake-up timer TMRCLKTRIM 0 TMRUEN aaa-015352 Figure 6. NHS3100 clock generator block diagram 8.3.2 Reset Reset has three sources on the NHS3100: * The RESETN pin * Watchdog reset * A software reset NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 13 / 45 NHS3100 NXP Semiconductors Temperature logger 8.4 Power management The Power Management Unit (PMU) controls the switching between available power sources and the powering of the different voltage domains in the IC. 8.4.1 System power architecture The NHS3100 accepts power from two different sources: from the external power supply pin VDDBAT, or from the built-in NFC/RFID rectifier. The NHS3100 has a small automatic source selector that monitors the power inputs (VBAT and VNFC, see Figure 7) as well as pin RESETN. The PSWBAT switch is kept open until a trigger is given on pin RESETN or via the NFC field. If the trigger is given, the always-on domain, VDD_ALON, itself is powered via the PSWBAT or the PSWNFC switch: via VBAT, if VBAT > 1.72 V, or VNFC. Priority is given to VBAT when both VBAT and VNFC are present. The automatic source selector unit in the PMU decides on the powering of the internal domains based on the power source. * If a voltage > 1.72 V is detected on VBAT and not VNFC, VBAT powers the internal domains after a trigger on pin RESETN or via NFC. * If a voltage 1.72 V is detected on VBAT, and a higher voltage is detected on VNFC, the internal domains are powered from VNFC. * If a voltage > 1.72 V is detected at both VBAT and VNFC, the internal domains are powered from VBAT. * Switchover between power sources is possible. If initially both VBAT and VNFC are available, the system is powered from VBAT. If VBAT then becomes unavailable (because it is switched off externally, or by a PSWBAT/PSWNFC power switch override), the internal domains are immediately powered from VNFC. Switchover is supported in both directions. * The user can force the selection of the VBAT input by disabling the automatic power switch, which disables the automatic source selector voltage comparator. When on NFC power only (passive operation), connecting one or more 100 nF external capacitors in parallel to a GPIO pad, and setting that pad as an output driven to logic 1, is advised. Preferably a high-drive pin should be chosen and several pins can be connected in parallel. PSWNFC and PSWBAT are the power switches. PSWNFC connects power to the VDD_ALON power net when an RF field is present. PSWBAT connects power from the battery when a positive edge is detected on RESETN. If no RF power is available, the PMU can open this PSWBAT switch, effectively switching off the device. After connecting VDDBAT to a power source, the PSWBAT switch is open until a rising edge is detected on RESETN or RF power is applied. Each component of the NHS3100 resides in one of several internal power domains, as indicated in Figure 7. The domains are VBAT, VNFC, VDD_ALON, VDD1V2 and VDD1V6. The domains VDD_ALON, VDD1V2 and VDD1V6 are either powered or not powered, depending on the mode of the NHS3100. There are 5 modes: * * * * NHS3100 Product data sheet Active Sleep Deep-sleep Deep power-down All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 14 / 45 NHS3100 NXP Semiconductors Temperature logger * Battery-off The VDD_ALON domain contains BrownOut Detection (BOD). When enabled, it raises a BOD interrupt if the VDD_ALON voltage drops below 1.8 V. The PMU controls the Active, Sleep, Deep-sleep, and Deep power-down modes. In this way, the power flows to the different internal components. The PMU has two LDOs powering the internal VDD1V2 and VDD1V6 voltage domains. LDO1V2 converts voltages in the range 1.72 V to 3.6 V to 1.22 V. LDO1V6 converts voltages in the range 1.72 V to 3.6 V to 1.6 V. Each LDO can be enabled separately. When powered via VNFC, a 1.2 nF buffer capacitor is included at the input of the LDOs. The trigger detector (not shown in Figure 7) and the power gate have a leakage of less than 50 nA, allowing a long shelf life before activation. LA NFC core LB VDDBAT VNFC < 1.85 V VBAT 1.72 V to 3.6 V PSWNFC 1.6 V LDO1V6 PSWBAT ANALOG PERIPHERALS, FLASH MEMORY EEPROM MEMORY 1.72 V to 3.6 V AUTOMATIC SOURCE SELECTOR UNIT VDD_ALON ALWAYS-ON DOMAIN 75 k 32 kHz FRO RESETN RTC PMU PIO0_0 WAKEUP LDO1V2 BOD GPREGx pin mode override if PCON.WAKEUP set, when entering Deep power-down mode 1.2 V DIGITAL CORE PERIPHERALS SFRO aaa-019962 Figure 7. NHS3100 power architecture Table 9 summarizes the PMU states and settings of the LDOs. Figure 8 shows the state transitions. Table 10 and Table 11 summarize the events that can influence wake-up from Deep power-down or Deep-sleep modes (DEEPPDN or DEEPSLEEP to ACTIVE state transition). Table 9. IC power states State VDD_ALON DPDN BATTERY-OFF (No power) no X ACTIVE yes DEEPPDN yes NHS3100 Product data sheet [1] LDO1 (1.2 V) LDO2 (1.6 V) X off off 0 0 on on 1 0 off off [2] Sleep or Deepsleep [2] All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 15 / 45 NHS3100 NXP Semiconductors Temperature logger State VDD_ALON DPDN SLEEP/DEEPSLEEP yes 0 [1] [2] [1] Sleep or Deepsleep LDO1 (1.2 V) LDO2 (1.6 V) 1 on on DPDN indicates whether the system is in Deep power-down mode. X = don't care. BATTERY-OFF ACTIVE SLEEP OR DEEP-SLEEP DEEP POWER-DOWN aaa-019373 Figure 8. PMU state transition diagram Figure 9 shows the power-up sequence. Applying battery power when the PSWBAT switch is closed, or NFC power becomes available, provides the always-on part with a Power-On Reset (POR) signal. The TFRO is initiated, which starts a state machine in the PMU. In the first state, the LDO1V2, powering the digital domain, is started. In the second state, the LDO1V6, powering the analog domain, is started which starts the flash memory. Enabling the LDO1V2, and the SFRO stabilizing, triggers the system_por. The system is now considered to be `on'. The system can boot when the flash memory is fully operational. The total start-up time from trigger to active mode/boot is about 2.5 ms. If there is no battery power, but there is RF power, the same procedure is followed except that PSWNFC connects power to the LDOs. The user cannot disable the TFRO as it is used by the PMU. Table 10. State transition events for DEEPSLEEP to ACTIVE NHS3100 Product data sheet Event Description RESETN reset asserted RTC event if the timer reaches preset value Watchdog watchdog issues interrupt or reset WAKEUP signal on WAKEUP pin RF field RF field is detected, potential NFC command input (if set in PMU) Start logic interrupt one of the enabled start logic interrupts is asserted All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 16 / 45 NHS3100 NXP Semiconductors Temperature logger Table 11. State transition events for DEEPPDN to ACTIVE Event Description RESETN reset asserted RTC event if the timer reaches preset value WAKEUP signal on WAKEUP pin (when enabled) RF field RF field is detected, potential NFC command input (if set in PMU) VDD_ALON off POR always-on domain start TFRO enable 1.2 V LDO enable 1.6 V LDO for analog domain and flash memory SFRO starts running power flash and digital power analog SFRO stable (64 s) system_por on aaa-016479 Figure 9. NHS3100 power-up sequence 8.4.2 Power Management Unit (PMU) The Power Management Unit (PMU) partly resides in the digital power domain and partly in the always-on domain. The PMU controls the Sleep, Deep-sleep, and Deep powerdown modes and the power flow to the different internal circuit blocks. Five generalpurpose registers in the PMU can be used to retain data during Deep power-down mode. These registers are located in the always-on domain. When configured, the PMU also raises a BOD interrupt if VDD_ALON drops to below 1.8 V. The power to the different APB analog slaves is controlled through a power-down configuration register. The power control register selects whether an ARM Cortex-M0+ controlled Power-down mode (Sleep mode or Deep-sleep mode) or the Deep power-down mode is entered. It also provides the flags for Sleep or Deep-sleep modes and Deep power-down mode respectively. In addition, it contains the overrides for the power source selection. 8.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is a part of the ARM Cortex-M0+. The tight integration of the processor core and NVIC enables fast processing of interrupts, dramatically reducing the interrupt latency. 8.5.1 Features * NVIC that is a part of the ARM Cortex-M0+ * Tightly coupled interrupt controller provides low interrupt latency * Controls system exceptions and peripheral interrupts NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 17 / 45 NHS3100 NXP Semiconductors Temperature logger * Four programmable interrupt priority levels with hardware priority level masking * Software interrupt generation 8.5.2 Interrupt sources Table 12 lists the interrupt sources for each peripheral function. Each peripheral device may have one or more interrupt lines to the Nested Vectored Interrupt Controller. Each line may represent more than one interrupt source. There is no significance or priority about which line is connected where, except for certain standards from ARM. Table 12. Connection of interrupt source to the Nested Vector Interrupt Controller Exception Vector number offset Function Flags 0 to 12 - start logic wake-up interrupts each interrupt connected to a PIO0 input pin serves [1] as wake-up from Deep-sleep mode 13 - RFID/NFC RFID/NFC access detected/command received/read acknowledge 14 - RTC On/Off timer RTC on/off timer event interrupt 2 15 - I C Slave Input (SI) (state change) 16 - CT16B 16-bit timer 17 - PMU power from NFC field detected 18 - CT32B 32-bit timer 19 - BOD brownout detection (power drop) 20 - SPI/SSP TX FIFO half empty/RX FIFO half full/RX time-out/RX overrun 21 - TSENS temperature sensor end of conversion/low threshold/ high threshold 22 to 25 - - (reserved) 26 - WDT watchdog interrupt (WDINT) 27 - flash flash memory 28 - EEPROM EEPROM memory 29 to 30 - - (reserved) 31 - PIO0 GPIO interrupt status of port 0 [1] Interrupt 0 to 10 correspond to PIO0_0 to PIO0_10; interrupt 11 corresponds to RFID/NFC external access; interrupt 12 corresponds to the RTC On/Off timer. 8.6 I/O configuration The I/O configuration registers control the electrical characteristics of the pads. The following features are programmable: * * * * NHS3100 Product data sheet Pin function Internal pull-up/pull-down resistor or bus keeper function Low-pass filter 2 2 I C-bus mode for pads hosting the I C-bus function All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 18 / 45 NHS3100 NXP Semiconductors Temperature logger The IOCON registers control the function (GPIO or peripheral function), the input mode, 2 and the hysteresis of all PIO0_m pins. In addition, the I C-bus pins can be configured for 2 different I C-bus modes. The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000) or to a peripheral function. If the pins are GPIO pins, the GPIO0DIR registers determine whether the pin is configured as an input or output. For any peripheral function, the pin direction is controlled automatically depending on the functionality of the pin. The GPIO0DIR registers have no effect on peripheral functions. 8.6.1 PIO0 pin mode The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull-down resistors for each pin, or to select the repeater mode. The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. The default value is no pull-up or pull-down enabled. The repeater mode enables the pull-up resistor when the pin is at logic 1, and enables the pull-down resistor when the pin is at logic 0. This mode causes the pin to retain its last known state if it is configured as an input and is not driven externally. The state retention is not applicable to the Deep powerdown mode. Repeater mode is typically used to prevent a pin from floating when it is temporarily not driven. Allowing it to float could potentially use significant power. NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 19 / 45 NHS3100 NXP Semiconductors Temperature logger 2 8.6.2 PIO0 I C-bus mode 2 2 If the FUNC bits of registers PIO0_4 and PIO0_5 select the I C-bus function, the I C-bus 2 pins can be configured for different I C-bus modes: 2 * Standard-mode/Fast-mode I C-bus with input glitch filter (including an open-drain 2 output according to the I C-bus specification) * Standard open-drain I/O functionality without input filter 8.6.3 PIO0 current source mode PIO0_3, PIO0_7, PIO0_10 and PIO0_11 are high-source pads that can deliver up to 20 mA to the load. These PIO pins can be set to either digital mode or analog current sink mode. In digital mode, the output voltage of the pad switches between VSS and VDD. In analog current drive mode, the output current sink switches between the values set by the ILO and IHI bits. The maximum pad voltage is limited to 5 V. CDRIVE configured as output ESD data output PIN ESD CURRENT SINK ILO[7:0] IHI[7:0] pull-up enable configured as input repeater mode enable pull-up enable data input aaa-015353 Figure 10. Pin configuration with current source mode 8.7 Fast general-purpose parallel I/O The GPIO registers control device pins that are not connected to a specific peripheral function. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. The NHS3100 uses accelerated GPIO functions: * GPIO registers are on the ARM Cortex-M0+ I/O bus for fastest possible single-cycle I/O timing * An entire port value can be written in one instruction * Mask, set, and clear operations are supported for the entire port All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be moved to another pin. NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 20 / 45 NHS3100 NXP Semiconductors Temperature logger 8.7.1 Features * Bit level port registers allow a single instruction to set and clear any number of bits in one write operation * Direction control of individual bits * After reset, all I/Os default to GPIO inputs without pull-up or pull-down resistors; The 2 I C-bus true open-drain pins PIO0_4 and PIO0_5 and the SWD pins PIO0_10 and PIO0_11 are exceptions * Pull-up/pull-down Configuration, Repeater, and Open-drain modes can be programmed through the IOCON block for each GPIO pin * Direction (input/output) can be set and cleared individually per pin * Pin direction bits can be toggled 2 8.8 I C-bus controller 8.8.1 Features 2 Standard I C-bus compliant interfaces may be configured as master, slave, or master/ slave. * Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus 2 * Programmable clock allows adjustment of I C-bus transfer rates * Data transfer is bidirectional between masters and slaves * Serial clock synchronization allows devices with different bit rates to communicate via one serial bus * Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer * Supports Standard-mode (100 kbit/s) and Fast-mode (400 kbit/s) * Optional recognition of up to four slave addresses 2 * Monitor mode allows observing all I C-bus traffic, regardless of slave address 2 * The I C-bus can be used for test and diagnostic purposes 2 2 * The I C-bus contains a standard I C-bus compliant interface with two pins 2 * Possibility to wake up NHS3100 on matching I C-bus slave address NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 21 / 45 NHS3100 NXP Semiconductors Temperature logger 8.8.2 General description 2 Two types of data transfers are possible on the I C-bus, depending on the state of the direction bit (R/W): * Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. * Data transfer from a slave transmitter to a master receiver The master transmits the first byte (the slave address). The slave then returns an acknowledge bit. The slave then transmits the data bytes to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. As a repeated START 2 condition is also the beginning of the next serial transfer, the I C-bus is not released. 2 The I C-bus interface is byte oriented and has four operating modes: Master transmitter mode, Master receiver mode, Slave transmitter mode, and Slave receiver mode. 2 2 The I C-bus interface is completely I C-bus compliant, supporting the ability to power off 2 the NHS3100 independent of other devices on the same I C-bus. 2 The I C-bus interface requires a minimum 2 MHz system clock to operate in Normal mode, and 8 MHz for Fast-mode. 2 8.8.3 I C-bus pin description 2 Table 13. I C-bus pin description Pin Type Description SDA I/O I C-bus serial data SCL I/O I C-bus serial clock 2 2 2 The I C-bus pins must be configured through the PIO0_4 and PIO0_5 registers for 2 Standard-mode or Fast-mode. The I C-bus pins are open-drain outputs and fully 2 compatible with the I C-bus specification. 8.9 SPI controller 8.9.1 Features * Compatible with Motorola SPI, 4-wire Texas Instruments Synchronous Serial Interface (SSI), and National Semiconductor Microwire buses * Synchronous serial communication * Supports master or slave operation * Eight-frame FIFOs for both transmit and receive * 4-bit to 16-bit frame NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 22 / 45 NHS3100 NXP Semiconductors Temperature logger 8.9.2 General description The SPI/SSP is a Synchronous Serial Port (SSP) controller capable of operation on an SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames from 4 bits to 16 bits of bidirectional data flowing between master and slave. In practice, often only one of these two data flows carries meaningful data. 8.9.3 Pin description Table 14. SPI pin description Pin name Type Interface pin SPI SSI Microwire Description SCLK I/O SCLK CLK SK serial clock SSEL I/O SSEL FS CS frame sync/slave select MISO I/O MISO DR (M) DX (S) SI (M) SO (S) master input slave output MOSI I/O MOSI DX (M) DR (S) SO (M) SI (S) master output slave input 8.9.3.1 Pin detailed description Serial clock SCK/CLK/SK is a clock signal used to synchronize the transfer of data. The master drives the clock signal and the slave receives it. When SPI/SSP interface is used, the clock is programmable to be active HIGH or active LOW, otherwise it is always active HIGH. SCK only switches during a data transfer. At any other time, the SPI/SSP interface either stays in its inactive state or is not driven (remains in high-impedance state). Frame sync/slave select When the SPI/SSP interface is a bus master, it drives this signal to an active state before the start of serial data. It then releases it to an inactive state after the data has been sent. The active state can be HIGH or LOW depending upon the selected bus and mode. When the SPI/SSP interface is a bus slave, this signal qualifies the presence of data from the master according to the protocol in use. When there is only one master and slave, the master signals, frame sync, or slave select, can be connected directly to the corresponding slave input. When there are multiple slaves, further qualification of frame sync/slave select inputs is normally necessary to prevent more than one slave from responding to a transfer. Master Input Slave Output (MISO) The MISO signal transfers serial data from the slave to the master. When the SPI/SSP is a slave, it outputs serial data on this signal. When the SPI/SSP is a master, it clocks in serial data from this signal. It does not drive this signal and leaves it in a high-impedance state when the SPI/SSP is a slave and not selected by FS/SSEL. Master Output Slave Input (MOSI) NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 23 / 45 NHS3100 NXP Semiconductors Temperature logger The MOSI signal transfers serial data from the master to the slave. When the SPI/SSP is a master, it outputs serial data on this signal. When the SPI/SSP is a slave, it clocks in serial data from this signal. 8.10 RFID/NFC communication unit 8.10.1 Features * * * * * ISO/IEC14443A part 1 to part 3 compatible MIFARE (Ultralight) EV1 compatible NFC Forum Type 2 compatible Easy interfacing with standard user memory space READ/WRITE commands Passive operation possible 8.10.2 General description The RFID/NFC interface allows communication using 13.56 MHz proximity signaling. APB LA LB RFID ANALOG SUBSYSTEM TP EEPROM SUBSYSTEM RFID ANALOG INTERFACE EEPROM INTERFACE RFID MAIN CONTROLLER RFID DIGITAL SUBSYSTEM VDD_RFID SRAM CMDIN APB INTERFACE DATAOUT SR Register APB SLAVE SUBSYSTEM irq aaa-015354 Figure 11. Block diagram of the RFID/NFC interface The CMDIN, DATAOUT, Status Register (SR), and SRAM are mapped in the user memory space of the RFID core. The RFID READ and WRITE commands allow wireless communication to this shared memory. Messages can be in Raw mode (user proprietary protocol) or formatted according to NFC Forum Type 2 NDEF messaging and ISO/IEC 11073. NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 24 / 45 NHS3100 NXP Semiconductors Temperature logger 8.11 16-bit timer 8.11.1 Features One 16-bit timer with a programmable 16-bit prescaler. * Timer operation * Four 16-bit match registers that allow: - Continuous operation with optional interrupt generation on match - Stop timer on match with optional interrupt generation - Reset timer on match with optional interrupt generation * Up to two CT16B external outputs corresponding to the match registers with the following capabilities: - Set LOW on match - Set HIGH on match - Toggle on match - Do nothing on match * Up to two match registers can be configured as Pulse Width Modulation (PWM) allowing the use of up to two match outputs as single edge controlled PWM outputs 8.11.2 General description The peripheral clock (PCLK), which is derived from the system clock, clocks the timer. The timer can optionally generate interrupts or perform other actions at specified timer values based on four match registers. The peripheral clock is provided by the system clock. Each timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. In PWM mode, four match registers can be used to provide a single-edge controlled PWM output on the match output pins. The use of the match registers that are not pinned out to control the PWM cycle length is recommended. NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 25 / 45 NHS3100 NXP Semiconductors Temperature logger 8.12 32-bit timer 8.12.1 Features One 32-bit timer with a programmable 32-bit prescaler. * Timer operation * Four 32-bit match registers that allow: - Continuous operation with optional interrupt generation on match - Stop timer on match with optional interrupt generation - Reset timer on match with optional interrupt generation * Up to two CT32B external outputs corresponding to the match registers with the following capabilities: - Set LOW on match - Set HIGH on match - Toggle on match - Do nothing on match * Up to two match registers can be configured as PWM allowing the use of up to two match outputs as single edge controlled PWM outputs 8.12.2 General description The peripheral clock (PCLK), which is derived from the system clock, clocks the timer. The timer can optionally generate interrupts or perform other actions at specified timer values based on four match registers. The peripheral clock is provided by the system clock. Each timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. In PWM mode, four match registers can be used to provide a single-edge controlled PWM output on the match output pins. Use of the match registers that are not pinned out to control the PWM cycle length is recommended. NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 26 / 45 NHS3100 NXP Semiconductors Temperature logger 8.13 WatchDog Timer (WDT) If the microcontroller enters an erroneous state, the purpose of the WatchDog Timer (WDT) is to reset it within a reasonable amount of time. When enabled, if the user program fails to feed (or reload) the WDT within a predetermined amount of time, the WDT generates a system reset. 8.13.1 Features * If not periodically reloaded, it internally resets the microcontroller * Debug mode * Enabled by software but requires a hardware reset or a WDT reset/interrupt to be disabled * If enabled, incorrect/incomplete feed sequence causes reset/interrupt * Flag to indicate WDT reset * Programmable 24-bit timer with internal prescaler 24 * Selectable time period from (TWDCLK x 256 x 4) to (TWDCLK x 2 x 4) in multiples of TWDCLK x 4 * The WDT clock (WDCLK) source is a 2 MHz clock derived from the SFRO, or the external clock as set by the SYSCLKCTRL register 8.13.2 General description The WDT consists of a divide by 4 fixed prescaler and a 24-bit counter. The clock is fed to the timer via a prescaler. The timer decrements when clocked. The minimum value by which the counter is decremented is 0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence the minimum WDT interval is (TWDCLK x 256 x 4) 24 and the maximum is (TWDCLK x 2 x 4), in multiples of (TWDCLK x 4). 8.14 System tick timer 8.14.1 Features * Simple 24-bit timer * Uses dedicated exception vector * Clocked internally by the system clock or the system clock divided by two 8.14.2 General description The SYSTICK timer is a part of the Cortex-M0+. The SYSTICK timer can be used to generate a fixed periodic interrupt for use by an operating system or other system. Since the SYSTICK timer is a part of the Cortex-M0+, it facilitates porting of software by providing a standard timer available on Cortex-M0+ based devices. The SYSTICK timer can be used for management software. Refer to the Cortex-M0+ Devices - Generic User Guide (Ref. 2) for details. NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 27 / 45 NHS3100 NXP Semiconductors Temperature logger 8.15 Real-Time Clock (RTC) timer 8.15.1 Features The Real-Time Clock (RTC) block contains two counters: * A countdown timer generating a wake-up signal when it expires * A continuous counter that counts seconds since power-up or the last system reset The countdown timer runs on a low speed clock and runs in an always-on power domain. The delay, as well as a clock tuning prescaler, can be configured via the APB bus. The RTC countdown timer generates both the deep power-down wake-up signal and the RTC interrupt signal (wake-up interrupt 12). The deep power-down wake-up signal is always generated, while the interrupt can be masked according to the settings in the RTCIMSC register. 8.15.2 General description The RTC module consists of two parts: * The RTC core module, implementing the RTC timers themselves. This module runs in the always-on VDD_ALON domain. * The AMBA APB slave interface. This module allows configuration of the RTC core via an APB bus. This module runs in the switched power domain. 8.16 Temperature sensor 8.16.1 Features The temperature sensor block measures the chip temperature and outputs a raw value or a calibrated value in Kelvin. 8.16.2 General description The temperature is measured using a high-precision, zoom-ADC. The analog part is able 1 to measure a highly temperature-dependent X = Vbe / Vbe . It determines the value of X by first applying a coarse search (successive approximation), and then a sigma-delta in a limited range. The conversion time depends on the resolution mode as shown in Table 15. Table 15. Conversion time for different resolution of TSENS Resolution (bit) Resolution (C) Conversion time (ms) 7 0.8 4 8 0.4 7 9 0.2 14 10 0.1 26 1 Vbe is the base-emitter voltage of a bipolar transistor. Basically, the temperature sensor measures the voltage drop over a diode formed by the base-emitter junction of a bipolar transistor. It compares the Vbe at different current levels (from which follows the Vbe). NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 28 / 45 NHS3100 NXP Semiconductors Temperature logger Resolution (bit) Resolution (C) Conversion time (ms) 11 0.05 50 12 0.025 100 8.17 Serial Wire Debug (SWD) The debug functions are integrated into the ARM Cortex-M0+. Serial Wire Debug (SWD) functions are supported. The ARM Cortex-M0+ is configured to support up to four breakpoints and two watchpoints. * * * * Supports ARM SWD mode Direct debug access to all memories, registers, and peripherals No target resources are required for the debugging session Four breakpoints Four instruction breakpoints that can also be used to remap instruction addresses for code patches. Two data comparators that can be used to remap addresses for patches to literal values. * Two data watchpoints that can also be used as triggers 8.18 On-chip flash memory The NHS3100 contains a 32 kB flash memory of which 30 kB can be used as program and data memory. The flash is organized in 32 sectors of 1 kB. Each sector consists of 16 rows of 16 x 32bit words. 8.18.1 Reading from flash Reading is done via the AHB interface. The memory is mapped on the bus address space as a contiguous address space. Memory data words are seen on the bus using a little endian arrangement. 8.18.2 Writing to flash Writing to flash means copying a word of data over the AHB to the page buffer of the flash. It does not actually program the data in the memory array. This programming is done by subsequent erase and program cycles. NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 29 / 45 NHS3100 NXP Semiconductors Temperature logger 8.18.3 Erasing/programming flash Erasing and programming are separate operations. Both are possible only on memory sectors that are unprotected and unlocked. Protect/lock information is stored inside the memory itself, so the controller is not aware of protection status. Therefore, if a program/ erase operation is performed on a protected or locked sector, it does not flag an error. Protection At exit from reset, all sectors are protected against accidental modification. To allow modification, a sector must be unprotected. It can then be protected again after that the modification is performed. Locking Each flash sector has a lock bit. Lock bits can be set but cannot be cleared. Locked sectors cannot be erased and reprogramed. 8.19 On-chip SRAM The NHS3100 contains a total of 8 kB on-chip SRAM memory configured as 256 x 2 x 4 x 32 bit. 8.20 On-chip EEPROM The NHS3100 contains a 4 kB EEPROM. This EEPROM is organized in 64 rows of 32 x 16-bit words. Of these rows, the last four contain calibration and test data and are locked. This data is either used by the boot loader after reset, or made accessible to the application via firmware Application Programming Interface (API). 8.20.1 Reading from EEPROM Reading is done via the AHB interface. The memory is mapped on the bus address space, as a contiguous address space. Memory data words are seen on the bus using a little endian arrangement. 8.20.2 Writing to EEPROM Erasing and programming is performed, as a single operation, on one or more words inside a single page. Previous write operations have transferred the data to be programmed into the memory page buffer. The page buffer tracks which words were written to (offset within the page only). Words not written to, retain their previous content. NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 30 / 45 NHS3100 NXP Semiconductors Temperature logger 9 Limiting values Table 16. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage VI input voltage Conditions Min Max Unit -0.5 +3.6 V normal PIO pads (VDD = 0.6 V) -0.5 +3.6 V high-source PIO pads -0.5 +5.5 V LA/LB pads -0.5 +5.5 V IDD supply current per supply pin - 100 mA ISS ground supply current per supply pin - 100 mA Ilu latch-up current I/O; -0.5VDD < VI < +1.5VDD; Tj < 125 C - 100 mA Tstg storage temperature -40 +125 C Tj junction temperature - 125 C Ptot total power dissipation - 1 W VESD electrostatic discharge voltage human body model; all pins -2000 +2000 V charged device model; all pins -500 +500 V NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 31 / 45 NHS3100 NXP Semiconductors Temperature logger 10 Static characteristics Table 17. Static characteristics Tamb = -40 C to +85 C, unless otherwise stated. Symbol Parameter Conditions Min Typ Max Unit 1.72 3.0 3.60 V - - - A - - 50 nA - 3 - A Supply pins VDD supply voltage IDD supply current voltage and clock frequency dependent IL(off) off-state leakage current IDD(pd) power-down mode supply current [1] Deep power-down mode Standard GPIO pins VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 0.4 - - V Rpd pull-down resistance - 72 - k Rpu pull-up resistance IS source current - 73 - k HIGH-level VDD = 1.8 V [2] - 2 - mA HIGH-level VDD = 3.6 V [2] - 8 - mA LOW-level VDD = 1.8 V [2] - 4 - mA LOW-level VDD = 3.6 V [2] - 16 - mA HIGH-level VDD = 1.8 V [3] 4 - 6 mA HIGH-level VDD = 3.6 V [3] 13 - 18 mA LOW-level VDD = 1.8 V [3] 5.5 - 8 mA LOW-level VDD = 3.6 V [3] 22 - 32 mA LOW-level VDD = 1.8 V [4] 2 - 8.5 mA LOW-level VDD = 3.6 V [4] 9.5 - 38 mA falling VDD - 1.8 - V rising VDD - 1.875 - V - 75 - mV High-drive GPIO pins IS source current 2 I C-bus pins IS source current Brownout detect Vtrip(bo) Vhys brownout trip voltage hysteresis voltage General Rpu(int) internal pull-up resistance on pin RESETN - 100 - k Cext external capacitance on pin RESETN - - 1 nF [1] [2] [3] [4] See Figure 12 PIO0_0, PIO0_1, PIO0_2, PIO0_6, PIO0_8, PIO0_9 PIO0_3, PIO0_7, PIO0_10, PIO0_11 PIO0_4, PIO0_5 NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 32 / 45 NHS3100 NXP Semiconductors Temperature logger aaa-022790 1000 (6) IDD (A) 800 600 (5) 400 (4) (3) (2) (1) 200 0 1.5 2 2.5 3 3.5 VDD (V) 4 Plot of IDD / VDD when ARM running a while - 1 loop in Normal mode, no NFC field present. (1) System clock = 250 kHz (2) System clock = 500 kHz (3) System clock = 1 MHz (4) System clock = 2 MHz (5) System clock = 4 MHz (6) System clock = 8 MHz Figure 12. Active current consumption Table 18. Temperature sensor characteristics Symbol Parameter Conditions Min Typ Max Unit ICC(pd) power-down mode supply current TSENS disabled - - 1 nA Istb standby current TSENS enabled - 6 7 A ICC(oper) operating supply current TSENS converting - 10 12 A Tacc temperature accuracy Tamb = 0 C to +40 C -0.3 - +0.3 C Tamb = -40 C to +85 C -0.5 - +0.5 C 12-bit mode - 0.025 - C 8-bit mode - 0.4 - C 12-bit mode - 100 - ms 8-bit mode - 7 - ms Tres Tconv temperature resolution conversion period Note: The absolute accuracy is valid for the factory calibration of the temperature sensor. The sensor can be user-calibrated to reach higher accuracy. NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 33 / 45 NHS3100 NXP Semiconductors Temperature logger Table 19. Antenna input characteristics Symbol Parameter Ci input capacitance fi input frequency [1] Conditions [1] Min Typ Max Unit - 50 - pF - 13.56 - MHz Tamb = 22 C, f = 13.56 MHz, RMS voltage between LA and LB is 1.5 V Table 20. EEPROM characteristics Symbol Parameter Conditions Min Typ Max Unit tret(data) data retention time Tamb = 22 C 10 - - year NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 34 / 45 NHS3100 NXP Semiconductors Temperature logger 11 Dynamic characteristics 11.1 I/O pins Table 21. I/O dynamic characteristics These characteristics apply to standard port pins and RESETN pin. Tamb = -40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns 2 11.2 I C-bus 2 Table 22. I C-bus dynamic characteristics 2 [1] See UM10204 - I C-bus specification and user manual (Ref. 3) for details. Tamb = -40 C to +85 C ; see the timing diagram in Figure 13. Symbol Parameter Conditions Min Typ Max Unit fSCL SCL clock frequency Standard-mode 0 - 100 kHz Fast-mode tf tLOW tHIGH tSU;DAT [1] [2] [3] [4] [5] [6] [7] [8] - 400 kHz - - 300 ns 20 + 0.1 x Cb - 300 ns fall time of both SDA and SCL signals Standard-mode Fast-mode [2] [3] [4] LOW period of the SCL clock Standard-mode 4.7 - - s Fast-mode 1.3 - - s Standard-mode 4.0 - - s HIGH period of the SCL clock Fast-mode tHD;DAT 0 [2] [3] [4] data hold time data setup time 0.6 - - s Standard-mode [2] [5] [6] 0 - - s Fast-mode [2] [5] [6] 0 - - s Standard-mode [7] [8] 250 - - ns Fast-mode [7] [8] 100 - - ns Parameters are valid over operating temperature range unless otherwise specified. A device must internally provide a hold time of at least 300 ns for the SDA signal (regarding the VIH(min) of the SCL signal). The hold time is to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. It allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode. However, it must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see Ref. 3). Only meet this maximum if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the setup time before it releases the clock. tSU;DAT is the data setup time that is measured against the rising edge of SCL; applies to data in transmission and the acknowledge. 2 2 A Fast-mode I C-bus device can be used in a Standard-mode I C-bus system but it must meet the requirement tSU;DAT = 250 ns. This requirement is automatically the case if the device does not stretch the LOW period of the SCL signal. If it does, it must output the next data bit to the SDA line 2 tr(max) + tSU;DAT = 1000 + 250 = 1250 ns before the SCL line is released. This procedure is in accordance with the Standard-mode I C-bus specification. Also, the acknowledge timing must meet this setup time. NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 35 / 45 NHS3100 NXP Semiconductors Temperature logger tf tSU;DAT 70 % 30 % SDA 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW 1 / fSCL S 002aaf425 2 Figure 13. I C-bus pins clock timing 11.3 SPI interfaces Table 23. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit SPI master tcy(clk) tSU;DAT tHD;DAT tv(Q) th(Q) full-duplex mode [1] 50 - - ns when only transmitting [1] 40 - - ns 2.4 V VDD < 3.6 V [2] 15 - - ns 2.0 V VDD < 2.4 V [2] 20 - - ns 1.8 V VDD < 2.0 V [2] 24 - - ns data hold time [2] 0 - - ns data output valid time [2] - - 10 ns data output hold time [2] 0 - - ns PCLK cycle time [3] [4] 0 - - ns data hold time [3] [4] 3 x Tcy(PCLK) + 4 - - ns data output valid time [3] [4] - - 3 x Tcy(PCLK) + 11 ns data output hold time [3] [4] - - 2 x Tcy(PCLK) + 5 clock cycle time data setup time SPI slave Tcy(PCLK) tHD;DAT tv(Q) th(Q) [1] [2] [3] [4] ns tcy(clk) = (SSPCLKDIV x (1 + SCR) x CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate tcy(clk) is a function of: * The main clock frequency fmain * The SPI peripheral clock divider (SSPCLKDIV) * The SPI SCR parameter (specified in the SSP0CR0 register) * The SPI CPSDVSR parameter (specified in the SPI clock prescale register) Tamb = -40 C to +105 C tcy(clk) = 12 x Tcy(PCLK) Tamb = 25 C for normal voltage supply: VDD = 3.3 V NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 36 / 45 NHS3100 NXP Semiconductors Temperature logger tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tSU;DAT DATA VALID MISO DATA VALID tv(Q) MOSI th(Q) DATA VALID DATA VALID tSU;DAT MISO CPHA = 1 tHD;DAT DATA VALID tHD;DAT CPHA = 0 DATA VALID aaa-024226 Figure 14. SPI master timing in SPI mode tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tSU;DAT MOSI DATA VALID tHD;DAT DATA VALID tv(Q) MISO th(Q) DATA VALID tSU;DAT MOSI DATA VALID tHD;DAT DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID aaa-024227 Figure 15. SPI slave timing in SPI mode NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 37 / 45 NHS3100 NXP Semiconductors Temperature logger 12 Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm B D SOT616-3 A terminal 1 index area A E A1 c detail X e1 e 7 C 1/2 e b v w 12 y1 C C A B C y L 13 6 e e2 Eh 1/2 e 1 18 terminal 1 index area 24 19 X Dh 0 2.5 scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A(1) 1 A1 b 0.05 0.30 0.00 0.18 c 0.2 5 mm D(1) Dh E(1) Eh 4.1 2.75 4.1 2.75 3.9 2.45 3.9 2.45 e e1 0.5 2.5 e2 2.5 L 0.5 0.3 v 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT616-3 References IEC JEDEC JEITA sot616-3_po European projection Issue date 16-02-17 16-07-14 MO-220 Figure 16. HVQFN24 package outline NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 38 / 45 NHS3100 NXP Semiconductors Temperature logger WLCSP25: wafer level chip-scale package, 25 balls; 2.51 x 2.51 x 0.5 mm B D SOT1401-1 A ball A1 index area A2 E A A1 detail X e1 C e Ov Ow b C A B C y E D e e2 C B A ball A1 index area 1 2 3 4 5 X 0 3 mm scale Dimensions (mm are the original dimensions) Unit mm A max 0.54 nom 0.50 min 0.46 A1 A2 b D E e e1 e2 v w y 0.23 0.20 0.17 0.325 0.300 0.275 0.29 0.26 0.23 2.54 2.51 2.48 2.54 2.51 2.48 0.4 1.6 1.6 0.15 0.05 0.03 sot1401-1_po Outline version References IEC JEDEC sot1401-1 JEITA European projection Issue date 15-10-05 16-07-26 --- Figure 17. WLCSP25 package outline NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 39 / 45 NHS3100 NXP Semiconductors Temperature logger Bumped die with 8 functional bumps; 2.51 mm x 2.51 mm x 0.16 mm 2.51 0.03 B SOT1870-1 A 0.160 0.015 0.150 0.015 2.51 0.03 detail X 0.010 0.002 terminal 1 index area 1.058 0.382 terminal 1 index area C 2 3 4 0.512 X 1.058 1 0.682 12 11 0.18 0.291 10 5 1.058 0.763 6 9 8 7 0.422 1.012 1.058 0 2 mm scale Dimensions are in mm Outline version SOT1870-1 References IEC JEDEC JEITA sot1870-1_ssv European projection --- Figure 18. Bumped die package outline NHS3100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 40 / 45 NHS3100 NXP Semiconductors Temperature logger 13 Abbreviations Table 24. Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus API Application Programming Interface ARM Advanced RISC Machine BOD BrownOut Detection CGU Clock Generator Unit EEPROM Electrically Erasable Programmable Read-Only Memory GPIO General Purpose Input Output 2 NHS3100 Product data sheet I C Inter-Integrated Circuit LDO Low DropOut MISO Master Input Slave Output MOSI Master Output Slave Input NDEF NFC Data Exchange Format NFC Near Field Communication NVIC Nested Vectored Interrupt Controller PMU Power Management Unit POR Power-On Reset PWM Pulse Width Modulation RFID Radio Frequency Identification RISC Reduced Instruction Set Computer RTC Real-Time Clock SFRO System Free-Running Oscillator SI Slave Input SO Slave Output SPI Serial Peripheral Interface SR Status Register SSI Synchronous Serial Interface SSP Synchronous Serial Port SWD Serial Wire Debug TFRO Timer Free-Running Oscillator WDT WatchDog Timer All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 41 / 45 NHS3100 NXP Semiconductors Temperature logger 14 References 1 DDI0484C_cortex_m0p_r0p1_trm Cortex-M0+ Devices - Technical Reference Manual 2 DUI0662B_cortex_m0p_r0p1_dgug Cortex-M0+ Devices - Generic User Guide 3 UM10204 user manual I C-bus specification and user manual; 2014, NXP Semiconductors 2 15 Revision history Table 25. Revision history Document ID Release date Data sheet status Change notice Supersedes NHS3100 v.6 <Tbd> Product data sheet - NHS3100 v.5 Modifications: * NFC certification and logo have been added. * Text has been updated throughout the document. NHS3100 v.5 20161205 Modifications * Addition of NHS3100W8 package data NHS3100 v.4 20160905 Modifications * General update * Static characteristics updated * Drawing revisions NHS3100 v.3 20160601 Modifications * General update NHS3100 v.2 20160531 Modifications * * * * * * * * NHS3100 v.1 20150811 NHS3100 Product data sheet Product data sheet - NHS3100 v.4 - NHS3100 v.3 Preliminary data sheet - NHS3100 v.2 Objective data sheet - NHS3100 v.1 Product data sheet Section 7.1 "Pinning" updated Section 8.4 "Power Management Unit (PMU)" major revision 2 Section 11.2 "I C-bus" updated Section 11.3 "SPI interfaces" added WLCSP25 package added Cautions added Table 15 "Static characteristics" updated Section 8.7 "Fast General-Purpose parallel I/O" added Objective data sheet - All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 - (c) NXP B.V. 2018. All rights reserved. 42 / 45 NHS3100 NXP Semiconductors Temperature logger 16 Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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This document supersedes and replaces all information supplied prior to the publication hereof. NHS3100 Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 43 / 45 NHS3100 NXP Semiconductors Temperature logger Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. NHS3100 Product data sheet 16.4 Licenses Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/ IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards. Purchase of NXP Semiconductors IC does not include a license to any NXP patent (or other IP right) covering combinations of those products with other products, whether hardware or software. 16.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. MIFARE -- is a trademark of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 6.03 -- 15 June 2018 (c) NXP B.V. 2018. All rights reserved. 44 / 45 NHS3100 NXP Semiconductors Temperature logger Contents 1 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 4 5 6 7 7.1 7.1.1 7.1.2 7.1.3 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.5 8.5.1 8.5.2 8.6 8.6.1 8.6.2 8.6.3 8.7 8.7.1 8.8 8.8.1 8.8.2 8.8.3 8.9 8.9.1 8.9.2 8.9.3 8.9.3.1 8.10 8.10.1 8.10.2 8.11 8.11.1 8.11.2 8.12 General description ............................................ 1 Features and benefits .........................................2 System ............................................................... 2 Memory .............................................................. 2 Digital peripherals .............................................. 2 Analog peripherals .............................................2 Communication interfaces ................................. 2 Clock generation ................................................2 Power control .....................................................3 General .............................................................. 3 Applications .........................................................3 Ordering information .......................................... 3 Marking .................................................................3 Block diagram ..................................................... 4 Pinning information ............................................ 5 Pinning ............................................................... 5 HVQFN24 package ............................................5 WLCSP25 package ........................................... 7 NHS3100W8 gold bump version ....................... 9 Functional description ......................................11 ARM Cortex-M0+ core .....................................11 Memory map ....................................................11 System configuration ....................................... 12 Clock generation ..............................................12 Reset ................................................................13 Power management .........................................14 System power architecture .............................. 14 Power Management Unit (PMU) ......................17 Nested Vectored Interrupt Controller (NVIC) ....17 Features ...........................................................17 Interrupt sources ..............................................18 I/O configuration .............................................. 18 PIO0 pin mode ................................................ 19 PIO0 I2C-bus mode .........................................20 PIO0 current source mode .............................. 20 Fast general-purpose parallel I/O .................... 20 Features ...........................................................21 I2C-bus controller ............................................ 21 Features ...........................................................21 General description ..........................................22 I2C-bus pin description ....................................22 SPI controller ................................................... 22 Features ...........................................................22 General description ..........................................23 Pin description ................................................. 23 Pin detailed description ................................... 23 RFID/NFC communication unit ........................ 24 Features ...........................................................24 General description ..........................................24 16-bit timer .......................................................25 Features ...........................................................25 General description ..........................................25 32-bit timer .......................................................26 8.12.1 8.12.2 8.13 8.13.1 8.13.2 8.14 8.14.1 8.14.2 8.15 8.15.1 8.15.2 8.16 8.16.1 8.16.2 8.17 8.18 8.18.1 8.18.2 8.18.3 8.19 8.20 8.20.1 8.20.2 9 10 11 11.1 11.2 11.3 12 13 14 15 16 Features ...........................................................26 General description ..........................................26 WatchDog Timer (WDT) .................................. 27 Features ...........................................................27 General description ..........................................27 System tick timer ............................................. 27 Features ...........................................................27 General description ..........................................27 Real-Time Clock (RTC) timer .......................... 28 Features ...........................................................28 General description ..........................................28 Temperature sensor ........................................ 28 Features ...........................................................28 General description ..........................................28 Serial Wire Debug (SWD) ............................... 29 On-chip flash memory ..................................... 29 Reading from flash .......................................... 29 Writing to flash .................................................29 Erasing/programming flash .............................. 30 On-chip SRAM .................................................30 On-chip EEPROM ............................................30 Reading from EEPROM .................................. 30 Writing to EEPROM .........................................30 Limiting values .................................................. 31 Static characteristics ........................................ 32 Dynamic characteristics ...................................35 I/O pins ............................................................ 35 I2C-bus ............................................................ 35 SPI interfaces .................................................. 36 Package outline .................................................38 Abbreviations .................................................... 41 References ......................................................... 42 Revision history ................................................ 42 Legal information .............................................. 43 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. (c) NXP B.V. 2018. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 June 2018 Document identifier: NHS3100