DS1873
________________________________________________________________
Maxim Integrated Products
1
19-4986; Rev 1; 11/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
SFP+ Controller with Analog LDD Interface
General Description
The DS1873 controls and monitors all functions for SFF,
SFP, and SFP+ modules including all SFF-8472 func-
tionality. The DS1873 provides APC loop, modulation
current control, and eye safety functionality. The
DS1873 continuously monitors for high output current,
high bias current, and low and high transmit power to
ensure that laser shutdown for eye safety requirements
are met without adding external components.
Six ADC channels monitor VCC, temperature, and four
external monitor inputs (MON1–MON4) that can be
used to meet all monitoring requirements. MON3 is dif-
ferential with support for common mode to VCC. Two
digital-to-analog (DAC) outputs with temperature-
indexed lookup tables (LUTs) are available for addition-
al monitoring and control functionality.
Applications
SFF, SFP, and SFP+ Transceiver Modules
Features
♦Meets All SFF-8472 Control and Monitoring
Requirements
♦Six Analog Monitor Channels: Temperature, VCC,
MON1–MON4
MON1–MON4 Support Internal and External
Calibration
Scalable Dynamic Range
Internal Direct-to-Digital Temperature Sensor
Alarm and Warning Flags for All Monitored
Channels
♦Four 10-Bit Delta-Sigma Outputs with 36 Entry
Temperature LUTs
Laser Bias Controlled by APC Loop and
Temperature LUT to Compensate for Tracking
Error
Laser Modulation Controlled by 72-Entry
Temperature LUT
Two Additional DACs Controlled by One
72-Entry and One 36-Entry Temperature LUT
♦Digital I/O Pins: Five Inputs, Five Outputs
♦Comprehensive Fault-Measurement System with
Maskable Laser Shutdown Capability
♦Flexible, Two-Level Password Scheme Provides
Three Levels of Security
♦120 Bytes of Password-1 Protected Memory
♦128 Bytes of Password-2 Protected Memory in
Main Device Address
♦256 Additional Bytes Located at A0h Slave
Address
♦I2C-Compatible Interface
♦+2.85V to +3.9V Operating Voltage Range
♦-40°C to +95°C Operating Temperature Range
♦28-Pin TQFN (5mm x 5mm) Package
THIN QFN
(5mm × 5mm × 0.8mm)
TOP VIEW
26
27
25
24
10
9
11
SCL
TXF
LOS
IN1
TXD
12
RSELOUT
BIAS
GND
MON2
GND
VCC
N.C.
12
DAC2
4567
2021 19 17 16 15
VCC
LOSOUT
MON3P
MON4
TXDOUT
RSEL
SDA MOD
3
18
28 8
OUT1 GND
DAC1
23 13 MON3N
N.C.
22 14 MON1
REFIN
DS1873
*EP
+
*EXPOSED PAD.
Pin Configuration
Ordering Information
+
Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*
EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
DS1873T+ -40°C to +95°C 28 TQFN-EP*
DS1873T+T&R -40°C to +95°C 28 TQFN-EP*
DS1873
2 _______________________________________________________________________________________
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
MOD, BIAS, DAC1, DAC2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Analog Quick Trip Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Analog Voltage Monitoring Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Digital Thermometer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Timing Characteristics (Control Loop and Quick Trip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
I2C AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Nonvolatile Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
BIAS DAC/APC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
BIAS and MOD Output Control During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
BIAS and MOD DACs as a Function of Transmit Disable (TXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
APC and Quick-Trip Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Monitors and Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Five Quick-Trip Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Six ADC Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Differential MON3 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Enhanced RSSI Monitoring (Dual-Range Functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Power-On Analog (POA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Delta-Sigma Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
LOS, LOSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
IN1, RSEL, OUT1, RSELOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
TXF, TXD, TXDOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Transmit Fault (TXF) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
TABLE OF CONTENTS
SFP+ Controller with Analog LDD Interface
DS1873
_______________________________________________________________________________________ 3
I2C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
I2C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Shadowed EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Lower Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 01h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 02h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 04h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 05h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 06h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 07h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 08h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Auxiliary A0h Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Lower Memory Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 02h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 04h Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Table 06h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Table 07h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 08h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Auxiliary Memory A0h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
SDA and SCL Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
TABLE OF CONTENTS (continued)
SFP+ Controller with Analog LDD Interface
DS1873
SFP+ Controller with Analog LDD Interface
4 _______________________________________________________________________________________
Figure 1. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 2. TXD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 3. APC Loop and Quick-Trip Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 4. ADC Round-Robin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 5. MON3 Differential Input for High-Side RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 6. RSSI Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 7. RSSI with Crossover Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 8. RSSI with Crossover Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 9. Low-Voltage Hysteresis Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 10. Recommended RC Filter for DAC1/DAC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 11. 3-Bit Delta-Sigma Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 12. MOD, DAC1, and DAC2 Offset LUTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 13. Logic Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 14. Logic Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 15a. TXF Nonlatched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 15b. TXF Latched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 16. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 17. Example I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 18. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 1. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 2. ADC Default Monitor Full-Scale Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 3. MON3 Hysteresis Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 4. MON3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
LIST OF FIGURES
LIST OF TABLES
DS1873
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on MON1–MON4, RSEL,
IN1, LOS, TXF, and TXD Pins
Relative to Ground .................................-0.5V to (VCC + 0.5V)*
Voltage Range on VCC, SDA, SCL, OUT1,
RSELOUT, and LOSOUT Pins
Relative to Ground..............................................-0.5V to +4.2V
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range .........................0°C to +95°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Main Supply Voltage VCC (Note 1) +2.85 +3.9 V
High-Level Input Voltage
(SDA, SCL) VIH:1 0.7 x
VCC
VCC +
0.3 V
Low-Level Input Voltage
(SDA, SCL) VIL:1 -0.3 0.3 x
VCC V
High-Level Input Voltage
(TXD, TXF, RSEL, IN1, LOS) VIH:2 2.0 VCC +
0.3 V
Low-Level Input Voltage
(TXD, TXF, RSEL, IN1, LOS) VIL:2 -0.3 +0.8 V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
*
Subject to not exceeding +4.2V.
RECOMMENDED OPERATING CONDITIONS
(TA= -40°C to +95°C, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
SFP+ Controller with Analog LDD Interface
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current ICC (Notes 1, 2) 2.5 10 mA
Output Leakage
(SDA, OUT1, RSELOUT,
LOSOUT, TXF)
ILO 1 μA
IOL = 4mA 0.4
Low-Level Output Voltage
(SDA, MOD, BIAS, OUT1,
RSELOUT, LOSOUT, TXDOUT,
DAC1, DAC2, TXF)
VOL
IOL = 6mA 0.6
V
High-Level Output Voltage
(MOD, BIAS, DAC1, DAC2,
TXDOUT)
VOH I
OH = 4mA VCC -
0.4 V
TXDOUT Before EEPROM Recall See Figure 13 10 100 nA
MOD, BIAS, DAC1, and DAC2
Before LUT Recall See Figure 12 10 100 nA
Input Leakage Current
(SCL, TXD, LOS, RSEL, IN1) ILI 1 μA
Digital Power-On Reset POD 1.0 2.2 V
Analog Power-On Reset POA 2.0 2.75 V
DS1873
SFP+ Controller with Analog LDD Interface
6 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC Resolution 13 Bits
Input/Supply Accuracy
(MON1–MON4, VCC)ACC At factory setting 0.25 0.50 %FS
Update Rate for Temperature,
MON1–MON4, and VCC tRR 64 75 ms
Input/Supply Offset
(MON1–MON4, VCC)VOS (Note 3) 0 5 LSB
MON1–MON4 2.5
VCC 6.5536 V
Factory Setting
MON3 Fine
(Note 4)
312.5 μV
ANALOG VOLTAGE MONITORING CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MON2, TXP HI, TXP LO Full-
Scale Voltage VAPC 2.5 V
HBIAS LOS Full-Scale Voltage 1.25 V
MON2 Input Resistance 35 50 65 k
Resolution 8 Bits
Error TA = +25°C ±2 %FS
Integral Nonlinearity -1 +1 LSB
Differential Nonlinearity -1 +1 LSB
Temperature Drift -2.5 +2.5 %FS
LOS Offset -5 mV
ANALOG QUICK TRIP CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Main Oscillator Frequency fOSC 5 MHz
Delta-Sigma Input-Clock
Frequency fDS f
OSC/2 MHz
Reference Voltage Input (REFIN) VREFIN Minimum 0.1μF to GND 2 VCC V
Output Range 0 VREFIN V
Output Resolution 10 Bits
Output Impedance RDS 35 100
MOD, BIAS, DAC1, DAC2 ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
DS1873
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output-Enable Time Following POA tINIT (Note 5) 20 ms
Binary Search Time tSEARCH (Note 9) 8 10 BIAS
Samples
SFP+ Controller with Analog LDD Interface
_______________________________________________________________________________________ 7
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TXD Enable tOFF From TXD to BIAS DAC and MOD DAC
disable 5 μs
Recovery from TXD Disable
(Figure 13) tON From TXD to BIAS DAC and MOD DAC
enable 5 μs
Recovery After Power-Up tINIT_DAC From VCC > VCC LO alarm (Note 5) 20 ms
tINITR1 From TXD 131
Fault Reset Time (to TXF = 0) tINITR2 From VCC > VCC LO alarm (Note 5) 161 ms
Fault Assert Time (to TXF = 1) tFAULT After HTXP, LTXP, HBATH, IBIASMAX
(Note 6) 15 μs
LOSOUT Assert Time tLOSS_ON LLOS (Notes 6, 7) 15 μs
LOSOUT Deassert Time tLOSS_OFF HLOS (Notes 6, 8) 15 μs
TIMING CHARACTERISTICS (CONTROL LOOP AND QUICK TRIP)
(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Thermometer Error TERR -40°C to +95°C -3 +3 °C
DIGITAL THERMOMETER CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)
Note 1: All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Note 2: Inputs are at supply rail. Outputs are not loaded.
Note 3: This parameter is guaranteed by design.
Note 4: Full-scale is user programmable.
Note 5: A temperature conversion is completed and the MOD DAC value is recalled from the LUT and VCC has been measured to
be above VCC LO alarm.
Note 6: The sampling time is 1.6µs per cycle. Each input is sampled every 8 cycles.
Note 7: This specification is the time it takes from MON3 voltage falling below the LLOS trip threshold to LOSOUT asserted high.
Note 8: This specification is the time it takes from MON3 voltage rising above the HLOS trip threshold to LOSOUT asserted low.
Note 9: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias output will be within 3% within the time specified by the binary search time. See the
BIAS and MOD Output
Control During Power-Up
section.
Note 10: I2C interface timing shown is for fast mode (400kHz). This device is also backward compatible with I2C standard mode
timing.
Note 11: CB—the total capacitance of one bus line in pF.
Note 12: EEPROM write begins after a STOP condition occurs.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency fSCL (Note 10) 0 400 kHz
Clock Pulse-Width Low tLOW 1.3 μs
Clock Pulse-Width High tHIGH 0.6 μs
Bus-Free Time Between STOP and START
Condition tBUF 1.3 μs
START Hold Time tHD:STA 0.6 μs
START Setup Time tSU:STA 0.6 μs
Data Out Hold Time tHD:DAT 0 0.9 μs
Data In Setup Time tSU:DAT 100 ns
Rise Time of Both SDA and SCL Signals tR (Note 11) 20 + 0.1CB 300 ns
Fall Time of Both SDA and SCL Signals tF (Note 11) 20 + 0.1CB 300 ns
STOP Setup Time tSU:STO 0.6 μs
EEPROM Write Time tWR (Note 12) 20 ms
Capacitive Load for Each Bus Line CB 400 pF
DS1873
SFP+ Controller with Analog LDD Interface
8 _______________________________________________________________________________________
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +3.9V, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
At +25°C 200,000
EEPROM Write Cycles At +85°C 50,000
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.) (See Figure 16.)
DS1873
SFP+ Controller with Analog LDD Interface
_______________________________________________________________________________________
9
Typical Operating Characteristics
(VCC = +2.85V to +3.9V, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS1873 toc01
VCC (V)
SUPPLY CURRENT (mA)
3.753.453.15
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.1
2.85
SDA = SCL = VCC
+95°C
+25°C
-40°C
SUPPLY CURRENT vs. TEMPERATURE
DS1873 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.1
-40 85
SDA = SCL = VCC
VCC = 3.9V VCC = 2.8V
VCC = 3.3V
DAC1 AND DAC2 DNL
DS1873 toc03
DAC1 AND DAC2 POSITION (DEC)
DAC1 AND DAC2 DNL (LSB)
1000800600400200
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0
DAC1 AND DAC2 INL
DS1873 toc04
DAC1 AND DAC2 POSITION (DEC)
DAC1 AND DAC2 INL (LSB)
1000800600400200
-2
-1
0
1
2
3
-3
0
MON1 TO MON4 INL
DS1873 toc05
MON1 TO MON4 INPUT VOLTAGE (V)
MON1 TO MON4 INL (LSB)
2.01.51.00.5
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 2.5
USING FACTORY PROGRAMMED
FULL-SCALE VALUE OF 2.5V
MON1 TO MON4 DNL
DS1873 toc06
MON1 TO MON4 INPUT VOLTAGE (V)
MON1 TO MON4 DNL (LSB)
2.01.51.00.5
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 2.5
USING FACTORY PROGRAMMED
FULL-SCALE VALUE OF 2.5V
DAC SETTLING TIME
(40% TO 60%)
DS1873 toc07
TIME (
μ
s)
DAC OUTPUT
1.0193ms
67.7% OF PEAK
DAC SETTLING TIME
(60% TO 40%)
DS1873 toc08
TIME (
μ
s)
DAC OUTPUT
990.4μs
33.3% OF LOW
DS1873
SFP+ Controller with Analog LDD Interface
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 RSELOUT Open-Drain Rate-Select Output
2 SCL I2C Serial-Clock Input
3 SDA I2C Serial-Data Input/Output
4 TXF Transmit-Fault Input and Output. The output is open drain.
5 LOS Loss-of-Signal Input
6 IN1 Digital Input. General-purpose input with AS1 in SFF-8079 or RS1 in SFF-8431.
7 TXD Transmit-Disable Input
8, 18, 21 GND Ground Connection
9 RSEL Rate-Select Input
10 TXDOUT Transmit-Disable Output
11 MON4 External Monitor Input 4
12, 13 MON3P, MON3N Differential External Monitor Input 3 and LOS LO Quick Trip
14 MON1 External Monitor Input 1 and HBATH Quick Trip
15, 23 N.C. No Connection
16, 26 VCC Power-Supply Input
17 MON2 External Monitor Input 2. Feedback voltage for APC loop and HTXP/LTXP quick trip.
19 MOD MOD DAC, Delta-Sigma Output
20 BIAS BIAS DAC, Delta-Sigma Output
22 REFIN Reference Input for DAC1 and DAC2
24, 25 DAC1, DAC2 Delta-Sigma Output 1/2
27 LOSOUT Open-Drain Receive Loss-of-Signal Output
28 OUT1
Open-Drain Digital Output. General-purpose output with AS1 output in SFF-8079 or RS1 output
in SFF-8431.
— EP Exposed Pad (Connect to GND)
Typical Operating Characteristics (continued)
(VCC = +2.85V to +3.9V, TA= +25°C, unless otherwise noted.)
DAC OUTPUT RIPPLE AT 0001h
DS1873 toc09
TIME (100
μ
s/div)
0.68mV
FILTER
OUTPUT
DAC2
OUTPUT
DAC POSITION = 0001h
3V/div
DAC OUTPUT RIPPLE AT 3FFFh
DS1873 toc10
TIME (100
μ
s/div)
0.1mV
DAC2
OUTPUT
DAC POSITION = 3FFFh
3V/div
FILTER
OUTPUT
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 11
Block Diagram
ANALOG MUX
MAIN MEMORY
EEPROM/SRAM
ADC CONFIGURATION/RESULTS,
SYSTEM STATUS/CONTROL BITS,
ALARMS/WARNINGS,
LOOKUP TABLES,
USER MEMORY
I2C
INTERFACE
TEMPERATURE
SENSOR
APC
INTEGRATOR
LOGIC
CONTROL
POWER-ON
ANALOG
INTERRUPT
13-BIT
ADC
EEPROM
256 BYTES
AT A0h
SDA
SCL
VCC
VCC
VCC
MON1
MON2
MON4
TXD
MON3P
MON3N
LOGIC
CONTROL
DAC1
10 BITS
DAC2
10 BITS
8-BIT
QTs
DAC1
DAC2
MOD DAC
10 BITS MOD
BIAS DAC
10 BITS BIAS
TXF
REFIN
TXDOUT
RSELOUT
OUT1
LOSOUT
RSEL
IN1
LOS
GND
DS1873
VCC
DS1873
SFP+ Controller with Analog LDD Interface
12 ______________________________________________________________________________________
LOS
TXF
TXD
TXDOUT
DISABLE
BIAS MON
LOS
LOSOUT
TX_FAULT
SDA
SCL
MODE_DEF2 (SDA)
LOS
MODE_DEF1 (SCL)
TX_DISABLE
MOD
DAC
BIAS
DAC
LDD
EEPROM
QUICK
TRIP
LOS
ADC
I2C
DS1873
MON1
MON2
MON3
RMON
100Ω
+3.3V
RBD
ROSA
TOSA
Detailed Description
The DS1873 integrates the control and monitoring func-
tionality required to implement an SFP or SFP+ system.
Key components of the DS1873 are shown in the
Block
Diagram
and described in subsequent sections.
BIAS DAC/APC Control
The DS1873 controls its laser bias current using its
BIAS DAC and the APC loop. The APC loop’s feedback
to the DS1873 is the monitor diode (MON2) current,
which is converted to a voltage using an external resis-
tor. The feedback is sampled by a comparator and
compared to a digital set-point value. The output of the
comparator has three states: up, down, or no-opera-
tion. The no-operation state prevents the output from
excessive toggling once steady state is reached. As
long as the comparator output is in either the up or
down states, the bias is adjusted by incrementing and
decrementing the BIAS DAC setting.
The DS1873 has an LUT to allow the APC set point to
change as a function of temperature to compensate for
tracking error (TE). The TE LUT has 36 entries that
determine the APC setting in 4°C windows between
-40°C to +100°C.
Typical Operating Circuit
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 13
BIAS and MOD Output Control
During Power-Up
On power-up, the DS1873 sets the MOD and BIAS
DACs to 0. After a temperature conversion is complet-
ed and if the VCC LO alarm is enabled, an additional
VCC conversion above the customer-defined VCC LO
alarm level is required before the MOD DAC is updated
with the value determined by the temperature conver-
sion and the modulation LUT.
When the MOD DAC is set, the BIAS DAC is set to a
value equal to ISTEP (see Figure 1). The startup algo-
rithm checks if this bias current causes a feedback
voltage above the APC set point, and if not, it continues
increasing the BIAS DAC by ISTEP until the APC set-
point is exceeded. When the APC set point is exceed-
ed, the device begins a binary search to quickly reach
the bias current corresponding to the proper power
level. After the binary search is completed, the APC
integrator is enabled and single LSB steps are used to
tightly control the average power.
The TXP HI, TXP LO, HBAL, and BIAS MAX QT alarms
are masked until the binary search is completed.
However, the BIAS MAX alarm is monitored during this
time to prevent the BIAS DAC from exceeding IBIASMAX.
During the bias current initialization, the BIAS DAC is
not allowed to exceed IBIASMAX. If this occurs during
the ISTEP sequence, then the binary search routine is
Table 1. Acronyms
ACRONYM DEFINITION
ADC Analog-to-Digital Converter
AGC Automatic Gain Control
APC Automatic Power Control
APD Avalanche Photodiode
ATB Alarm Trap Bytes
BM Burst Mode
DAC Digital-to-Analog Converter
LOS Loss of Signal
LUT Lookup Table
NV Nonvolatile
QT Quick Trip
TE Tracking Error
TIA Transimpedance Amplifier
ROSA Receiver Optical Subassembly
SEE Shadowed EEPROM
SFF Small Form Factor
SFF-8472 Document Defining Register Map of SFPs
and SFFs
SFP Small Form Factor Pluggable
SFP+ Enhanced SFP
TOSA Transmit Optical Subassembly
TXP Transmit Power
12345678910111213
VPOA
MOD DAC
BIAS DAC
VCC
BIAS SAMPLE
tINIT
tSEARCH
BINARY SEARCH
APC INTEGRATOR ON
4x ISTEP
3x ISTEP
2x ISTEP
ISTEP
Figure 1. Power-Up Timing
DS1873
SFP+ Controller with Analog LDD Interface
14 ______________________________________________________________________________________
enabled. If IBIASMAX is exceeded during the binary
search, the next smaller step is activated. ISTEP or
binary increments that would cause the BIAS DAC to
exceed IBIASMAX are not taken. Masking the alarms
until the completion of the binary search prevents false
positive alarms during startup.
ISTEP is programmed by the customer using Table
02h, Register BBh. ISTEP should be programmed to
the maximum safe increase that is allowable during
startup. If this value is programmed too low, the
DS1873 still operates, but it could take significantly
longer for the algorithm to converge and hence to con-
trol the average power.
If a fault is detected, and TXD is toggled to reenable
the outputs, the DS1873 powers up following a similar
sequence to an initial power-up. The only difference is
that the DS1873 already has determined the present
temperature, so the tINIT time is not required for the
DS1873 to recall the APC and MOD set points from
EEPROM.
BIAS and MOD DACs as a Function of
Transmit Disable (TXD)
If TXD is asserted (logic 1) during normal operation, the
outputs are disabled within tOFF. When TXD is
deasserted (logic 0), the DS1873 sets the MOD DAC
register with the value associated with the present tem-
perature, and initializes the BIAS DAC using the same
search algorithm as done at startup. When asserted,
soft TXD (TXDC) (Lower Memory, Register 6Eh) would
allow a software control identical to the TXD pin (see
Figure 2).
APC and Quick-Trip Timing
As shown in Figure 3, the DS1873’s input comparator is
shared between the APC control loop and the quick-trip
alarms (TXP HI, TXP LO, LOS LO, and BIAS HI). The
comparator polls the alarms in a multiplexed sequence.
Five of every eight comparator readings are used for
APC loop bias-current control. The other three updates
are used to check the HTXP/LTXP (monitor diode volt-
age), the HBATH (MON1), and LOS (MON3) signals
against the internal APC, BIAS, and MON3 reference,
respectively. If the last APC comparison was higher
than the APC set point, it makes an HTXP comparison,
and if it is lower, it makes an LTXP comparison.
Depending on the results of the comparison, the corre-
sponding alarms and warnings (TXP HI, TXP LO) are
asserted or deasserted.
The DS1873 has a programmable comparator sample
time based on an internally generated clock to facilitate
a wide variety of external filtering options and time
delays. The UPDATE RATE register (Table 02h,
Register 88h) determines the sampling time. Samples
occur at a regular interval, tREP, which is set at 1.6µs.
Table 2 shows the sample rate options available. Any
quick-trip alarm that is detected by default remains
active until a subsequent comparator sample shows
the condition no longer exists. A second bias current
monitor (BIAS MAX) compares the BIAS DAC’s code to
a digital value stored in the IBIASMAX register. This
comparison is made at every bias current update to
ensure that a high-bias current is quickly detected.
The quick-trip comparator uses a 1.6μs window to sam-
ple each input. After an APC comparison that requires
APC QUICK-TRIP SAMPLE TIMES HBIAS
SAMPLE
HBIAS
SAMPLE
LOS
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
HTXP/LTXP
SAMPLE
tREP
Figure 3. APC Loop and Quick-Trip Sample Timing
tOFF
tOFF
tON
tON
TXD
BIAS DAC
MOD DAC SETTING
Figure 2. TXD Timing
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 15
an update to the BIAS DAC, a settling time (as calculat-
ed below) is required to allow for the feedback on BMD
(MON2) to stabilize. This time is dependent on the time
constant of the filter pole used for the delta-to-sigma
BIAS output. During the timing of the settling rate, com-
parisons of APC comparisons of BMD are ignored until
32 sample periods (tREP) have passed.
SettlingTime = 51.2µs x (APC_SR[3:0] + 1)
Monitors and Fault Detection
Monitors
Monitoring functions on the DS1873 include five quick-
trip comparators and six ADC channels. This monitor-
ing combined with the alarm enables (Table 01h/05h)
determines when/if the DS1873 turns off the MOD and
BIAS DACs and triggers the TXF and TXDOUT outputs.
All the monitoring levels and interrupt masks are user
programmable.
Five Quick-Trip Monitors and Alarms
Five quick-trip monitors are provided to detect potential
laser safety issues and LOS status. These monitor the
following:
1) High Bias Current (HBATH)
2) Low Transmit Power (LTXP)
3) High Transmit Power (HTXP)
4) Max Output Current (IBIASMAX)
5) Loss-of-Signal (LOS LO)
The high-transmit and low-transmit power quick-trip
registers (HTXP and LTXP) set the thresholds used to
compare against the MON2 voltage to determine if the
transmit power is within specification. The HBATH
quick trip compares the MON1 input (generally from the
laser driver’s bias monitor output) against its threshold
setting to determine if the present bias current is above
specification. The BIAS MAX quick trip determines if the
BIAS DAC is above specification (IBIASMAX). When the
new BIAS DAC value is calculated, it is compared
against the IBIASMAX register. The BIAS DAC is not
allowed to exceed the value set in the IBIASMAX regis-
ter. When the DS1873 detects that the bias is at the
limit, it sets the BIASMAX status bit and holds the BIAS
DAC setting at the IBIASMAX level. The bias and power
quick trips are routed to the TXF through interrupt
masks to allow combinations of these alarms to be
used to trigger these outputs. The user can program up
to eight different temperature-indexed threshold levels
for MON1 (Table 02h, Register D1h). The LOS LO quick
trip compares the MON3 input against its threshold set-
ting to determine if the present received power is below
the specification. The LOS LO quick trip can be used to
set the LOSOUT pin.
Six ADC Monitors and Alarms
The ADC monitors six channels that measure tempera-
ture (internal temp sensor), VCC, and MON1–MON4
using an analog multiplexer to measure them round
robin with a single ADC (see the
ADC Timing
section).
The five voltage channels have a customer-programma-
ble full-scale range and all channels have a customer-
programmable offset value that is factory programmed
to default value (see Table 2). Additionally,
MON1–MON4 can right-shift results by up to 7 bits
before the results are compared to alarm thresholds or
read over the I2C bus. This allows customers with speci-
fied ADC ranges to calibrate the ADC full scale to a fac-
tor of 1/2nof their specified range to measure small
signals. The DS1873 can then right-shift the results by n
bits to maintain the bit weight of their specification (see
the
Right-Shifting ADC Result
and
Enhanced RSSI
Monitoring (Dual-Range Functionality)
sections).
The ADC results (after right-shifting, if used) are com-
pared to the alarm and warning thresholds after each
conversion, and the corresponding alarms are set,
which can be used to trigger the TXF output. These
ADC thresholds are user programmable, as are the
masking registers that can be used to prevent the
alarms from triggering the TXF output.
ADC Timing
There are six analog channels that are digitized in a
round-robin fashion in the order shown in Figure 4. The
total time required to convert all six channels is tRR (see
the
Analog Voltage Monitoring Characteristics
for
details).
Right-Shifting ADC Result
If the weighting of the ADC digital reading must con-
form to a predetermined full-scale (PFS) value defined
by a standard’s specification (e.g., SFF-8472), then
right-shifting can be used to adjust the PFS analog
measurement range while maintaining the weighting of
Table 2. ADC Default Monitor Full-Scale
Ranges
SIGNAL +FS
SIGNAL
+FS
hex
-FS
SIGNAL
-FS
hex
Temperature (°C) 127.996 7FFF -128 8000
VCC (V) 6.5528 FFF8 0 0000
MON1–MON4 (V) 2.4997 FFF8 0 0000
DS1873
SFP+ Controller with Analog LDD Interface
16 ______________________________________________________________________________________
TEMP VCC MON1 MON2 MON3 MON4 TEMP
ONE ROUND-ROBIN ADC CYCLE
tRR
NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC
IS ABOVE THE VCC ALARM LOW THRESHOLD.
the ADC results. The DS1873’s range is wide enough to
cover all requirements; when the maximum input value
is ≤1/2 of the FS value, right-shifting can be used to
obtain greater accuracy. For instance, the maximum
voltage might be 1/8 the specified PFS value, so only
1/8 the converter’s range is effective over this range.
An alternative is to calibrate the ADC’s full-scale range
to 1/8 the readable PFS value and use a right-shift
value of 3. With this implementation, the resolution of
the measurement is increased by a factor of 8, and
because the result is digitally divided by 8 by right-
shifting, the bit weight of the measurement still meets
the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried out
based on the contents of right-shift control registers
(Table 02h, Registers 8Dh–8Fh) in EEPROM. Four ana-
log channels, MON1–MON4, each have 3 bits allocated
to set the number of right-shifts. Up to 7 right-shift oper-
ations are allowed and are executed as a part of every
conversion before the results are compared to the high-
alarm and low-alarm levels, or loaded into their corre-
sponding measurement registers (Lower Memory,
Registers 64h–6Bh). This is true during the setup of
internal calibration as well as during subsequent data
conversions.
Differential MON3 Input
The DS1873 offers a fully differential input for MON3.
This enables high-side monitoring of RSSI, as shown in
Figure 5. This reduces board complexity by eliminating
the need for a high-side differential amplifier or a cur-
rent mirror.
Enhanced RSSI Monitoring (Dual-Range
Functionality)
The DS1873 offers a feature to improve the accuracy
and range of MON3, which is most commonly used for
monitoring RSSI. The accuracy of the RSSI measure-
ments is increased at the small cost of reduced range
(of input signal swing). The DS1873 eliminates this
trade-off by offering “dual range” calibration on the
MON3 channel (see Figure 5). This feature enables
right-shifting (along with its gain and offset settings)
when the input signal is below a set threshold (within the
range that benefits using right-shifting) and then automat-
ically disables right-shifting (recalling different gain and
offset settings) when the input signal exceeds the thresh-
old. Also, to prevent “chattering,” hysteresis prevents
excessive switching between modes in addition to ensur-
ing that continuity is maintained. Dual-range operation is
enabled by default (factory programmed in EEPROM).
However, it can easily be disabled through the RSSI_FC
and RSSI_FF bits, which are described in the
Register
Descriptions
section. When dual-range operation is dis-
abled, MON3 operates identically to the other MON
channels, although featuring a differential input.
Dual-range functionality consists of two modes of opera-
tion: fine mode and coarse mode. Each mode is calibrat-
ed for a unique transfer function, hence the term, dual
range. Table 4 highlights the registers related to MON3.
Fine mode is equivalent to the other MON channels. Fine
mode is calibrated using the gain, offset, and right-shift-
ing registers at locations shown in Table 4 and is ideal
for relatively small analog input voltages. Coarse mode is
automatically switched to when the input exceeds a
threshold (to be discussed in a subsequent paragraph).
Coarse mode is calibrated using different gain and offset
registers, but lacks right-shifting (since coarse mode is
only used on large input signals). The gain and offset
registers for coarse mode are also shown in Table 4.
DS1873
MON3P
MON3N ADC
100Ω
ROSA
VCC
Figure 5. MON3 Differential Input for High-Side RSSI
Figure 4. ADC Round-Robin Timing
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 17
Additional information for each of the registers can be
found in the
Register Descriptions
section.
Dual-range operation is transparent to the end user.
The results of MON3 analog-to-digital conversions are
still stored/reported in the same memory locations
(68h–69h, Lower Memory) regardless of whether the
conversion was performed in fine mode or coarse
mode. The only way to tell which mode generated the
digital result is by reading the RSSIR bit.
When the DS1873 is powered up, analog-to-digital con-
versions begin in a round-robin fashion. Every MON3
timeslice begins with a fine mode analog-to-digital con-
version (using fine mode’s gain, offset, and right-shifting
settings). See the flowchart in Figure 6 for more details.
Then, depending on whether the last MON3 timeslice
resulted in a coarse-mode conversion and also depend-
ing on the value of the current fine conversion, decisions
are made whether to use the current fine-mode conver-
sion result or to make an additional conversion (within
the same MON3 timeslice), using coarse mode (using
coarse mode’s gain and offset settings and no right-
shifting) and reporting the coarse-mode result. The flow-
chart in Figure 6 also illustrates how hysteresis is
implemented. The fine-mode conversion is compared to
one of two thresholds. The actual threshold values are a
function of the number of right-shifts being used. With
the use of right-shifting, the fine mode full-scale is pro-
grammed to (1/2nth) of the coarse mode full-scale. The
DS1873 now auto ranges to choose the range that gives
the best resolution for the measurement. Hysteresis is
applied to eliminate chatter when the input resides at
the boundary of the two ranges. See Figure 6 for details.
Table 3 shows the threshold values for each possible
number of right-shifts.
Table 4. MON3 Configuration Registers
REGISTER FINE MODE COARSE MODE
GAIN 98h–99h, Table 02h 9Ch–9Dh, Table 02h
OFFSET A8h–A9h, Table 02h ACh–ADh, Table 02h
RIGHT-SHIFT08Fh, Table 02h —
CNFGC 8Bh, Table 02h
UPDATE
(RSSIR BIT) 6Fh, Lower Memory
MON3 VALUE 68h–69h, Lower Memory
NUMBER OF
RIGHT-SHIFTS
FINE MODE
MAX (hex)
COARSE MODE
MIN* (hex)
0 FFF8 F000
1 7FFC 7800
2 3FFE 3C00
3 1FFF 1E00
4 0FFF 0F00
5 07FF 0780
6 03FF 03C0
7 01FF 01E0
MON3
TIMESLICE
END OF MON3
TIMESLICE
PERFORM FINE-
MODE CONVERSION
REPORT FINE
CONVERSION RESULT
REPORT COARSE
CONVERSION RESULT
DID PRIOR MON3
TIMESLICE RESULT IN A
COARSE CONVERSION?
(LAST RSSIR = 1?)
LAST RSSIR = 0 LAST RSSIR = 1
WAS CURRENT FINE-
MODE CONVERSION
≥ 93.75% OF FS?
PERFORM COARSE-
MODE CONVERSION
DID CURRENT FINE-
MODE CONVERSION
REACH MAX?
N
Y
YY
N
N
Figure 6. RSSI Flowchart
Table 3. MON3 Hysteresis Threshold
Values
*
This is the minimum reported coarse-mode conversion.
DS1873
SFP+ Controller with Analog LDD Interface
18 ______________________________________________________________________________________
The RSSI_FF and RSSI_FC bits are used to force fine-
mode or coarse-mode conversions, or to disable the
dual-range functionality. Dual-range functionality is
enabled by default (both RSSI_FC and RSSI_FF are
factory programmed to 0 in EEPROM). It can be dis-
abled by setting RSSI_FC to 0 and RSSI_FF to 1. These
bits are also useful when calibrating MON3. For addi-
tional information, see Figure 18. The dual-range cali-
bration can operate in two modes: crossover enabled
and crossover disabled.
•Crossover Enabled: For systems with nonlinear
relationships between the ADC input and the desired
ADC result, the mode should be set to crossover
enabled. The RSSI measurement of an APD receiver
is one such application. Using the crossover-
enabled mode allows a piecewise linear approxima-
tion of the nonlinear response of the APD’s gain fac-
tor. The crossover point is the point between fine and
coarse points. The ADC result transitions between
the fine and coarse ranges with no hysteresis. Right-
shifting, slope adjustment, and offset are config-
urable for both the fine and coarse ranges. See
Figure 7.
•Crossover Disabled: The crossover-disabled mode
is intended for systems with a linear relationship
between the MON3 input and the desired ADC
result. Hysteresis allows for a nonjittery response
when the input is at the crossover boundary of the
fine and coarse ADC. In a nonlinear system, the hys-
teresis could cause significant errors in the ADC
result. See Figure 8.
RSSI RESULT
FINE FULL-SCALE RESPONSE
COARSE FULL-SCALE RESPONSE
FINE RIGHT-SHIFT = 3
MON3 INPUT
FINE COARSE
HYSTERESIS
Figure 8. RSSI with Crossover Disabled
CROSSOVER POINT
RSSI RESULT
IDEAL RESPONSE MON3 INPUT
Figure 7. RSSI with Crossover Enabled
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 19
VPOA
VPOD
VCC
SEE RECALLED VALUE RECALLED VALUE
PRECHARGED
TO 0
PRECHARGED
TO 0
PRECHARGED TO 0
SEE RECALL SEE RECALL
Figure 9. Low-Voltage Hysteresis Example
Low-Voltage Operation
The DS1873 contains two power-on reset (POR) levels.
The lower level is a digital POR (POD) and the higher
level is an analog POR (POA). At startup, before the
supply voltage rises above POA, the outputs are dis-
abled, all SRAM locations are set to their defaults,
shadowed EEPROM (SEE) locations are zero, and all
analog circuitry is disabled. When VCC reaches POA,
the SEE is recalled, and the analog circuitry is enabled.
While VCC remains above POA, the device is in its nor-
mal operating state, and it responds based on its non-
volatile configuration. If during operation VCC falls
below POA, but is still above POD, then the SRAM
retains the SEE settings from the first SEE recall, but the
device analog is shut down and the outputs disabled. If
the supply voltage recovers back above POA, then the
device immediately resumes normal operation. If the
supply voltage falls below POD, then the device SRAM
is placed in its default state and another SEE recall is
required to reload the nonvolatile settings. The EEP-
ROM recall occurs the next time VCC exceeds POA.
Figure 9 shows the sequence of events as the voltage
varies.
Any time VCC is above POD, the I2C interface can be
used to determine if VCC is below the POA level. This is
accomplished by checking the RDYB bit in the STATUS
(Lower Memory, Register 6Eh) byte. RDYB is set when
VCC is below POA; when VCC rises above POA, RDYB
is timed (within 500µs) to go to 0, at which point the
part is fully functional.
For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
until VCC exceeds POA, allowing the device address to
be recalled from the EEPROM.
Power-On Analog (POA)
POA holds the DS1873 in reset until VCC is at a suitable
level (VCC > POA) for the device to accurately measure
with its ADC and compare analog signals with its quick-
trip monitors. Because VCC cannot be measured by the
ADC when VCC is less than POA, POA also asserts the
VCC LO alarm, which is cleared by a VCC ADC conver-
sion greater than the customer-programmable VCC
alarm LO ADC limit. This allows a programmable limit to
ensure that the headroom requirements of the trans-
ceiver are satisfied during a slow power-up. The TXF
output does not latch until there is a conversion above
VCC low limit. The POA alarm is nonmaskable. The TXF
output is asserted when VCC is below POA. See the
Low-Voltage Operation
section for more information.
Delta-Sigma Outputs
Four delta-sigma outputs are provided: MOD DAC,
BIAS DAC, DAC1, and DAC2. With the addition of an
external RC filter, these outputs provide 10-bit resolu-
tion analog outputs with the full-scale range set by the
input REFIN. Each output is either manually controlled
or controlled using a temperature-indexed LUT, or in
the case of the BIAS DAC, controlled by the APC loop.
A delta-sigma is a digital output using pulse-density
modulation. It provides much lower output ripple than a
DS1873
SFP+ Controller with Analog LDD Interface
20 ______________________________________________________________________________________
standard digital PWM output given the same clock rate
and filter components. Before tINIT, the DAC outputs
are high impedance.
The external RC filter components are chosen based
on ripple requirements, output load, delta-sigma fre-
quency, and desired response time. A recommended
filter is shown in Figure 10.
The DS1873’s delta-sigma outputs are 10 bits. For illus-
trative purposes, a 3-bit example is provided. Each
possible output of this 3-bit delta-sigma DAC is given in
Figure 11.
In LUT mode, MOD, DAC1, and DAC2 are each con-
trolled by an LUT with high-temperature resolution and
an OFFSET LUT with lower temperature resolution. The
MOD and DAC1 high-resolution LUTs each have 2°C
resolution. The DAC2 high-resolution LUT has 4°C reso-
lution. The OFFSET LUTs are located in the upper eight
registers (F8h–FFh) of the table containing each high-
resolution LUT. MOD DAC, DAC1 VALUE, and DAC2
VALUE are determined as follows:
MOD DAC = MOD LUT + 4 x (MOD OFFSET LUT)
DAC1 VALUE = DAC1 LUT + 4 x (DAC1 OFFSET LUT)
DAC2 VALUE = DAC1 LUT + 4 x (DAC1 OFFSET LUT)
Example calculation for MOD DAC:
Assumptions:
1) Temperature is 43°C.
2) Table 04h (MOD OFFSET LUT), Register FCh = 2Ah.
3) Table 04h (MOD LUT), Register A9h = 7Bh.
Because the temperature is 43°C, the MOD LUT index
is A9h and the MOD OFFSET LUT index is FCh.
MOD DAC = 7Bh + 4 x 2Ah = 123h = 291
When temperature controlled, the DACs are updated
after each temperature conversion.
The reference input, REFIN, is the supply voltage for all
four DACs. The voltage connected to REFIN and its
decoupling must be able to support the edge rate
requirements of the delta-sigma outputs.
DS1873
DAC
3.24kΩ3.24kΩ
0.01μF 0.01μF
OUTPUT
1
2
3
4
5
6
7
0
Figure 11. 3-Bit Delta-Sigma Example
Figure 10. Recommended RC Filter for DAC1/DAC2
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 21
MOD, DAC1, AND DAC2 OFFSET LUTs (04h, 07h, AND 08h)
EIGHT REGISTERS PER DAC
0
255
511
DELTA-SIGMA MOD, DAC1, AND DAC2
767
1023
EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN
0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE
AND NEGATVE TEMPCO.
DAC
LUT
BITS
7:0
F8h DAC
LUT
BITS
7:0
F9h DAC
LUT
BITS
7:0
FAh DAC
LUT
BITS
7:0
FBh DAC
LUT
BITS
7:0
FCh DAC
LUT
BITS
7:0
FDh
DAC
LUT
BITS
7:0
FEh
DAC
LUT
BITS
7:0
FFh
0
255
511
-40°C-8°C+8°C +24°C +40°C +56°C +70°C +88°C +104°C
DELTA-SIGMA MOD, DAC1, AND DAC2
767
1023
EACH OFFSET REGISTER CAN BE INDEPENDENTLY
SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS
EXAMPLE ILLUSTRATES POSITIVE TEMPCO.
DAC
LUT
BITS
7:0
F8h
DAC
LUT
BITS
7:0
F9h DAC
LUT
BITS
7:0
FAh DAC
LUT
BITS
7:0
FBh DAC
LUT
BITS
7:0
FCh
DAC
LUT
BITS
7:0
FDh
DAC
LUT
BITS
7:0
FEh
DAC
LUT
BITS
7:0
FFh
MOD, DAC1, AND DAC2 OFFSET LUTs (04h, 07h, AND 08h)
EIGHT REGISTERS PER DAC
-40°C-8°C+8°C +24°C +40°C +56°C +70°C +88°C +104°C
Figure 12. MOD, DAC1, and DAC2 Offset LUTs
Digital I/O Pins
Five digital input and five digital output pins are provid-
ed for monitoring and control.
LOS, LOSOUT
By default (LOSC = 1, Table 02h, Register 89h), the
LOS pin is used to convert a standard comparator out-
put for loss of signal (LOS) to an open-collector output.
This means the mux shown in the
Block Diagram
by
default selects the LOS pin as the source for the
LOSOUT output transistor. The output of the mux can
be read in the STATUS byte (Lower Memory,
Register 6Eh) as the RXL bit. The RXL signal can be
inverted (INV LOS = 1) before driving the open-drain
output transistor using the XOR gate provided. Setting
LOSC = 0 configures the mux to be controlled by LOS
LO, which is driven by the output of the LOS quick trip
(Table 02h, Registers BEh and BFh). The mux setting
(stored in EEPROM) does not take effect until VCC >
POA, allowing the EEPROM to recall.
IN1, RSEL, OUT1, RSELOUT
The digital input IN1 and RSEL pins primarily serve to
meet the rate-select requirements of SFP and SFP+.
They also serve as general-purpose inputs. OUT1 and
RSELOUT are driven by a combination of the IN1,
RSEL, and logic dictated by control registers in the
EEPROM (Figure 14). The levels of IN1 and RSEL can
be read using the STATUS register (Lower Memory,
Register 6Eh). The open-drain output OUT1 can be
controlled and/or inverted using the CNFGB register
(Table 02h, Register 8Ah). The open-drain RSELOUT
output is software-controlled and/or inverted through
the STATUS register and CNFGA register (Table 02h,
Register 89h). External pullup resistors must be provid-
ed on OUT1 and RSELOUT to realize high logic levels.
DS1873
SFP+ Controller with Analog LDD Interface
22 ______________________________________________________________________________________
TXF, TXD, TXDOUT
TXDOUT is generated from a combination of TXF, TXD,
and the internal signal FETG. A software control identical
to TXD is available (TXDC, Lower Memory, Register
6Eh). A TXD pulse is internally extended (TXDEXT) by
time tINITR1 to inhibit the latching of low alarms and
warnings related to the APC loop to allow for the loop to
stabilize. The nonlatching alarms and warnings are TXP
LO, LOS LO, and MON1–MON4 LO alarms and warn-
ings. In addition, TXP LO is disabled from creating FETG.
TXF is both an input and an output (Figure 13). See the
Transmit Fault (TXF) Output
section for a detailed expla-
nation of TXF. Figure 13 shows that the same signals and
faults can also be used to generate the internal signal
FETG (Table 01h/05h, Registers FAh and FBh). FETG is
used to send a fast “turn-off” command to the laser dri-
ver. The intended use is a direct connection to the laser
driver’s TXD input if this is desired. When VCC < POA,
TXDOUT is high impedance.
INVOUT1
IN1C
IN1
IN1S OUT1
INV LOSLOSC
MUX
LOSOUT
RSELOUT
RSELC
RSEL
LOS
LOS LO
RSELS
RXL
= PINS
Figure 14. Logic Diagram 2
C
C
D
Q
Q
S
R
OUT IN
TXDS
RPU
TXF
SET BIAS DAC AND
MOD DAC TO 0
TXD
MINT
HBAL FLAG
TXP LO FLAG
TXP HI FLAG
BIAS MAX FLAG
TXP HI FLAG
TXP HI ENABLE
BIAS MAX
BIAS MAX ENABLE
HBAL FLAG
HBAL ENABLE
TXP LO FLAG
TXP LO ENABLE
TXDEXT
TXDC
= PINS
VCC
TXD
TXF
TXDOUT
TXDIO
TXDFG
FETG
TXDFLT
FAULT RESET TIMER
(130ms)
IN
OUT
POWER-ON
RESET
Figure 13. Logic Diagram 1
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 23
Transmit Fault (TXF) Output
TXF can be triggered by all alarms, warnings, and
quick trips (Figure 13). The six ADC alarms, warnings,
and the LOS quick trips require enabling (Table
01h/05h, Registers F8h and FDh). See Figures 15a and
15b for nonlatched and latched operation. Latching of
the alarms is controlled by the CNFGB and CNFGC
registers (Table 02h, Registers 8Ah–8Bh).
Die Identification
The DS1873 has an ID hardcoded in its die. Two regis-
ters (Table 02h, Registers CEh–CFh) are assigned for
this feature. The CEh register reads 73h to identify the
part as the DS1873, while the CFh register reads the
current device version.
I2C Communication
I2C Definitions
The following terminology is commonly used to
describe I2C data transfers.
Master device: The master device controls the
slave devices on the bus. The master device gen-
erates SCL clock pulses and START and STOP
conditions.
Slave devices: Slave devices send and receive
data at the master’s request.
Bus idle or not busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states.
START condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 16 for applicable timing.
STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 16 for applicable timing.
Repeated START condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one.
Repeated STARTs are commonly used during read
operations to identify a specific memory address to
begin a data transfer. A repeated START condition
is issued identically to a normal START condition.
See Figure 16 for applicable timing.
DETECTION OF TXF FAULT
TXD OR TXF RESET
TXF
Figure 15b. TXF Latched Operation
DETECTION OF TXF FAULT
TXF
Figure 15a. TXF Nonlatched Operation
DS1873
SFP+ Controller with Analog LDD Interface
24 ______________________________________________________________________________________
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
SDA
STOP START REPEATED
START
tBUF
tHD:STA
tHD:DAT tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
Figure 16. I2C Timing
Bit write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL
plus the setup and hold time requirements (Figure
16). Data is shifted into the device during the rising
edge of the SCL.
Bit read: At the end a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 16) before the next rising edge
of SCL during a bit read. The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse and the data bit is valid at the rising edge
of the current SCL pulse. Remember that the master
generates all SCL clock pulses, including when it is
reading bits from the slave.
Acknowledgement (ACK and NACK): An acknowl-
edgement (ACK) or not acknowledge (NACK) is
always the ninth bit transmitted during a byte trans-
fer. The device receiving data (the master during a
read or the slave during a write operation) performs
an ACK by transmitting a zero during the ninth bit. A
device performs a NACK by transmitting a one dur-
ing the 9th bit. Timing (Figure 16) for the ACK and
NACK is identical to all other bit writes. An ACK is
the acknowledgment that the device is properly
receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
Byte write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement
from the slave to the master. The 8 bits transmitted
by the master are done according to the bit-write
definition and the acknowledgement is read using
the bit-read definition.
Byte read: A byte read is an 8-bit information trans-
fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit-read definition, and the master
transmits an ACK using the bit-write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave returns control of SDA to the master.
Slave address byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/Wbit in the least significant bit.
The DS1873 responds to two slave addresses. The
auxiliary memory always responds to a fixed I2C
slave address, A0h. The Lower Memory and Tables
00h–08h respond to I2C slave addresses that can
be configured to any value between 00h–FEh using
the DEVICE ADDRESS byte (Table 02h, Register
8Ch). The user also must set the ASEL bit (Table
02h, Register 89h) for this address to be active. By
writing the correct slave address with R/W= 0, the
master indicates it will write data to the slave. If R/W
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 25
= 1, the master reads data from the slave. If an
incorrect slave address is written, the DS1873
assumes the master is communicating with another
I2C device and ignores the communications until the
next START condition is sent. If the main device’s
slave address is programmed to be A0h, access to
the auxiliary memory is disabled.
Memory address: During an I2C write operation to
the DS1873, the master must transmit a memory
address to identify the memory location where the
slave is to store the data. The memory address is
always the second byte transmitted during a write
operation following the slave address byte.
I2C Protocol
Writing a single byte to a slave: The master must
generate a START condition, write the slave address
byte (R/W= 0), write the memory address, write the
byte of data, and generate a STOP condition.
Remember the master must read the slave’s
acknowledgement during all byte-write operations.
Writing multiple bytes to a slave: To write multiple
bytes to a slave, the master generates a START con-
dition, writes the slave address byte (R/W= 0),
writes the memory address, writes up to 8 data
bytes, and generates a STOP condition. The
DS1873 writes 1 to 8 bytes (one page or row) with a
single write transaction. This is internally controlled
by an address counter that allows data to be written
to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one 8-byte page
(one row of the memory map). Attempts to write to
additional pages of memory without sending a STOP
condition between pages results in the address
counter wrapping around to the beginning of the
present row.
For example, a 3-byte write starts at address 06h
and writes three data bytes (11h, 22h, and 33h) to
three “consecutive” addresses. The result is that
addresses 06h and 07h would contain 11h and 22h,
respectively, and the third data byte, 33h, would be
written to address 00h.
To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM
write time to elapse. Then the master can generate a
new START condition and write the slave address
START
START STOP
SLAVE
ACK
SLAVE
ACK
STOP
SINGLE-BYTE WRITE
-WRITE 00h TO REGISTER BAh
TWO-BYTE WRITE
-WRITE 01h AND 75h
TO C8h AND C9h
SINGLE-BYTE READ
-READ REGISTER BAh
TWO-BYTE READ
-READ C8h AND C9h
REPEATED
START
MASTER
NACK
10100010
A2h
10111010
BAh
SLAVE
ACK
START SLAVE
ACK
10100010
A2h
10100011
A3h
10111010
BAh
SLAVE
ACK
SLAVE
ACK
STOP
00000000
00h
STOP
SLAVE
ACK
STOP
01110101
75h
START SLAVE
ACK
10100010
A2h
11001000
C8h
SLAVE
ACK
SLAVE
ACK
00000001
01h
SLAVE
ACK DATA IN BAh
DATA
REPEATED
START
MASTER
ACK
START SLAVE
ACK
10100010
A2h
10100011
A3h
11001000
C8h
SLAVE
ACK
SLAVE
ACK DATA IN C8h
DATA
MASTER
NACK
DATA IN C9h
DATA
EXAMPLE I2C TRANSACTIONS WITH A2h AS THE MAIN MEMORY DEVICE ADDRESS
*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h FOR THE MAIN MEMORY.
IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Ch FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED
ADDRESS FOR THE MAIN MEMORY IS A0h.
TYPICAL I2C WRITE TRANSACTION
A)
C)
B)
D)
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
REGISTER ADDRESS
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
DATA
SLAVE
ACK
SLAVE
ACK
SLAVE
ADDRESS*
1 0 1 0 0 0 1 R/W
MSB LSB
READ/
WRITE
Figure 17. Example I2C Timing
DS1873
SFP+ Controller with Analog LDD Interface
26 ______________________________________________________________________________________
byte (R/W= 0) and the first memory address of the
next memory row before continuing to write data.
Acknowledge polling: Any time a EEPROM page is
written, the DS1873 requires the EEPROM write time
(tW) after the STOP condition to write the contents of
the page to EEPROM. During the EEPROM write
time, the DS1873 will not acknowledge its slave
address because it is busy. It is possible to take
advantage of that phenomenon by repeatedly
addressing the DS1873, which allows the next page
to be written as soon as the DS1873 is ready to
receive the data. The alternative to acknowledge
polling is to wait for maximum period of tWto elapse
before attempting to write again to the DS1873.
EEPROM write cycles: When EEPROM writes occur,
the DS1873 writes the whole EEPROM memory page,
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page
is written, bytes on the page that were not modified
during the transaction are still subject to a write
cycle. This can result in a whole page being worn out
over time by writing a single byte repeatedly. Writing
a page one byte at a time wears the EEPROM out
eight times faster than writing the entire page at
once. The DS1873’s EEPROM write cycles are speci-
fied in the
Nonvolatile Memory Characteristics
table.
The specification shown is at the worst-case temper-
ature. It can handle approximately ten times that
many writes at room temperature. Writing to SRAM-
shadowed EEPROM memory with SEEB = 1 does not
count as an EEPROM write cycle when evaluating
the EEPROM’s estimated lifetime.
Reading a single byte from a slave: Unlike the
write operation that uses the memory address byte
to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the
slave, the master generates a START condition,
writes the slave address byte with R/W= 1, reads
the data byte with a NACK to indicate the end of the
transfer, and generates a STOP condition.
Manipulating the address counter for reads: A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the master
generates a START condition, writes the slave
address byte (R/W= 0), writes the memory address
where it desires to read, generates a repeated
START condition, writes the slave address byte (R/W
= 1), reads data with ACK or NACK as applicable,
and generates a STOP condition.
Memory Organization
The DS1873 features nine separate memory tables that
are internally organized into 8-byte rows.
The DS1873 has two passwords that are each 4 bytes
long. The lower level password (PW1) has all the
access of a normal user plus those made available with
PW1. The higher level password (PW2) has all the
access of PW1 plus those made available with PW2.
The values of the passwords reside in EEPROM inside
of PW2 memory. At power-up, all PWE bits are set to 1,
and all reads at this location are 0.
The Lower Memory is addressed from 00h to 7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, password entry area (PWE),
and the table-select byte.
Table 01h primarily contains user EEPROM (with PW1
level access) as well as alarm and warning-enable
bytes.
Table 02h is a multifunction space that contains config-
uration registers, scaling and offset values, passwords,
interrupt registers as well as other miscellaneous con-
trol bytes.
Table 04h contains a temperature-indexed LUT for
control of the modulation output. The modulation LUT
can be programmed in 2°C increments over the -40°C
to +102°C range. The table also contains a tempera-
ture-indexed LUT for MOD offsets.
Table 05h is empty by default. It can be configured to
contain the alarm- and warning-enable bytes from Table
01h, Registers F8h–FFh with the MASK bit enabled
(Table 02h, Register 89h). In this case Table 01h is
empty.
Table 06h contains a temperature-indexed LUT that
allows the APC set point to change as a function of
temperature to compensate for tracking error (TE). The
APC LUT has 36 entries that determine the APC setting
in 4°C windows between -40°C and +100°C. The table
also contains a temperature-indexed LUT for HBIAS
thresholds.
Table 07h contains a temperature-indexed LUT for con-
trol of DAC1. The LUT has 72 entries that determine the
DAC setting in 4°C windows between -40°C and
+100°C. The table also contains a temperature-indexed
LUT for DAC1 offsets.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 27
Table 08h contains a temperature-indexed LUT for
control of DAC2. The LUT has 36 entries that determine
the DAC setting in 4°C windows between -40°C and
+100°C.
Auxiliary Memory (device A0h) contains 256 bytes of
EE memory accessible from address 00h–FFh. It is
selected with the device address of A0h.
See the
Register Descriptions
section for more com-
plete details of each byte’s function, as well as for
read/write permissions for each byte.
Shadowed EEPROM
Many NV memory locations (listed within the
Register
Descriptions
section) are actually shadowed EEPROM
that are controlled by the SEEB bit in Table 02h,
Register 80h.
The DS1873 incorporates shadowed-EEPROM memory
locations for key memory addresses that can be written
many times. By default the shadowed-EEPROM bit,
SEEB, is not set and these locations act as ordinary EEP-
ROM. By setting SEEB, these locations function like
SRAM cells, which allow an infinite number of write cycles
without concern of wearing out the EEPROM. Setting
SEEB also eliminates the requirement for the EEPROM
write time, tWR. Because changes made with SEEB
enabled do not affect the EEPROM, these changes are
not retained through power cycles. The power-on value is
the last value written with SEEB disabled. This function
can be used to limit the number of EEPROM writes during
calibration or to change the monitor thresholds periodical-
ly during normal operation helping to reduce the number
of times EEPROM is written. Figure 18 indicates which
locations are shadowed EEPROM.
EEPROM
(256 BYTES)
FFh
I2C ADDRESS A0h I2C ADDRESS A2h (DEFAULT)
AUXILIARY DEVICE
MAIN DEVICE
00h
ALARM-
ENABLE ROW
(8 BYTES)
PASSWORD ENTRY
(PWE) (4 BYTES)
TABLE-SELECT
BYTE
FFh
80h
F8h
MOD OFFSET
LUT
FFh
F8h
TABLE 01h
EEPROM
(120 BYTES)
F7h
7Fh
00h
LOWER
MEMORY
FFh
80h
TABLE 02h
NONLOOKUP
TABLE CONTROL
AND
CONFIGURATION
REGISTERS
80h
TABLE 04h
MOD
LOOKUP TABLE
(72 BYTES)
C7h
F8h TABLE 05h
ALARM-ENABLE ROW
(8 BYTES) FFh
80h TABLE 06h
TRACKING ERROR
LOOKUP TABLE
(36 BYTES) A3h
80h
TABLE 07h
DAC1 LUT
C7h
80h
TABLE 08h
DAC2 LUT
A3h
NOTE 1: IF ASEL = 0, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS A2h.
IF ASEL = 1, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS DETERMINED BY THE VALUE IN
TABLE 02h, REGISTER 8Ch.
NOTE 2: TABLE 00h DOES NOT EXIST.
NOTE 3: ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING THE
MASK BIT IN TABLE 02h, REGISTER 89h.
DAC1 OFFSET
LUT
FFh
F8h
DAC2 OFFSET
LUT
FFh
F8h
HBIAS LUT
FFh
F8h
Figure 18. Memory Map
DS1873
SFP+ Controller with Analog LDD Interface
28 ______________________________________________________________________________________
Register Descriptions
The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is locat-
ed in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is one/two
memory locations beyond the previous byte/word’s address. A total of 8 bytes are present on each row. For more
information about each of these bytes see the corresponding register description.
Lower Memory Register Map
LOWER MEMORY
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(hex) ROW NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
00 <1>THRESHOLD0 TEMP ALARM HI TEMP ALARM LO TEMP WARN HI TEMP WARN LO
08 <1>THRESHOLD1 V
CC ALARM HI VCC ALARM LO VCC WARN HI VCC WARN LO
10 <1>THRESHOLD2 MON1 ALARM HI MON1 ALARM LO MON1 WARN HI MON1 WARN LO
18 <1>THRESHOLD3 MON2 ALARM HI MON2 ALARM LO MON2 WARN HI MON2 WARN LO
20 <1>THRESHOLD4 MON3 ALARM HI MON3 ALARM LO MON3 WARN HI MON3 WARN LO
28 <1>THRESHOLD5 MON4 ALARM HI MON4 ALARM LO MON4 WARN HI MON4 WARN LO
30–5F <1>EEPROM EE EE EE EE EE EE EE EE
60 <2>ADC
VALUES0TEMP VALUE VCC VALUE MON1 VALUE MON2 VALUE
68 <0>ADC
VALUES1
<2>MON3 VALUE <2>MON4 VALUE <2>RESERVED <0>STATUS <3>UPDATE
70 <2>ALARM/
WARN ALARM3ALARM2ALARM1 ALARM0 WARN3WARN2RESERVED
78 <0>TABLE
SELECT
<2>RESERVED <2>
RESERVED
<6>PWE MSW <6>PWE LSW <5>TBL
SEL
ACCESS
CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately PW2 N/A
All and
DS1873
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
These registers also allow for custom permissions.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 29
Table 01h Register Map
The ALARM ENABLE bytes (Registers F8h–FFh) can be configured to exist in Table 05h instead of here at Table 01h
with the MASK bit (Table 02h, Register 89h). If the row is configured to exist in Table 05h, then these locations are
empty in Table 01h.
TABLE 01h
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(hex)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–BF <8>EEPROM EE EE EE EE EE EE EE EE
C0–F7 <8>EEPROM EE EE EE EE EE EE EE EE
F8 <8>ALARM
ENABLE
ALARM
EN3
ALARM
EN2
ALARM
EN1
ALARM
EN0WARN EN3WARN EN2RESERVED RESERVED
ACCESS
CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately PW2 N/A
All and
DS1873
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
These registers also allow for custom permissions.
DS1873
SFP+ Controller with Analog LDD Interface
30 ______________________________________________________________________________________
Table 02h Register Map
TABLE 02h
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(hex)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80 <0>CONFIG0<8>MODE <4>TINDEX <4>MOD DAC <4>DAC1 VALUE <4>DAC2 VALUE
88 <8>CONFIG1UPDATE
RATE CNFGA CNFGB CNFGC DEVICE
ADDRESS RSHIFT2 RSHIFT1RSHIFT0
90 <8>SCALE0XOVER COARSE VCC SCALE MON1 SCALE MON2 SCALE
98 <8>SCALE1MON3 FINE SCALE MON4 SCALE MON3 COARSE SCALE RESERVED
A0 <8>OFFSET0XOVER FINE VCC OFFSET MON1 OFFSET MON2 OFFSET
A8 <8>OFFSET1MON3 FINE OFFSET MON4 OFFSET MON3 COARSE OFFSET INTERNAL TEMP
OFFSET*
B0 <9>PWD VALUE PW1 MSW PW1 LSW PW2 MSW PW2 LSW
B8 <8>THRESHOLD LOS
RANGING
COMP
RANGING IBIASMAX ISTEP HTXP LTXP HLOS LLOS
C0 <8>PWD
ENABLE PW_ENA PW_ENB RESERVED RESERVED RESERVED RESERVED POLARITY TBLSELPON
C8 <0>BIAS <4>MAN BIAS <4>MAN_
CNTL
<10>BIAS DAC RESERVED <10>DEVICE
ID
<10>DEVICE
VER
D0 <0>APC <4>APC
DAC
<8>HBIAS
DAC RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
D8–FF EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
ACCESS
CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately PW2 N/A
All and
DS1873
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
*
The final result must be XORed with BB40h before writing to this register.
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
These registers also allow for custom permissions.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 31
Table 04h Register Map
TABLE 04h (MODULATION LUT)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(hex)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD
88 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD
90 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD
98 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD
A0 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD
A8 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD
B0 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD
B8 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD
C0 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD
C8–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
F8 <8>MOD
OFFSET MOD OFF MOD OFF MOD OFF MOD OFF MOD OFF MOD OFF MOD OFF MOD OFF
ACCESS
CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately PW2 N/A
All and
DS1873
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
Table 05h Register Map
Table 05h is empty by default. It can be configured to contain the alarm and warning-enable bytes from Table 01h,
Registers F8h–FFh with the MASK bit enabled (Table 02h, Register 89h). In this case Table 01h is empty.
TABLE 05h
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(hex)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
F8 <8>ALARM
ENABLE
ALARM
EN3
ALARM
EN2
ALARM
EN1
ALARM
EN0WARN EN3WARN EN2RESERVED RESERVED
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
These registers also allow for custom permissions.
DS1873
SFP+ Controller with Analog LDD Interface
32 ______________________________________________________________________________________
TABLE 07h (DAC1 LUT)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(hex)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80 <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1
88 <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1
90 <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1
98 <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1
A0 <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1
A8 <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1
B0 <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1
B8 <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1
C0 <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1
C8–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
F8 <8>DAC1
OFFSET DAC1 OFF DAC1 OFF DAC1 OFF DAC1 OFF DAC1 OFF DAC1 OFF DAC1 OFF DAC1 OFF
ACCESS
CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately PW2 N/A
All and
DS1873
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
Table 07h Register Map
Table 06h Register Map
TABLE 06h (APC LUT)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(hex)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–9F <8>LUT6 APC REF APC REF APC REF APC REF APC REF APC REF APC REF APC REF
88 <8>LUT6 APC REF APC REF APC REF APC REF APC REF APC REF APC REF APC REF
90 <8>LUT6 APC REF APC REF APC REF APC REF APC REF APC REF APC REF APC REF
98 <8>LUT6 APC REF APC REF APC REF APC REF APC REF APC REF APC REF APC REF
A0 <8>LUT6 APC REF APC REF APC REF APC REF RESERVED RESERVED RESERVED RESERVED
A8–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
F8 <8>HBATH HBIAS HBIAS HBIAS HBIAS HBIAS HBIAS HBIAS HBIAS
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
These registers also allow for custom permissions.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 33
Table 08h Register Map
ACCESS
CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately PW2 N/A
All and
DS1873
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
TABLE 08h (DAC2 LUT)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(hex)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80 <8>LUT8 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2
88 <8>LUT8 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2
90 <8>LUT8 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2
98 <8>LUT8 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2
A0 <8>LUT8 DAC2 DAC2 DAC2 DAC2 RESERVED RESERVED RESERVED RESERVED
C8–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
F8 <8>DAC2
OFFSET DAC2 OFF DAC2 OFF DAC2 OFF DAC2 OFF DAC2 OFF DAC2 OFF DAC2 OFF DAC2 OFF
Auxiliary A0h Memory Register Map
AUXILIARY MEMORY (A0h)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(hex)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
00–7F <5>AUX EE EE EE EE EE EE EE EE EE
80–FF <5>AUX EE EE EE EE EE EE EE EE EE
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
These registers also allow for custom permissions.
DS1873
SFP+ Controller with Analog LDD Interface
34 ______________________________________________________________________________________
Lower Memory Register Descriptions
Lower Memory, Register 00h–01h: TEMP ALARM HI
Lower Memory, Register 04h–05h: TEMP WARN HI
FACTORY DEFAULT 7FFFh
READ ACCESS All
WRITE ACCESS PW2 or (PW1 and WLOWER)
MEMORY TYPE Nonvolatile (SEE)
00h, 04h S 26 2
5 2
4 2
3 2
2 2
1 2
0
01h, 05h 2-1 2
-2 2
-3 2
-4 2
-5 2
-6 2
-7 2
-8
BIT 7 BIT 0
Temperature measurement updates above this two’s complement threshold set corresponding alarm or warning bits.
Temperature measurement updates equal to or below this threshold clear alarm or warning bits.
Lower Memory, Register 02h–03h: TEMP ALARM LO
Lower Memory, Register 06h–07h: TEMP WARN LO
FACTORY DEFAULT 8000h
READ ACCESS All
WRITE ACCESS PW2 or (PW1 and WLOWER)
MEMORY TYPE Nonvolatile (SEE)
02h, 06h S 26 2
5 2
4 2
3 2
2 2
1 2
0
03h, 07h 2-1 2
-2 2
-3 2
-4 2
-5 2
-6 2
-7 2
-8
BIT 7 BIT 0
Temperature measurement updates below this two’s complement threshold set corresponding alarm or warning bits.
Temperature measurement updates equal to or above this threshold clear alarm or warning bits.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 35
Lower Memory, Register 08h–09h: VCC ALARM HI
Lower Memory, Register 0Ch–0Dh: VCC WARN HI
Lower Memory, Register 10h–11h: MON1 ALARM HI
Lower Memory, Register 14h–15h: MON1 WARN HI
Lower Memory, Register 18h–19h: MON2 ALARM HI
Lower Memory, Register 1Ch–1Dh: MON2 WARN HI
Lower Memory, Register 20h–21h: MON3 ALARM HI
Lower Memory, Register 24h–25h: MON3 WARN HI
Lower Memory, Register 28h–29h: MON4 ALARM HI
Lower Memory, Register 2Ch–2Dh: MON4 WARN HI
FACTORY DEFAULT FFFFh
READ ACCESS All
WRITE ACCESS PW2 or (PW1 and WLOWER)
MEMORY TYPE Nonvolatile (SEE)
08h, 0Ch, 10h,
14h, 18h, 1Ch,
20h, 24h, 28h,
2Ch
215 214 2
13 2
12 2
11 2
10 2
9 2
8
09h, 0Dh, 11h,
15h, 19h, 1Dh,
21h, 25h, 29h,
2Dh
27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Voltage measurement updates above this unsigned threshold set corresponding alarm or warning bits. Voltage
measurements equal to or below this threshold clear alarm or warning bits.
DS1873
SFP+ Controller with Analog LDD Interface
36 ______________________________________________________________________________________
Lower Memory, Register 0Ah–0Bh: VCC ALARM LO
Lower Memory, Register 0Eh–0Fh: VCC WARN LO
Lower Memory, Register 12h–13h: MON1 ALARM LO
Lower Memory, Register 16h–17h: MON1 WARN LO
Lower Memory, Register 1Ah–1Bh: MON2 ALARM LO
Lower Memory, Register 1Eh–1Fh: MON2 WARN LO
Lower Memory, Register 22h–23h: MON3 ALARM LO
Lower Memory, Register 26h–27h: MON3 WARN LO
Lower Memory, Register 2Ah–2Bh: MON4 ALARM LO
Lower Memory, Register 2Eh–2Fh: MON4 WARN LO
FACTORY DEFAULT 0000h
READ ACCESS All
WRITE ACCESS PW2 or (PW1 and WLOWER)
MEMORY TYPE Nonvolatile (SEE)
0Ah, 0Eh,
12h, 16h,
1Ah, 1Eh,
22h, 26h,
2Ah, 2Eh
215 214 2
13 2
12 2
11 2
10 2
9 2
8
0Bh, 0Fh,
13h, 17h,
1Bh, 1Fh,
23h, 27h,
2Bh, 2Fh
27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Voltage measurement updates below this unsigned threshold set corresponding alarm or warning bits. Voltage
measurements equal to or above this threshold clear alarm or warning bits.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 37
Lower Memory, Register 30h–5Fh: EE
FACTORY DEFAULT 00h
READ ACCESS All
WRITE ACCESS PW2 or (PW1 and WLOWER)
MEMORY TYPE Nonvolatile (EE)
30h–5Fh EE EE EE EE EE EE EE EE
BIT 7 BIT 0
PW2 level access-controlled EEPROM.
POWER-ON VALUE 0000h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
60h S 26 2
5 2
4 2
3 2
2 2
1 2
0
61h 2-1 2
-2 2
-3 2
-4 2
-5 2
-6 2
-7 2
-8
BIT 7 BIT 0
Signed two’s complement direct-to-temperature measurement.
Lower Memory, Register 60h–61h: TEMP VALUE
DS1873
SFP+ Controller with Analog LDD Interface
38 ______________________________________________________________________________________
Lower Memory, Register 6Ch–6Dh: RESERVED
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE
6Ch, 6Dh 0 0 0 0 0 0 0 0
BIT 7 BIT 0
These registers are reserved. The value when read is 00h.
POWER-ON VALUE 0000h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
62h, 64h,
66h, 68h,
6Ah
215 214 2
13 2
12 2
11 2
10 2
9 2
8
63h, 65h,
67h, 69h,
6Bh
27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Left-justified unsigned voltage measurement.
Lower Memory, Register 62h–63h: VCC VALUE
Lower Memory, Register 64h–65h: MON1 VALUE
Lower Memory, Register 66h–67h: MON2 VALUE
Lower Memory, Register 68h–69h: MON3 VALUE
Lower Memory, Register 6Ah–6Bh: MON4 VALUE
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 39
POWER-ON VALUE X0XX 0XXXb
READ ACCESS All
WRITE ACCESS See below
MEMORY TYPE Volatile
Write Access N/A All N/A All All N/A N/A N/A
6Eh TXDS TXDC IN1S RSELS RSELC TXFS RXL RDYB
BIT 7 BIT 0
BIT 7
TXDS: TXD Status Bit. Reflects the logic state of the TXD pin (read only).
0 = TXD pin is logic-low.
1 = TXD pin is logic-high.
BIT 6
TXDC: TXD Software Control Bit. This bit allows for software control that is identical to the TXD pin.
See the section on TXD for further information. Its value is wire-ORed with the logic value of the
TXD pin (writable by all users).
0 = (Default).
1 = Forces the device into a TXD state regardless of the value of the TXD pin.
BIT 5
IN1S: IN1 Status Bit. Reflects the logic state of the IN1 pin (read only).
0 = IN1 pin is logic-low.
1 = IN1 pin is logic-high.
BIT 4
RSELS: RSEL Status Bit. Reflects the logic state of the RSEL pin (read only).
0 = RSEL pin is logic-low.
1 = RSEL pin is logic-high.
BIT 3
RSELC: RSEL Software Control Bit. This bit allows for software control that is identical to the RSEL
pin. Its value is wire-ORed with the logic value of the RSEL pin to create the RSELOUT pin’s logic
value (writable by all users).
0 = (Default).
1 = Forces the device into a RSEL state regardless of the value of the RSEL pin.
BIT 2
TXFS: Reflects the driven state of the TXF pin (read only).
0 = TXF pin is low.
1 = TXF pin is high.
BIT 1
RXL: Reflects the driven state of the LOSOUT pin (read only).
0 = LOSOUT pin is driven low.
1 = LOSOUT pin is pulled high.
BIT 0
RDYB: Ready Bar.
0 = VCC is above POA.
1 = VCC is below POA and/or too low to communicate over the I2C bus.
Lower Memory, Register 6Eh: STATUS
DS1873
SFP+ Controller with Analog LDD Interface
40 ______________________________________________________________________________________
Lower Memory, Register 6Fh: UPDATE
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS All and DS1873 Hardware
MEMORY TYPE Volatile
6Fh TEMP RDY VCC RDY MON1 RDY MON2 RDY MON3 RDY MON4 RDY RESERVED RSSIR
BIT 7 BIT 0
BITS 7:2
Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is
completed. These bits can be cleared so that a completion of a new conversion is verified.
BIT 1 RESERVED
BIT 0
RSSIR: RSSI Range. Reports the range used for conversion update of MON3.
0 = Fine range is the reported value.
1 = Coarse range is the reported value.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 41
POWER-ON VALUE 10h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
70h TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
BIT 7 BIT 0
BIT 7
TEMP HI: High-alarm status for temperature measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
TEMP LO: Low-alarm status for temperature measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
VCC HI: High-alarm status for VCC measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
VCC LO: Low-alarm status for VCC measurement. This bit is set when the VCC supply is below the POA trip
point value. It clears itself when a VCC measurement is completed and the value is above the low threshold.
0 = Last measurement was equal to or above threshold setting.
1 = (Default) Last measurement was below threshold setting.
BIT 3
MON1 HI: High-alarm status for MON1 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 2
MON1 LO: Low-alarm status for MON1 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 1
MON2 HI: High-alarm status for MON2 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 0
MON2 LO: Low-alarm status for MON2 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
Lower Memory, Register 70h: ALARM3
DS1873
SFP+ Controller with Analog LDD Interface
42 ______________________________________________________________________________________
Lower Memory, Register 71h: ALARM2
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
71h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED TXFINT
BIT 7 BIT 0
BIT 7
MON3 HI: High-alarm status for MON3 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
MON3 LO: Low-alarm status for MON3 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
MON4 HI: High-alarm status for MON4 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
MON4 LO: Low-alarm status for MON4 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BITS 3:1 RESERVED
BIT 0
TXFINT: TXF Interrupt. This bit is the wire-ORed logic of all alarms and warnings wire-ANDed with their
corresponding enable bits in addition to nonmaskable alarms TXP HI, TXP LO, BIAS MAX, and HBAL. The
enable bits are found in Table 01h/05h, Registers F8h–FFh.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 43
Lower Memory, Register 72h: ALARM1
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
72h RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI TXP LO
BIT 7 BIT 0
BITS 7:4 RESERVED
BIT 3
HBAL: High-Bias Alarm Status; Fast Comparison. A TXD event clears this alarm.
0 = (Default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
BIT 2 RESERVED
BIT 1
TXP HI: High-Alarm Status TXP; Fast Comparison. A TXD event clears this alarm.
0 = (Default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
BIT 0
TXP LO: Low-Alarm Status TXP; Fast Comparison. A TXD event clears this alarm.
0 = (Default) Last comparison was above threshold setting.
1 = Last comparison was below threshold setting.
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
73h LOS HI LOS LO RESERVED RESERVED BIAS MAX RESERVED RESERVED RESERVED
BIT 7 BIT 0
BIT 7
LOS HI: High-Alarm Status for MON3; Fast Comparison. A TXD event does not clear this alarm.
0 = (Default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
BIT 6
LOS LO: Low-Alarm Status for MON3; Fast Comparison. A TXD event does not clear this alarm.
0 = (Default) Last comparison was above threshold setting.
1 = Last comparison was below threshold setting.
BITS 5:4 RESERVED
BIT 3
BIAS MAX: Alarm status for maximum digital setting of BIAS. A TXD event clears this alarm.
0 = (Default) The value for BIAS is equal to or below the IBIASMAX register.
1 = Requested value for BIAS is greater than the IBIASMAX register.
BITS 2:0 RESERVED
Lower Memory, Register 73h: ALARM0
DS1873
SFP+ Controller with Analog LDD Interface
44 ______________________________________________________________________________________
Lower Memory, Register 74h: WARN3
POWER-ON VALUE 10h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
74h TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
BIT 7 BIT 0
BIT 7
TEMP HI: High-warning status for temperature measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
TEMP LO: Low-warning status for temperature measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
VCC HI: High-warning status for VCC measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
VCC LO: Low-warning status for VCC measurement. This bit is set when the VCC supply is below the POA
trip point value. It clears itself when a VCC measurement is completed and the value is above the low
threshold.
0 = Last measurement was equal to or above threshold setting.
1 = (Default) Last measurement was below threshold setting.
BIT 3
MON1 HI: High-warning status for MON1 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 2
MON1 LO: Low-warning status for MON1 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 1
MON2 HI: High-warning status for MON2 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 0
MON2 LO: Low-warning status for MON2 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 45
Lower Memory, Register 75h: WARN2
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
75h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED
BIT 7 BIT 0
BIT 7
MON3 HI: High-warning status for MON3 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
MON3 LO: Low-warning status for MON3 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
MON4 HI: High-warning status for MON4 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
MON4 LO: Low-warning status for MON4 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BITS 3:0 RESERVED
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE
These registers are reserved. The value when read is 00h.
Lower Memory, Register 76h–7Ah: RESERVED
DS1873
SFP+ Controller with Analog LDD Interface
46 ______________________________________________________________________________________
Lower Memory, Register 7Bh–7Eh: Password Entry (PWE)
POWER-ON VALUE FFFF FFFFh
READ ACCESS N/A
WRITE ACCESS All
MEMORY TYPE Volatile
7Bh 231 230 2
29 2
28 227 2
26 2
25 2
24
7Ch 223 222 2
21 2
20 219 2
18 2
17 2
16
7Dh 215 214 2
13 2
12 2
11 2
10 2
9 2
8
7Eh 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
There are two passwords for the DS1873. Each password is 4 bytes long. The lower level password (PW1) has all the
access of a normal user plus those made available with PW1. The higher level password (PW2) has all the access of
PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside PW2 memory. At
power-up, all PWE bits are set to 1. All reads at this location are 0.
POWER-ON VALUE TBLSELPON (Table 02h, Register C7h)
READ ACCESS All
WRITE ACCESS All
MEMORY TYPE Volatile
7Fh 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
The upper memory tables of the DS1873 are accessible by writing the desired table value in this register. The power-on
value of this register is defined by the value written to TBLSELPON (Table 02h, Register C7h).
Lower Memory, Register 7Fh: Table Select (TBL SEL)
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 47
Table 01h Register Descriptions
Table 01h, Register 80h–BFh: EEPROM
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A)
WRITE ACCESS PW2 or (PW1 and RWTBL1A)
MEMORY TYPE Nonvolatile (EE)
80h–BFh EE EE EE EE EE EE EE EE
BIT 7 BIT 0
EEPROM for PW1 and/or PW2 level access.
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1B) or (PW1 and RTBL1B)
WRITE ACCESS PW2 or (PW1 and RWTBL1B)
MEMORY TYPE Nonvolatile (EE)
C0h–F7h EE EE EE EE EE EE EE EE
BIT 7 BIT 0
EEPROM for PW1 and/or PW2 level access.
Table 01h, Register C0h–F7h: EEPROM
DS1873
SFP+ Controller with Analog LDD Interface
48 ______________________________________________________________________________________
Table 01h, Register F8h: ALARM EN3
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
F8h TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
BIT 7 BIT 0
Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h
or 05h.
BIT 7
TEMP HI:
0 = Disables interrupt from TEMP HI alarm.
1 = Enables interrupt from TEMP HI alarm.
BIT 6
TEMP LO:
0 = Disables interrupt from TEMP LO alarm.
1 = Enables interrupt from TEMP LO alarm.
BIT 5
VCC HI:
0 = Disables interrupt from VCC HI alarm.
1 = Enables interrupt from VCC HI alarm.
BIT 4
VCC LO:
0 = Disables interrupt from VCC LO alarm.
1 = Enables interrupt from VCC LO alarm.
BIT 3
MON1 HI:
0 = Disables interrupt from MON1 HI alarm.
1 = Enables interrupt from MON1 HI alarm.
BIT 2
MON1 LO:
0 = Disables interrupt from MON1 LO alarm.
1 = Enables interrupt from MON1 LO alarm.
BIT 1
MON2 HI:
0 = Disables interrupt from MON2 HI alarm.
1 = Enables interrupt from MON2 HI alarm.
BIT 0
MON2 LO:
0 = Disables interrupt from MON2 LO alarm.
1 = Enables interrupt from MON2 LO alarm.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 49
Table 01h, Register F9h: ALARM EN2
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
F9h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED
BIT 7 BIT 0
Layout is identical to ALARM2 in Lower Memory, Register 71h. Enables alarms to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h or
05h.
BIT 7
MON3 HI:
0 = Disables interrupt from MON3 HI alarm.
1 = Enables interrupt from MON3 HI alarm.
BIT 6
MON3 LO:
0 = Disables interrupt from MON3 LO alarm.
1 = Enables interrupt from MON3 LO alarm.
BIT 5
MON4 HI:
0 = Disables interrupt from MON4 HI alarm.
1 = Enables interrupt from MON4 HI alarm.
BIT 4
MON4 LO:
0 = Disables interrupt from MON4 LO alarm.
1 = Enables interrupt from MON4 LO alarm.
BIT 3:0 RESERVED
DS1873
SFP+ Controller with Analog LDD Interface
50 ______________________________________________________________________________________
Table 01h, Register FAh: ALARM EN1
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
FAh RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI TXP LO
BIT 7 BIT 0
Layout is identical to ALARM1 in Lower Memory, Register 72h. Enables alarms to create internal signal FETG (see
Figure 13) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h or
05h.
BITS 7:4 RESERVED
BIT 3
HBAL:
0 = Disables interrupt from HBAL alarm.
1 = Enables interrupt from HBAL alarm.
BIT 2 RESERVED
BIT 1
TXP HI:
0 = Disables interrupt from TXP HI alarm.
1 = Enables interrupt from TXP HI alarm.
BIT 0
TXP LO:
0 = Disables interrupt from TXP LO alarm.
1 = Enables interrupt from TXP LO alarm.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 51
Table 01h, Register FBh: ALARM EN0
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
FBh LOS HI LOS LO RESERVED RESERVED BIAS MAX RESERVED RESERVED RESERVED
BIT 7 BIT 0
Layout is identical to ALARM0 in Lower Memory, Register 73h. The MASK bit (Table 02h, Register 89h) determines
whether this memory exists in Table 01h or 05h.
BIT 7
LOS HI: Enables alarm to create TXFINT (Lower Memory, Register 71h) logic.
0 = Disables interrupt from LOS HI alarm.
1 = Enables interrupt from LOS HI alarm.
BIT 6
LOS LO: Enables alarm to create TXFINT (Lower Memory, Register 71h) logic.
0 = Disables interrupt from LOS LO alarm.
1 = Enables interrupt from LOS LO alarm.
BITS 5:4 RESERVED
BIT 3
BIAS MAX: Enables alarm to create internal signal FETG (see Figure 13) logic.
0 = Disables interrupt from BIAS MAX alarm.
1 = Enables interrupt from BIAS MAX alarm.
BITS 2:0 RESERVED
DS1873
SFP+ Controller with Analog LDD Interface
52 ______________________________________________________________________________________
Table 01h, Register FCh: WARN EN3
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
FCh TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
BIT 7 BIT 0
Layout is identical to WARN3 in Lower Memory, Register 74h. Enables warnings to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h
or 05h.
BIT 7
TEMP HI:
0 = Disables interrupt from TEMP HI warning.
1 = Enables interrupt from TEMP HI warning.
BIT 6
TEMP LO:
0 = Disables interrupt from TEMP LO warning.
1 = Enables interrupt from TEMP LO warning.
BIT 5
VCC HI:
0 = Disables interrupt from VCC HI warning.
1 = Enables interrupt from VCC HI warning.
BIT 4
VCC LO:
0 = Disables interrupt from VCC LO warning.
1 = Enables interrupt from VCC LO warning.
BIT 3
MON1 HI:
0 = Disables interrupt from MON1 HI warning.
1 = Enables interrupt from MON1 HI warning.
BIT 2
MON1 LO:
0 = Disables interrupt from MON1 LO warning.
1 = Enables interrupt from MON1 LO warning.
BIT 1
MON2 HI:
0 = Disables interrupt from MON2 HI warning.
1 = Enables interrupt from MON2 HI warning.
BIT 0
MON2 LO:
0 = Disables interrupt from MON2 LO warning.
1 = Enables interrupt from MON2 LO warning.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 53
Table 01h, Register FDh: WARN EN2
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
FDh MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED
BIT 7 BIT 0
Layout is identical to WARN2 in Lower Memory, Register 75h. Enables warnings to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h or
05h.
BIT 7
MON3 HI:
0 = Disables interrupt from MON3 HI warning.
1 = Enables interrupt from MON3 HI warning.
BIT 6
MON3 LO:
0 = Disables interrupt from MON3 LO warning.
1 = Enables interrupt from MON3 LO warning.
BIT 5
MON4 HI:
0 = Disables interrupt from MON4 HI warning.
1 = Enables interrupt from MON4 HI warning.
BIT 4
MON4 LO:
0 = Disables interrupt from MON4 LO warning.
1 = Enables interrupt from MON4 LO warning.
BITS 3:0 RESERVED
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
These registers are reserved.
Table 01h, Register FEh–FFh: RESERVED
DS1873
SFP+ Controller with Analog LDD Interface
54 ______________________________________________________________________________________
Table 02h Register Descriptions
Table 02h, Register 80h: MODE
POWER-ON VALUE 3Fh
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and PRTBL2)
MEMORY TYPE Volatile
80h SEEB RESERVED DAC1 EN DAC2 EN AEN MOD EN APC EN BIAS EN
BIT 7 BIT 0
BIT 7
SEEB:
0 = (Default) Enables EEPROM writes to SEE bytes.
1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part
is not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write the
SEE locations again for data to be written to the EEPROM.
BIT 6 RESERVED
BIT 5
DAC1 EN:
0 = DAC1 VALUE is writable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the values for DAC1. The output is updated with the new
value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for DAC1 VALUE.
BIT 4
DAC2 EN:
0 = DAC2 VALUE is writable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the values for DAC2. The output is updated with the new
value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for DAC2 VALUE.
BIT 3
AEN:
0 = The temperature-calculated index value TINDEX is writable by users and the updates of
calculated indexes are disabled. This allows users to interactively test their modules by
controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC
registers after the next completion of a temperature conversion.
BIT 2
MOD EN:
0 = Modulation is writable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the DAC value for modulation. The output is updated with the
new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for modulation.
BIT 1
APC EN:
0 = APC DAC is writable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the DAC value for APC reference. The I2C STOP condition is
the end of the write cycle. The HBIAS DAC is also writable if recalls are disabled.
1 = (Default) Enables auto control of the LUT for APC reference.
BIT 0
BIAS EN:
0 = BIAS DAC is controlled by the user and the APC is in manual mode. This allows the user to
interactively test their modules by writing the DAC value for bias.
1 = (Default) Enables auto control for the APC feedback.
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 55
Table 02h, Register 81h: Temperature Index (TINDEX)
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS (PW2 and AEN = 0) or (PW1 and RWTBL2 and AEN = 0)
MEMORY TYPE Volatile
81h 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
Holds the calculated index based on the temperature measurement. This index is used for the address during
lookup of Tables 04h, 06h–08h. Temperature measurements below -40°C or above +102°C are clamped to 80h and
C7h, respectively. The calculation of TINDEX is as follows:
TINDEX =Temp _ Value +40°C
2°C
+80h
For the temperature-indexed LUTs (2°C and 4°C), the index used during the lookup function for each table is as follows:
Table 04h (MOD) 1 TINDEX6 TINDEX5 TINDEX4TINDEX3 TINDEX2 TINDEX1 TINDEX0
Table 06h (APC) 1 0 TINDEX6 TINDEX5 TINDEX4TINDEX3 TINDEX2 TINDEX1
Table 07h (DAC1) 1 TINDEX6TINDEX5 TINDEX4TINDEX3 TINDEX2 TINDEX1 TINDEX0
Table 08h (DAC2) 1 0 TINDEX6 TINDEX5TINDEX4 TINDEX3 TINDEX2 TINDEX1
For the 8-position LUT tables, the following table shows the lookup function:
TINDEX 1000_0xxx 1001_0xxx 1001_1xxx 1010_0xxx 1010_1xxx 1011_0xxx 1011_1xxx 11xx_xxxx
BYTE F8 F9 FA FB FC FD FE FF
TEMP
(°C) < -8 -8 to +8 8 to 24 24 to 40 40 to 56 56 to 72 72 to 88 88
DS1873
SFP+ Controller with Analog LDD Interface
56 ______________________________________________________________________________________
Table 02h, Register 84h–85h: DAC1 VALUE
FACTORY DEFAULT 0000h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS (PW2 and DAC1 EN = 0) or (PW1 and RWTBL246 and DAC1 EN = 0)
MEMORY TYPE Volatile
84h 0 0 0 0 0 0 0 28
85h 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
The digital value used for DAC1. It is the result of LUT7 plus DAC1 OFFSET times 4 recalled from Table 07h at the
adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.
DAC1 VALUE =LUT7 +DAC1 OFFSET 4
V
DAC1
=V
REFIN
1024
DAC1 VALUE
FACTORY DEFAULT 0000h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS (PW2 and MOD EN = 0) or (PW1 and RWTBL2 and MOD EN = 0)
MEMORY TYPE Volatile
82h 0 0 0 0 0 0 0 28
83h 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
The digital value used for MOD DAC. It is the result of LUT4 plus MOD OFFSET times 4 recalled from Table 04h at
the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.
MOD VALUE =LUT4 +MOD OFFSET 4
VMOD =VREFIN
1024
MOD VALUE
Table 02h, Register 82h–83h: MOD DAC
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 57
Table 02h, Register 88h: UPDATE RATE
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
88h SEE SEE SEE SEE APC_SR3APC_SR2APC_SR1APC_SR0
BIT 7 BIT 0
BITS 7:4 SEE
BITS 3:0
APC_SR[3:0]: 4-bit sample rate for comparison of APC control. Defines the sample rate for comparison of
APC control.
The quick-trip comparator uses a 1.6μs window to sample each input. After an APC comparison that requires an
update to the BIAS DAC, a settling time (as calculated below) is required to allow for the feedback on BMD (MON2)
to stabilize. This time is dependent on the time constant of the filter pole used for the delta-to-sigma BIAS output.
During the timing of the settling rate, comparisons of APC comparisons of BMD are ignored until 32 sample periods
(tREP) have passed.
SettlingTime = 51.2μs x (APC_SR[3:0] + 1)
FACTORY DEFAULT 0000h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS (PW2 and DAC2 EN = 0) or (PW1 and RWTBL246 and DAC2 EN = 0)
MEMORY TYPE Volatile
86h 0 0 0 0 0 0 0 28
87h 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
The digital value used for DAC2. It is the result of LUT8 plus DAC2 OFFSET times 4 recalled from Table 08h at the
adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.
DAC2 VALUE =LUT8 +DAC2 OFFSET 4
VDAC2 =VREFIN
1024
DAC2 VALUE
Table 02h, Register 86h–87h: DAC2 VALUE
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SFP+ Controller with Analog LDD Interface
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FACTORY DEFAULT 80h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
89h LOSC RESERVED INV LOS ASEL MASK INVRSOUT RESERVED RESERVED
BIT 7 BIT 0
BIT 7
LOSC: LOS Configuration. Defines the source for the LOSOUT pin (see Figure 14).
0 = LOS LO alarm is used as the source.
1 = (Default) LOS input pin is used as the source.
BIT 6 RESERVED
BIT 5
INV LOS: Inverts the buffered input pin LOS to output pin LOSOUT (see Figure 14).
0 = Noninverted LOS to LOSOUT pin.
1 = Inverted LOS to LOSOUT pin.
BIT 4
ASEL: Address Select.
0 = Device address is A2h.
1 = Byte DEVICE ADDRESS in Table 02h, Register 8Ch is used as the device address.
BIT 3
MASK:
0 = Alarm-enable row exists at Table 01h, Registers F8h–FFh. Table 05h, Registers F8h–FFh are
empty.
1 = Alarm-enable row exists at Table 05h, Registers F8h–FFh. Table 01h, Registers F8h–FFh are
empty.
BIT 2
INVRSOUT: Allow for inversion of RSELOUT pin (see Figure 14).
0 = RSELOUT is not inverted.
1 = RSELOUT is inverted.
BITS 1:0 RESERVED
Table 02h, Register 89h: CNFGA
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SFP+ Controller with Analog LDD Interface
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Table 02h, Register 8Ah: CNFGB
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
8Ah IN1C INVOUT1 RESERVED RESERVED RESERVED ALATCH QTLATCH WLATCH
BIT 7 BIT 0
BIT 7
IN1C: IN1 Software Control Bit (see Figure 14).
0 = IN1 pin’s logic controls OUT1 pin.
1 = OUT1 is active (bit 6 defines the polarity).
BIT 6
INVOUT1: Inverts the active state for OUT1 (see Figure 14).
0 = Noninverted.
1 = Inverted.
BITS 5:3 RESERVED
BIT 2
ALATCH: ADC Alarm’s Comparison Latch. Lower Memory, Registers 70h–71h.
0 = ADC alarm flags reflect the status of the last comparison.
1 = ADC alarm flags remain set.
BIT 1
QTLATCH: Quick Trip’s Comparison Latch. Lower Memory, Registers 72h–73h.
0 = QT alarm and warning flags reflect the status of the last comparison.
1 = QT alarm and warning flags remain set.
BIT 0
WLATCH: ADC Warning’s Comparison Latch. Lower Memory, Registers 74h–75h.
0 = ADC warning flags reflect the status of the last comparison.
1 = ADC warning flags remain set.
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SFP+ Controller with Analog LDD Interface
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Table 02h, Register 8Bh: CNFGC
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
8Bh XOVEREN RESERVED TXDM34 TXDFG TXDFLT TXDIO RSSI_FC RSSI_FF
BIT 7 BIT 0
BIT 7
XOVEREN: Enables RSSI conversion to use the XOVER FINE (Table 02h, Register A0h–A1h) value
during MON3 conversions.
0 = Uses hysteresis for linear RSSI measurements.
1 = XOVER value is enabled for nonlinear RSSI measurements.
BIT 6 RESERVED
BIT 5
TXDM34: Enables TXD to reset alarms, warnings, and quick trips associated to MON3 and MON4
during a TXD event.
0 = TXD event has no effect on the MON3 and MON4 alarms, warnings, and quick trips.
1 = MON3 and MON4 alarms, warnings, and quick trips are reset during a TXD event.
BIT 4
TXDFG: See Figure 13.
0 = FETG, an internal signal, has no effect on TXDOUT.
1 = FETG is enabled and ORed with other possible signals to create TXDOUT.
BIT 3
TXDFLT: See Figure 13.
0 = TXF pin has no effect on TXDOUT.
1 = TXF pin is enabled and ORed with other possible signals to create TXDOUT.
BIT 2
TXDIO: See Figure 13.
0 = (Default) TXD input signal has no effect on TXDOUT.
1 = TXD input signal is enabled and ORed with other possible signals to create TXDOUT.
BITS 1:0
RSSI_FC and RSSI_FF: RSSI Force Coarse and RSSI Force Fine. Control bits for RSSI mode of
operation on the MON3 conversion.
00b = Normal RSSI mode of operation (default).
01b = The fine settings of scale and offset are used for MON3 conversions.
10b = The coarse settings of scale and offset are used for MON3 conversions.
11b = Normal RSSI mode of operation.
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SFP+ Controller with Analog LDD Interface
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FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
8Ch 2726 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
This value becomes the I2C slave address for the main memory when the ASEL (Table 02h, Register 89h) bit is
set. If A0h is programmed to this register, the auxiliary memory is disabled.
Table 02h, Register 8Ch: DEVICE ADDRESS
Table 02h, Register 8Dh: RIGHT-SHIFT2(RSHIFT2)
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
8Dh RESERVED RESERVED RESERVED RESERVED RESERVED MON3C2MON3C1MON3C0
BIT 7 BIT 0
Allows for right-shifting the final answer of MON3 coarse voltage measurement. This allows for scaling the
measurement to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to
the correct LSB.
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SFP+ Controller with Analog LDD Interface
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FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
8Eh RESERVED MON12MON11MON10RESERVED MON22MON21MON20
BIT 7 BIT 0
Allows for right-shifting the final answer of MON1 and MON2 voltage measurements. This allows for scaling the
measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted
to the correct LSB.
FACTORY DEFAULT 30h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
8Fh RESERVED MON3F2MON3F1MON3F0RESERVED MON42MON41MON40
BIT 7 BIT 0
Allows for right-shifting the final answer of MON3 fine and MON4 voltage measurements. This allows for scaling
the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is
weighted to the correct LSB. The MON3 right-shifting is only available for the fine mode of operation. The coarse
mode does not right-shift.
Table 02h, Register 8Eh: RIGHT-SHIFT1(RSHIFT1)
Table 02h, Register 8Fh: RIGHT-SHIFT0(RSHIFT0)
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SFP+ Controller with Analog LDD Interface
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Table 02h, Register 90h–91h: XOVER COARSE
FACTORY DEFAULT 0000h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
90h 215 214 2
13 2
12 2
11 2
10 2
9 2
8
91h 27 2
6 2
5 2
4 2
3 2
2 2
1 0
BIT 7 BIT 0
Defines the crossover value for RSSI measurements of nonlinear inputs when XOVEREN is set to a 1 (Table 02h,
Register 8Bh). MON3 coarse conversion results (before right-shifting) less than this register are clamped to the
value of this register.
FACTORY CALIBRATED
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
92h, 94h,
96h, 98h,
9Ah, 9Ch
215 214 2
13 2
12 2
11 2
10 2
9 2
8
93h, 95h,
97h, 99h,
9Bh, 9Dh
27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Controls the scaling or gain of the FS voltage measurements. The factory-calibrated value produces an FS
voltage of 6.5536V for VCC; 2.5V for MON1, MON2, MON4; and 0.3125V for MON3 fine.
Table 02h, Register 92h–93h: VCC SCALE
Table 02h, Register 94h–95h: MON1 SCALE
Table 02h, Register 96h–97h: MON2 SCALE
Table 02h, Register 98h–99h: MON3 FINE SCALE
Table 02h, Register 9Ah–9Bh: MON4 SCALE
Table 02h, Register 9Ch–9Dh: MON3 COARSE SCALE
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SFP+ Controller with Analog LDD Interface
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FACTORY DEFAULT FFFFh
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
A0h 215 214 2
13 2
12 2
11 2
10 2
9 2
8
A1h 27 2
6 2
5 2
4 2
3 2
2 2
1 0
BIT 7 BIT 0
Defines the crossover value for RSSI measurements of nonlinear inputs when XOVEREN is set to a 1 (Table 02h,
Register 8Bh). MON3 fine conversion results (before right-shifting) greater than this register require a MON3
coarse conversion.
Table 02h, Register A0h–A1h: XOVER FINE
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
These registers are reserved.
Table 02h, Register 9Eh–9Fh: RESERVED
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SFP+ Controller with Analog LDD Interface
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Table 02h, Register A2h–A3h: VCC OFFSET
Table 02h, Register A4h–A5h: MON1 OFFSET
Table 02h, Register A6h–A7h: MON2 OFFSET
Table 02h, Register A8h–A9h: MON3 FINE OFFSET
Table 02h, Register AAh–ABh: MON4 OFFSET
Table 02h, Register ACh–ADh: MON3 COARSE OFFSET
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
A2h, A4h,
A6h, A8h,
AAh, ACh
S S 215 214 2
13 2
12 2
11 2
10
A3h, A5h,
A7h, A9h,
ABh, ADh
29 2
8 2
7 2
6 2
5 2
4 2
3 2
2
BIT 7 BIT 0
Allows for offset control of these voltage measurements if desired. This number is two’s complement.
FACTORY CALIBRATED
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
AEh S 282726 2
5 2
4 2
3 2
2
AFh 21 2
0 2
-1 2
-2 2
-3 2
-4 2
-5 2
-6
BIT 7 BIT 0
Allows for offset control of temperature measurement if desired. The final result must be XORed with BB40h
before writing to this register. Factory calibration contains the desired value for a reading in degrees Celsius.
Table 02h, Register AEh–AFh: INTERNAL TEMP OFFSET
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SFP+ Controller with Analog LDD Interface
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Table 02h, Register B0h–B3h: PW1
FACTORY DEFAULT FFFF FFFFh
READ ACCESS N/A
WRITE ACCESS PW2 or (PW1 and WPW1)
MEMORY TYPE Nonvolatile (SEE)
B0h 231 230 2
29 2
28 2
27 2
26 2
25 2
24
B1h 223 2
22 2
21 2
20 2
19 2
18 2
17 2
16
B2h 215 214 2
13 2
12 2
11 2
10 2
9 2
8
B3h 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the
PWE value is set to all ones. Thus, writing these bytes to all ones grants PW1 access on power-on without
writing the password entry. All reads of this register are 00h.
FACTORY DEFAULT FFFF FFFFh
READ ACCESS N/A
WRITE ACCESS PW2
MEMORY TYPE Nonvolatile (SEE)
B4h 231 230 2
29 2
28 2
27 2
26 2
25 2
24
B5h 223 2
22 2
21 2
20 2
19 2
18 2
17 2
16
B6h 215 214 2
13 2
12 2
11 2
10 2
9 2
8
B7h 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the
PWE value is set to all ones. Thus, writing these bytes to all ones grants PW2 access on power-on without
writing the password entry. All reads of this register are 00h.
Table 02h, Register B4h–B7h: PW2
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SFP+ Controller with Analog LDD Interface
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Table 02h, Register B8h: LOS RANGING
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
B8h RESERVED HLOS2 HLOS1 HLOS0 RESERVED LLOS2 LLOS1 LLOS0
BIT 7 BIT 0
This register controls the full-scale range of the quick-trip monitoring for the differential input’s of MON3.
BIT 7 RESERVED (Default = 0)
BITS 6:4
HLOS[2:0]: HLOS Full-Scale Ranging. 3-bit value to select the FS comparison voltage for high LOS
found on MON3. Default is 000b and creates an FS of 1.25V.
HLOS[2:0] % of 1.25V FS Voltage
000b 100.00 1.250
001b 80.00 1.000
010b 66.67 0.833
011b 50.00 0.625
100b 40.00 0.500
101b 33.33 0.417
110b 28.57 0.357
111b 25.00 0.313
BIT 3 RESERVED (Default = 0)
BITS 2:0
LLOS[2:0]: LLOS Full-Scale Ranging. 3-bit value to select the FS comparison voltage for low LOS
found on MON3. Default is 000b and creates an FS of 1.25V.
LLOS[2:0] % of 1.25V FS Voltage
000b 100.00 1.250
001b 80.00 1.000
010b 66.67 0.833
011b 50.00 0.625
100b 40.00 0.500
101b 33.33 0.417
110b 28.57 0.357
111b 25.00 0.313
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SFP+ Controller with Analog LDD Interface
68 ______________________________________________________________________________________
Table 02h, Register B9h: COMP RANGING
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
B9h RESERVED HBIAS2 HBIAS1 HBIAS0 RESERVED APC2 APC1 APC0
BIT 7 BIT 0
The upper nibble of this byte controls the full-scale range of the quick-trip monitoring for BIAS. The lower nibble of
this byte controls the full-scale range for the quick-trip monitoring of the APC reference as well as the closed-loop
monitoring of APC.
BIT 7 RESERVED (Default = 0)
BITS 6:4
HBIAS[2:0]: HBIAS Full-Scale Ranging. 3-bit value to select the FS comparison voltage for BIAS
found on MON1. Default is 000b and creates an FS of 1.25V.
HBIAS[2:0] % of 1.25V FS Voltage
000b 100.00 1.250
001b 80.00 1.000
010b 66.67 0.833
011b 50.00 0.625
100b 40.00 0.500
101b 33.33 0.417
110b 28.57 0.357
111b 25.00 0.313
BIT 3 RESERVED (Default = 0)
BITS 2:0
APC[2:0]: APC Full-Scale Ranging. 3-bit value to select the FS comparison voltage for MON2 with
the APC. Default is 000b and creates an FS of 2.5V.
APC[2:0] % of 2.50V FS Voltage
000b 100.00 2.500
001b 80.00 2.000
010b 66.67 1.667
011b 50.00 1.250
100b 40.00 1.000
101b 33.33 0.833
110b 28.57 0.714
111b 25.00 0.625
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SFP+ Controller with Analog LDD Interface
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Table 02h, Register BAh: IBIASMAX
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
BAh 29 2
8 2
7 2
6 2
5 2
4 2
322
BIT 7 BIT 0
This value defines the maximum DAC value allowed for the upper 8 bits of BIAS output during APC closed-loop
operations. During the intial step and binary search, this value does not cause an alarm, but does still clamp the
BIAS DAC value. After the startup sequence (or normal APC operations), if the APC loop tries to create a BIAS
value greater than this setting, it is clamped and creates a MAX BIAS alarm.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
BBh 29 2
8 2
7 2
6 2
5 2
4 2
3 2
2
BIT 7 BIT 0
The initial step value used at power-on or after a TXD pulse to control the BIAS DAC. At startup, this value plus
20 = 1 is continuously added to the BIAS DAC value until the APC feedback (MON2) is greater than its threshold.
At that time, a binary search is used to complete the startup of the APC closed loop. If the resulting math
operation is greater than IBIASMAX (Table 02h, Register BAh), the result is not loaded into the BIAS DAC, but the
binary search is begun to complete the initial search for APC. During startup, the BIAS DAC steps causing a
higher bias value than IBIASMAX do not create the BIAS MAX alarm. The BIAS MAX alarm detection is enabled at
the end of the binary search.
Table 02h, Register BBh: ISTEP
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SFP+ Controller with Analog LDD Interface
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Table 02h, Register BDh: LTXP
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
BDh 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Fast-comparison DAC threshold adjust for low TXP. This value is subtracted from the APC DAC value recalled
from Table 06h. If the difference is less than 0x00, 0x00 is used. Comparisons less than VLTXP, compared
against VMON2, create a TXP LO alarm. The same ranging applied to the APC DAC should be used here.
V
LTXP
=Full Scale
255
APC DAC LTXP
()
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
BCh 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Fast-comparison DAC threshold adjust for high TXP. This value is added to the APC DAC value recalled from
Table 06h. If the sum is greater than 0xFF, 0xFF is used. Comparisons greater than VHTXP, compared against
VMON2, create a TXP HI alarm. The same ranging applied to the APC DAC should be used here.
V
HTXP
=Full Scale
255
HTXP +APC DAC
()
Table 02h, Register BCh: HTXP
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SFP+ Controller with Analog LDD Interface
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FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
BEh 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Fast-comparison DAC threshold adjust for high LOS. The combination of HLOS and LLOS creates a hysteresis
comparator. As RSSI falls below the LLOS threshold, the LOS LO alarm bit is set to 1. The LOS alarm remains set
until the RSSI input is found above the HLOS threshold setting, which clears the LOS LO alarm bit and sets the
LOS HI alarm bit. At power-on, both LOS LO and LOS HI alarm bits are 0 and the hysteresis comparator uses the
LLOS threshold setting.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
BFh 2726 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Fast-comparison DAC threshold adjust for low LOS. See HLOS (Table 02h, Register BEh) for functional description.
Table 02h, Register BEh: HLOS
Table 02h, Register BFh: LLOS
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SFP+ Controller with Analog LDD Interface
72 ______________________________________________________________________________________
Table 02h, Register C0h: PW_ENA
FACTORY DEFAULT 10h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
C0h RWTBL78 RWTBL1C RWTBL2 RWTBL1A RWTBL1B WLOWER WAUXA WAUXB
BIT 7 BIT 0
BIT 7
RWTBL78: Tables 07h–08h
0 = (Default) Read and write access for PW2 only.
1 = Read and write access for both PW1 and PW2.
BIT 6
RWTBL1C: Table 01h or 05h bytes F8h–FFh. Table address is dependent on MASK bit (Table 02h,
Register 89h).
0 = (Default) Read and write access for PW2 only.
1 = Read and write access for both PW1 and PW2.
BIT 5
RWTBL2: Tables 02h. Writing a nonvolatile value to this bit requires PW2 access.
0 = (Default) Read and write access for PW2 only.
1 = Read and write access for both PW1 and PW2.
BIT 4
RWTBL1A: Table 01h, Registers 80h–BFh
0 = Read and write access for PW2 only.
1 = (Default) Read and write access for both PW1 and PW2.
BIT 3
RWTBL1B: Table 01h, Registers C0h–F7h
0 = (Default) Read and write access for PW2 only.
1 = Read and write access for both PW1 and PW2.
BIT 2
WLOWER: Bytes 00h–5Fh in main memory. All users can read this area.
0 = (Default) Write access for PW2 only.
1 = Write access for both PW1 and PW2.
BIT 1
WAUXA: Auxiliary Memory, Registers 00h–7Fh. All users can read this area.
0 = (Default) Write access for PW2 only.
1 = Write access for both PW1 and PW2.
BIT 0
WAUXB: Auxiliary Memory, Registers 80h–FFh. All users can read this area.
0 = (Default) Write access for PW2 only.
1 = Write access for both PW1 and PW2.
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SFP+ Controller with Analog LDD Interface
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Table 02h, Register C1h: PW_ENB
FACTORY DEFAULT 03h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
C1h RWTBL46 RTBL1C RTBL2 RTBL1A RTBL1B WPW1 WAUXAU WAUXBU
BIT 7 BIT 0
BIT 7
RWTBL46: Tables 04h and 06h
0 = (Default) Read and write access for PW2 only.
1 = Read and write access for PW1.
BIT 6
RTBL1C: Table 01h or Table 05h, Registers F8h–FFh. Table address is dependent on MASK bit
(Table 02h, Register 89h).
0 = (Default) Read access for PW2 only.
1 = Read access for PW1.
BIT 5
RTBL2: Table 02h
0 = (Default) Read access for PW2 only.
1 = Read access for PW1.
BIT 4
RTBL1A: Table 01h, Registers 80h–BFh
0 = (Default) Read access for PW2 only.
1 = Read access for PW1.
BIT 3
RTBL1B: Table 01h, Registers C0h–F7h
0 = (Default) Read access for PW2 only.
1 = Read access for PW1.
BIT 2
WPW1: Register PW1 (Table 02h, Registers B0h–B3h). For security purposes these registers are
not readable.
0 = (Default) Write access for PW2 only.
1 = Write access for PW1.
BIT 1
WAUXAU: Auxiliary Memory, Registers 00h–7Fh. All users can read this area.
0 = Write access for PW2 only.
1 = (Default) Write access for user, PW1 and PW2.
BIT 0
WAUXBU: Auxiliary Memory, Registers 80h–FFh. All users can read this area.
0 = Write access for PW2 only.
1 = (Default) Write access for user, PW1 and PW2.
Table 02h, Register C2h–C5h: RESERVED
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
These registers are reserved.
DS1873
SFP+ Controller with Analog LDD Interface
74 ______________________________________________________________________________________
Table 02h, Register C6h: POLARITY
FACTORY DEFAULT 0Ch
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
C6h RESERVED RESERVED RESERVED RESERVED MODP BIASP DAC1P DAC2P
BIT 7 BIT 0
BITS 7:4 RESERVED
BIT 3
MODP: MOD DAC Polarity. The MOD DAC (Table 02h, Registers 82h–83h) range is 000h–3FFh. A
setting of 000h creates a pulse density of zero and 3FFh creates a pulse density of 1023/1024. This
polarity bit allows the user to use GND or VREFIN as the reference. The power-on of MOD DAC is 000h,
thus an application that needs VREFIN to be in off state should use the inverted polarity.
0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND and a
setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN.
1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN and a
setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND.
BIT 2
BIASP: BIAS DAC Polarity. The BIAS DAC (Table 02h, Registers CBh–CCh) range is 000h–3FFh. A
setting of 000h creates a pulse density of zero and 3FFh creates a pulse density of 1023/1024. This
polarity bit allows the user to use GND or VREFIN as the reference. The power-on of BIAS DAC is 000h,
thus an application that needs VREFIN to be the off state should use the inverted polarity.
0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND and a
setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN.
1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN and a
setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND.
BIT 1
DAC1P: DAC1 VALUE Polarity. The DAC1 VALUE (Table 02h, Registers 84h–85h) range is 000h–
3FFh. A setting of 000h creates a pulse density of zero and 3FFh creates a pulse density of
1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of
DAC1 VALUE is 000h, thus an application that needs VREFIN to be the off state should use the
inverted polarity.
0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND and a
setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN.
1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN and a
setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND.
BIT 0
DAC2P: DAC2 VALUE Polarity. The DAC2 VALUE (Table 02h, Registers 86h–87h) range is 000h–
3FFh. A setting of 000h creates a pulse-density of zero and 3FFh creates a pulse density of
1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of
DAC2 VALUE is 000h, thus an application that needs VREFIN to be the off state should use the
inverted polarity.
0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND and a
setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN.
1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN and a
setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND.
DS1873
SFP+ Controller with Analog LDD Interface
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Table 02h, Register C7h: TBLSELPON
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
C7h 2726 2
52423222120
BIT 7 BIT 0
Chooses the initial value for the table-select byte (Lower Memory, Register 7Fh) at power-on.
FACTORY DEFAULT 0000h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS (PW2 and BIAS EN = 0) or (PW1 and RWTBL2 and BIAS EN = 0)
MEMORY TYPE Volatile
C8h 0 0 0 0 0 0 0 28
C9h 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
When BIAS EN (Table 02h, Register 80h) is written to 0, writes to these bytes control the BIAS DAC.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS (PW2 and BIAS EN = 0) or (PW1 and RWTBL2 and BIAS EN = 0)
MEMORY TYPE Volatile
CAh RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED MAN_CLK
BIT 7 BIT 0
When BIAS EN (Table 02h, Register 80h) is written to 0, MAN_CLK controls the updates of the MAN BIAS value to
the BIAS DAC. The values of MAN BIAS must be written with a separate write command. Setting MAN_CLK to a 1
clocks the MAN BIAS value to the BIAS DAC.
1) Write the MAN BIAS value with a write command.
2) Set the MAN_CLK bit to a 1 with a separate write command.
3) Clear the MAN_CLK bit to a 0 with a separate write command.
Table 02h, Register C8h–C9h: MAN BIAS
Table 02h, Register CAh: MAN_CNTL
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SFP+ Controller with Analog LDD Interface
76 ______________________________________________________________________________________
Table 02h, Register CBh–CCh: BIAS DAC
FACTORY DEFAULT 0000h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS N/A
MEMORY TYPE Volatile
CBh RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 29 2
8
CCh 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
The digital value used for BIAS and resolved from the APC. This register is updated after each decision of the
APC loop.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS N/A
MEMORY TYPE N/A
This register is reserved.
FACTORY DEFAULT 73h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS N/A
MEMORY TYPE ROM
CEh 0 1 1 1 0 0 1 1
BIT 7 BIT 0
Hardwired connections to show the device ID.
Table 02h, Register CDh: RESERVED
Table 02h, Register CEh: DEVICE ID
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SFP+ Controller with Analog LDD Interface
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Table 02h, Register CFh: DEVICE VER
FACTORY DEFAULT DEVICE VERSION
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS N/A
MEMORY TYPE ROM
CFh DEVICE VERSION
BIT 7 BIT 0
Hardwired connections to show the device version.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS (PW2 and APC EN = 0) or (PW1 and RWTBL2 and APC EN = 0)
MEMORY TYPE Volatile
D0h 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
The digital value used for APC reference and recalled from Table 06h at the adjusted memory address found in
TINDEX. This register is updated at the end of the temperature conversion.
Table 02h, Register D0h: APC DAC
DS1873
SFP+ Controller with Analog LDD Interface
78 ______________________________________________________________________________________
Table 02h, Register D2h–D7h: RESERVED
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS (PW2 and APC EN = 0) or (PW1 and RWTBL2 and APC EN = 0)
MEMORY TYPE Volatile
D1h 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
The digital value used for HBIAS reference and recalled from Table 06h at the adjusted memory address found
in TINDEX. This register is updated at the end of the temperature conversion.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS N/A
MEMORY TYPE N/A
These registers are reserved.
FACTORY DEFAULT 00h
READ ACCESS N/A
WRITE ACCESS N/A
MEMORY TYPE None
These registers do not exist.
Table 02h, Register D1h: HBIAS DAC
Table 02h, Register D8h–FFh: EMPTY
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SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 79
Table 04h, Register F8h–FFh: MOD OFFSET LUT
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL46) or (PW1 and RTBL46)
WRITE ACCESS PW2 or (PW1 and RWTBL46)
MEMORY TYPE Nonvolatile (EE)
F8h–FFh 29 2
8 2
7 2
6 2
5 2
4 2
3 2
2
BIT 7 BIT 0
The digital value for the temperature offset of the MOD DAC output.
F8h Less than or equal to -8°C
F9h Greater than -8°C up to +8°C
FAh Greater than +8°C up to +24°C
FBh Greater than +24°C up to +40°C
FCh Greater than +40°C up to +56°C
FDh Greater than +56°C up to +72°C
FEh Greater than +72°C up to +88°C
FFh Greater than +88°C
The MOD DAC is a 10-bit register. The MODULATION LUT is an 8-bit LUT. The MOD OFFSET LUT times 4 plus
the MODULATION LUT makes use of the entire 10-bit range.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL46) or (PW1 and RTBL46)
WRITE ACCESS PW2 or (PW1 and RWTBL46)
MEMORY TYPE Nonvolatile (EE)
80h–C7h 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
The digital value for the modulation DAC output.
The MODULATION LUT is a set of registers assigned to hold the temperature profile for the MOD DAC. The
values in this table determine the set point for the modulation voltage. The temperature measurement is used to
index the LUT (TINDEX, Table 02h, Register 81h) in 2°C increments from -40°C to +102°C, starting at 80h in
Table 04h. Register 80h defines the -40°C to -38°C MOD output, Register 81h defines the -38°C to -36°C MOD
output, and so on. Values recalled from this EEPROM memory table are written into the MOD DAC (Table 02h,
Register 82h–83h) location that holds the value until the next temperature conversion. The DS1873 can be
placed into a manual mode (MOD EN bit, Table 02h, Register 80h), where the MOD DAC is directly controlled for
calibration. If the temperature compensation functionality is not required, then program the entire Table 04h to the
desired modulation setting.
Table 04h Register Description
Table 04h, Register 80h–C7h: MODULATION LUT
DS1873
SFP+ Controller with Analog LDD Interface
80 ______________________________________________________________________________________
Table 06h Register Descriptions
Table 06h, Register 80h–A3h: APC LUT
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL46) or (PW1 and RTBL46)
WRITE ACCESS PW2 or (PW1 and RWTBL46)
MEMORY TYPE Nonvolatile (EE)
80h–A3h 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
The APC LUT is a set of registers assigned to hold the temperature profile for the APC reference DAC. The
values in this table combined with the APC bits in the COMP RANGING register (Table 02h, Register B9h)
determine the set point for the APC loop. The temperature measurement is used to index the LUT (TINDEX, Table
02h, Register 81h) in 4°C increments from -40°C to +100°C, starting at Register 80h. Register 80h defines the
-40°C to -36°C APC reference value, Register 81h defines the -36°C to -32°C APC reference value, and so on.
Values recalled from this EEPROM memory table are written into the APC DAC (Table 02h, Register D0h) location
that holds the value until the next temperature conversion. The DS1873 can be placed into a manual mode (APC
EN bit, Table 02h, Register 80h), where APC DAC can be directly controlled for calibration. If TE temperature
compensation is not required by the application, program the entire LUT to the desired APC set point.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL46) or (PW1 and RTBL46)
WRITE ACCESS PW2 or (PW1 and RWTBL46)
MEMORY TYPE Nonvolatile (EE)
These registers are reserved.
Table 06h, Register A4h–A7h: RESERVED
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SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 81
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL46) or (PW1 and RTBL46)
WRITE ACCESS PW2 or (PW1 and RWTBL46)
MEMORY TYPE Nonvolatile (EE)
F8h–FFh 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
High bias alarm threshold (HBATH) is a digital clamp used to ensure that the DAC setting for BIAS currents does
not exceed a set value. The table below shows the range of temp for each byte’s location. The table shows a
rising temperature; for a falling temperature there is 1°C of hysteresis.
F8h Less than or equal to -8°C
F9h Greater than -8°C up to +8°C
FAh Greater than +8°C up to +24°C
FBh Greater than +24°C up to +40°C
FCh Greater than +40°C up to +56°C
FDh Greater than +56°C up to +72°C
FEh Greater than +72°C up to +88°C
FFh Greater than +88°C
Table 06h, Register F8h–FFh: HBIAS LUT
Table 07h Register Descriptions
Table 07h, Register 80h–C7h: DAC1 LUT
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78)
WRITE ACCESS PW2 or (PW1 and RWTBL78)
MEMORY TYPE Nonvolatile (EE)
80h–C7h 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
The DAC1 LUT is a set of registers assigned to hold the PWM profile for DAC1. The values in this table
determine the set point for DAC1. The temperature measurement is used to index the LUT (TINDEX, Table 02h,
Register 81h) in 2°C increments from -40°C to +102°C, starting at Register 80h in Table 07h. Register 80h
defines the -40°C to -38°C DAC1 value, Register 81h defines -38°C to -36°C DAC1 value, and so on. Values
recalled from this EEPROM memory table are written into the DAC1 VALUE (Table 02h, Registers 84h–85h)
location, which holds the value until the next temperature conversion. The part can be placed into a manual
mode (DAC1 EN bit, Table 02h, Register 80h), where DAC1 can be directly controlled for calibration. If
temperature compensation is not required by the application, program the entire LUT to the desired DAC1 set
point.
DS1873
SFP+ Controller with Analog LDD Interface
82 ______________________________________________________________________________________
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78)
WRITE ACCESS PW2 or (PW1 and RWTBL78)
MEMORY TYPE Nonvolatile (EE)
F8h–FFh 29 2
8 2
7 2
6 2
5 2
4 2
3 2
2
BIT 7 BIT 0
The digital value for the temperature offset of the DAC1 output.
F8h Less than or equal to -8°C
F9h Greater than -8°C up to +8°C
FAh Greater than +8°C up to +24°C
FBh Greater than +24°C up to +40°C
FCh Greater than +40°C up to +56°C
FDh Greater than +56°C up to +72°C
FEh Greater than +72°C up to +88°C
FFh Greater than +88°C
The DAC1 VALUE is a 10-bit register. The DAC1 LUT is an 8-bit LUT. The DAC1 OFFSET LUT times 4 plus the
DAC1 LUT makes use of the entire 10-bit range.
Table 07h, Register F8h–FFh: DAC1 OFFSET LUT
FACTORY DEFAULT 00h
READ ACCESS N/A
WRITE ACCESS N/A
MEMORY TYPE None
These registers do not exist.
Table 07h, Register C8h–F7h: EMPTY
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SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 83
Table 08h Register Descriptions
Table 08h, Register 80h–A3h: DAC2 LUT
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78)
WRITE ACCESS PW2 or (PW1 and RWTBL78)
MEMORY TYPE Nonvolatile (EE)
80h–A3h 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
The DAC2 LUT is set of registers assigned to hold the PWM profile for DAC2. The values in this table determine
the set point for DAC2. The temperature measurement is used to index the LUT (TINDEX, Table 02h, Register
81h) in 4°C increments from -40°C to +100°C, starting at Register 80h. Register 80h defines the -40°C to -36°C
DAC2 value, Register 81h defines -36°C to -32°C DAC2 value, and so on. Values recalled from this EEPROM
memory table are written into the DAC2 VALUE (Table 02h, Registers 86h–87h) location that holds the value until
the next temperature conversion. The DS1873 can be placed into a manual mode (DAC2 EN bit, Table 02h,
Register 80h), where DAC2 can be directly controlled for calibration. If temperature compensation is not required
by the application, program the entire LUT to the desired DAC2 set point.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78)
WRITE ACCESS PW2 or (PW1 and RWTBL78)
MEMORY TYPE Nonvolatile (EE)
These registers are reserved.
Table 08h, Register A4h–A7h: RESERVED
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SFP+ Controller with Analog LDD Interface
84 ______________________________________________________________________________________
FACTORY DEFAULT 00h
READ ACCESS ALL
WRITE ACCESS PW2 or (PW1 and WAUXA) or WAUXAU
MEMORY TYPE Nonvolatile (EE)
00h–7Fh 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Accessible with the slave address A0h.
Auxiliary Memory A0h Register Descriptions
Auxiliary Memory A0h, Register 00h–7Fh: EEPROM
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78)
WRITE ACCESS PW2 or (PW1 and RWTBL78)
MEMORY TYPE Nonvolatile (EE)
F8h–FFh 29 2
8 2
7 2
6 2
5 2
4 2
3 2
2
BIT 7 BIT 0
The digital value for the temperature offset of the DAC2 output.
F8h Less than or equal to -8°C
F9h Greater than -8°C up to +8°C
FAh Greater than +8°C up to +24°C
FBh Greater than +24°C up to +40°C
FCh Greater than +40°C up to +56°C
FDh Greater than +56°C up to +72°C
FEh Greater than +72°C up to +88°C
FFh Greater than +88°C
The DAC2 VALUE is a 10-bit register. The DAC2 LUT is an 8-bit LUT. The DAC2 OFFSET LUT times 4 plus the
DAC2 LUT makes use of the entire 10-bit range.
Table 08h, Register F8h–FFh: DAC2 OFFSET LUT
DS1873
SFP+ Controller with Analog LDD Interface
______________________________________________________________________________________ 85
Applications Information
Power-Supply Decoupling
To achieve best results, it is recommended that the power
supply is decoupled with a 0.01µF or a 0.1µF capacitor.
Use high-quality, ceramic, surface-mount capacitors,
and mount the capacitors as close as possible to the
VCC and GND pins to minimize lead inductance.
SDA and SCL Pullup Resistors
SDA is an open-collector output on the DS1873 that
requires a pullup resistor to realize high logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be uti-
lized for SCL. Pullup resistor values should be chosen
to ensure that the rise and fall times listed in the
I
2
C AC
Electrical Characteristics
table are within specification.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 TQFN-EP T2855+6 21-0140
FACTORY DEFAULT 00h
READ ACCESS ALL
WRITE ACCESS PW2 or (PW1 and RWAUXB) or RWAUXBU
MEMORY TYPE Nonvolatile (EE)
80h–FFh 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Accessible with the slave address A0h.
Auxiliary Memory A0h, Register 80h–FFh: EEPROM
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
DS1873
SFP+ Controller with Analog LDD Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
86
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/09 Initial release. —
Changed the default state for the TXDIO bit in Table 02h, Register 8Bh: CNFGC. 60
1 11/09
Corrected the factory default value for Table 02h, Register C6h: POLARITY from
00h to 0Ch. 74
