MAX1282EVC16 - Maxim Integrated

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MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

________________________________________________________________ Maxim Integrated Products 1

VDD1 VDD2

SCLK

DIN

SSTRB

DOUT

GND

REFADJ

TOP VIEW

MAX1282/

MAX1283

TSSOP

CH0

CH1

COM

CH2

CH3

SHDN

REF

19-1688; Rev 0; 5/00

Typical Operating Circuit appears at end of data sheet.

Pin Configuration

Ordering Information

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

General Description

The MAX1282/MAX1283 12-bit analog-to-digital convert-

ers (ADCs) combine a 4-channel analog-input multiplexer,

high-bandwidth track/hold (T/H), and serial interface with

high conversion speed and low power consumption. The

MAX1282 operates from a single +4.5V to +5.5V supply;

the MAX1283 operates from a single +2.7V to +3.6V sup-

ply. Both devices’ analog inputs are software configurable

for unipolar/bipolar and single-ended/pseudo-differential

operation.

The 4-wire serial interface connects directly to

SPI™/QSPI™/MICROWIRE™ devices without external

logic. A serial strobe output allows direct connection to

TMS320-family digital signal processors. The MAX1282/

MAX1283 use an external serial-interface clock to perform

successive-approximation analog-to-digital conversions.

The devices feature an internal +2.5V reference and a ref-

erence-buffer amplifier with a ±1.5% voltage-adjustment

range. An external reference with a 1V to VDD range may

also be used.

The MAX1282/MAX1283 provide a hardwired SHDN pin

and four software-selectable power modes (normal opera-

tion, reduced power (REDP), fast power-down (FASTPD),

and full power-down (FULLPD)). These devices can be

programmed to automatically shut down at the end of a

conversion or to operate with reduced power. When using

the power-down modes, accessing the serial interface

automatically powers up the devices, and the quick turn-

on time allows them to be shut down between all conver-

sions.

The MAX1282/MAX1283 are available in 16-pin TSSOP

packages.

Applications

Portable Data Logging

Data Acquisition

Medical Instruments

Battery-Powered Instruments

Pen Digitizers

Process Control

Features

♦4-Channel Single-Ended or 2-Channel

Pseudo-Differential Inputs

♦Internal Multiplexer and Track/Hold

♦Single-Supply Operation

+4.5V to +5.5V (MAX1282)

+2.7V to +3.6V (MAX1283)

♦Internal +2.5V Reference

♦400kHz Sampling Rate (MAX1282)

♦Low Power: 2.5mA (400ksps)

1.3mA (REDP)

0.9mA (FASTPD)

2µA (FULLPD)

♦SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire

Serial Interface

♦Software-Configurable Unipolar or Bipolar Inputs

♦16-Pin TSSOP Package

±116 TSSOP0°C to +70°C

MAX1283BCUE

±116 TSSOP-40°C to +85°CMAX1283BEUE

±116 TSSOP-40°C to +85°CMAX1282BEUE

INL

(LSB)

PIN-

PACKAGE

TEMP.

RANGE

PART

±116 TSSOP0°C to +70°C

MAX1282BCUE

EVALUATION KIT

AVAILABLE

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS—MAX1282

(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fOSC = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD_ to GND ........................................................... -0.3V to +6V

VDD1 to VDD2 ....................................................... -0.3V to +0.3V

CH0–CH3, COM to GND .......................... -0.3V to (VDD_ +0.3V)

REF, REFADJ to GND................................ -0.3V to VDD_ +0.3V)

Digital Inputs to GND .............................................. -0.3V to +6V

Digital Outputs to GND............................. -0.3V to (VDD_ +0.3V)

Digital Output Sink Current .................................................25mA

Continuous Power Dissipation (TA= +70°C)

16-Pin TSSOP (derate 6.7mW/°C above +70°C) ........ 535mW

Operating Temperature Ranges

MAX1282BCUE/MAX1283BCUE ....................... 0°C to +70°C

MAX1282BEUE/MAX1283BEUE..................... -40°C to +85°C

Storage Temperature Range ............................ -60°C to +150°C

Lead Temperature (soldering, 10s) ................................ +300°C

SINAD > 68dB

-3dB point

200kHz, VIN = 2.5Vp-p

fIN1 = 99kHz, fIN2 =102kHz

No missing codes over temperature

Up to the 5th harmonic

CONDITIONS

MHz

0.5 6.4

fSCLK

Serial Clock Frequency

<50

Aperture Jitter

Aperture Delay

400

tACQ

Track/Hold Acquisition Time

µs

2.5

tCONV

Conversion Time (Note 5)

kHz

350

Full-Linear Bandwidth

MHz

Full-Power Bandwidth

-78

Channel-to-Channel Crosstalk

(Note 4)

IMDIntermodulation Distortion

SFDRSpurious-Free Dynamic Range

-81

THDTotal Harmonic Distortion

Bits

Resolution

SINAD

Signal-to-Noise plus Distortion

Ratio

LSB

±0.2

Channel-to-Channel Offset-Error

Matching

ppm/°C

±1.6

Gain-Error Temperature

Coefficient

±1.0

LSB

±1.0

DNLDifferential Nonlinearity

LSB

±6.0

Offset Error

LSB

±6.0

Gain Error (Note 3)

UNITSMIN TYP MAXSYMBOLPARAMETER

40 60

Duty Cycle

DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)

DC ACCURACY (Note 1)

CONVERSION RATE

LSBINLRelative Accuracy (Note 2)

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS—MAX1282 (continued)

(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fOSC = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

To power down the internal reference

For small adjustments, from 1.22V

0 to 1mA output load

On/off leakage current, VCOM, VCH_ = 0 or

VDD1

TA= +25°C

Bipolar, VCOM or VCH_ = VREF/2, referenced

to COM or CH_

Unipolar, VCOM = 0

V/V

+2.05

Buffer Voltage Gain

1.4 VDD1 - 1.0

REFADJ Buffer Disable

Threshold

±100

REFADJ Input Range

1.22

REFADJ Output Voltage

µF

0.01 10

Capacitive Bypass at REFADJ

µF

4.7 10

Capacitive Bypass at REF

mV/mA

0.05 2.0

Load Regulation (Note 7)

ppm/°C

±15

TC VREF

REF Output Temperature

Coefficient

REF Short-Circuit Current

2.480 2.500 2.520

VREF

REF Output Voltage

pF18Input Capacitance

µA

±0.001 ±1

Multiplexer Leakage Current

±VREF/2 V

VREF

VCH_

Input Voltage Range, Single-

Ended and Differential (Note 6)

VIN = 0 or VDD2

In full power-down mode, fSCLK = 0

VREF = 2.500V, fSCLK = 0

VREF = 2.500V, fSCLK = fMAX

(Note 8)

pFCIN

Input Capacitance

µA±1IIN

Input Leakage

V0.2VHYST

Input Hysteresis

V0.8VINL

Input Low Voltage

V3.0VINH

Input High Voltage

320 µA

200 350

REF Input Current

1.0 VDD1 +

50mV

REF Input Voltage Range

ISINK = 5mA V0.4VOL

Output Voltage Low

ISOURCE = 1mA V4VOH

Output Voltage High

CS = VDD2 µA±10IL

Three-State Leakage Current

CS = VDD2 pF15COUT

Three-State Output Capacitance

ANALOG INPUTS (CH3–CH0, COM)

EXTERNAL REFERENCE (reference buffer disabled, reference applied to REF)

INTERNAL REFERENCE

DIGITAL INPUTS (DIN, SCLK, CS, SHDN)

DIGITAL OUTPUTS (DOUT, SSTRB)

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

4 _______________________________________________________________________________________

VDD1 =

VDD2 =

5.5V

VDD1 = VDD2 = 5V ±10%, midscale input

CONDITIONS

2.5 4.0

IVDD1+

IVDD2

Supply Current

V4.5 5.5

VDD1,

VDD2

Positive Supply Voltage

(Note 9)

1.3 2.0

0.9 1.5

µA2.0 10

mV±0.5 ±2.0PSRPower-Supply Rejection

UNITSMIN TYP MAXSYMBOLPARAMETER

Normal operating mode (Note 10)

Reduced-power mode (Note 11)

Fast power-down mode (Note 11)

Full power-down mode (Note 11)

ELECTRICAL CHARACTERISTICS—MAX1282 (continued)

(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fOSC = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

ELECTRICAL CHARACTERISTICS—MAX1283

(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fOSC = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

SINAD > 68dB

-3dB point

f = 150kHz, VIN = 2.5Vp-p

fIN1 = 73kHz, fIN2 = 77kHz

No missing codes over temperature

Up to the 5th harmonic

CONDITIONS

kHz

250

Full-Linear Bandwidth

MHz

Full-Power Bandwidth

-78

Channel-to-Channel Crosstalk

(Note 4)

IMDIntermodulation Distortion

SFDRSpurious-Free Dynamic Range

-70

THDTotal Harmonic Distortion

Bits

Resolution

SINAD

Signal-to-Noise plus Distortion

Ratio

LSB

±0.2

Channel-to-Channel Offset-Error

Matching

ppm/°C

±1.6

Gain-Error Temperature

Coefficient

±1.0

LSB

±1.0

DNLDifferential Nonlinearity

LSB

±6.0

Offset Error

LSB

±6.0

Gain Error (Note 3)

UNITSMIN TYP MAXSYMBOLPARAMETER

POWER SUPPLY

LSB

INLRelative Accuracy (Note 2)

DC ACCURACY (Note 1)

DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS—MAX1283 (continued)

(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fOSC = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

Normal operating mode

CONDITIONS

MHz

0.5 4.8

fSCLK

Serial Clock Frequency

<50

Aperture Jitter

Aperture Delay

625

tACQ

Track/Hold Acquisition Time

µs

3.3

tCONV

Conversion Time (Note 5)

UNITSMIN TYP MAXSYMBOLPARAMETER

To power down the internal reference

For small adjustments, from 1.22V

0 to 0.75mA output load

On/off leakage current, VCH_ = 0 or VDD1

TA= +25°C

Bipolar, VCOM or VCH_ = VREF/2,

referenced to COM or CH_

Unipolar, VCOM = 0

V/V

2.05

Buffer Voltage Gain

1.4 VDD1 - 1.0

REFADJ Buffer Disable

Threshold

±100

REFADJ Input Range

1.22

REFADJ Output Voltage

µF

0.01 10

Capacitive Bypass at REFADJ

µF

4.7 10

Capacitive Bypass at REF

mV/mA

0.1 2.0

Load Regulation (Note 7)

ppm/°C

±15

TC VREF

REF Output Temperature

Coefficient

REF Short-Circuit Current

2.480 2.500 2.520

VREF

REF Output Voltage

pF18Input Capacitance

µA

±0.001 ±1

Multiplexer Leakage Current

±VREF/2

40 60

Duty Cycle

VREF

VCH_

Input Voltage Range, Single

Ended and Differential (Note 6)

VIN = 0 or VDD2

In full power-down mode, fSCLK = 0

VREF = 2.500V, fSCLK = 0

VREF = 2.500V, fSCLK = fMAX

(Note 8)

CIN

Input Capacitance

µA

±1

IIN

Input Leakage

0.2

VHYST

Input Hysteresis

0.8

VINL

Input Low Voltage

2.0

VINH

Input High Voltage

REF Input Current 320 µA

200 350

1.0 VDD1 +

50mV

REF Input Voltage Range

V/V

2.05

Buffer Voltage Gain

CONVERSION RATE

ANALOG INPUTS (CH3–CH0, COM)

INTERNAL REFERENCE

EXTERNAL REFERENCE (reference buffer disabled, reference applied to REF)

DIGITAL INPUTS (DIN, SCLK, CS, SHDN)

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

6 _______________________________________________________________________________________

VDD1 =

VDD2 =

3.6V

ISOURCE = 0.5mA

VDD1 = VDD2 = 2.7V to 3.6V, midscale input

CONDITIONS

2.5 3.5

IVDD1 +

IVDD2

Supply Current

V2.7 3.6

VDD1,

VDD2

VVDD2 - 0.5VVOH

Output Voltage High

Positive Supply Voltage

(Note 9)

1.3 2.0

Normal operating mode (Note 10)

Reduced-power mode (Note 11)

0.9 1.5Fast power-down mode (Note 11)

Full power-down mode (Note 11) µA2.0 10

mV±0.5 ±2.0PSRPower-Supply Rejection

UNITSMIN TYP MAXSYMBOLPARAMETER

ISINK = 5mA V0.4VOL

Output Voltage Low

CS = VDD2 µA±10IL

Three-State Leakage Current

CS = VDD2 pF15COUT

Three-State Output Capacitance

ELECTRICAL CHARACTERISTICS—MAX1283 (continued)

(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fOSC = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external

+2.5V at REF, REFADJ = VDD1, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

TIMING CHARACTERISTICS—MAX1282

(Figures 1, 2, 5, 6; VDD1 = VDD2 = +4.5V to +5.5V, TA= TMIN to TMAX, unless otherwise noted.)

CLOAD = 20pF

CONDITIONS

100

tCSW

CS Pulse Width High

tSTE

CS Fall to SSTRB Enable

tDOE

CS Fall to DOUT Enable

10 65

tSTD

CS Rise to SSTRB Disable

10 65

tDOD

CS Rise to DOUT Disable

tSTV

SCLK Rise to SSTRB Valid

tDOV

SCLK Rise to DOUT Valid

tCL

SCLK Pulse Width Low

tCH

156

tCP

SCLK Period

SCLK Pulse Width High

10 20

tSTH

SCLK Rise to SSTRB Hold

10 20

tDOH

SCLK Rise to DOUT Hold

tCS1

CS Rise to SCLK Rise Ignore

tCSO

SCLK Rise to CS Fall Ignore

tDS

DIN to SCLK Setup

tDH

DIN to SCLK Hold

tCSS

CS Fall to SCLK Rise Setup

tCSH

SCLK Rise to CS Rise Hold

UNITSMIN TYP MAXSYMBOLPARAMETER

DIGITAL OUTPUTS (DOUT, SSTRB)

POWER SUPPLY

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 7

TIMING CHARACTERISTICS—MAX1283

(Figures 1, 2, 5, 6; VDD1 = VDD2 = +2.7V to +3.6V, TA= TMIN to TMAX, unless otherwise noted.)

CLOAD = 20pF

CONDITIONS

100

tCSW

CS Pulse Width High

tSTE

CS Fall to SSTRB Enable

tDOE

CS Fall to DOUT Enable

13 85

tSTD

CS Rise to SSTRB Disable

13 85

tDOD

CS Rise to DOUT Disable

100

tSTV

SCLK Rise to SSTRB Valid

100

tDOV

SCLK Rise to DOUT Valid

tCL

SCLK Pulse Width Low

tCH

208

tCP

SCLK Period

SCLK Pulse Width High

13 20

tSTH

SCLK Rise to SSTRB Hold

13 20

tDOH

SCLK Rise to DOUT Hold

tCS1

CS Rise to SCLK Rise Ignore

tCSO

SCLK Rise to CS Fall Ignore

tDS

DIN to SCLK Setup

tDH

DIN to SCLK Hold

tCSS

CS Fall to SCLK Rise Setup

tCSH

SCLK Rise to CS Rise Hold

UNITSMIN TYP MAXSYMBOLPARAMETER

Note 1: Tested at VDD1 = VDD2 = VDD(MIN), COM = GND, unipolar single-ended input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: Offset nulled.

Note 4: Ground the “on” channel; sine wave is applied to all “off” channels.

Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 6: The common-mode range for the analog inputs (CH3–CH0 and COM) is from GND to VDD1.

Note 7: External load should not change during conversion for specified accuracy.

Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p. An external reference below 2.5V compro-

mises the performance of the ADC.

Note 9: Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) to VDD1(MAX) = VDD2(MIN). For operations beyond

this range, see Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.

Note 10: AIN = midscale, unipolar mode. MAX1282 tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 6.4MHz, 0 to 5V.

MAX1283 tested with same loads, fSCLK = 4.8MHz, 0 to 3V.

Note 11: SCLK = DIN = GND, CS = VDD1.

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

8 _______________________________________________________________________________________

Typical Operating Characteristics

(MAX1282: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1283: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor

at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)

0 1500 2000500 1000 2500 3000 3500 4000 4500

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1280/1-01

DIGITAL OUTPUT CODE

INL (LSB)

-0.2

0.2

0.4

-0.3

-0.4

-0.1

0.1

0.3

-0.5

-0.4

-0.2

0.3

0.4

0.5

0 1000500 1500 2000 2500 3000 3500 4000 4500

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1280/1-02

DNL (LSB)

DIGITAL OUTPUT CODE

0.2

0.1

-0.1

-0.3

3.5

3.0

2.5

2.0

1.5

2.5 4.03.0 3.5 4.5 5.0 5.5

SUPPLY CURRENT vs. SUPPLY

VOLTAGE (CONVERTING)

MAX1282/3-03

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

2.0

2.4

2.2

2.8

2.6

3.0

3.2

-40 20 40-20 0 60 80 100

SUPPLY CURRENT vs. TEMPERATURE

MAX1282/3-04

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

MAX1283

MAX1282

NORMAL OPERATION (PD1 = PD0 = 1)

REDP (PD1 = 1, PD0 = 0)

FASTDP (PD1 = 0, PD0 = 1)

0.5

1.5

1.0

2.0

2.5

2.5 3.53.0 4.0 4.5 5.0 5.5

SUPPLY CURRENT vs. SUPPLY

VOLTAGE (STATIC)

MAX1282/3-05

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

0.5

1.5

1.0

2.0

2.5

-40 0-20 20406080100

SUPPLY CURRENT vs. TEMPERATURE

(STATIC)

MAX1282/3-06

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

MAX1282 (PD1 = 1, PD0 = 1)

MAX1282 (PD1 = 1, PD0 = 0)

MAX1282 (PD1 = 0, PD0 = 1)

MAX1283 (PD1 = 1, PD0 = 1)

MAX1283 (PD1 = 1, PD0 = 0)

MAX1283 (PD1 = 0, PD0 = 1)

2.5 3.53.0 4.0 4.5 5.0 5.5

SHUTDOWN CURRENT

vs. SUPPLY VOLTAGE

MAX1282/3-07

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

(PD1 = PD0 = 0)

0.5

1.5

1.0

2.0

2.5

-40 0-20 20 40 60 80 100

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

MAX1282/3-08

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

MAX1283

MAX1282

(PD1 = PD0 = 0)

2.4995

2.4997

2.5001

2.4999

2.5003

2.5005

2.5 3.53.0 4.0 4.5 5.0 5.5

REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

MAX1282/3-09

SUPPLY VOLTAGE (V)

REFERENCE VOLTAGE (V)

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 9

2.4988

2.4992

2.4990

2.4996

2.4994

2.5000

2.4998

2.5002

-40 0 20-20 40 60 80 100

REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1282/3-10

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

MAX1283

MAX1282

-2.0

-1.0

-1.5

0.5

-0.5

1.5

1.0

2.0

OFFSET ERROR vs. SUPPLY VOLTAGE

MAX1282/3-11

SUPPLY VOLTAGE (V)

OFFSET ERROR (LSB)

2.5 3.0 4.53.5 4.0 5.0 5.5

-2.5

-1.5

-2.0

-0.5

-1.0

0.5

-40 10-15 35 60 85

OFFSET ERROR vs. TEMPERATURE

MAX1282/3-12

TEMPERATURE (°C)

OFFSET ERROR (LSB)

-1.0

0.4

0.2

-0.4

-0.6

-0.8

-0.2

0.6

0.8

1.0

2.5 3.0 4.53.5 4.0 5.0 5.5

GAIN ERROR vs. SUPPLY VOLTAGE

MAX1282/3-13

SUPPLY VOLTAGE (V)

GAIN ERROR (LSB)

-2.0

-1.5

-0.5

-1.0

0.5

GAIN ERROR vs. TEMPERATURE

MAX1282/3-14

TEMPERATURE (°C)

GAIN ERROR (LSB)

-40 10-15 35 60 85

Typical Operating Characteristics (continued)

(MAX1282: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1283: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor

at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

10 ______________________________________________________________________________________

Pin Description

Positive Supply VoltageVDD2

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to VDD1.REFADJ9

Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High impedance

when CS is high.

SSTRB12

Serial-Data Input. Data is clocked in at SCLK’s rising edge.DIN13

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT and

SSTRB are high impedance.

Serial-Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty cycle

must be 40% to 60%.)

SCLK15

Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In

internal reference mode, the reference buffer provides a 2.500V nominal output, externally adjustable at

REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD1.

REF8

GroundGND10

Serial-Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.

DOUT11

Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA (typ).SHDN

Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be

stable to ±0.5LSB.

COM6

Positive Supply VoltageVDD1

FUNCTIONNAME

VDD2

GND

DOUT

CLOAD

50pF

CLOAD

50pF

GND

DOUT

a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL

VDD2

GND

DOUT

CLOAD

70pF

CLOAD

20pF

GND

DOUT

a) VOH to High-Z b) VOL to High-Z

Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time

Sampling Analog InputsCH0–CH32–5

Detailed Description

The MAX1282/MAX1283 ADCs use a successive-

approximation conversion technique and input T/H cir-

cuitry to convert an analog signal to a 12-bit digital out-

put. A flexible serial interface provides easy interface to

microprocessors (µPs). Figure 3 shows a functional dia-

gram of the MAX1282/MAX1283.

Pseudo-Differential Input

The equivalent circuit of Figure 4 shows the MAX1282/

MAX1283’s input architecture, which is composed of a

T/H, input multiplexer, input comparator, switched-

capacitor DAC, and reference.

In single-ended mode, the positive input (IN+) is con-

nected to the selected input channel and the negative

input (IN-) is set to COM. In differential mode, IN+ and

IN- are selected from the following pairs: CH0/CH1 and

CH2/CH3. Configure the channels according to Tables

1 and 2.

The MAX1282/MAX1283 input configuration is pseudo-

differential because only the signal at IN+ is sampled.

The return side (IN-) is connected to the sampling

capacitor while converting and must remain stable

within ±0.5LSB (±0.1LSB for best results) with respect

to GND during a conversion.

If a varying signal is applied to the selected IN-, its

amplitude and frequency must be limited to maintain

accuracy. The following equations express the relation-

ship between the maximum signal amplitude and its

frequency to maintain ±0.5LSB accuracy. Assuming a

sinusoidal signal at IN-, the input voltage is determined

by:

The maximum voltage variation is determined by:

A 0.65Vp-p, 60Hz signal at IN- will generate a ±0.5LSB

error when using a +2.5V reference voltage and a

2.5µs conversion time (15 / fSCLK). When a DC refer-

ence voltage is used at IN-, connect a 0.1µF capacitor

to GND to minimize noise at the input.

During the acquisition interval, the channel selected as

the positive input (IN+) charges capacitor CHOLD. The

acquisition interval spans three SCLK cycles and ends

on the falling SCLK edge after the input control word’s

last bit has been entered. At the end of the acquisition

interval, the T/H switch opens, retaining charge on

CHOLD as a sample of the signal at IN+. The conver-

sion interval begins with the input multiplexer switching

CHOLD from IN+ to IN-. This unbalances node ZERO at

the comparator’s input. The capacitive DAC adjusts

during the remainder of the conversion cycle to restore

node ZERO to VDD1 / 2 within the limits of 12-bit resolu-

tion. This action is equivalent to transferring a

12pF ✕(VIN+ - VIN-) charge from CHOLD to the binary-

weighted capacitive DAC, which in turn forms a digital

representation of the analog input signal.

max d

dt V2f

1LSB

CONV

REF

12 CONV

νπ

IN IN

−=−≤ =

()

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 11

INPUT

SHIFT

LOGIC

INT

CLOCK

OUTPUT

SHIFT

+1.22V

REFERENCE

T/H

ANALOG

INPUT

MUX

12-BIT

SAR ADC

DOUT

SSTRB

VDD1

VDD2

GND

SCLK

DIN

COM

REFADJ

REF

OUT

REF

CLOCK

+2.500V

17k

CH1 3

CH2 4

CH3 5

CH0 2

MAX1282

MAX1283

SHDN

2.05

A≈

Figure 3. Functional Diagram

CHOLD

12pF

RIN

800Ω

HOLD

INPUT

MUX

CSWITCH*

*INCLUDES ALL INPUT PARASITICS

SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM.

PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM

PAIRS OF CH0/CH1 AND CH2/CH3.

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES FROM

THE SELECTED IN+ CHANNEL TO

THE SELECTED IN- CHANNEL.

CH0

REF

GND

CH1

CH2

CH3

COM

ZERO

VDD1/2

COMPARATOR

CAPACITIVE

DAC

6pF

TRACK

Figure 4. Equivalent Input Circuit

νπ

IN IN

V sin(2 ft)−=−

()

Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)

Table 2. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0)

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

12 ______________________________________________________________________________________

Track/Hold

The T/H enters its tracking mode on the falling clock

edge after the fifth bit of the 8-bit control word has been

shifted in. It enters its hold mode on the falling clock

edge after the eighth bit of the control word has been

shifted in. If the converter is set up for single-ended

inputs, IN- is connected to COM and the converter

samples the “+” input. If the converter is set up for dif-

ferential inputs, the difference of

[(

IN+) - (IN-)

]

is con-

verted. At the end of the conversion, the positive input

connects back to IN+ and CHOLD charges to the input

signal.

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens, and more time must be

allowed between conversions. The acquisition time,

tACQ, is the maximum time the device takes to acquire

the signal and the minimum time needed for the signal

to be acquired. It is calculated by the following equa-

tion:

tACQ = 9 ✕(RS+ RIN) ✕18pF

where RIN = 800Ωand RS= the source impedance of

the input signal; tACQ is never less than 400ns

(MAX1282) or 625ns (MAX1283). Note that source

impedances below 2kΩdo not significantly affect the

ADC’s AC performance.

Input Bandwidth

The ADC’s input tracking circuitry has a 6MHz

(MAX1282) or 3MHz (MAX1283) small-signal band-

width, so it is possible to digitize high-speed transient

events and measure periodic signals with bandwidths

exceeding the ADC’s sampling rate by using under-

sampling techniques. To avoid high-frequency signals

being aliased into the frequency band of interest, anti-

alias filtering is recommended.

Analog Input Protection

Internal protection diodes, which clamp the analog input

to VDD1 and GND, allow the channel input pins to swing

from GND - 0.3V to VDD1 + 0.3V without damage.

However, for accurate conversions near full scale, the

inputs must not exceed VDD1 by more than 50mV or be

lower than GND by 50mV.

If the analog input exceeds 50mV beyond the sup-

plies, do not allow the input current to exceed 2mA.

Starting a Conversion

Start a conversion by clocking a control byte into DIN.

With CS low, each rising edge on SCLK clocks a bit from

DIN into the MAX1282/MAX1283’s internal shift register.

After CS falls, the first arriving logic “1” bit defines the

control byte’s MSB. Until this first “start” bit arrives, any

number of logic “0” bits can be clocked into DIN with no

effect. Table 3 shows the control-byte format.

The MAX1282/MAX1283 are compatible with SPI/

QSPI/MICROWIRE devices. For SPI, select the correct

clock polarity and sampling edge in the SPI control reg-

isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,

and QSPI all transmit a byte and receive a byte at the

same time. Using the Typical Operating Circuit, the sim-

plest software interface requires only three 8-bit transfers

to perform a conversion (one 8-bit transfer to configure

the ADC, and two more 8-bit transfers to clock out the

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 COM

00 1+ –

10 1 + –

01 0 + –

11 0 + –

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3

00 1+–

01 0 +–

10 1–+

11 0 –+

conversion result). (See Figure 16 for MAX1282/

MAX1283 QSPI connections.)

Simple Software Interface

Make sure the CPU’s serial interface runs in master

mode so the CPU generates the serial clock. Choose a

clock frequency from 500kHz to 6.4MHz (MAX1282) or

4.8MHz (MAX1283).

1) Set up the control byte and call it TB1. TB1 should

be in the format: 1XXXXXXX binary, where the Xs

denote the particular channel, selected conversion

mode, and power mode.

2) Use a general-purpose I/O line on the CPU to pull

CS low.

3) Transmit TB1 and, simultaneously, receive a byte

and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB2.

5) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB3.

6) Pull CS high.

Figure 5 shows the timing for this sequence. Bytes RB2

and RB3 contain the result of the conversion, padded

with three leading zeros, and one trailing zero. The total

conversion time is a function of the serial-clock fre-

quency and the amount of idle time between 8-bit

transfers. To avoid excessive T/H droop, make sure the

total conversion time does not exceed 120µs.

Digital Output

In unipolar input mode, the output is straight binary

(Figure 13). For bipolar input mode, the output is two’s

complement (Figure 14). Data is clocked out on the ris-

ing edge of SCLK in MSB-first format.

Serial Clock

The external clock not only shifts data in and out, but it

also drives the analog-to-digital conversion steps.

SSTRB pulses high for one clock period after the last bit

of the control byte. Successive-approximation bit deci-

sions are made and appear at DOUT on each of the

next 12 SCLK rising edges, MSB first (Figure 5). SSTRB

and DOUT go into a high-impedance state when CS

goes high; after the next CS falling edge, SSTRB out-

puts a logic low. Figure 6 shows the detailed serial-inter-

face timings.

The conversion must complete in 120µs or less, or

droop on the sample-and-hold capacitors may degrade

conversion results.

Data Framing

The falling edge of CS does not start a conversion.

The first logic high clocked into DIN is interpreted as a

start bit and defines the first bit of the control byte. A

conversion starts on SCLK’s falling edge, after the eighth

bit of the control byte (the PD0 bit) is clocked into DIN.

The start bit is defined as follows:

The first high bit clocked into DIN with CS low any

time the converter is idle, e.g., after VDD1 and VDD2

are applied.

The first high bit clocked into DIN after B6 of a con-

version in progress is clocked onto the DOUT pin

(Figure 7).

Once a start bit has been recognized, the current conver-

sion may only be terminated by pulling SHDN low.

The fastest the MAX1282/MAX1283 can run with CS held

low between conversions is 16 clocks per conversion.

Figure 7 shows the serial-interface timing necessary to

perform a conversion every 16 SCLK cycles. If CS is tied

low and SCLK is continuous, guarantee a start bit by first

clocking in 16 zeros.

___________Applications Information

Power-On Reset

When power is first applied, and if SHDN is not pulled

low, internal power-on reset circuitry activates the

MAX1282/MAX1283 in normal operating mode, ready to

convert with SSTRB = low. After the power supplies sta-

bilize, the internal reset time is 10µs, and no conver-

sions should be performed during this phase. If CS is

low, the first logic 1 on DIN is interpreted as a start bit.

Until a conversion takes place, DOUT shifts out zeros.

Additionally, wait for the reference to stabilize when

using the internal reference.

Power Modes

Save power by placing the converter in one of two low-

current operating modes or in full power-down between

conversions. Select the power-down mode through bit

1 and bit 0 of the DIN control byte (Tables 3 and 4), or

force the converter into hardware shutdown by driving

SHDN to GND.

The software power-down modes take effect after the

conversion is completed; SHDN overrides any software

power mode and immediately stops any conversion in

progress. In software power-down mode, the serial

interface remains active while waiting for a new control

byte to start conversion and switch to full-power mode.

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 13

MAX1282/MAX1283

Once conversion is completed, the device goes into the

programmed power mode until a new control byte is

written.

The power-up delay is dependent on the power-down

state. Software low-power modes will be able to start

conversion immediately when running at decreased

clock rates (see Power-Down Sequencing). Upon

power-on reset, when exiting software full power-down

mode, or when exiting hardware shutdown, the device

goes immediately into full-power mode and is ready to

convert after 2µs when using an external reference.

When using the internal reference, wait for the typical

power-up delay from a full power-down (software or

hardware) as shown in Figure 8.

Software Power-Down

Software power-down is activated using bits PD1 and

PD0 of the control byte. When software power-down is

asserted, the ADC completes the conversion in

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

14 ______________________________________________________________________________________

BIT NAME DESCRIPTION

7(MSB) START The first logic 1 bit after CS goes low defines the beginning of the control byte.

6 SEL2 These three bits select which of the eight channels are used for the conversion (Tables 1 and 2).

5 SEL1

4 SEL0

3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an

analog input signal from 0 to VREF can be converted; in bipolar mode, the differential signal can

range from -VREF/2 to +VREF/2.

2 SGL/DIF 1 = single ended, 0 = pseudo-differential. Selects single-ended or pseudo-differential conver-

sions. In single-ended mode, input signal voltages are referred to COM. In pseudo-differential

mode, the voltage difference between two channels is measured (Tables 1 and 2).

1 PD1 Select operating mode.

0(LSB) PD0 PD1 PD0 Mode

0 0 Full power-down

0 1 Fast power-down

1 0 Reduced power

1 1 Normal operation

Table 3. Control-Byte Format

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

(MSB) (LSB)

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

PD1/PD0 MODE CONVERTING

(mA)

AFTER

CONVERSION INPUT COMPARATOR REFERENCE

00 Full Power-Down

(FULLPD) 2.5 2µA Off Off

01 Fast Power-Down

(FASTPD) 2.5 0.9mA Reduced Power On

10 Reduced-Power

Mode (REDP) 2.5 1.3mA Reduced Power On

11 Normal Operating 2.5 2.0mA Full Power On

CIRCUIT SECTIONS*TOTAL SUPPLY CURRENT

Table 4. Software-Controlled Power Modes

*Circuit operation between conversions; during conversion all circuits are fully powered up.

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 15

progress and powers down into the specified low-qui-

escent-current state (2µA, 0.9mA, or 1.3mA).

The first logic 1 on DIN is interpreted as a start bit and

puts the MAX1282/MAX1283 into its full-power mode.

Following the start bit, the data input word or control

byte also determines the next power-down state. For

example, if the DIN word contains PD1 = 0 and PD0 = 1,

a 0.9mA power-down resumes after one conversion.

Table 4 details the four power modes with the corre-

sponding supply current and operating sections.

Hardware Power-Down

Pulling SHDN low places the converter in hardware

power-down. Unlike software power-down mode, the

conversion is not completed; it stops coincidentally with

SHDN being brought low. When returning to normal

operation—from SHDN, with an external reference—the

MAX1282/MAX1283 can be considered fully powered

up within 2µs of actively pulling SHDN high. When

using the internal reference, the conversion should be

initiated only when the reference has settled; its recov-

ery time is dependent on the external bypass capaci-

tors and the time between conversions.

Power-Down Sequencing

The MAX1282/MAX1283 auto power-down modes can

save considerable power when operating at less than

maximum sample rates. Figures 9 and 10 show the

average supply current as a function of the sampling

rate. The following sections discuss the various power-

down sequences. Other combinations of clock rates

and power-down modes may attain the lowest power

consumption in other applications.

Using Full Power-Down Mode

Full power-down mode (FULLPD) achieves the lowest

power consumption, up to 1000 conversions per chan-

nel per second. Figure 9a shows the MAX1283’s power

consumption for one- or four-channel conversions utiliz-

ing full power-down mode (PD1 = PD0 = 0), with the

internal reference and conversion controlled at the

maximum clock speed. A 0.01µF bypass capacitor at

REFADJ forms an RC filter with the internal 17kΩrefer-

ence resistor, with a 170µs time constant. To achieve

full 12-bit accuracy, nine time constants or 1.5ms are

required after power-up if the bypass capacitor is fully

discharged between conversions. Waiting this 1.5ms

duration in fast power-down (FASTPD) or reduced-

power (REDP) mode instead of in full power-up can fur-

ther reduce power consumption. This is achieved by

using the sequence shown in Figure 11a.

Figure 9b shows the MAX1283’s power consumption for

one- or four-channel conversions utilizing FULLPD

mode (PD1 = PD0 = 0), with an external reference and

conversion controlled at the maximum clock speed.

One dummy conversion to power up the device is

needed, but no waiting time is necessary to start the

second conversion, thereby achieving lower power

consumption as low as half the full sampling rate.

400ns

(CLK = 6.4MHz)

IDLE

SCLK

DIN

SSTRB

DOUT

A/D STATE

tACQ

IDLECONVERSION

RB3RB2

RB1

SEL

START

4 891216 2024

SEL

UNI/

BIP

SGL/

DIF PD2 PD2

B11 B10 B9 B8 B7

B5 B4 B3 B2 B1 B0

Figure 5. Single-Conversion Timing

MAX1282/MAX1283

Using Fast Power-Down

and Reduced-Power Modes

FASTPD and REDP modes achieve the lowest power

consumption at speeds close to the maximum sampling

rate. Figure 10 shows the MAX1283’s power

consumption in FASTPD mode (PD1 = 0, PD0 = 1),

REDP mode (PD1 = 1, PD0 = 0), and, for comparison,

normal operating mode (PD1 = 1, PD0 = 1). The figure

shows power consumption using the specified power-

down mode, with the internal reference and conversion

controlled at the maximum clock speed. The clock

speed in FASTPD or REDP should be limited to 4.8MHz

for the MAX1282/MAX1283. FULLPD mode may provide

increased power savings in applications where the

MAX1282/MAX1283 are inactive for long periods of time,

but intermittent bursts of high-speed conversions are

required. Figure 11b shows FASTPD and REDP timing.

Internal and External References

The MAX1282/MAX1283 can be used with an internal

or external reference voltage. An external reference

can be connected directly at REF or at the REFADJ pin.

An internal buffer is designed to provide 2.5V at

REF for the MAX1282/MAX1283. The internally trimmed

1.22V reference is buffered with a 2.05 gain.

Internal Reference

The MAX1282/MAX1283’s full-scale range with the inter-

nal reference is 2.5V with unipolar inputs and ±1.25V

with bipolar inputs. The internal reference voltage is

adjustable by ±100mV with the circuit in Figure 12.

External Reference

The MAX1282/MAX1283’s external reference can be

placed at the input (REFADJ) or the output (REF) of the

internal reference-buffer amplifier. The REFADJ input

impedance is typically 17kΩ. At REF, the DC input

resistance is a minimum of 18kΩ. During conversion, an

external reference at REF must deliver up to 350µA DC

load current and have 10Ωor less output impedance. If

the reference has a higher output impedance or is

noisy, bypass it close to the REF pin with a 4.7µF

capacitor.

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

16 ______________________________________________________________________________________

SCLK

DIN

DOUT

SSTRB

tCSS tCH

tCSO tCL

tDH

tDOE

tDS

tSTE

tCSW

tCP tCSH

tCS1

tSTD

tDOD

tDOV

tDOH

tSTV

tSTH

#10

Figure 6. Detailed Serial-Interface Timing

UNIPOLAR MODE BIPOLAR MODE

Full Scale Zero Scale Positive Zero Negative

Full Scale Scale Full Scale

Table 5. Full Scale and Zero Scale

VREF + VCOM VREF / 2

+ VCOM

VREF / 2

+ VCOM

VCOM

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 17

SCLK

11 15885812 12 1216 16 1 516

B6B11B0B6B11B0

DIN

SSTRB

DOUT

CONTROL BYTE 0SSSCONTROL BYTE 1

CONVERSION RESULT 1CONVERSION RESULT 0

CONTROL BYTE 2 S ETC

B6B11

Figure 7. Continuous 16-Clock/Conversion Timing

0.50

0.25

1.00

0.75

1.25

1.50

0.0001 0.010.001 0.1 1 10

TIME IN SHUTDOWN (s)

REFERENCE POWER-UP DELAY (ms)

MAX1283, VDD1 = VDD2 = 3.0V

CLOAD = 20pF

CODE = 101010000000

100

0.1 101 100 1k 10k

SAMPLING RATE (sps)

SUPPLY CURRENT (µA)

4 CHANNELS

1 CHANNEL

10k

100

110010 1k 10k 100k

SAMPLING RATE (sps)

SUPPLY CURRENT (µA)

MAX1283, VDD1 = VDD 2 = 3.0V

CLOAD = 20pF

CODE = 101010000000

4 CHANNELS

1 CHANNEL

Figure 8. Reference Power-Up Delay vs. Time in Shutdown

Figure 9a. Average Supply Current vs. Conversion Rate with

Internal Reference in FULLPD

Figure 9b. Average Supply Current vs. Conversion Rate with

External Reference in FULLPD

2.5

2.0

1.0

1.5

0.5

0150 250

100

50 200 300 350

SAMPLING RATE (sps)

SUPPLY CURRENT (mA)

MAX1283, VDD1 = VDD2 = 3.0V

CLOAD = 20pF

CODE = 101010000000

REDP

FASTPD

NORMAL OPERATION

Figure 10. Average Supply Current vs. Sampling Rate (in

FASTPD, REDP, and Normal Operation)

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

18 ______________________________________________________________________________________

Figure 11a. Full Power-Down Timing

RE FADJ 1.22V 1.22V

2.5mA 2.5mA

1.3mA OR 0.9mA

DIN

IVDD1 + IVDD2

REF

FULLPD REDP

WAIT 2ms (10 x RC)

FULLPD

10011

γ = RC = 17kΩ x 0.01µF

DUMMY CONVERSION

1000

2.5V

2.5mA

0mA 0mA

2.5V

Figure 11b. FASTPD and REDP Timing

2.5V (ALWAYS ON)

2.5mA 2.5mA

DIN

IVDD1 + IVDD2

REF

REDP REDP FASTPD

11011

1001

2.5mA

0.9mA 0.9mA 1.3mA

To use the direct REF input, disable the internal buffer by

connecting REFADJ to VDD1. Using the REFADJ input

makes buffering the external reference unnecessary.

Transfer Function

Table 5 shows the full-scale voltage ranges for unipolar

and bipolar modes.

Figure 13 depicts the nominal, unipolar input/output

(I/O) transfer function, and Figure 14 shows the bipolar

I/O transfer function. Code transitions occur halfway

between successive-integer LSB values. Output coding

is binary, with 1LSB = 0.61mV (2.500V / 4096) for unipo-

lar operation, and 1LSB = 0.61mV [(2.500V / 2) / 4096]

for bipolar operation.

Layout, Grounding, and Bypassing

For best performance, use PC boards; wire-wrap

boards are not recommended. Board layout should

ensure that digital and analog signal lines are separated

from each other. Do not run analog and digital (espe-

cially clock) lines parallel to one another, or digital lines

underneath the ADC package.

Figure 15 shows the recommended system ground

connections. Establish a single-point analog ground

(star ground point) at GND. Connect all other analog

grounds to the star ground. Connect the digital system

ground to this ground only at this point. For lowest-

noise operation, the ground return to the star ground’s

power supply should be low impedance and as short

as possible.

High-frequency noise in the VDD1 power supply may

affect the high-speed comparator in the ADC. Bypass

the supply to the star ground with 0.1µF and 10µF

capacitors close to VDD1 of the MAX1282/MAX1283.

Minimize capacitor lead lengths for best supply-noise

rejection. If the power supply is very noisy, a 10Ωresis-

tor can be connected as a lowpass filter (Figure 15).

High-Speed Digital Interfacing with QSPI

The MAX1282/MAX1283 can interface with QSPI using

the circuit in Figure 16 (CPOL = 0, CPHA = 0). This

QSPI circuit can be programmed to do a conversion on

each of the four channels. The result is stored in memory

without taxing the CPU, since QSPI incorporates its own

microsequencer.

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 19

TMS320LC3x Interface

Figure 17 shows an application circuit to interface the

MAX1282/MAX1283 to the TMS320 in external clock

mode. The timing diagram for this interface circuit is

shown in Figure 18.

Use the following steps to initiate a conversion in the

MAX1282/MAX1283 and to read the results:

1) The TMS320 should be configured with CLKX (trans-

mit clock) as an active-high output clock and CLKR

(TMS320 receive clock) as an active-high input clock.

CLKX and CLKR on the TMS320 are connected to

the MAX1282/MAX1283’s SCLK input.

2) The MAX1282/MAX1283’s CS pin is driven low by the

TMS320’s XF_ I/O port to enable data to be clocked

into the MAX1282/MAX1283’s DIN pin.

3) An 8-bit word (1XXXXX11) should be written to the

MAX1282/MAX1283 to initiate a conversion and

place the device into normal operating mode. See

Table 3 to select the proper XXXXX bit values for your

specific application.

4) The MAX1282/MAX1283’s SSTRB output is moni-

tored through the TMS320’s FSR input. A falling

edge on the SSTRB output indicates that the conver-

sion is in progress and data is ready to be received

from the device.

5) The TMS320 reads in 1 data bit on each of the next

16 rising edges of SCLK. These data bits represent

the 12-bit conversion result followed by 4 trailing bits,

which should be ignored.

6) Pull CS high to disable the MAX1282/MAX1283 until

the next conversion is initiated.

+3.3V

510k

24k

100k

0.047µF

12 REFADJ

MAX1282

MAX1283

Figure 12. MAX1282/MAX1283 Reference-Adjust Circuit

OUTPUT CODE

FULL-SCALE

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000

123

(COM)

FS - 3/2LSB

FS = VREF + VCOM

ZS = VCOM

INPUT VOLTAGE (LSB)

1LSB = VREF

4096

Figure 13. Unipolar Transfer Function, Full Scale (FS) =

VREF + VCOM, Zero Scale (ZS) = VCOM

011 . . . 111

011 . . . 110

000 . . . 010

000 . . . 001

000 . . . 000

111 . . . 111

111 . . . 110

111 . . . 101

100 . . . 001

100 . . . 000

- FS COM*

INPUT VOLTAGE (LSB)

OUTPUT CODE

ZS = VCOM

+FS - 1LSB

*VCOM VREF / 2

+ VCOM

FS = VREF

-FS = + VCOM

-VREF

1LSB = VREF

4096

≤

Figure 14. Bipolar Transfer Function, Full Scale (FS) =

VREF / 2 + VCOM, Zero Scale (ZS) = VCOM

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

20 ______________________________________________________________________________________

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

from a straight line on an actual transfer function. This

straight line can be a best-straight-line fit or a line

drawn between the endpoints of the transfer function,

once offset and gain errors have been nullified. The

static linearity parameters for the MAX1282/MAX1283

are measured using the best straight-line fit method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1LSB. A

DNL error specification of less than 1LSB guarantees

no missing codes and a monotonic transfer function.

Aperture Width

Aperture width (tAW) is the time the T/H circuit requires

to disconnect the hold capacitor from the input circuit

(for instance, to turn off the sampling bridge, and put

the T/H unit in hold mode).

Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation in

the time between the samples.

Aperture Delay

Aperture delay (tAD) is the time defined between the

rising edge of the sampling clock and the instant when

an actual sample is taken.

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital

samples, the SNR is the ratio of the full-scale analog

input (RMS value) to the RMS quantization error (resid-

ual error). The ideal, theoretical minimum analog-to-dig-

ital noise is caused only by quantization error and

results directly from the ADC’s resolution (N bits):

SNR = (6.02 ✕N + 1.76)dB

In reality, there are other noise sources besides quanti-

zation noise, including thermal noise, reference noise,

clock jitter, etc. Therefore, SNR is calculated by taking

the ratio of the RMS signal to the RMS noise, which

includes all spectral components minus the fundamen-

tal, the first five harmonics, and the DC offset.

Signal-to-Noise Plus

Distortion (SINAD)

SINAD is the ratio of the fundamental input frequency’s

RMS amplitude to RMS equivalent of all other ADC out-

put signals:

SINAD (dB) = 20 ✕log (SignalRMS / NoiseRMS)

Effective Number of Bits (ENOB)

ENOB indicates the global accuracy of an ADC at a

specific input frequency and sampling rate. An ideal

ADC’s error consists only of quantization noise. With an

input range equal to the ADC’s full-scale range, calcu-

late ENOB as follows:

ENOB = (SINAD - 1.76) / 6.02

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the input signal’s

first five harmonics to the fundamental itself. This is

expressed as:

where V1is the fundamental amplitude, and V2through

V5 are the amplitudes of the 2nd- through 5th-order

harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the RMS amplitude of the funda-

mental (maximum signal component) to the RMS value

of the next-largest distortion component.

THD 20 log

VVVVV

2232424252

=×

++++

⎛

⎝

⎜⎞

⎠

⎟

+3V +3V

SUPPLIES

DGND+3VVDD2

COM

GNDVDD1

DIGITAL

CIRCUITRY

MAX1282

MAX1283

*R = 10Ω

*OPTIONAL

GND

Figure 15. Power-Supply Grounding Connection

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 21

MC683XX

(POWER SUPPLIES)

SCK

PCS0

MOSI

MISO

0.1µF10µF

(GND)

0.01µF

4.7µF

ANALOG

INPUTS

+5V

+3V

+5V

+3V

MAX1282

MAX1283

VDD2

SCLK

CSB

DIN

SSTRB

DOUT

GND

REFADJ

VDD1

CH0

CH1

COM

CH2

CH3

SHDN

REF

10µF0.1µF

VDD1

Figure 16. QSPI Connections

CLKX

CLKR

FSR

SCLK

DIN

DOUT

SSTRB

TMS320LC3x

MAX1282

MAX1283

Figure 17. MAX1282/MAX1283-to-TMS320 Serial Interface

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

22 ______________________________________________________________________________________

SCLK

DIN

DOUT

SSTRB

SEL2START SEL1 SEL0 PD1 PD0

UNI/BIP SGI/DIF

B10 B1

MSB B0

HIGH IMPEDANCE

Figure 18. MAX1282/MAX1283-to-TMS320 Serial Interface

Typical Operating Circuit

VDD

I/O

SCK (SK)

MOSI (SO)

MISO (SI)

VSS

SSTRB

DOUT

DIN

SCLK

COM

GND

VDD2

VDD1

CH3

4.7µF

0.1µF

CH0

0 TO

+2.5V

ANALOG

INPUTS MAX1282

MAX1283 CPU

SHDN

+5V OR

+3V

REF

0.01µF

REFADJ

Chip Information

TRANSISTOR COUNT: 4286

PROCESS: BiCMOS

MAX1282/MAX1283

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23

MAX1282/MAX1283

300ksps/400ksps, Single-Supply, 4-Channel,

Serial 12-Bit ADCs with Internal Reference

TSSOP4.40mm.EPS

PACKAGE OUTLINE, TSSOP 4.40mm BODY

21-0066

Note: The MAX1282/MAX1283 do not have an exposed die pad.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)