© Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
Freescale Semiconductor
Product Brief
MC9S12CFAMPB
Rev. 5, 03/2006
MC9S12C-Family
16-Bit Microcontroller
Based on Freescale’s market-leading flash technology, members of the MC9S12C-Family deliver the
power and flexibility of our 16 Bit core (CPU12) family to a whole new range of cost and space sensitive,
general purpose Industrial and Automotive network applications. MC9S12C-Family members are
comprised of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K
bytes of Flash EEPROM or ROM, up to 4K bytes of RAM, an asynchronous serial communications
interface (SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel
8-bit pulse width modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC) and up to one
CAN 2.0 A, B software compatible module (MSCAN12). The MC9S12C-Family has full 16-bit data paths
throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to
suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O
port bits are available with Wakeup capability from STOP or WAIT mode. The MC9S12C-Family is
available in 48-pin and 52-pin LQFP, and in 80-pin QFP packages (all RoHS Compliant J-STD-020C); the
80-pin version is pin-compatible with the HCS12B- and D-Family derivatives.
The C-Family includes ROM versions MC3S12C128/96/64/32/16 of all devices which provide a further
cost reduction path for applications with high volume and stable code.
1Features
• 16-Bit HCS12 CORE
— HCS12 CPU
— MMC (memory map and interface)
— INT (interrupt control)
— BDM (background debug mode)
— DBG12 (enhanced debug12 module including breakpoints and change-of-flow trace buffer)
— Multiplexed Expansion Bus (available only in 80-pin package version)
MC9S12C-Family, Rev. 5
Features
Freescale Semiconductor2
• 16-Bit HCS12 CPU
— Upward compatible with M68HC11 instruction set
— Interrupt stacking and programmer’s model identical to M68HC11
— Instruction queue
— Enhanced indexed addressing
• Wake-up Interrupt Inputs
— Up to 10-port bits available for wake up interrupt function
• Memory Options
— 16K, 32K, 64K, 96K and 128K Byte Flash EEPROM (erasable in 512-byte sectors) or
— 16K, 32K, 64K, 96K and 128K Byte ROM
— 1K, 2K, and 4K Byte RAM
• Analog-to-Digital Converters
— One 8-channel module with 10-bit resolution.
— External conversion trigger capability
• Up to One 1M Bit Per Second, CAN 2.0 A, B Software Compatible Modules
— Five receive and three transmit buffers
— Flexible identifier filter programmable as 2x32 bit, 4x16 bit or 8x8bit
— Four separate interrupt channels for receive, transmit, error and wake-up
— Low-pass filter wake-up function
— Loop-back for self test operation
• Timer Module (TIM)
— 16-bit Counter with 7-bit Prescaler
— 8 programmable input capture or output compare channels
— Simple PWM Mode
— Modulo Reset of Timer Counter
— 16-Bit Pulse Accumulator
— External Event Counting
— Gated Time Accumulation
• 6 PWM Channels
— Programmable period and duty cycle
— 8-bit 6-channel or 16-bit 3-channel
— Separate control for each pulse width and duty cycle
— Center-aligned or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
— Fast emergency shutdown input
Features
MC9S12C-Family, Rev. 5
Freescale Semiconductor 3
• Serial Interfaces
— One asynchronous serial communications interface (SCI)
— One synchronous serial peripheral interface (SPI)
• CRG (Clock Reset Generator Module)
— Windowed COP watchdog,
— Real time interrupt,
— Clock monitor,
— Clock generation
— Reset Generation
— Phase-locked loop clock frequency multiplier
— Limp home mode in absence of external clock
— Low power 0.5 to 16 MHz crystal oscillator reference clock
• Operation Frequency
— 32MHz equivalent to 16MHz Bus Speed for single chip
— 32MHz equivalent to 16MHz Bus Speed in expanded bus modes
— Option: 50MHz equivalent to 25MHz Bus Speed
— Internal 2.5V Regulator
— Supports an input voltage range from 3.3V-10% to 5.5V
— Low power mode capability
— Includes low voltage reset (LVR) circuitry
— Includes low voltage interrupt (LVI) circuitry
• 48-pin LQFP, 52-pin LQFP, or 80-pin QFP Package (all RoHS Compliant J-STD-020C)
— Up to 58 I/O lines with 5V input and drive capability
— Up to 2 dedicated 5V input only lines (IRQ, XIRQ)
— 5V A/D converter inputs and 5V I/O
• Development Support
— Single-wire background debug™ mode (BDM)
— On-chip hardware breakpoints
— Enhanced DBG12 debug features
MC9S12C-Family, Rev. 5
MC9S12C-Family Members
Freescale Semiconductor4
2 MC9S12C-Family Members
Table 1. List of MC9S12C-Family Members
Flash ROM RAM Package Device CAN SCI SPI A/D PWM Timer I/O
128K 0 4K
48LQFP MC9S12C128 1 1 1 8ch 6ch 8ch 31
52LQFP MC9S12C128 1 1 1 8ch 6ch 8ch 35
80QFP MC9S12C128 1 1 1 8ch 6ch 8ch 60
96K 0 4K
48LQFP MC9S12C96 1 1 1 8ch 6ch 8ch 31
52LQFP MC9S12C96 1 1 1 8ch 6ch 8ch 35
80QFP MC9S12C96 1 1 1 8ch 6ch 8ch 60
64K 0 4K
48LQFP MC9S12C64 1 1 1 8ch 6ch 8ch 31
52LQFP MC9S12C64 1 1 1 8ch 6ch 8ch 35
80QFP MC9S12C64 1 1 1 8ch 6ch 8ch 60
32K 0 2K
48LQFP MC9S12C32 1 1 1 8ch 6ch 8ch 31
52LQFP MC9S12C32 1 1 1 8ch 6ch 8ch 35
80QFP MC9S12C32 1 1 1 8ch 6ch 8ch 60
32K 0 2K
48LQFP MC9S12GC32 0 1 1 8ch 6ch 8ch 31
52LQFP MC9S12GC32 0 1 1 8ch 6ch 8ch 35
80QFP MC9S12GC32 0 1 1 8ch 6ch 8ch 60
16K 0 1K
48LQFP MC9S12GC16 0 1 1 8ch 6ch 8ch 31
52LQFP MC9S12GC16 0 1 1 8ch 6ch 8ch 35
80QFP MC9S12GC16 0 1 1 8ch 6ch 8ch 60
0 128K 4K
48LQFP MC3S12C128 1 1 1 8ch 6ch 8ch 31
52LQFP MC3S12C128 1 1 1 8ch 6ch 8ch 35
80QFP MC3S12C128 1 1 1 8ch 6ch 8ch 60
0 96K 4K
48LQFP MC3S12C96 1 1 1 8ch 6ch 8ch 31
52LQFP MC3S12C96 1 1 1 8ch 6ch 8ch 35
80QFP MC3S12C96 1 1 1 8ch 6ch 8ch 60
0 64K 4K
48LQFP MC3S12C64 1 1 1 8ch 6ch 8ch 31
52LQFP MC3S12C64 1 1 1 8ch 6ch 8ch 35
80QFP MC3S12C64 1 1 1 8ch 6ch 8ch 60
0 32K 2K
48LQFP MC3S12C32 1 1 1 8ch 6ch 8ch 31
52LQFP MC3S12C32 1 1 1 8ch 6ch 8ch 35
80QFP MC3S12C32 1 1 1 8ch 6ch 8ch 60
0 32K 2K
48LQFP MC3S12GC32 0 1 1 8ch 6ch 8ch 31
52LQFP MC3S12GC32 0 1 1 8ch 6ch 8ch 35
80QFP MC3S12GC32 0 1 1 8ch 6ch 8ch 60
0 16K 1K
48LQFP MC3S12GC16 0 1 1 8ch 6ch 8ch 31
52LQFP MC3S12GC16 0 1 1 8ch 6ch 8ch 35
80QFP MC3S12GC16 0 1 1 8ch 6ch 8ch 60
Pin Out Explanations
MC9S12C-Family, Rev. 5
Freescale Semiconductor 5
3 Pin Out Explanations
I/O is the sum of ports capable to act as digital input or output.
• For 80 Pin Versions:
— Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 8, S = 4, T = 8, PAD = 8.
— 12 inputs provide Interrupt capability (P = 8, J = 2, IRQ, XIRQ)
• For 52 Pin Versions:
— Port A = 3, B = 1, E = 2 + 2 input only, M = 6, P = 3, S = 2, T = 8, PAD = 8.
— 5 inputs provide Interrupt capability (P = 3, IRQ, XIRQ)
• For 48 Pin Versions:
— Port A = 1, B = 1, E = 2 + 2 input only, M = 6, P = 1, S = 2, T = 8, PAD = 8.
— 3 inputs provide Interrupt capability (P = 1, IRQ, XIRQ)
MC9S12C-Family, Rev. 5
Block Diagram
Freescale Semiconductor6
4 Block Diagram
Figure 1. Block Diagram
32K, 64K, 96K, 128K Byte Flash/ROM
1K, 2K, 4K Byte RAM
MSCAN
VDDR
VDDA
VSSA
VRH
VRL
ATD
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5
PAD3
PAD4
PAD5
PAD6
PAD7
PAD0
PAD1
PAD2
IOC2
IOC6
IOC0
IOC7
IOC1
IOC3
IOC4
IOC5
PT3
PT4
PT5
PT6
PT7
PT0
PT1
PT2
RXCAN
TXCAN
SCK
MISO
PS3
PS0
PS1
PS2
SS
SPI
PTAD
PTT
DDRT
PTS
DDRS
Voltage Regulator
VDD1
VSS1
PWM
Signals shown in Bold are not available on the 52 or 48 Pin Package
DDRAD
VDDA
VSSA
Timer
Module
VDDX
VSSX
VRH
VRL
VSSR
RESET
EXTAL
XTAL
BKGD
R/W
MODB/IPIPE1
XIRQ
NOACC/XCLKS
System
Integration
Module
(SIM)
HCS12
Periodic Interrupt
COP Watchdog
Clock Monitor
Single-wire Background
PLL
VSSPLL
XFC
VDDPLL
Multiplexed Address/Data Bus
Multiplexed
Wide Bus
IRQ
LSTRB/TAGLO
ECLK
MODA/IPIPE0
PA4
PA3
PA2
PA1
PA0
PA7
PA6
PA5
TEST/VPP
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR15
ADDR14
ADDR13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA15
DATA14
DATA13
PB4
PB3
PB2
PB1
PB0
PB7
PB6
PB5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
ADDR7
ADDR6
ADDR5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
PE3
PE4
PE5
PE6
PE7
PE0
PE1
PE2
DDRA DDRB
PTA PTB
DDRE
PTE
Clock and
Reset
Generation
Module
Debug12 Module
VDD2
VSS2
Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package
CPU
PM3
PM4
PM5
PM0
PM1
PM2
PTM
DDRM
PW2
PW0
PW1
PW3
PW4
PW5
PP3
PP4
PP5
PP6
PP7
PP0
PP1
PP2
PTP
DDRP
PJ6
PJ7
PTJ
DDRJ
VDD1,2
VSS1,2
VDDX
VSSX
Internal Logic 2.5V
VDDPLL
VSSPLL
PLL 2.5V
I/O Driver 5V
VDDA
VSSA
A/D Converter 5V
VDDR
VSSR
Voltage Regulator 5V & I/O
VRL is bonded internally to VSSA
for 52 and 48 Pin packages
MOSI
Module
Keypad Interrupt
Key Int
SCI RXD
TXD
MUX
User Configurable Memory Maps
MC9S12C-Family, Rev. 5
Freescale Semiconductor 7
5 User Configurable Memory Maps
Figure 2. MCxS12C128 User Configurable Memory Map
$0000
$FFFF
$C000
$8000
$4000
$0400
$FF00
EXT
NORMAL
SINGLE CHIP
EXPANDED SPECIAL
SINGLE CHIP
VECTORS
VECTORS
$FF00
$FFFF
BDM
(If Active)
$C000
$FFFF
16K Fixed Flash EEPROM/ROM
$8000
$BFFF
16K Page Window
8 * 16K Flash EEPROM/ROM Pages
$4000
$7FFF
16K Fixed Flash EEPROM/ROM
$3000
$3FFF
$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
Mappable to any 4K Boundary
4K Bytes RAM
$3000
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)
$0000
$3FFF
16K Fixed Flash EEPROM/ROM
VECTORS
Flash Erase Sector Size is 1024 Bytes
MC9S12C-Family, Rev. 5
User Configurable Memory Maps
Freescale Semiconductor8
Figure 3. MCxS12C96 User Configurable Memory Map
$0000
$FFFF
$C000
$8000
$4000
$0400
$FF00
EXT
NORMAL
SINGLE CHIP
EXPANDED SPECIAL
SINGLE CHIP
VECTORS
VECTORS
$FF00
$FFFF
BDM
(If Active)
$C000
$FFFF
16K Fixed Flash EEPROM/ROM
$8000
$BFFF
16K Page Window
6 * 16K Flash EEPROM/ROM Pages
$4000
$7FFF
16K Fixed Flash EEPROM/ROM
$3000
$3FFF
$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
Mappable to any 4K Boundary
4K Bytes RAM
$3000
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)
$0000
$3FFF
16K Fixed Flash EEPROM/ROM
VECTORS
Flash Erase Sector Size is 1024 Bytes
User Configurable Memory Maps
MC9S12C-Family, Rev. 5
Freescale Semiconductor 9
Figure 4. MCxS12C64 User Configurable Memory Map
$0000
$FFFF
$C000
$8000
$4000
$0400
$FF00
EXT
NORMAL
SINGLE CHIP
EXPANDED SPECIAL
SINGLE CHIP
VECTORS
VECTORS
$FF00
$FFFF
BDM
(If Active)
$C000
$FFFF
16K Fixed Flash EEPROM/ROM
$8000
$BFFF
16K Page Window
4 * 16K Flash EEPROM/ROM Pages
$4000
$7FFF
16K Fixed Flash EEPROM/ROM
$3000
$3FFF
$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
Mappable to any 4K Boundary
4K Bytes RAM
$3000
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)
$0000
$3FFF
16K Fixed Flash EEPROM/ROM
VECTORS
Flash Erase Sector Size is 512 Bytes
MC9S12C-Family, Rev. 5
User Configurable Memory Maps
Freescale Semiconductor10
Figure 5. MCxS12C32 User Configurable Memory Map
$0000
$FFFF
$C000
$8000
$4000
$0400
$FF00
EXT
NORMAL
SINGLE CHIP
EXPANDED SPECIAL
SINGLE CHIP
VECTORS
VECTORS
$FF00
$FFFF
BDM
(If Active)
$C000
$FFFF
16K Fixed Flash EEPROM/ROM
$8000
$BFFF
16K Page Window
2 * 16K Flash EEPROM/ROM Pages
$3800
$3FFF
$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
Mappable to any 2K Boundary
2K Bytes RAM
$3800
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0800 - $0FFF: 2K RAM
VECTORS
Flash Erase Sector Size is 512 Bytes
User Configurable Memory Maps
MC9S12C-Family, Rev. 5
Freescale Semiconductor 11
Figure 6. MCxS12C16 User Configurable Memory Map
$0000
$FFFF
$C000
$8000
$4000
$0400
$FF00
EXT
NORMAL
SINGLE CHIP
EXPANDED SPECIAL
SINGLE CHIP
VECTORS
VECTORS
$FF00
$FFFF
BDM
(If Active)
$C000
$FFFF
16K Fixed Flash EEPROM/ROM
$8000
$BFFF
16K Page Window
1 * 16K Flash EEPROM/ROM Page
$3800
$3FFF
$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
Mappable to any 2K Boundary
2K Bytes RAM
$3800
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0800 - $0FFF: 2K RAM
VECTORS
Flash Erase Sector Size is 512 Bytes
MC9S12C-Family, Rev. 5
User Configurable Memory Maps
Freescale Semiconductor12
Figure 7. MCxS12GC16 User Configurable Memory Map
$0000
$FFFF
$C000
$8000
$4000
$0400
$FF00
EXT
NORMAL
SINGLE CHIP
EXPANDED SPECIAL
SINGLE CHIP
VECTORS
VECTORS
$FF00
$FFFF
BDM
(If Active)
$C000
$FFFF
16K Fixed Flash EEPROM/ROM
$8000
$BFFF
16K Page Window
1 * 16K Flash EEPROM/ROM Page
$3C00
$3FFF
$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
Mappable to any 2K Boundary
1K Bytes RAM
$3C00
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0C00 - $0FFF: 1K RAM
VECTORS
Flash Erase Sector Size is 512 Bytes
Pin Assignments
MC9S12C-Family, Rev. 5
Freescale Semiconductor 13
6 Pin Assignments
Figure 8. Pin Assignments for 80-pin QFP for MC9S12C-Family
!!! Pin-out is Subject to Change !!!
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
MC9S12C-Family
80 QFP
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
PP4/KWP4/PW4
PP5/KWP5/PW5
PP7/KWP7
VDDX
VSSX
PM0/RXCAN
PM1/TXCAN
PM2/MISO
PM3/SS
PM4/MOSI
PM5/SCK
PJ6/KWJ6
PJ7/KWJ7
PP6/KWP6/ROMONE
PS3
PS2
PS1/TXD
PS0/RXD
VSSA
VRL
PW3/KWP3/PP3
PW2/KWP2/PP2
PW1/KWP1/PP1
PW0/KWP0/PP0
PW0/IOC0/PT0
PW1/IOC1/PT1
PW2/IOC2/PT2
PW3/IOC3/PT3
VDD1
VSS1
PW4/IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
XCLKS/NOACC/PE7
MODB/IPIPE1/PE6
MODA/IPIPE0/PE5
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST/VPP
LSTRB/TAGLO/PE3
R/W/PE2
IRQ/PE1
XIRQ/PE0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
Signals shown in Bold are not available on the 52 or 48 Pin Package
Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package
MC9S12C-Family, Rev. 5
Pin Assignments
Freescale Semiconductor14
Figure 9. Pin Assignments for 52-pin LQFP for MC9S12C-Family
MC9S12C-Family
52 LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
* Signals shown in Bold are not available on the 48 Pin Package
PP4/KWP4/PW4
PP5/KWP5/PW5
VDDX
VSSX
PM0/RXCAN
PM1/TXCAN
PM2/MISO
PM3/SS
PM4/MOSI
PM5/SCK
PS1/TXD
PS0/RXD
VSSA
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
PA2
PA1
PA0
XCLKS/PE7
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST/VPP
IRQ/PE1
XIRQ/PE0
PW3/KWP3/PP3
PW0/IOC0/PT0
PW1/IOC1/PT1
PW2/IOC2/PT2
PW3/IOC3/PT3
VDD1
VSS1
PW4/IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
MODC/BKGD
PB4
Pin Assignments
MC9S12C-Family, Rev. 5
Freescale Semiconductor 15
Figure 10. Pin Assignments for 48-pin LQFP for MC9S12C-Family
MC9S12C-Family
48 LQFP
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
PP5/KWP5
VDDX
VSSX
PM0/RXCAN
PM1/TXCAN
PM2/MISO
PM3/SS
PM4/MOSI
PM5/SCK
PS1/TXD
PS0/RXD
VSSA
PW0/IOC0/PT0
PW1/IOC1/PT1
PW2/IOC2/PT2
PW3/IOC3/PT3
VDD1
VSS1
PW4/IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
MODC/BKGD
PB4
XCLKS/PE7
ECLK/PE4
VSSR
VDDR
RESET
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST/VPP
IRQ/PE1
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
PA0
XIRQ/PE0
MC9S12C-Family, Rev. 5
Package Mechanical Information
Freescale Semiconductor16
7 Package Mechanical Information
Refer to the following pages for detailed package dimensions.
Package Mechanical Information
MC9S12C-Family, Rev. 5
Freescale Semiconductor 17
MC9S12C-Family, Rev. 5
Package Mechanical Information
Freescale Semiconductor18
Package Mechanical Information
MC9S12C-Family, Rev. 5
Freescale Semiconductor 19
MC9S12C-Family, Rev. 5
Package Mechanical Information
Freescale Semiconductor20
Package Mechanical Information
MC9S12C-Family, Rev. 5
Freescale Semiconductor 21
MC9S12C-Family, Rev. 5
Package Mechanical Information
Freescale Semiconductor22
Package Mechanical Information
MC9S12C-Family, Rev. 5
Freescale Semiconductor 23
MC9S12C-Family, Rev. 5
Package Mechanical Information
Freescale Semiconductor24
Package Mechanical Information
MC9S12C-Family, Rev. 5
Freescale Semiconductor 25
MC9S12CFAMPB
Rev. 5, 03/2006
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