DATASHEET ISL85005, ISL85005A FN8871 Rev.2.00 May 17, 2018 4.5V to 18V Input, 5A High Efficiency Synchronous Buck Regulator The ISL85005 and ISL85005A are monolithic, synchronous buck regulators with integrated 5A, 18V high-side and low-side FETs. These devices provide an integrated bootstrap diode for the high-side gate driver to reduce the external parts count. These devices also have a wide input voltage range to support applications with input voltage from multi-cell batteries or regulated 5V and 12V power rails. Features The ISL85005 and ISL85005A regulate the output voltage with current mode control and have an internal oscillator. The switching frequency of the ISL85005 is internally set as 500kHz, and can be synchronized to an external clock signal with frequency ranges from 300kHz to 2MHz. The ISL85005A has a fixed 500kHz switching frequency. * Current mode control with internal slope compensation * 4.5V to 18V input voltage range * Internal 5A, 18V high-side and low-side MOSFET switches * 1%, 0.8V feedback voltage reference * Integrated bootstrap diode with undervoltage detection * Internal or external compensation options * Default internally set 500kHz switching frequency * Synchronization capability to external clock (ISL85005) * Diode Emulation Mode (DEM) and Forced CCM (FCCM) options (ISL85005) * Adjustable soft-start time (ISL85005A) * Output Power-Good (PG) indicator * Input Undervoltage Lockout (UVLO), input and output overvoltage protection * High-side cycle-by-cycle current limit, low-side forward and reverse overcurrent protection, and thermal shutdown The ISL85005 has a fixed 2.3ms soft-start, while the ISL85005A features programmable soft-start to limit inrush current during startup. With the SS pin floating, the soft-start time of ISL85005A is also 2.3ms. The ISL85005 can be configured in either forced Continuous Conduction Mode (CCM) or Diode Emulation Mode (DEM). DEM enables high efficiency at light-load conditions. The ISL85005A always operates in forced CCM. * Small 12-pin 3mmx4mm Dual Flat No-Lead (DFN) package with EPAD for enhanced thermal performance The ISL85005 and ISL85005A have built-in protections including input UVLO protection, input and output overvoltage protection, high-side cycle-by-cycle current limit, low-side forward current limit and reverse current limit, and thermal shutdown. Applications * Network and communications equipment * Battery powered systems Related Literature * Multifunction printers * Point-of-load regulators For a full list of related documents, visit our website * Standard 12V rail supplies * ISL85005, ISL85005A product pages * Embedded computing systems Typical Application 95 1 SYNC/ MODE PG 2 PG VDD 11 EN 3 EN VIN 10 PGND VIN 9 5 COMP PHASE 8 6 AGND PHASE 7 4 FB R1 R2 C1 85 C4 BOOT 12 C3 VIN 4.5V TO 18V C5 L1 C8 C6 VOUT 5A MAX C9 EFFICIENCY (%) MODE 90 ISL85005 GND = DEM; VCC = FCCM 80 75 70 12V TO 5V 65 12V TO 3.3V 60 12V TO 1.8V 55 50 0 1 2 3 4 OUTPUT CURRENT (A) FIGURE 1. ISL85005 WITH INTERNAL COMPENSATION FN8871 Rev.2.00 May 17, 2018 FIGURE 2. EFFICIENCY vs OUTPUT CURRENT Page 1 of 23 5 ISL85005, ISL85005A Table of Contents Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operation Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FCCM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Light-Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable, Soft-Start, and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 15 16 16 Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forward Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 16 16 16 16 16 Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 17 18 18 19 Compensator Design Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 High DC Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FN8871 Rev.2.00 May 17, 2018 Page 2 of 23 ISL85005, ISL85005A Functional Block Diagram 1 SS (ISL85005A) SOFT-START BOOT CONTROL 12 BOOT UVP SYNC/MODE (ISL85005) 1 VDD UNDERVOLTAGE VIN LDO EN LOCKOUT 11 9 OSCILLATOR 10 CSA 2 PG FAULT 0.8V MONITOR REFERENCE + SLOPE COMP CIRCUITS + - 3 EN + + THERMAL SHUTDOWN 4 FB 600k COMP AGND 8 13 ZERO CROSS DETECTOR AND NEGATIVE CURRENT LIMIT GND DETECTION 6 7 VDD PGND EA - 30pF 5 PHASE GATE DRIVE CONTROL CIRCUIT POSITIVE LS OCP CIRCUIT FIGURE 3. BLOCK DIAGRAM FN8871 Rev.2.00 May 17, 2018 Page 3 of 23 ISL85005, ISL85005A Pin Configurations ISL85005A (12 LD 3x4 DFN) TOP VIEW ISL85005 (12 LD 3x4 DFN) TOP VIEW SYNC/MODE 1 12 BOOT SS 1 12 BOOT PG 2 11 VDD PG 2 11 VDD EN 3 10 VIN EN 3 10 VIN FB 4 9 VIN FB 4 9 VIN COMP 5 8 PHASE COMP 5 8 PHASE AGND 6 7 PHASE AGND 6 7 PHASE PGND (EPAD) PGND (EPAD) Pin Descriptions PIN NUMBER PIN NAME 1 (ISL85005) SYNC/ MODE Synchronization and mode selection input. Connect to VDD for Forced Continuous Conduction Mode (FCCM). Connect to AGND for Diode Emulation Mode (DEM). Connect to an external function generator for synchronization with the positive edge trigger. The internal 1M pull-up resistor to VDD prevents an undefined logic state when SYNC is floating. 1 (ISL85005A) SS Soft-start input. This pin provides a programmable soft-start. When the chip is enabled, the regulated 3.5A pull-up current source charges a capacitor connected from SS to ground. The output voltage of the converter follows the ramping voltage on this pin. Without the external capacitor, the default soft-start is 2.3ms. 2 PG Power-good, open-drain output. Connect a 10k to 100k pull-up resistor between PG and VDD or between PG and a voltage not exceeding 5.5V. PG transitions high about 1.5ms after the switching regulator's output voltage reaches the regulation threshold, which is typically 85% of the regulated output voltage. 3 EN Enable input. The regulator is held off when the pin is pulled to ground. The device is enabled when the voltage on this pin rises above 0.6V. 4 FB Feedback input. The synchronous buck regulator employs a current mode control loop. FB is the negative input to the voltage loop error amplifier. The output voltage is set by an external resistor divider connected to FB. The output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.8V reference. 5 COMP Compensation node. This pin is connected to the output of the error amplifier and compensates the loop. Internal compensation meets most applications. Connect COMP to AGND to select internal compensation. Connect a compensation network between COMP and FB to use external compensation. 6 AGND The AGND terminal. Provides the return path for the core analog control circuitry within the device. Connect AGND to the board ground plane. AGND and PGND are connected internally within the device. Do not operate the device with AGND and PGND connected to dissimilar voltages. Phase switch output node. Connect to the external output inductor. DESCRIPTION 7, 8 PHASE 9, 10 VIN Voltage supply input. The main power input for the IC. Connect to a suitable voltage supply. Place a ceramic capacitor from VIN to PGND, close to the IC for decoupling. 11 VDD Low dropout linear regulator decoupling pin. VDD is the internally generated 5V supply voltage and is derived from VIN. The VDD powers all the internal core analog control blocks and drivers. Connect a 1F capacitor from VDD to the board ground plane. If VIN is between 3V to 5.5V, then connect VDD directly to VIN to improve efficiency. 12 BOOT Bootstrap input. A floating bootstrap supply pin for the upper power MOSFET gate driver. Connect a 0.1F capacitor between BOOT and PHASE. (EPAD) PGND Power ground terminal. Provides thermal relief for the package and is connected to the source of the low-side output MOSFET. Connect PGND to the board ground plane using as many vias as possible. AGND and PGND are connected internally within the device. Do not operate the device with AGND and PGND connected to dissimilar voltages. FN8871 Rev.2.00 May 17, 2018 Page 4 of 23 ISL85005, ISL85005A Ordering Information PART NUMBER (Notes 2, 3, 4) PART MARKING TEMP. RANGE (C) OPTION FREQUENCY (kHz) TAPE AND REEL PACKAGE (UNITS) (Note 1) (RoHS COMPLIANT) PKG. DWG. # ISL85005FRZ 005F -40 to +125 SYNC 500 - 12 Ld DFN L12.3x4 ISL85005FRZ-T 005F -40 to +125 SYNC 500 6k 12 Ld DFN L12.3x4 ISL85005FRZ-TK 005F -40 to +125 SYNC 500 1k 12 Ld DFN L12.3x4 ISL85005FRZ-T7A 005F -40 to +125 SYNC 500 250 12 Ld DFN L12.3x4 ISL85005AFRZ 005A -40 to +125 SOFT-START 500 - 12 Ld DFN L12.3x4 ISL85005AFRZ-T 005A -40 to +125 SOFT-START 500 6k 12 Ld DFN L12.3x4 ISL85005AFRZ-TK 005A -40 to +125 SOFT-START 500 1k 12 Ld DFN L12.3x4 ISL85005AFRZ-T7A 005A -40 to +125 SOFT-START 500 250 12 Ld DFN L12.3x4 ISL85005AEVAL1Z Evaluation Board ISL85005ADEMO1Z Demonstration Board ISL85005EVAL1Z Evaluation Board ISL85005DEMO1Z Demonstration Board NOTES: 1. Refer to TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), see the ISL85005, ISL85005A product information pages. For more information about MSL, refer to TB363. 4. The ISL85005 is provided with a frequency synchronization input. The ISL85005A is a version of the part with programmable soft-start. TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS INTERNAL/EXTERNAL COMPENSATION EXTERNAL FREQUENCY SYNC PROGRAMMABLE SOFT-START SWITCHING FREQUENCY (kHz) CURRENT RATING ISL85005A Yes No Yes 500 5A ISL85005 Yes Yes No 500 5A ISL85003 Yes Yes No 500 3A ISL85003A Yes No Yes 500 3A PART NUMBER FN8871 Rev.2.00 May 17, 2018 Page 5 of 23 ISL85005, ISL85005A Typical Application Schematics ISL85005 GND = DEM; VCC = FCCM MODE 1 SYNC/ BOOT 12 MODE PG EN 2 PG VDD 11 3 EN VIN 10 PGND 4 FB R1 R2 C1 VIN 9 5 COMP PHASE 8 6 AGND PHASE 7 C4 VIN 4.5V TO 18V C3 C6 C5 VOUT 5A MAX L1 C8 C9 FIGURE 4. ISL85005 VIN RANGE FROM 4.5V TO 18V WITH INTERNAL COMPENSATION ISL85005A CSS 1 SS BOOT 12 PG 2 PG VDD 11 EN 3 EN 4 FB R1 R2 C1 C4 VIN 4.5V TO 18V VIN 10 PGND VIN 9 5 COMP PHASE 8 6 AGND PHASE 7 C3 C6 C5 VOUT 5A MAX L1 C8 C9 FIGURE 5. ISL85005A VIN RANGE FROM 4.5V TO 18V, WITH INTERNAL COMPENSATION WITH PROGRAMMABLE SOFT-START TABLE 2. COMPONENTS SELECTION (REFER TO Figures 1 AND 2) VOUT 1.2V 1.8V 2.5V 3.3V 5V C5, C6 1OF 1OF 1OF 1OF 1OF C8, C9 47F 47F 47F 47F 47F C1 12pF 12pF 12pF 12pF 12pF L1 3.3H 3.3H 3.3H 3.3H 3.3H R1 499k 499k 499k 499k 499k R2 998k 392k 232k 157k 95.3k NOTE: VIN = 12V, IOUT = 5A; The components selection table is a suggestion for typical application using internal compensation mode. For application that requires high output capacitance greater than 200F, R1 should be adjusted to maintain loop response bandwidth about 40kHz. See "Loop Compensation Design" on page 19 for more detail. FN8871 Rev.2.00 May 17, 2018 Page 6 of 23 ISL85005, ISL85005A Absolute Maximum Ratings Thermal Information VIN, EN to AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to + 24V PHASE to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . -0.7V to +24V (DC) PHASE to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . -2V to +24V (40ns) FB to AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to + 7V BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to + 7V VDD, COMP, SYNC, PG to AGND and PGND . . . . . . . . . . . . . . . -0.3V to + 7V Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . .-55C to +150C ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .2.5kV Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . 150V Charged Device Model (Tested per JESD22-C101-E) . . . . . . . . . . . . . 1kV Latch-Up (Tested per JESD-78D; Class 2, Level A) . . . . . . . . . . . . . . 100mA Thermal Resistance JA (C/W) JC (C/W) DFN Package (Notes 5, 6) . . . . . . . . . . . . . . 41 3 Maximum Storage Temperature Range . . . . . . . . . . . . . .-65C to +150C Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40C to +125C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 18V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 5A CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with "direct attach" features. See TB379. 6. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. Electrical Specifications All parameter limits are established over the recommended operating conditions with TJ = -40C to +125C, and with VIN = 12V unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply across the operating junction temperature range, -40C to +125C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 7) MAX (Note 7) UNIT 18 V 3.2 4.5 mA TYP SUPPLY VOLTAGE VIN Voltage Range VIN VIN Quiescent Supply Current IQ SYNC = Low, EN > 1V, FB = 0.85V, not switching VIN Shutdown Supply Current ISD EN = AGND 6 11 A Rising edge 4.20 4.35 V 4.5 UNDERVOLTAGE LOCKOUT VIN UVLO Threshold Falling edge 3.5 3.8 VIN = 6V to 18V, IVDD = 0mA to 30mA 4.30 5.00 V INTERNAL VDD LDO VDD Output Voltage VDD Output Current Limit 5.50 50 V mA OSCILLATOR Nominal Switching Frequency fSW Minimum On-Time tON Minimum Off-Time Synchronization Range 400 500 600 kHz IOUT = 0mA (Note 8) 120 140 ns tOFF (Note 8) 140 180 ns SYNC ISL85005 300 2000 kHz SYNC High-Time tHI ISL85005 100 ns SYNC Low-Time tLO ISL85005 100 ns SYNC Logic Input Low ISL85005 0.50 SYNC Logic Input High ISL85005 1.20 VIN = 4.5V to 18V 0.792 V V ERROR AMPLIFIER FB Regulation Voltage VFB FB Leakage Current Open-Loop Bandwidth Gain FN8871 Rev.2.00 May 17, 2018 VFB = 0.8V (Note 8) BW 0.800 0.808 V 0.3 10.0 nA 5.5 MHz 70 dB Page 7 of 23 ISL85005, ISL85005A Electrical Specifications All parameter limits are established over the recommended operating conditions with TJ = -40C to +125C, and with VIN = 12V unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply across the operating junction temperature range, -40C to +125C. (Continued) PARAMETER SYMBOL Output Drive TEST CONDITIONS MIN (Note 7) VCOMP = 1.5V Current Sense Gain RT Slope Compensation Se fSW = 500kHz TYP MAX (Note 7) UNIT 110 A 0.15 550 mV/s ENABLE INPUT EN Input Threshold Rising edge 0.5 0.6 0.7 V Hysteresis 60 100 140 mV Default Soft-Start Time ISL85005, ISL85005A with SS pin floating 1.0 2.3 3.6 ms SS Internal Soft-Start Charging Current ISL85005A 2.5 3.5 4.5 A SOFT-START FUNCTION POWER-GOOD OPEN-DRAIN OUTPUT Output Low Voltage IPG = 5mA sinking 0.25 V PG Pin Leakage Current VPG = VDD 0.01 A PG Lower Threshold Percentage of output regulation 80 85 90 PG Upper Threshold Percentage of output regulation 110 115 120 PG Thresholds Hysteresis Delay Time % % 3 % Rising edge 1.5 ms Falling edge 18 s FAULT PROTECTION High-Side MOSFET Forward Current Limit Threshold IPOCP Low-Side MOSFET Reverse Current Limit Threshold INOCP 6 7.8 A 9.5 Current forced into PHASE node, high-side MOSFET is off, SYNC = High -3.3 A Low-Side MOSFET Forward Current Limit Threshold Current in low-side MOSFET at end of low-side cycle. 8.6 A VIN Overvoltage Threshold VIN rising 20 V 1 V 19 Hysteresis Thermal Shutdown Threshold TSD Temperature rising 165 C THYS Hysteresis 10 C High-Side MOSFET On-Resistance RHDS IPHASE = 100mA 57 95 m Low-Side MOSFET On-Resistance RLDS IPHASE = 100mA 40 75 m EN = AGND 10 k ISL85005 150 mA POWER MOSFET PHASE Pull-Down Resistor DIODE EMULATION Zero-Cross Detection Threshold NOTE: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. 8. Compliance to limits is assured by characterization and design. FN8871 Rev.2.00 May 17, 2018 Page 8 of 23 ISL85005, ISL85005A 10 10 9 9 QUIESCENT CURRENT (mA) SHUTDOWN CURRENT (A) Typical Characteristics VIN = 12V, TA = +25C, unless otherwise noted. 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 0 0 -40 -25 -10 5 20 35 50 65 80 95 -40 110 125 -25 -10 0.83 0.9 0.82 0.8 EN THRESHOLD (V) FB REFERENCE VOLTAGE (V) 20 35 50 65 80 95 110 125 FIGURE 7. VIN QUIESCENT CURRENT vs JUNCTION TEMPERATURE FIGURE 6. VIN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 0.81 0.80 0.79 0.78 EN RISING EN FALLING 0.7 0.6 0.5 0.4 0.3 0.2 0.77 -40 -25 -10 5 20 35 50 65 80 95 -40 110 125 -25 -10 JUNCTION TEMPERATURE (oC) 5 20 35 50 65 80 95 110 125 JUNCTION TEMPERATURE (oC) FIGURE 8. FEEDBACK VOLTAGE vs JUNCTION TEMPERATURE FIGURE 9. ENABLE THRESHOLDS vs JUNCTION TEMPERATURE 4.5 560 UVLO START SWITCHING SWITCHING FREQUENCY (kHz) VIN UVLO THRESHOLD (V) 5 JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC) UVLO STOP SWITCHING 4.3 4.1 3.9 3.7 3.5 3.3 540 520 500 480 460 440 420 400 -40 -25 -10 5 20 35 50 65 80 95 110 125 JUNCTION TEMPERATURE (oC) FIGURE 10. VIN UVLO THRESHOLD vs JUNCTION TEMPERATURE FN8871 Rev.2.00 May 17, 2018 -40 -25 -10 5 20 35 50 65 80 95 110 125 JUNCTION TEMPERATURE (oC) FIGURE 11. SWITCHING FREQUENCY vs JUNCTION TEMPERATURE Page 9 of 23 ISL85005, ISL85005A Typical Characteristics VIN = 12V, TA = +25C, unless otherwise noted. (Continued) 2.4 26 PG RISING EDGE DELAY (ms) PG FALLING EDGE DELAY (s) 28 24 22 20 18 16 14 12 2.0 1.6 1.2 0.8 10 -40 -25 -10 5 20 35 50 65 80 95 0.4 110 125 -40 -25 -10 JUNCTION TEMPERATURE (oC) 12 35 50 65 80 95 110 125 0 REVERSE OCP THRESHOLD (A) FORWARD OCP THRESHOLD (A) 20 FIGURE 13. PG DELAY (RISING) vs JUNCTION TEMPERATURE FIGURE 12. PG DELAY (FALLING) vs JUNCTION TEMPERATURE 11 10 9 8 7 6 HIGH SIDE MOSFET 5 LOW SIDE MOSFET -1 -2 -3 -4 -5 -6 4 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 JUNCTION TEMPERATURE (oC) 5 20 35 50 65 80 95 110 125 JUNCTION TEMPERATURE (oC) FIGURE 14. FORWARD OCP THRESHOLD vs JUNCTION TEMPERATURE FIGURE 15. LOW-SIDE REVERSE OCP THRESHOLD vs JUNCTION TEMPERATURE 80 80 LOW-SIDE ON-RESISTANCE (m) HIGH-SIDE ON-RESISTANCE (m) 5 JUNCTION TEMPERATURE (oC) 70 60 50 40 30 20 10 0 70 60 50 40 30 20 10 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 JUNCTION TEMPERATURE (oC) FIGURE 16. HIGH-SIDE rDS(ON) vs JUNCTION TEMPERATURE FN8871 Rev.2.00 May 17, 2018 -40 -25 -10 5 20 35 50 65 80 95 110 125 JUNCTION TEMPERATURE (oC) FIGURE 17. LOW-SIDE rDS(ON) vs JUNCTION TEMPERATURE Page 10 of 23 ISL85005, ISL85005A Typical Performance Curves Circuit of Figure 1. VIN = 12V, VOUT = 5V, L = 3.3H, fSW = 500kHz, TA = +25C, unless 100 100 95 95 90 90 85 85 EFFICIENCY (%) EFFICIENCY (%) otherwise noted. 80 75 70 65 80 75 70 65 60 VIN = 12V, DEM 60 55 VIN = 12V, FORCED CCM 55 VIN = 12V, DEM VIN = 5V, DEM 50 50 0 1 2 3 4 0 5 1 100 95 95 90 90 85 EFFICIENCY (%) EFFICIENCY (%) 100 80 75 70 VIN = 12V, FORCED CCM 4 80 75 70 65 60 VIN = 12V, DEM 55 VIN = 5V, DEM 50 50 VIN = 5V, FORCED CCM 0 1 2 5 85 55 60 3 4 0 5 1 2 3 4 5 OUTPUT CURRENT (A) OUTPUT CURRENT (A) FIGURE 20. EFFICIENCY vs LOAD, VOUT = 3.3V, FORCED CCM FIGURE 21. EFFICIENCY vs LOAD, VOUT = 2.5V, DEM 100 100 95 95 90 90 85 85 EFFICIENCY (%) EFFICIENCY (%) 3 FIGURE 19. EFFICIENCY vs LOAD, VOUT = 3.3V, DEM FIGURE 18. EFFICIENCY vs LOAD, VOUT = 5V 65 2 OUTPUT CURRENT (A) OUTPUT CURRENT (A) 80 75 70 65 80 75 70 65 60 V IN = 12V, FORCED CCM 60 VIN = 12V, DEM 55 V IN = 5V, FORCED CCM 55 VIN = 5V, DEM 50 50 0 1 2 3 4 5 OUTPUT CURRENT (A) FIGURE 22. EFFICIENCY vs LOAD, VOUT = 2.5V, FORCED CCM FN8871 Rev.2.00 May 17, 2018 0 1 2 3 4 5 OUTPUT CURRENT (A) FIGURE 23. EFFICIENCY vs LOAD, VOUT = 1.8V, DEM Page 11 of 23 ISL85005, ISL85005A Typical Performance Curves Circuit of Figure 1. VIN = 12V, VOUT = 5V, L = 3.3H, fSW = 500kHz, TA = +25C, unless 100 100 95 95 90 90 85 85 EFFICIENCY (%) EFFICIENCY (%) otherwise noted. (Continued) 80 75 70 65 80 75 70 65 60 VIN = 12V, FORCED CCM 60 VIN = 12V, DEM 55 VIN = 5V, FORCED CCM 55 VIN = 5V, DEM 50 50 0 1 2 3 4 5 0 1 2 3 4 5 OUTPUT CURRENT (A) OUTPUT CURRENT (A) FIGURE 24. EFFICIENCY vs LOAD, VOUT = 1.8V, FORCED CCM FIGURE 25. EFFICIENCY vs LOAD, VOUT = 1.2V, DEM 100 95 VOUT (2V/DIV) EFFICIENCY (%) 90 85 80 75 70 65 60 VIN = 12V, FORCED CCM 55 VIN = 5V, FORCED CCM IL (2A/DIV) EN (10V/DIV) 50 0 1 2 3 4 5 1ms/DIV OU TPUT CURRENT (A) FIGURE 26. EFFICIENCY vs LOAD, VOUT = 1.2V, FORCED CCM FIGURE 27. START-UP WITH EN, NO LOAD VOUT (2V/DIV) VOUT (2V/DIV) IL (2A/DIV) IL (2A/DIV) VIN (5V/DIV) EN (10V/DIV) 1ms/DIV 2ms/DIV FIGURE 28. START-UP WITH EN, IOUT = 5A FIGURE 29. START-UP WITH VIN, NO LOAD FN8871 Rev.2.00 May 17, 2018 Page 12 of 23 ISL85005, ISL85005A Typical Performance Curves Circuit of Figure 1. VIN = 12V, VOUT = 5V, L = 3.3H, fSW = 500kHz, TA = +25C, unless otherwise noted. (Continued) VOUT (2V/DIV) VOUT (2V/DIV) IL (2A/DIV) IL (2A/DIV) VIN (5V/DIV) EN (10V/DIV) 2ms/DIV 50ms/DIV FIGURE 30. START-UP WITH VIN, IOUT = 5A FIGURE 31. SHUTDOWN WITH EN, IOUT = 10mA VOUT (2V/DIV) VOUT (2V/DIV) IL (2A/DIV) IL (2A/DIV) VIN (10V/DIV) EN (10V/DIV) 200s/DIV 50ms/DIV FIGURE 32. SHUTDOWN WITH EN, IOUT = 5A FIGURE 33. SHUTDOWN WITH VIN, IOUT = 10mA VOUT (2V/DIV) IL (500mA/DIV) IL (2A/DIV) VIN (10V/DIV) PHASE (5V/DIV) 200s/DIV 1s/DIV FIGURE 34. SHUTDOWN WITH VIN, IOUT = 5A FIGURE 35. STEADY STATE OPERATION IN DCM, IOUT = 0.2A FN8871 Rev.2.00 May 17, 2018 Page 13 of 23 ISL85005, ISL85005A Typical Performance Curves Circuit of Figure 1. VIN = 12V, VOUT = 5V, L = 3.3H, fSW = 500kHz, TA = +25C, unless otherwise noted. (Continued) IL (500mA/DIV) VOUT (100mV/DIV), AC COUPLING IOUT (1A/DIV) PHASE (5V/DIV) 1s/DIV 50s/DIV FIGURE 36. STEADY STATE IN FORCED CCM, IOUT = 0.2A FIGURE 37. LOAD TRANSIENT, 0A 2.5A 0A, 2.5A/s VOUT (200mV/DIV), AC COUPLING VOUT (2V/DIV) IL (2A/DIV) IOUT (2A/DIV) 50s/DIV 2ms/DIV FIGURE 38. LOAD TRANSIENT, 0A 5A 0A, 2.5A/s FIGURE 39. HIGH-SIDE FORWARD OVER CURRENT PROTECTION IL (2A/DIV) IL (2A/DIV) PHASE (5V/DIV) PHASE (10V/DIV) 20s/DIV FIGURE 40. OUTPUT SHORT-CIRCUIT BEHAVIOR FN8871 Rev.2.00 May 17, 2018 1s/DIV FIGURE 41. LOW-SIDE MOSFET REVERSE OVER CURRENT PROTECTION Page 14 of 23 ISL85005, ISL85005A Detailed Description The ISL85005 and ISL85005A combine a synchronous buck controller with a pair of integrated switching MOSFETs. The buck controller drives the internal high-side and low-side N-channel MOSFETs to deliver load currents up to 5A. The buck regulator can operate from an unregulated DC source, such as a battery, with a voltage ranging from +4.5V to +18V. An internal 5V LDO voltage regulator is used to bias the controller. The converter output voltage is programmed using an external resistor divider and generates regulated voltages down to 0.8V. These features make the regulator suited for a wide range of applications. The controller uses a current mode loop, which simplifies the loop compensation and permits fixed frequency operation over a wide range of input and output voltages. The internal feedback loop compensation option allows for a lower number of external components. The regulator switches at a default of 500kHz, or it can be synchronized from 300kHz to 2MHz on the ISL85005. The buck regulator is equipped with a lossless current limit scheme. The current in the output stage is derived from temperature compensated measurements of the drain-to-source voltage of the internal power MOSFETs. The current limit threshold is internally set at 7.8A. Operation Initialization To start operation, pull EN above 0.6V (typical). The power-on reset circuitry prevents operation if the input voltage is below 4.2V. When the power-on reset requirement is met, the controller soft-starts with a 2.3ms ramp on the ISL85005 or at a rate determined by the value of a capacitor connected between SS and AGND on the ISL85005A. FCCM Control Scheme The regulator employs a current mode Pulse-Width Modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. The current loop consists of the oscillator, the PWM comparator, current-sensing circuit, and a slope compensation circuit. The gain of the current-sensing circuit is typically 150mV/A and the slope compensation is 1.1V/T. The reference for the current loop is in turn provided by the output of an Error Amplifier (EA), which compares the feedback signal at the FB pin to the integrated 0.8V reference. Therefore, the output voltage is regulated by using the error amplifier to control the reference for the current loop. The error amplifier is an operational amplifier that converts the voltage error signal to a voltage output. The voltage loop is internally compensated with the 30pF and 600k RC network that can support most applications. PWM operation is initialized by the clock from the oscillator. The upper MOSFET is turned on at the beginning of a cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA signal and the slope compensation reaches the control reference of the current loop, the PWM comparator sends a signal to the logic to turn off the upper MOSFET and turn on the lower MOSFET. The lower MOSFET stays on until the end of the cycle. Figure 42 shows the typical operating waveforms during Continuous Conduction Mode (CCM) operation. The dotted lines illustrate the sum of the compensation ramp and the current-sense amplifier's output. VEAMP VCSA DUTY CYCLE IL VOUT FIGURE 42. CCM OPERATION WAVEFORMS Light-Load Operation The ISL85005 monitors both the current in the low-side MOSFET and the voltage of the FB node for regulation. Pulling the SYNC/MODE pin low allows the ISL85005 to enter discontinuous operation when lightly loaded by operating the low-side MOSFET in Diode Emulation Mode (DEM). In this mode, reverse current is not allowed in the inductor, and the output falls naturally to the regulation voltage before the high-side MOSFET is switched for the next cycle. The boundary is set by Equation 1: V OUT 1 - D I OUT = ----------------------------------2Lf SW (EQ. 1) where D = duty cycle, fSW = switching frequency, L = inductor value, IOUT = output loading current, VOUT = output voltage. Synchronization Control The ISL85005 can be synchronized from 300kHz to 2MHz by an external signal applied to the SYNC pin. The rising edge on the SYNC triggers the rising edge of the PHASE pulse. Make sure that the on-time of the SYNC pulse is greater than 100ns. Although the maximum synchronized frequency can be as high as 2MHz, the ISL85005 is a current mode regulator that requires a minimum of 140ns on-time to regulate properly. As an example, the maximum recommended synchronized frequency will be about 600kHz with 12VIN and 1VOUT. FN8871 Rev.2.00 May 17, 2018 Page 15 of 23 ISL85005, ISL85005A Enable, Soft-Start, and Disable Forward Overcurrent Protection Chip operation begins after VIN exceeds its rising POR trip point (nominal 4.2V). If EN is held low externally, nothing happens until this pin is released. When the voltage on the EN pin is above 0.6V, the LDO powers up and soft-start control begins. The default soft-start time is 2.3ms. The current flowing through the internal high-side MOSFET is monitored during the on-time and compared to a typical 7.8A overcurrent limit threshold. If the current exceeds the overcurrent limit threshold, the high-side MOSFET is immediately turned off and does not turn on again until the next switching cycle. The current through the low-side switching MOSFET is sampled during off time. If the low-side MOSFET current exceeds 8.6A at the end of the low-side cycle, then the high-side MOSFET skips the next cycle, allowing the inductor current to decay to a safe level before resuming switching. On the ISL85005A, let SS float to select the internal soft-start time with a default of 2.3ms. The soft-start time is extended by connecting an external capacitor between SS and AGND. A 3.5A current source charges up the capacitor. The soft-start capacitor is charged until the voltage on the SS pin reaches a 2.0V clamp level. However, the output voltage reaches its regulation value when the voltage on the SS pin reaches approximately 0.9V. The capacitor, along with an internal 3.5A current source, sets the soft-start interval of the converter, tSS, according to Equation 2: C SS nF = 3.5 t SS mS - 1.6nF (EQ. 2) Output Voltage Selection The regulator output voltage is programmed using an external resistor divider that scales the feedback relative to the internal reference voltage. The scaled voltage is fed back to the inverting input of the error amplifier (see Figure 43). The output voltage programming resistor, R2, depends on the value chosen for the feedback resistor, R1, and the desired regulator output voltage, VOUT (see Equation 2). The R1 value determines the gain of the feedback loop. See "Loop Compensation Design" on page 19 for more details. The value for the feedback resistor is typically between 10k and 600k. R 1 0.8V R 2 = ---------------------------------V OUT - 0.8V (EQ. 3) If the output voltage desired is 0.8V, then R2 is left unpopulated. R1 is still required to set the low frequency pole of the modulator compensation. VOUT R1 + - EA R2 0.8V REFERENCE FIGURE 43. EXTERNAL RESISTOR DIVIDER Reverse Overcurrent Protection Similar to the overcurrent, the negative current protection is enabled by monitoring the current across the low-side MOSFET, as shown in Figure 41 on page 14. When the inductor current reaches -3.3A, the synchronous rectifier is turned off. This limits the ability of the regulator to actively pull down the output voltage and prevents large reverse currents that may fall outside the range of the high-side current-sense amplifier. Output Overvoltage Protection The output overvoltage protection is triggered when the output voltage exceeds 115% of the nominal voltage setting point. In this condition, high-side and low-side MOSFETs are turned off until the output drops to within the regulation band. When the output is in regulation, the controller restarts under internal SS control. Input Overvoltage Protection The input overvoltage protection system prevents operation of the switching regulator when the input voltage is higher than 20V. The high-side and low-side MOSFETs are turned off and the converter restarts under internal SS control when the input voltage returns to normal. Thermal Overload Protection Thermal overload protection limits the maximum die temperature, and thus the total power dissipation in the regulator. A sensor on the chip monitors the junction temperature. A signal is sent to the fault monitor circuits whenever the junction temperature (TJ) exceeds +165C, and this causes the switching regulator and LDO to shut down. The switching regulator turns on again and soft-starts after the IC's junction temperature cools by 10C. For continuous operation, do not exceed the +125C junction temperature rating. Protection Features Power Derating Characteristics The regulator limits current in all on-chip power devices. Overcurrent limits are applied to the two output switching MOSFETs as well as to the LDO linear regulator that feeds VDD. Input and output overvoltage protection circuitry on the switching regulator provides a second layer of protection. To prevent the regulator from exceeding the maximum junction temperature, some thermal analysis is required. The temperature rise is given by Equation 4: T RISE = PD JA (EQ. 4) where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient FN8871 Rev.2.00 May 17, 2018 Page 16 of 23 ISL85005, ISL85005A temperature. The junction temperature, TJ, is given by Equation 5: the manufacturer of the load on specific decoupling requirements. (EQ. 5) T J = T A + T RISE where TA is the ambient temperature. The DFN package's JA is 49 (C/W). The actual junction temperature should not exceed the absolute maximum junction temperature of +125C when considering the thermal design. T Application Guidelines Boot Undervoltage Detection The internal driver of the high-side FET is equipped with a boot Undervoltage (UV) detection circuit. If the voltage difference between BOOT and PHASE falls below 2.5V, the UV detection circuit allows the low-side MOSFET on for 300ns to recharge the bootstrap capacitor. Although the ISL85005 and ISL85005A include an internal bootstrap diode, efficiency can be improved by using an external supply voltage and bootstrap Schottky diode. The external diode is then sourced from a fixed external 5V supply or from the output of the switching regulator if this is at 5V. The bootstrap diode can be a low cost type, such as the BAT54. The shape of the output voltage waveform during a load transient that represents the worst case loading conditions ultimately determines the number of output capacitors and their type. When this load transient is applied to the converter, most of the energy required by the load is initially delivered from the output capacitors. This is due to the finite amount of time required for the inductor current to slew up to the level of the output current required by the load. This phenomenon results in a temporary dip in the output voltage. At the very edge of the transient, the Equivalent Series Inductance (ESL) of each capacitor induces a spike that adds on top of the existing voltage drop due to the ESR. After the initial spike, attributable to the ESR and ESL of the capacitors, the output voltage experiences sag. This sag is a direct consequence of the amount of capacitance on the output. During the removal of the same output load, the energy stored in the inductor is dumped into the output capacitors. This energy dumping creates a temporary hump in the output voltage. This hump, as with the sag, can be attributed to the total amount of capacitance on the output. Figure 45 shows a typical response to a load transient. PHASE ISL85005 ISL85005A BOOT VHUMP C4 0.1F VOUT VESR VSAG BAT54 VESL 5VOUT or 5V SOURCE FIGURE 44. EXTERNAL BOOTSTRAP DIODE IOUT Switching Regulator Output Capacitor Selection An output capacitor is required to filter the inductor current and supply the load transient current. The filtering requirements are a function of the switching frequency, the ripple current, and the required output ripple. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitor types and careful layout. High-frequency ceramic capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the Equivalent Series Resistance (ESR) and voltage rating requirements rather than actual capacitance requirements. Place he high-frequency decoupling capacitors as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with FN8871 Rev.2.00 May 17, 2018 Itran FIGURE 45. TYPICAL TRANSIENT RESPONSE The amplitudes of the different types of voltage excursions can be approximated using Equations 6, 7, 8, and 9. V ESR = ESR I tran (EQ. 6) dI tran V ESL = ESL --------------dt (EQ. 7) 2 L OUT I tran V SAG = ----------------------------------------------------------C OUT V IN - V OUT (EQ. 8) Page 17 of 23 ISL85005, ISL85005A 2 L OUT I tran V HUMP = -------------------------------------C OUT V OUT (EQ. 9) where Itran = Output load current transient and COUT = Total output capacitance. In a typical converter design, the ESR of the output capacitor bank dominates the transient response. The ESR and the ESL are typically the major contributing factors in determining the output capacitance. The number of output capacitors can be determined by using Equation 10, which relates the ESR and ESL of the capacitors to the transient load step and the voltage limit (VO): L x Itran tRISE = VIN - VOUT L x Itran (EQ. 10) If VSAG or VHUMP are too large for the output voltage limits, then the amount of capacitance may need to be increased. In this situation, a trade-off between output inductance and output capacitance may be necessary. The ESL of the capacitors, which is an important parameter in the above equations, is not usually listed in the specification. Practically, it can be approximated using Equation 11 if an Impedance vs Frequency curve is given for a specific capacitor: (EQ. 11) where fres is the resonant frequency in which the lowest impedance is achieved. The ESL of the capacitors becomes a concern when designing circuits that supply power to loads with high rates of change in the current. Output Inductor Selection Select the output inductor to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the output ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by Equations 12 and 13: (EQ. 12) VOUT = I x ESR (EQ. 13) Increasing the inductance value reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. Furthermore, the ripple current is an important signed-in current mode control. Therefore, set the ripple inductor current to approximately 30% of the maximum output current for optimized performance. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the regulator will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the VOUT (EQ. 14) (EQ. 15) where Itran is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection Use a mix of input bypass capacitors to control the input voltage ripple. Use ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the switching MOSFET turns on. Place the ceramic capacitors physically close to the MOSFET VIN pins (switching MOSFET drain) and PGND. The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. For most cases, the RMS current rating requirement for the input capacitor of a buck regulator is approximately half the DC load current. The maximum RMS current required by the regulator may be more closely approximated through Equation 16: I RMS V IN - V OUT V OUT I = ------------------------------------ ---------------V IN Fs L FN8871 Rev.2.00 May 17, 2018 The response time to a transient is different for the application of load and the removal of load. Equations 14 and 15 give the approximate response time interval for application and removal of a transient load: tFALL = ESL I tran ------------------------------ + ESR I tran dt Number of Caps = -------------------------------------------------------------------V O 1 ESL = ---------------------------------------2 C 2 f res inductor current from an initial current value to the transient current level. During this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. MAX = V OUT V IN - V OUT V OUT 2 2 1 -------------- I OUT + ------ ----------------------------- -------------- V IN V IN L fs 12 MAX (EQ. 16) For a through-hole design, several electrolytic capacitors may be needed, especially at temperatures less than -25C. The electrolytic's ESR can increase ten times higher than at room temperature and cause input line oscillation. In this case, use a more thermally stable capacitor such as X7R ceramic. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. Some capacitor series available from reputable manufacturers are surge current tested. Page 18 of 23 ISL85005, ISL85005A Compensator Design Goal Loop Compensation Design When COMP is not connected to GND, the COMP pin is active for external loop compensation. In an application with extreme temperatures, such as less than -10C or greater than +85C, use external compensation. The regulator uses constant frequency peak current mode control architecture to achieve a fast loop transient response. An accurate current sensing pilot device in parallel with the upper MOSFET is used for peak current control signal and overcurrent protection. The inductor is not considered a state variable because its peak current is constant, and the system becomes a single order system. It is much easier to design a Type II compensator to stabilize the loop than to implement voltage mode control. Peak current mode control has an inherent input voltage feed-forward function to achieve good line regulation. Figure 46 shows the small signal model of the synchronous buck regulator. + ^ iin ^ iL LP RLP V ^ ^ ILd 1:D IN d ^ VIN + GAIN (VLOOP (S(fi)) RT Rc Ro * Gain margin: >10dB * Phase margin: >40 The compensator design procedure is as follows: The loop gain at crossover frequency of fc has a unity gain. Therefore, the compensator resistance, R6, is determined by Equation 18. (EQ. 18) R 6 = 2f c C o R t R 1 f c C o R 1 Vo Co Ro Co C 6 = --------------- = ------------------10R 6 10I o R 6 Ti (S) d^ Choose Loop bandwidth fc of approximately 50kHz or 1/10 of the switching frequency. Note that Co is the actual capacitance seen by the regulator, which may include ceramic high frequency decoupling and bulk output capacitors. Ceramic may have to be derated by approximately 40% depending on dielectric, voltage stress, and temperature. Compensator capacitor C6 is then given by Equations 19 and 20. ^ v o Co High DC Gain K (EQ. 19) Fm + Rc Co 1 -,----------------] C 7 = max [-------------10R 6 f s R 6 Tv(S) He(S) ^ Vcomp -Av(S) FIGURE 46. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR R6 R1 C3 Put compensator zero, CZ2 from 1/2fc to fc. - VCOMP + VREF FIGURE 47. TYPE II COMPENSATOR Figure 47 shows the Type II compensator. Its transfer function is expressed, as shown in Equation 17: S S 1 + ------------ 1 + ------------- v comp 1 cz1 cz2 - = -------------------------------------- -------------------------------------------------------------A v S = --------------- C6 + C7 R1 S S v o S 1 + ------------- 1 + ------------ cp1 (EQ. 21) For internal compensation mode, R6 is equal 600k and C6 is 30pF. Equation 18 can be rearranged to solve for R1. C6 VFB R2 An optional zero can boost the phase margin. CZ2 is a zero due to R1 and C3. 1 C 3 = -------------------2f c R 1 C7 VO (EQ. 20) (EQ. 17) cp2 where: C6 + C7 1 1 cz1 = --------------- , cz2 = --------------- cp1 = ----------------------- cp2 350kHz R6 C6 C7 R6 C6 R1 C3 Layout Considerations The layout is very important in a high frequency switching converter design. With power devices switching efficiently at 500kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and Printed Circuit Board (PCB) design minimizes these voltage spikes. A snubber can be added to reduce voltage spikes. The snubber consists of a resistor and a capacitor that are connected in series from the PHASE pin to PGND pin. The snubber damps the voltage ringing caused by parasitic inductance and capacitance. Another option to reduce voltage spikes is to add a boot resistor in series with the boot capacitor, which slows down the turn-on of the high-side FET and allows more time for the parasitic network to discharge. As an example, consider the turn-off transition of the upper MOSFET. Before turn-off, the MOSFET is carrying the full load FN8871 Rev.2.00 May 17, 2018 Page 19 of 23 ISL85005, ISL85005A current. During turn-off, current stops flowing in the MOSFET and is picked up by the internal body diode. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimize the magnitude of voltage spikes. VIN CIN ISL85005 ISL85005A Place the switching components close to the regulator first. Minimize the length of the connections between the input capacitors, CIN, and the power switches by placing them nearby. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible. VOUT1 COMP C6 C7 R6 R1 FB PGND PAD LOAD COUT1 PGND R2 C3 KEY ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE FIGURE 48. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS The critical small signal components include any bypass capacitors, feedback components, and compensation components. Place the compensation components close to the FB and COMP pins. Place the feedback resistors as close as possible to the FB pin with vias tied straight to the ground plane. Figure 49 shows a recommended layout example. VIN PHASE L1 CIN GND COUT VOUT To dissipate heat generated by the internal LDO and MOSFETs, the ground pad should be connected to the internal ground plane through at least five vias. This allows the heat to move away from the IC and ties the pad to the ground plane through a low impedance path. L PHASE There are two sets of critical components in the regulator switching converter. The switching components are the most critical because they switch large amounts of energy and therefore tend to generate large amounts of noise. Next are the small signal components, which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer PCB is recommended. Figure 48 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PCB, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminals to the output inductor short. The power plane should support the input power and output power nodes. Use copper-filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. VIN FIGURE 49. RECOMMEND LAYOUT (TOP LAYER) FN8871 Rev.2.00 May 17, 2018 Page 20 of 23 ISL85005, ISL85005A Revision History The revision history provided is for informational purposes only and is believed to be accurate, however, not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION May 17, 2018 FN8871.2 Updated Pin Configuration labels from "4X3" to "3X4". Updated Ordering information by adding tape and reel parts to table, adding tape and reel quantity column, updating Note 1, adding demonstration board parts. Removed About Intersil section and updated disclaimer. Aug 17, 2017 FN8871.1 In the Component Selection Table, for C1, changed "15pF" to "12pF" for all voltages. Updated Figures 27-34. Updated Figure 39. In Output Voltage Selection on page 16, changed the maximum value of the feedback resistor from "400k" to "600k". In Layout Considerations on page 19, added the second paragraph, which is a description of a snubber. Updated Figure 49. Nov 28, 2016 FN8871.0 Initial release FN8871 Rev.2.00 May 17, 2018 CHANGE Page 21 of 23 ISL85005, ISL85005A Package Outline Drawing For the most recent package outline drawing, see L12.3x4. L12.3x4 12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/15 3.00 B 6 PIN 1 INDEX AREA 1 12 4.00 (4X) 6 PIN #1 INDEX AREA SEE DETAIL "X" A 3.30 0.10 0.10 2X 2.50 6 7 12X 0.25 0.05 0.10 M C A B TOP VIEW 0.90 MAX 4 C SIDE VIEW 1.70 0.10 10X 0.50 12X 0.40 0.05 BOTTOM VIEW (12X 0.60) ( 12 X 0.25) ( 3.30 ) ( 2.50) 0.10 C (10x 0.50) C 0 . 203 REF SEATING PLANE (1.70) 0.08 C 0 . 00 MIN. 0 . 05 MAX. ( 2.80 ) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: FN8871 Rev.2.00 May 17, 2018 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Reference document JEDEC MO-229. Page 22 of 23 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. 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