HEXFET® Power MOSFET
PD - 9.1103B
lAdavanced Process Technology
lUltra Low On-Resistance
lP-Channel MOSFET
lSurface Mount
lAvailable in Tape & Reel
lDynamic dv/dt Rating
lFast Switching
Description
Fourth Generation HEXFETs from International
Rectifier utilize advanced processing techniques to
achieve the lowest possible on-resistance per silicon
area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET
Power MOSFETs are well known for, provides the
designer with an extremely efficient device for use in
a wide variety of applications.
The SO-8 has been modified through a customized
leadframe for enhanced thermal characteristics and
dual-die capability making it ideal in a variety of power
applications. With these improvements, multiple
devices can be used in an application with dramatically
reduced board space. The package is designed for
vapor phase, infra red, or wave soldering techniques.
Power dissipation of greater than 0.8W is possible in
a typical PCB mount application.
IRF7204
SO-8
VDSS = -20V
RDS(on) = 0.060Ω
ID = -5.3A
8/25/97
To p Vie w
8
1
2
3
45
6
7
D
D
DG
S
A
D
S
S
Parameter Min. Typ. Max. Units
RθJA Maximum Junction-to-Ambient ––– ––– 50 °C/W
Parameter Max. Units
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V -5.3
ID @ TA = 70°C Continuous Drain Current, VGS @ 10V -4.2
IDM Pulsed Drain Current -21
PD @TC = 25°C Power Dissipation 2.5
Linear Derating Factor 0.020 W/°C
VGS Gate-to-Source Voltage ± 12 V
dv/dt Peak Diode Recovery dv/dt -1.7 V/nS
TJ,
TSTG Junction and Storage Temperature Range -55 to + 150
Absolute Maximum Ratings
A
Thermal Resistance Ratings
W
°C
IRF7204
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage -20 ––– ––– V VGS = 0V, ID = -250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– -0.022 ––– V/°C Reference to 25°C, ID = -1mA
––– ––– 0.060 VGS = -10V, ID = -5.3A
––– ––– 0.10 VGS = -4.5V, ID = -2.0A
VGS(th) Gate Threshold Voltage -1.0 ––– -2.5 V VDS = VGS, ID = -250µA
gfs Forward Transconductance ––– 7.9 ––– S VDS = -15V, ID = -5.3A
––– ––– -25 VDS = -16V, VGS = 0V
––– ––– -250 VDS = -16V, VGS = 0V, TJ = 125 °C
Gate-to-Source Forward Leakage ––– ––– -100 VGS = -12V
Gate-to-Source Reverse Leakage ––– ––– 100 VGS = 12V
QgTotal Gate Charge ––– 25 ––– ID = -5.3A
Qgs Gate-to-Source Charge ––– 5.0 ––– nC VDS = -10V
Qgd Gate-to-Drain ("Miller") Charge ––– 8. 0 ––– VGS = -10V
td(on) Turn-On Delay Time ––– 14 30 VDD = -10V
trRise Time ––– 26 60 ID = -1.0A
td(off) Turn-Off Delay Time ––– 100 1 50 RG = 6.0Ω
tfFall Time ––– 68 100 RD = 10Ω
Between lead,6mm(0.25in.)
from package and center
of die contact
Ciss Input Capacitance ––– 860 ––– VGS = 0V
Coss Output Capacitance ––– 750 ––– pF VDS = -10V
Crss Reverse Transfer Capacitance ––– 230 ––– ƒ = 1.0MHz
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– -1.2 V TJ = 25°C, IS = -1.25A, VGS = 0V
trr Reverse Recovery Time ––– 85 100 n s TJ = 25°C, IF = -2.4A
Qrr Reverse RecoveryCharge ––– 77 120 nC di/dt = 100A/µs
ton Forward Turn-On Time
Source-Drain Ratings and Characteristics
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Intrinsic turn-on time is negligible (turn-on is dominated by L S+LD)
––– ––– -15
––– ––– -2.5 A
IGSS
IDSS Drain-to-Source Leakage Current
LSInternal Source Inductance ––– 4.0 –––
LDInternal Drain Inductance ––– 2.5 ––– nH
ns
nA
µA
ΩRDS(ON) Static Drain-to-Source On-Resistance
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
ISD ≤ -5.3A, di/dt ≤ 90A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Surface mounted on FR-4 board, t ≤ 10sec.
S
D
G
S
D
G
IRF7204
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics
-ID , Drain-to-Source Current ( A )
-ID , Drain-to-Source Current ( A )
RDS (on) , Drain-to-Source On Resistance
( Normalized)
-VDS , Drain-to-Source Voltage ( V ) -VDS , Drain-to-Source Voltage ( V )
-VGS , Gate-to-Source Voltage ( V ) TJ , Junction Temperature ( °C )
-ID , Drain-to-Source Current ( A )
IRF7204
Fig 7. Typical Source-Drain Diode
Forward Voltage Fig 8. Maximum Safe Operating Area
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
-ISD , Reverse Drain Current ( A )
-VGS , Gate-to-Source Voltage ( V )
C , Capacitance ( pF )
-VDS , Drain-to-Source Voltage ( V ) QG , Total Gate Charge ( nC )
-VSD , Source-to-Drain Voltage ( V )
1
10
100
0.1 1 10 100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T = 150 C
= 25 C
°°
J
A
-V , Drain-to-Source Voltage (V)
-I , Drain Current (A)I , Drain Current (A)
DS
D
1ms
10ms
12
IRF7204
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 100
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJA A
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJA
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
Fig 9. Maximum Drain Current Vs.
Ambient Temperature
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
25 50 75 100 125 150
0.0
1.0
2.0
3.0
4.0
5.0
6.0
T , Case Temperature ( C)
-I , Drain Current (A)
°
C
D
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
VDS
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
VDD
RGD.U.T.
+
-
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
IRF7204
Fig 12b. Gate Charge Test Circuit
Fig 12a. Basic Gate Charge Waveform
Q
G
Q
GS
Q
GD
V
G
Charge
-10V
D.U.T. V
DS
I
D
I
G
-3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
IRF7204
Peak Diode Recovery dv/dt Test Circuit
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T*Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
* Reverse Polarity of D.U.T for P-Channel
VGS
[ ]
[ ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
[ ] ***
Fig 13. For P-Channel HEXFETS
IRF7204
Package Outline
SO8 Outline
SO8
Part Marking Information
EXAM PLE : THIS IS AN IRF7 101
DATE CODE (YWW)
Y = LAST DIG IT OF THE YEAR
WW = WEEK
W A FER
L OT CODE
(LAST 4 DIG ITS)
XXXX
BOTTOM
PART NUM BER
TOP
INTERNATIONAL
RECTIF IER
L OGO
F7101
312
K x 45°
C
8X
L
8X
θ
H
0.25 (.010) M A M
A
0.10 (.004)
B 8X
0.25 (.010) M C A S B S
- C -
6X
e
- B -
D
E
- A -
8 7 6 5
1 2 3 4
5
6
5
RECOMMENDED FOOTPRINT
0.72 (.028 )
8X
1.78 (.070)
8X
6.46 ( .255 )
1.27 ( .050 )
3X
DIM INCHES MILLIMETERS
MIN MAX MIN MAX
A .0532 .0688 1.35 1.75
A1 .0040 .0098 0.10 0.25
B .014 .018 0.36 0.46
C .0075 .0098 0.19 0.25
D .189 .196 4.80 4.98
E .150 .157 3.81 3.99
e .050 BASIC 1.27 BASIC
e1 .025 BASIC 0.635 BASIC
H .2284 .2440 5.80 6.20
K .011 .019 0.28 0.48
L 0.16 .050 0.41 1.27
θ
0° 8° 0° 8°
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M-1982.
2. CONTROLLING DIMENSION : INCH.
3. DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES).
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS
MOLD PROTRUSIONS NOT TO EXCEED 0.25 (.006).
DIMENSIONS IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE..
5
6
A1
e1
IRF7204
SO8
Dimensions are shown in millimeters (inches)
Tape & Reel Information
330. 00
(12.992)
M AX .
14.40 ( .566 )
12.40 ( .488 )
NO TES :
1. CO NTROLLING DIME NS IO N : MIL LIME TER.
2. OUTLINE CON FORMS TO EIA-481 & EIA-541.
FE ED DIRE CTIO N
TERMINAL NUMBER 1
12.3 ( .48 4 )
11.7 ( .46 1 )
8.1 ( .3 18 )
7.9 ( .3 12 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIM ENSIO NS AR E SHOWN IN MILLIMETER S(INC HES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
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http://www.irf.com/ Data and specifications subject to change without notice. 8/97
