68HC16 Module
68HC16 Module
2 _______________________________________________________________________________________
The 68HC16 uses a phase-locked loop (PLL) to set its
bus speed. Crystal Y1 is a 32.768kHz frequency refer-
ence. The internal oscillator runs 256 times faster than the
external crystal. When the 68HC16 is reset, it waits for the
PLL to lock before it executes any software. After the PLL
locks onto the reference frequency, the software doubles
the clock speed by writing to the clock synthesizer con-
trol register, selecting a bus speed of 16.78MHz.
U5, the user RAM area, is a 32kbyte CMOS static RAM.
The 74HCT245 octal buffer lets the 68HC16 module
access an 8-bit port on the 40-pin interface connector.
This memory-mapped port consists of separate read
and write strobes, four chip selects, four address LSBs,
and eight data bits.
Serial Communications
J3 is an RS-232 serial port, designed to be compatible
with the IBM PC 9-pin serial port. Use a straight-
through DB9 male-to-female cable to connect J3 to this
port. If the only available serial port has a 25-pin con-
nector, you may use a standard 25-pin to 9-pin
adapter. Table 1 shows the pinout of J3.
The MAX233 is an RS-232 interface voltage level shifter
with two transmitters and two receivers. It includes a
built-in charge pump with internal capacitors that gener-
ates the output voltages necessary to drive RS-232 lines.
40-Pin Data Connector J1
The 20 x 2 pin header connects the 68HC16 module to
a Maxim EV kit. Table 2 lists the function of each pin.
Note that 68HC16 object code is not compatible with
68HC11 object code. Use the 68HC16 module only
with those modules that are designed to support it, and
only download code that is targeted for the 68HC16
module. Downloading incorrect object code into the
68HC16 module will have unpredictable results.
Address Ranges
The 68HC16 µC generates various enable signals for dif-
ferent address ranges. The ROM and RAM enable sig-
nals are fed directly to the respective chips. Several
additional signals (J1.11–J1.14) are available on the data
connector to be used by Maxim EV kits. Table 3 outlines
the address ranges for each of the elements found on
the 68HC16 module, and Table 4 is a truth table that
describes the logic for each of the 68HC16’s chip-select
outputs. Because the addresses are not completely
decoded, the boot ROM and user RAM have shadows.
UnusedNone9
Handshake; hard-wired to RTSCTS8
Handshake; hard-wired to CTSRTS7
Handshake; hard-wired to DCD and DTRDSR6
Signal ground connectionGND5
Handshake; hard-wired to DCD and DSRDTR4
RS-232-compatible data input to
68HC16 module
TXD3
Handshake; hard-wired to DTR and DSRDCD1
FUNCTIONNAMEPIN
RS-232-compatible data output from
68HC16 module
RXD2
Table 1. Serial Communications Port J3
Table 2. 40-Pin Data-Connector Signals
General I/O port bit 7IC434
General I/O port bit 0 (LSB)IC127
Buffered data bus bits 1–7EXTD1–720–26
Buffered data bus 0 (LSB)EXTD019
GroundGND1–4
FUNCTIONNAMEPIN
Unregulated input voltageVPREREG5, 6
Read strobe
RD
9
+5V from on-board regulatorVCC7, 8
Chip select for 7E000–7E7FF
7E000
11
Chip select for 7F000–7F7FF
7F000
13
Write strobe
WR
10
Chip select for 7E800–7EFFF
7E800
12
Address bit 0 (LSB)A0015
Chip select for 7F800–7FFFF
7F800
14
Pulse-width-modulator outputPWMA40
QSPI chip-select outputPCS0/SS38
QSPI serial clockSCK37
QSPI master-out, slave-inMOSI36
QSPI master-in, slave-outMISO35
Address bit 1A0116
Address bit 2A0217
Address bit 3A0318
General I/O port bit 1IC228
General I/O port bit 2IC329
General I/O port bit 3OC130
General I/O port bit 4OC231
General I/O port bit 5OC332
General I/O port bit 6OC433
System clock outputCLKOUT39