ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com 14-Bit, 400-MSPS Analog-to-Digital Converter Check for Samples: ADS5474 FEATURES 1 * * * * * * * * * * * 23 * * 400-MSPS Sample Rate 14-Bit Resolution, 11.2-Bits ENOB 1.4-GHz Input Bandwidth SFDR = 80 dBc at 230 MHz and 400 MSPS SNR = 69.8 dBFS at 230 MHz and 400 MSPS 2.2-VPP Differential Input Voltage LVDS-Compatible Outputs Total Power Dissipation: 2.5 W Power Down Mode: 50 mW Offset Binary Output Format Output Data Transitions on the Rising and Falling Edges of a Half-Rate Output Clock On-Chip Analog Buffer, Track-and-Hold, and Reference Circuit * * TQFP-80 PowerPADTM Package (14 mm x 14 mm footprint) Industrial Temperature Range: -40C to +85C Pin-Similar/Compatible with 12-, 13-, and 14-Bit Family: ADS5463 and ADS5440/ADS5444 APPLICATIONS * * * * * * Test and Measurement Instrumentation Software-Defined Radio Data Acquisition Power Amplifier Linearization Communication Instrumentation Radar DESCRIPTION The ADS5474 is a 14-bit, 400-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3.3-V supply while providing LVDS-compatible digital outputs. This ADC is one of a family of 12-, 13-, and 14-bit ADCs that operate from 210 MSPS to 500 MSPS. The ADS5474 input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An internal reference generator is also provided to simplify the system design. Designed with a 1.4-GHz input bandwidth for the conversion of wide-bandwidth signals that exceed 400 MHz of input frequency at 400 MSPS, the ADS5474 has outstanding low-noise performance and spurious-free dynamic range over a large input frequency range. The ADS5474 is available in an TQFP-80 PowerPAD package. The device is built on Texas Instruments complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (-40C to +85C). VIN VIN A1 TH1 + TH2 S + TH3 A2 ADC1 A3 ADC3 - - VREF S DAC1 ADC2 DAC2 Reference 5 5 6 Digital Error Correction CLK CLK Timing OVR OVR DRY DRY D[13:0] 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007-2012, Texas Instruments Incorporated ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS5474 HTQFP-80 (2) PowerPAD PFP -40C to +85C ADS5474I (1) (2) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5474IPFP Tray, 96 ADS5474IPFPR Tape and Reel, 1000 For the most current product and ordering information see the Package Option Addendum located at the end of this document, or see the TI web site at www.ti.com. Thermal pad size: 6.15 mm x 6.15 mm (minimum), 7.5 mm x 7.5 mm (maximum). ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Supply voltage ADS5474 UNIT AVDD5 to GND 6 V AVDD3 to GND 5 V DVDD3 to GND 5 V -0.3 to (AVDD5 + 0.3) V -0.3 to (AVDD5 + 0.3) V Analog input to GND Valid when supplies are on and within normal ranges. See additional information in the Power Supplies portion of the applications information in the back of the datasheet regarding Clock and Analog Inputs when the Clock input to GND supplies are off. 2.5 V -0.3 to (DVDD3 + 0.3) V -40 to +85 C +150 C -65 to +150 C 2 kV CLK to CLK Digital data output to GND Operating temperature range Maximum junction temperature Storage temperature range ESD, human-body model (HBM) (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime are available upon request. THERMAL CHARACTERISTICS (1) PARAMETER RJA RJP (1) (2) (3) 2 (2) (3) TEST CONDITIONS TYP Soldered thermal pad, no airflow 23.7 Soldered thermal pad, 150-LFM airflow 17.8 Soldered thermal pad, 250-LFM airflow 16.4 Bottom of package (thermal pad) 2.99 UNIT C/W C/W Using 36 thermal vias (6 x 6 array). See PowerPAD Package in the Application Information section. RJA is the thermal resistance from the junction to ambient. RJP is the thermal resistance from the junction to the thermal pad. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS ADS5474 MIN NOM MAX UNIT SUPPLIES AVDD5 Analog supply voltage 4.75 5 5.25 V AVDD3 Analog supply voltage 3.1 3.3 3.6 V DVDD3 Output driver supply voltage 3 3.3 3.6 V ANALOG INPUT VCM Differential input range 2.2 VPP Input common mode 3.1 V 10 pF DIGITAL OUTPUT (DRY, DATA, OVR) Maximum differential output load CLOCK INPUT (CLK) CLK input sample rate (sine wave) 20 400 Clock amplitude, differential sine wave (see Figure 42) 0.5 5 Clock duty cycle (see Figure 46) TA 40 50 -40 Operating free-air temperature MSPS VPP 60 % +85 C ELECTRICAL CHARACTERISTICS Typical values at TA = +25C: minimum and maximum values over full temperature range TMIN = -40C to TMAX = +85C, sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1 dBFS differential input, and 3-VPP differential clock, unless otherwise noted. PARAMETER TEST CONDITIONS ADS5474 MIN Resolution TYP MAX UNIT 14 Bits 2.2 VPP ANALOG INPUTS Differential input range Analog input common-mode voltage Self-biased; see VCM specification below 3.1 V Input resistance (dc) Each input to VCM 500 Input capacitance Each input to GND 2.3 pF 1.44 GHz 100 dB 2.4 V Analog input bandwidth (-3dB) CMRR Common-mode rejection ratio Common-mode signal < 50 MHz (see Figure 27) INTERNAL REFERENCE VOLTAGE VREF VCM Reference voltage Analog input common-mode voltage reference output With internal VREF. Provided as an output via the VCM pin for dc-coupled applications. If an external VREF is used, the VCM pin tracks as illustrated in Figure 39 2.9 3.1 3.3 -0.8 VCM temperature coefficient V mV/C DYNAMIC ACCURACY No missing codes Assured DNL Differential linearity error fIN = 70 MHz INL Integral linearity error fIN = 70 MHz -0.99 0.7 -3 1 -11 Offset error Offset temperature coefficient 1.5 LSB 3 LSB 11 0.02 -5 Gain error 5 -0.02 Gain temperature coefficient mV mV/C %FS %FS/C Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 3 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values at TA = +25C: minimum and maximum values over full temperature range TMIN = -40C to TMAX = +85C, sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1 dBFS differential input, and 3-VPP differential clock, unless otherwise noted. PARAMETER ADS5474 TEST CONDITIONS MIN UNIT TYP MAX 338 372 mA 185 201 mA 75 83 mA 2.5 2.797 POWER SUPPLY IAVDD5 5-V analog supply current IAVDD3 3.3-V analog supply current IDVDD3 3.3-V digital supply current (includes LVDS) VIN = full-scale, fIN = 70 MHz, fS = 400 MSPS Total power dissipation Power-up time From turn-on of AVDD5 Wake-up time From PWD pin switched from HIGH (PWD active) to LOW (ADC awake) (see Figure 28) Power-down power dissipation PWD pin = logic HIGH PSRR Power-supply rejection ratio, AVDD5 supply PSRR Power-supply rejection ratio, AVDD3 supply PSRR Power-supply rejection ratio, DVDD3 supply s 5 s 50 Without 0.1-F board supply capacitors, with < 1-MHz supply noise (see Figure 49) W 50 350 mW 75 dB 90 dB 110 dB DYNAMIC AC CHARACTERISTICS fIN = 30 MHz fIN = 70 MHz 70.3 68.3 fIN = 130 MHz fIN = 230 MHz SNR Signal-to-noise ratio 70.1 68 69.1 fIN = 451 MHz 68.4 fIN = 651 MHz 67.5 fIN = 751 MHz 66.6 fIN = 999 MHz 64.7 fIN = 70 MHz fIN = 230 MHz HD2 4 Second-harmonic 86 80 71 80 fIN = 351 MHz 76 fIN = 451 MHz 71 fIN = 651 MHz 60 fIN = 751 MHz 55 fIN = 999 MHz 46 fIN = 30 MHz 89 fIN = 70 MHz 87 fIN = 130 MHz 90 fIN = 230 MHz 84 fIN = 351 MHz 76 fIN = 451 MHz 71 fIN = 651 MHz 74 fIN = 751 MHz 70 fIN = 999 MHz 55 Submit Documentation Feedback dBFS 88 74 fIN = 130 MHz Spurious-free dynamic range 69.8 fIN = 351 MHz fIN = 30 MHz SFDR 70.2 dBc dBc Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values at TA = +25C: minimum and maximum values over full temperature range TMIN = -40C to TMAX = +85C, sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1 dBFS differential input, and 3-VPP differential clock, unless otherwise noted. PARAMETER TEST CONDITIONS ADS5474 MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS (continued) HD3 Third-harmonic Worst harmonic/spur (other than HD2 and HD3) THD Total harmonic distortion fIN = 30 MHz 93 fIN = 70 MHz 86 fIN = 130 MHz 80 fIN = 230 MHz 80 fIN = 351 MHz 85 fIN = 451 MHz 71 fIN = 651 MHz 60 fIN = 751 MHz 55 fIN = 999 MHz 46 fIN = 30 MHz 95 fIN = 70 MHz 93 fIN = 130 MHz 85 fIN = 230 MHz 85 fIN = 351 MHz 87 fIN = 451 MHz 87 fIN = 651 MHz 90 fIN = 751 MHz 87 fIN = 999 MHz 80 fIN = 30 MHz 86 fIN = 70 MHz 83 fIN = 130 MHz 78 fIN = 230 MHz 77 fIN = 351 MHz 75 fIN = 451 MHz 68 fIN = 651 MHz 60 fIN = 751 MHz 55 fIN = 999 MHz 45 dBc dBc dBc Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 5 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values at TA = +25C: minimum and maximum values over full temperature range TMIN = -40C to TMAX = +85C, sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1 dBFS differential input, and 3-VPP differential clock, unless otherwise noted. PARAMETER TEST CONDITIONS ADS5474 MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS (continued) fIN = 30 MHz fIN = 70 MHz 69.2 67 fIN = 130 MHz fIN = 230 MHz SINAD Signal-to-noise and distortion Two-tone SFDR ENOB Effective number of bits RMS idle-channel noise 68.9 68.5 65.5 68.2 fIN = 351 MHz 67.3 fIN = 451 MHz 64.8 fIN = 651 MHz 58.5 fIN = 751 MHz 54 fIN = 999 MHz 45.4 fIN1 = 69 MHz, fIN2 = 70 MHz, each tone at -7 dBFS 93 fIN1 = 69 MHz, fIN2 = 70 MHz, each tone at -16 dBFS 95 fIN1 = 297.5 MHz, fIN2 = 302.5 MHz, each tone at -7 dBFS 85 fIN1 = 297.5 MHz, fIN2 = 302.5 MHz, each tone at -16 dBFS 83 dBc dBFS fIN = 70 MHz 10.8 11.2 fIN = 230 MHz 10.6 10.9 Inputs tied to common-mode Bits 1.8 LSB DIGITAL OUTPUTS VOD Differential output voltage () VOC Common-mode output voltage 247 350 1.125 454 1.375 mV V DIGITAL INPUTS VIH High level input voltage VIL Low level input voltage IIH High level input current IIL Low level input current 2.0 PWD (pin 33) 2 Submit Documentation Feedback V 1 A A -1 Input capacitance 6 V 0.8 pF Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com TIMING INFORMATION Sample N-1 N+4 N+2 ta N N+1 N+3 tCLKH N+5 tCLKL CLK CLK Latency = 3.5 Clock Cycles tDRY DRY DRY (1) tDATA D[13:0], OVR N N-1 N+1 D[13:0], OVR (1) Polarity of DRY is undetermined. For further information, see the Digital Outputs section. Figure 1. Timing Diagram TIMING CHARACTERISTICS (1) Typical values at TA = +25C: minimum and maximum values over full temperature range TMIN = -40C to TMAX = +85C, sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock, unless otherwise noted. PARAMETER ta TEST CONDITIONS MIN Aperture delay Aperture jitter, rms Internal jitter of the ADC Latency TYP MAX ps 103 fs 3.5 tCLK Clock period tCLKH Clock pulse duration, high tCLKL Clock pulse duration, low 2.5 (2) UNIT 200 cycles 50 ns 1 ns 1 ns Zero crossing, 10-pF parasitic loading to GND on each output pin 1000 1400 1800 ps 800 1400 2000 ps -500 0 500 ps tDRY CLK to DRY delay tDATA CLK to DATA/OVR delay (2) Zero crossing, 10-pF parasitic loading to GND on each output pin tSKEW DATA to DRY skew tDATA - tDRY, 10-pF parasitic loading to GND on each output pin tRISE DRY/DATA/OVR rise time 10-pF parasitic loading to GND on each output pin 500 ps tFALL DRY/DATA/OVR fall time 10-pF parasitic loading to GND on each output pin 500 ps (1) (2) Timing parameters are assured by design or characterization, but not production tested. DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation delay. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 7 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com PIN CONFIGURATION D6 D7 D6 D7 DGND D8 DVDD3 D9 D8 D10 D9 D11 D10 D12 D11 D13 D12 DRY D13 DRY PFP PACKAGE (TOP VIEW) DVDD3 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 DGND 2 59 D5 AVDD5 58 57 D4 NC 3 4 NC 5 56 D3 VREF 6 55 D3 AGND 54 D2 AVDD5 7 8 53 D2 AGND 9 52 DGND CLK 10 CLK 11 ADS5474 D5 D4 51 DVDD3 50 D1 AGND 12 49 D1 AVDD5 13 48 D0 AVDD5 14 47 D0 AGND 15 46 NC AIN 16 45 NC AIN 17 44 NC AGND 18 43 NC AVDD5 19 42 OVR AGND 20 41 OVR AGND AVDD3 AGND AGND AVDD3 AGND AVDD3 PWD AGND AGND AVDD5 VCM AGND AGND AVDD5 AGND AVDD5 AVDD5 AGND AVDD5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P0027-03 8 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com Table 2. TERMINAL FUNCTIONS TERMINAL NAME DESCRIPTION NO. AIN 16 Differential input signal (positive) AIN 17 Differential input signal (negative) AVDD5 3, 8, 13, 14, 19, 21, 23, 25, 27, 31 AVDD3 35, 37, 39 Analog power supply (3.3 V) (Suggestion for 250 MSPS: leave option to connect to 5 V for ADS5440/ADS5444 13-bit compatibility) DVDD3 1, 51, 66 Digital and output driver power supply (3.3 V) AGND 7, 9, 12, 15, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40 (Power Pad) DGND (not numbered) 2, 52, 65 Analog power supply (5 V) Analog Ground Power Pad for thermal relief, also Analog Ground Digital Ground CLK 10 Differential input clock (positive). Conversion is initiated on rising edge, digital outputs on falling edge. CLK 11 Differential input clock (negative) D0, D0 48, 47 LVDS digital output pair, least significant bit (LSB) D1-D12, D1-D12 49, 50, 53-64, 67-76 D13, D13 78, 77 LVDS digital output pair, most significant bit (MSB) DRY, DRY 80, 79 Data ready LVDS output pair NC OVR, OVR 4, 5, 43-46 42, 41 LVDS digital output pairs No connect (pins 4 and 5 should be left floating; pins 43 to 46 are possible future bit additions for this pinout and therefore can be connected to a digital bus or left floating) Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range. VCM 29 Common-mode voltage output (3.1 V nominal). Commonly used in DC-coupled applications to set the input signal to the correct common-mode voltage. A 0.1F capacitor from VCM to AGND is recommended, but not required. (This pin is not used on the ADS5440, ADS5444, and ADS5463) PWD 33 Power-down (active high). Device is in sleep mode when PWD pin is logic HIGH. ADC converter is awake when PWD is logic LOW (grounded). (This pin is not used on the ADS5440, ADS5444, and ADS5463) VREF 6 Reference voltage input/output (2.4 V nominal). A 0.1F capacitor from VREF to AGND is recommended, but not required. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 9 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS At TA = +25C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude = -1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted. SPECTRAL PERFORMANCE FFT FOR 30 MHz INPUT SIGNAL SPECTRAL PERFORMANCE FFT FOR 70 MHz INPUT SIGNAL 0 0 SFDR = 88.4 dBc SNR = 70.3 dBFS SINAD = 70.2 dBFS THD = 86 dBc -20 -20 -40 Amplitude - dB -40 Amplitude - dB SFDR = 86.6 dBc SNR = 70.1 dBFS SINAD = 69.9 dBFS THD = 82.9 dBc -60 -60 -80 -80 -100 -100 -120 -120 0 20 40 60 80 100 120 140 160 180 0 200 20 40 60 Frequency - MHz 0 140 160 SPECTRAL PERFORMANCE FFT FOR 130 MHz INPUT SIGNAL SPECTRAL PERFORMANCE FFT FOR 230 MHz INPUT SIGNAL 180 200 180 200 0 SFDR = 79.7 dBc SNR = 69.8 dBFS SINAD = 69.2 dBFS THD = 76.9 dBc -20 -40 Amplitude - dB Amplitude - dB 120 Figure 3. -40 -60 -60 -80 -80 -100 -100 -120 -120 0 20 40 60 80 100 120 140 160 180 200 0 Frequency - MHz 20 40 60 80 100 120 140 160 Frequency - MHz Figure 4. 10 100 Figure 2. SFDR = 78.5 dBc SNR = 70.1 dBFS SINAD = 69.5 dBFS THD = 77.4 dBc -20 80 Frequency - MHz Figure 5. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude = -1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted. SPECTRAL PERFORMANCE FFT FOR 351 MHz INPUT SIGNAL SPECTRAL PERFORMANCE FFT FOR 451 MHz INPUT SIGNAL 0 0 SFDR = 75.5 dBc SNR = 69.2 dBFS SINAD = 68.3 dBFS THD = 74.7 dBc -20 -20 -40 Amplitude - dB -40 Amplitude - dB SFDR = 71.4 dBc SNR = 68.4 dBFS SINAD = 65.8 dBFS THD = 68.3 dBc -60 -60 -80 -80 -100 -100 -120 -120 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 Frequency - MHz 100 120 140 160 Figure 6. Figure 7. SPECTRAL PERFORMANCE FFT FOR 751 MHz INPUT SIGNAL SPECTRAL PERFORMANCE FFT FOR 999 MHz INPUT SIGNAL 0 180 200 0 SFDR = 54.5 dBc SNR = 66.6 dBFS SINAD = 55.1 dBFS THD = 54.4 dBc -20 SFDR = 46 dBc SNR = 64.7 dBFS SINAD = 46.4 dBFS THD = 45.5 dBc -20 -40 Amplitude - dB -40 Amplitude - dB 80 Frequency - MHz -60 -60 -80 -80 -100 -100 -120 -120 0 20 40 60 80 100 120 140 160 180 200 0 Frequency - MHz 20 40 60 80 100 120 140 160 180 200 Frequency - MHz Figure 8. Figure 9. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 11 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude = -1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted. TWO-TONE INTERMODULATION DISTORTION (FFT for 69 MHz and 70 MHz at -7 dBFS) TWO-TONE INTERMODULATION DISTORTION (FFT for 297.5 MHz and 302.5 MHz at -7 dBFS) 0 0 fIN1 = 69 MHz, -7 dBFS fIN2 = 70 MHz, -7 dBFS IMD3 = 97.3 dBFS SFDR = 93.4 dBFS -20 -20 -40 Amplitude - dB -40 Amplitude - dB fIN1 = 297.5 MHz, -7 dBFS fIN2 = 302.5 MHz, -7 dBFS IMD3 = 85.1 dBFS SFDR = 85 dBFS -60 -60 -80 -80 -100 -100 -120 -120 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 Frequency - MHz 120 140 160 180 Figure 11. TWO-TONE INTERMODULATION DISTORTION (FFT for 69 MHz and 70 MHz at -16 dBFS) TWO-TONE INTERMODULATION DISTORTION (FFT for 297.5 MHz and 302.5 MHz at -16 dBFS) 0 fIN1 = 69 MHz, -16 dBFS fIN2 = 70 MHz, -16 dBFS IMD3 = 98 dBFS SFDR = 95.7 dFBS -20 200 fIN1 = 297.5 MHz, -16 dBFS fIN2 = 302.5 MHz, -16 dBFS IMD3 = 94.4 dBFS SFDR = 83.1 dFBS -20 -40 Amplitude - dB -40 Amplitude - dB 100 Figure 10. 0 -60 -60 -80 -80 -100 -100 -120 -120 0 12 80 Frequency - MHz 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 Frequency - MHz Frequency - MHz Figure 12. Figure 13. Submit Documentation Feedback 140 160 180 200 Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude = -1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted. NORMALIZED GAIN RESPONSE vs INPUT FREQUENCY DIFFERENTIAL NONLINEARITY 3 0.5 fS = 400 MSPS fIN = 70 MHz 0.4 0 0.3 -3 0.1 DNL - LSB Normalized Gain - dB 0.2 -6 -9 0 -0.1 -12 -0.2 -15 -0.3 -18 -0.4 fS = 400 MSPS AIN = 0.38 VPP -21 10 M -0.5 100 M 1G 5G 0 2048 Frequency - Hz 4096 6144 8192 10240 12288 14336 16384 Code Figure 14. Figure 15. INTEGRAL NONLINEARITY NOISE HISTOGRAM WITH INPUTS SHORTED 25 2.0 fS = 400 MSPS fIN = 70 MHz fS = 400 MSPS fIN = VCM 1.5 20 1.0 Percentage - % INL - LSB 0.5 0 -0.5 15 10 -1.0 5 -1.5 0 2048 4096 6144 8192 10240 12288 14336 16384 Code 8205 8206 8207 8208 8209 8210 8211 8212 8213 8214 8215 8216 8217 8218 8219 8220 8221 8222 8223 8224 8225 8226 8227 0 -2.0 Output Code Figure 16. Figure 17. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 13 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude = -1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted. AC PERFORMANCE vs INPUT AMPLITUDE (70 MHz Input Signal) AC PERFORMANCE vs INPUT AMPLITUDE (230 MHz Input Signal) 120 120 SFDR (dBFS) SFDR (dBFS) 100 100 SNR (dBFS) SNR (dBFS) 80 AC Performance - dB AC Performance - dB 80 60 40 SFDR (dBc) 20 0 60 40 SFDR (dBc) 20 0 SNR (dBc) SNR (dBc) -20 -40 -100 -90 -20 fS = 400 MSPS fIN = 70 MHz -80 -70 -60 -50 -40 -30 -20 -10 -40 -100 -90 0 fS = 400 MSPS fIN = 230 MHz -80 -70 Input Amplitude - dBFS -40 -30 -20 Figure 19. TWO-TONE PERFORMANCE vs INPUT AMPLITUDE (f1 = 297.5 MHz and f2 = 302.5 MHz) SFDR vs AVDD5 OVER TEMPERATURE 90 2f2 - f1 (dBc) 88 SFDR - Spurious-Free Dynamic Range - dBc 90 80 2f1 - f2 (dBc) 70 Performance - dB -50 Figure 18. 100 60 50 40 30 20 Worst Spur (dBc) 0 -100 -90 -10 0 fS = 400 MSPS fIN = 230 MHz 86 84 +40C +65C +25C 82 80 78 0C 76 +85C -40C +100C 74 72 10 70 -80 -70 -60 -50 -40 -30 -20 -10 0 4.7 4.8 4.9 5.0 5.1 5.2 5.3 AVDD5 - Supply Voltage - V AIN - dBFS Figure 20. 14 -60 Input Amplitude - dBFS Figure 21. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude = -1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted. SNR vs AVDD5 OVER TEMPERATURE SFDR vs AVDD3 OVER TEMPERATURE 71.0 90 fS = 400 MSPS fIN = 230 MHz SFDR - Spurious-Free Dynamic Range - dBc 70.5 SNR - Signal-to-Noise Ratio - dBFS fS = 400 MSPS fIN = 230 MHz 88 +25C +65C +40C 70.0 69.5 -40C 0C +85C +100C 69.0 68.5 86 84 +40C +25C +65C 82 80 78 +85C 0C 76 +100C -40C 74 72 68.0 70 4.7 4.8 4.9 5.0 5.1 5.2 3.0 5.3 3.1 AVDD5 - Supply Voltage - V 71.0 3.4 3.6 3.5 Figure 23. SNR vs AVDD3 OVER TEMPERATURE SFDR vs DVDD3 OVER TEMPERATURE 90 fS = 400 MSPS fIN = 230 MHz SFDR - Spurious-Free Dynamic Range - dBc 88 70.5 SNR - Signal-to-Noise Ratio - dBFS 3.3 Figure 22. fS = 400 MSPS fIN = 230 MHz +65C +40C +25C 70.0 69.5 0C 3.2 AVDD3 - Supply Voltage - V +85C -40C +100C 69.0 68.5 86 84 +25C 82 +65C +40C 80 78 76 +85C -40C 0C +100C 74 72 68.0 70 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 AVDD3 - Supply Voltage - V 3.1 3.2 3.3 3.4 3.5 3.6 DVDD3 - Supply Voltage - V Figure 24. Figure 25. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 15 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude = -1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted. SNR vs DVDD3 OVER TEMPERATURE CMRR vs COMMON-MODE INPUT FREQUENCY 0 71.0 fS = 400 MSPS fIN = 230 MHz CMRR - Common-Mode Rejection Ratio - dB -10 SNR - Signal-to-Noise Ratio - dBFS 70.5 +40C +25C 0C +65C 70.0 69.5 +85C -40C +100C 69.0 68.5 -20 -30 -40 -50 -60 -70 -80 -90 400 MSPS -100 -110 300 MSPS -120 68.0 3.0 3.1 3.2 3.3 3.4 -130 100 k 3.6 3.5 1M 10 M 100 M 1G 10 G Frequency - Hz DVDD3 - Supply Voltage - V Figure 26. Figure 27. ADC WAKEUP TIME 75 Wake from PDWN 70 65 60 55 SNR - dBFS 50 45 Wake from 5 V Supply 40 35 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 Time - ms Figure 28. 16 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude = -1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted. SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY 400 68 70 69 fS - Sampling Frequency - MHz 350 300 70 250 68 69 200 67 70 150 68 100 69 70 69 66 67 68 40 10 100 200 300 400 500 600 fIN - Input Frequency - MHz 54 56 58 60 62 64 66 68 70 SNR - dBFS Figure 29. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 17 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude = -1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted. SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY 400 80 85 350 77 65 73 80 70 fS - Sampling Frequency - MHz 77 300 80 85 250 65 73 77 85 200 70 77 80 85 150 73 100 80 85 85 65 70 77 60 40 10 100 200 300 400 500 600 fIN - Input Frequency - MHz 50 55 60 65 70 75 80 85 90 SFDR - dBc Figure 30. APPLICATIONS INFORMATION Theory of Operation The ADS5474 is a 14-bit, 400-MSPS, monolithic pipeline ADC. Its bipolar analog core operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is captured by the input track-and-hold (T&H), and the input sample is converted sequentially by a series of lower resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of 3.5 clock cycles, after which the output data are available as a 14-bit parallel word, coded in offset binary format. Input Configuration The analog input for the ADS5474 consists of an analog pseudo-differential buffer followed by a bipolar transistor T&H. The analog buffer isolates the source driving the input of the ADC from any internal switching and presents a high impedance that is easy to drive at high input frequencies, compared to an ADC without a buffered input. The input common-mode is set internally through a 500- resistor connected from 3.1 V to each of the inputs (common-mode is ~2.4V on 12- and 13-bit members of this family). This configuration results in a differential input impedance of 1 k. 18 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com ADS5463/5474/54RF63 AVDD5 ~ 2.5 nH Bond Wire Buffer AIN ~ 0.5 pF Package ~ 200 fF Bond Pad 500 W GND 1.6 pF VCM AVDD5 1.6 pF 500 W ~ 2.5 nH Bond Wire GND AIN ~ 0.5 pF Package ~ 200 fF Bond Pad Buffer GND S0293-01 Figure 31. Analog Input Equivalent Circuit For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings symmetrically between (3.1 V + 0.55 V) and (3.1 V - 0.55 V). This range means that each input has a maximum signal swing of 1.1 VPP for a total differential input signal swing of 2.2 VPP. Operation below 2.2 VPP is allowable, with the characteristics of performance versus input amplitude demonstrated in Figure 18 and Figure 19. For instance, for performance at 1.1 VPP rather than 2.2 VPP, refer to the SNR and SFDR at -6 dBFS (0 dBFS = 2.2 VPP). The maximum swing is determined by the internal reference voltage generator, eliminating the need for any external circuitry for this purpose. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 19 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com The ADS5474 performs optimally when the analog inputs are driven differentially. The circuit in Figure 32 shows one possible configuration using an RF transformer with termination either on the primary or on the secondary of the transformer. In addition, the evaluation module is configured with two back-to-back transformers, also demonstrating good performance. If voltage gain is required, a step-up transformer can be used. R0 50 W Z0 50 W AIN R 200 W AC Signal Source ADS5474 AIN Mini-Circuits JTX-4-10T Figure 32. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer In addition to the transformer configurations, Texas Instruments offers a wide selection of single-ended operational amplifiers that can be selected depending on the application. An RF gain-block amplifier, such as Texas Instruments' THS9001, can also be used for high-input-frequency applications. For large voltage gains at intermediate-frequencies in the 50 MHz to 400 MHz range, the configuration shown in Figure 33 can be used. The component values can be tuned for different intermediate frequencies. The example shown in Figure 33 is located on the evaluation module and is tuned for an IF of 170 MHz. More information regarding this configuration can be found in the ADS5474 EVM User Guide (SLAU194) and the THS9001 50-MHz to 350-MHz Cascadeable Amplifier data sheet (SLOS426), both available for download at www.ti.com. 1000 pF 1000 pF THS9001 VIN AIN 50 W 18 mH 39 pF ADS5474 50 W 0.1 mF THS9001 VIN 1000 pF AIN 1000 pF Figure 33. Using the THS9001 IF Amplifier With the ADS5474 20 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier such as the THS4509 (shown in Figure 34) provides good harmonic performance and low noise over a wide range of frequencies. VIN 348 W 100 W From 50 W Source 78.9 W +5V 49.9 W 0.22 mF 100 W AIN THS4509 49.9 W ADS5474 18 pF AIN VCM CM 49.9 W 0.22 mF 78.9 W 49.9 W 0.22 mF 0.1 mF 0.1 mF 348 W Figure 34. Using the THS4509 or THS4520 With the ADS5474 In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5474 by utilizing the VCM output pin of the ADC. The 50- resistors and 18-pF capacitor between the THS4509 outputs and ADS5474 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (-3 dB). Input termination is accomplished via the 78.9- resistor and 0.22-F capacitor to ground, in conjunction with the input impedance of the amplifier circuit. A 0.22-F capacitor and 49.9- resistor are inserted to ground across the 78.9- resistor and 0.22-F capacitor on the alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348- feedback resistor. See the THS4509 data sheet for further component values to set proper 50- termination for other common gains. Because the ADS5474 recommended input common-mode voltage is 3.1 V, the THS4509 operates from a single power-supply input with VS+ = 5 V and VS- = 0 V (ground). This configuration has the potential to slightly exceed the recommended output voltage from the THS4509 of 3.6V due to the ADC input common-mode of 3.1V and the +0.55V full-scale signal. This will not harm the THS4509 but may result in a degradation in the harmonic performance of the THS4509. An amplifier with a wider recommended output voltage range is the THS4520, which is optimized for low noise and low distortion in the range of frequencies up to ~20MHz. Applications that are not sensitive to harmonic distortion could consider either device at higher frequencies. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 21 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com External Voltage Reference For systems that require the analog signal gain to be adjusted or calibrated, this can be performed by using an external reference. The dependency on the signal amplitude to the value of the external reference voltage is characterized typically by Figure 35 (VREF = 2.4 V is normalized to 0 dB as this is the internal reference voltage). As can be seen in the linear fit, this equates to approximately -0.3 dB of signal adjustment per 100 mV of reference adjustment. The range of allowable variation depends on the analog input amplitude that is applied to the inputs and the desired spectral performance, as can be seen in the performance versus external reference graphs in Figure 36 and Figure 37. As the applied analog signal amplitude is reduced, more variation in the reference voltage is allowed in the positive direction (which equates to a reduction in signal amplitude), whereas an adjustment in reference voltage below the nominal 2.4 V (which equates to an increase in signal amplitude) is not recommended below approximately 2.35 V. The power consumption versus reference voltage and operating temperature should also be considered, especially at high ambient temperatures, because the lifetime of the device is affected by internal junction temperature, see Figure 50. For dc-coupled applications that use the VCM pin of the ADS5474 as the common mode of the signal in the analog signal gain path prior to the ADC inputs, the information in Figure 39 is useful to consider versus the allowable common-mode range of the device that is receiving the VCM voltage, such as an operational amplifier. Because it is pin-compatible, it is important to note that the ADS5463 does not have a VCM pin and primarily uses the VREF pin to provide the common-mode voltage in dc-coupled applications. The ADS5463 (VCM = 2.4 V) and ADS5474 (VCM = 3.1V) do not have the same common-mode voltage. To create a board layout that may accommodate both devices in dc-coupled applications, route VCM and VREF both to a common point that can be selected via a switch, jumper, or a 0 resistor. fS = 400 MSPS fIN = 70 MHz AIN = < -1 dBFS Normalized Gain Adjustment - dB 0.5 0 Best Fit: y = -3.14x + 7.5063 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 2.2 90 SFDR - Spurious-Free Dynamic Range - dBc 1.0 AIN = -5 dBFS 80 AIN = -4 dBFS 70 AIN = -3 dBFS 60 AIN = -2 dBFS AIN = -1 dBFS 50 fS = 400 MSPS fIN = 70 MHz 40 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15 External VREF Applied - V External VREF Applied - V Figure 35. Signal Gain Adjustment versus External Reference (VREF) 22 AIN = -6 dBFS Figure 36. SFDR versus External VREF and AIN Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com 3.4 fS = 400 MSPS fIN = 70 MHz AIN = -6 dBFS 70 3.2 65 3.0 Power - W SNR - Signal-to-Noise Ratio - V 75 60 AIN = -4 dBFS AIN = -3 dBFS 55 fS = 400 MSPS fIN = 70 MHz 2.8 2.6 AIN = -2 dBFS 50 2.4 AIN = -5 dBFS AIN = -1 dBFS 45 2.2 40 2.0 2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15 2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15 External VREF Applied - V External VREF Applied - V Figure 37. SNR versus External VREF and AIN 3.8 Figure 38. Total Power Consumption versus External VREF fS = 400 MSPS fIN = 70 MHz 3.7 VCM Pin Output Voltage - V 3.6 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15 External VREF Applied - V Figure 39. VCM Pin Output versus External VREF Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 23 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com Clock Inputs The ADS5474 clock input can be driven with either a differential clock signal or a single-ended clock input. The characterization of the ADS5474 is typically performed with a 3-VPP differential clock, but the ADC performs well with a differential clock amplitude down to ~0.5 VPP, as shown in Figure 42. The clock amplitude becomes more of a factor in performance as the analog input frequency increases. In low-input-frequency applications, where jitter may not be a big concern, the use of a single-ended clock could save cost and board space without much performance tradeoff. When clocked with this configuration, it is best to connect CLK to ground with a 0.01-F capacitor, while CLK is ac-coupled with a 0.01-F capacitor to the clock source, as shown in Figure 41. ADS5474 AVDD5 ~ 2.5 nH Bond Wire CLK ~ 200 fF Bond Pad ~ 0.5 pF Package Parasitic ~ 0.2 pF 1000 W GND AVDD5 Internal Clock Buffer ~ 2.4 V GND Parasitic ~ 0.2 pF 1000 W ~ 2.5 nH Bond Wire CLK ~ 200 fF Bond Pad ~ 0.5 pF Package GND S0292-04 Figure 40. Clock Input Circuit 90 fS = 400 MSPS fIN = 230 MHz 85 SFDR (dBc) Square Wave or Sine Wave AC Performance - dB CLK 0.01 mF ADS5474 CLK 0.01 mF 80 75 70 SNR (dBFS) 65 60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Clock Amplitude - VPP Figure 41. Single-Ended Clock 24 Figure 42. AC Performance versus Clock Level Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications because the board level clock jitter is superior. Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. In the case of a sinusoidal clock, larger amplitudes result in higher clock slew rates and reduces the impact of clock noise on jitter. At high analog input frequencies, the sampling process is sensitive to jitter. And at slow clock frequencies, a small amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR degradation. Figure 43 demonstrates a recommended method for converting a single-ended clock source into a differential clock; it is similar to the configuration found on the evaluation board and was used for much of the characterization. See also Clocking High Speed Data Converters (SLYT075) for more details. 0.1 mF Clock Source CLK ADS5474 CLK Figure 43. Differential Clock The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-k resistors. It is recommended to use ac coupling, but if this scheme is not possible, the ADS5474 features good tolerance to clock common-mode variation (as shown in Figure 44 and Figure 45). Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided. Performance degradation as a result of duty cycle can be seen in Figure 46. 75 90 230 MHz 70 MHz 10 MHz SNR - Signal-to-Noise Ratio - dBFS SFDR - Spurious-Free Dynamic Range - dBc 10 MHz 85 80 75 351 MHz 70 65 60 55 2 3 65 230 MHz 60 55 50 50 1 70 MHz 351 MHz fS = 400 MSPS VCLK = 3 VPP fS = 400 MSPS VCLK = 3 VPP 0 70 4 5 0 1 2 3 4 5 Clock Common Mode - V Clock Common Mode - V Figure 44. SFDR versus Clock Common Mode Figure 45. SNR versus Clock Common Mode Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 25 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com SFDR - Spurious-Free Dynamic Range - dBc 90 fIN = 10 MHz fIN = 70 MHz 85 80 75 fIN = 230 MHz 70 fIN = 300 MHz 65 60 55 fS = 400 MSPS Clock Input = 3 VPP 50 20 30 40 50 60 70 80 Clock Duty Cycle - % Figure 46. SFDR vs Clock Duty Cycle The ADS5474 is capable of achieving 69.2 dBFS SNR at 350 MHz of analog input frequency. In order to achieve the SNR at 350 MHz the clock source rms jitter must be at least 144 fsec in order for the total rms jitter to be 177 fsec. A summary of maximum recommended rms clock jitter as a function of analog input frequency is provided in Table 3. The equations used to create the table are also presented. Table 3. Recommended RMS Clock Jitter INPUT FREQUENCY (MHz) MEASURED SNR (dBc) TOTAL JITTER (fsec rms) MAXIMUM CLOCK JITTER (fsec rms) 30 69.3 1818 1816 70 69.1 798 791 130 69.1 429 417 230 68.8 251 229 350 68.2 177 144 450 67.4 151 110 750 65.6 111 42 1000 63.7 104 14 Equation 1 and Equation 2 are used to estimate the required clock source jitter. SNR (dBc) = -20 LOG10 (2 p fIN jTOTAL) 2 (1) 2 1/2 jTOTAL = (jADC + jCLOCK ) (2) where: jTOTAL = the rms summation of the clock and ADC aperture jitter; jADC = the ADC internal aperture jitter which is located in the data sheet; jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and fIN = the analog input frequency. Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates. For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC 26 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com Devices, on the Texas Instruments web site. Recommended clock distribution chips (CDCs) are the TI CDC7005, the CDCM7005 and CDCE72010. Depending on the jitter requirements, a band pass filter (BPF) is sometimes required between the CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude to be too low for the ADC, or the clock source amplitude is too low to begin with, an inexpensive amplifier can be placed between the CDC and the BPF. Figure 47 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCM7005 with the clock signal path optimized for maximum amplitude and minimum jitter. This type of conditioning might generally be well-suited for use with greater than 150 MHz of input frequency. The jitter of this setup is difficult to estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter provided by the CDC is still not adequate. The total jitter at the CDCM7005 output depends largely on the phase noise of the VCXO selected, as well as the CDCM7005, and typically has 50-100 fs of rms jitter. If it is determined that the jitter from the CDCM7005 with a VCXO is sufficient without further conditioning, it is possible to clock the ADS5474 directly from the CDCM7005 using differential LVPECL outputs, as illustrated in Figure 48 (see the CDCM7005 data sheet for the exact schematic). This scenario may be more suitable for less than 150 MHz of input frequency where jitter is not as critical. A careful analysis of the required jitter is recommended before determining the proper approach. Low-Jitter Clock Distribution AMP and/or BPF are Optional Board Master Reference Clock (high or low jitter) 10 MHz LVCMOS REF AMP BPF CLKIN XFMR CLKIN 400 MHz ADC 800 MHz (to transmit DAC) 100 MHz (to DSP) VCXO 1/4 Low-Jitter Oscillator 800 MHz LVPECL or LVCMOS ADS5474 200 MHz (to FPGA) To Other CDC (Clock Distribution Chip) CDCM7005 This is an example block diagram. Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output frequency and amplitude ranges. Figure 47. Optimum Jitter Clock Circuit Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 27 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com Low-Jitter Clock Distribution Board Master Reference Clock (high or low jitter) 10 MHz 400 MHz CLKIN LVPECL REF CLKIN ADC 800 MHz (to transmit DAC) ADS5474 100 MHz (to DSP) Low-Jitter Oscillator 800 MHz VCXO 1/4 LVPECL or LVCMOS 200 MHz (to FPGA) To Other CDC (Clock Distribution Chip) CDCM7005 This is an example block diagram. Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output frequency and amplitude ranges. Figure 48. Acceptable Jitter Clock Circuit Digital Outputs The ADC provides 14 LVDS-compatible, offset binary data outputs (D13 to D0; D13 is the MSB and D0 is the LSB), a data-ready signal (DRY), and an over-range indicator (OVR). It is recommended to use the DRY signal to capture the output data of the ADS5474. DRY is source-synchronous to the DATA/OVR outputs and operates at the same frequency, creating a half-rate DDR interface that updates data on both the rising and falling edges of DRY. It is recommended that the capacitive loading on the digital outputs be minimized. Higher capacitance shortens the data-valid timing window. The values given for timing (see Figure 1) were obtained with a measured 10-pF parasitic board capacitance to ground on each LVDS line (or 5-pF differential parasitic capacitance). When setting the time relationship between DRY and DATA at the receiving device, it is generally recommended that setup time be maximized, but this partially depends on the setup and hold times of the device receiving the digital data (like an FPGA or Field Programmable Field Array). Since DRY and DATA are coincident, it will likely be necessary to delay either DRY or DATA such that setup time is maximized. Referencing Figure 1, the polarity of DRY with respect to the sample N data output transition is undetermined because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N and the polarity of DRY could invert when power is cycled off/on or when the power-down pin is cycled. Data capture from the transition and not the polarity of DRY is recommended, but not required. If the synchronization of multiple ADS5474 devices is required, it might be necessary to use a form of the CLKIN signal rather than DRY to capture the data. The DRY frequency is identical on the ADS5474 and ADS5463 (where DRY equals 1/2 the CLK frequency), but different than it is on the pin-similar ADS5444/ADS5440 (where DRY equals the CLK frequency). The LVDS outputs all require an external 100- load between each output pair in order to meet the expected LVDS voltage levels. For long trace lengths, it may be necessary to place a 100- load on each digital output as close to the ADS5474 as possible and another 100- differential load at the end of the LVDS transmission line to provide matched impedance and avoid signal reflections. The effective load in this case reduces the LVDS voltage levels by half. The OVR output equals a logic high when the 14-bit output word attempts to exceed either all 0s or all 1s. This flag is provided as an indicator that the analog input signal exceeded the full-scale input limit of approximately 2.2 VPP ( gain error). The OVR indicator is provided for systems that use gain control to keep the analog input signal within acceptable limits. 28 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com Power Supplies The ADS5474 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5 and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched supplies tend to generate more noise components that can be coupled to the ADS5474. However, the PSRR value and the plot shown in Figure 49 were obtained without bulk supply decoupling capacitors. When bulk (0.1 F) decoupling capacitors are used, the board-level PSRR is much higher than the stated value for the ADC. The user may be able to supply power to the device with a less-than-ideal supply and still achieve good performance. It is not possible to make a single recommendation for every type of supply and level of decoupling for all systems. If the noise characteristics of the available supplies are understood, a study of the PSRR data for the ADS5474 may provide the user with enough information to select noisy supplies if the performance is still acceptable within the frequency range of interest. The power consumption of the ADS5474 does not change substantially over clock rate or input frequency as a result of the architecture and process. The DVDD3 PSRR is superior to both the AVDD5 and AVDD3 so was not graphed. Because there are two diodes connected in reverse between AVDD3 and DVDD3 internally, a power-up sequence is recommended. When there is a delay in power up between these two supplies, the one that lags could have current sinking through an internal diode before it powers up. The sink current can be large or small depending on the impedance of the external supply and could damage the device or affect the supply source. The best power up sequence is one of the following options (regardless of when AVDD5 powers up): 1) Power up both AVDD3 and DVDD3 at the same time (best scenario), OR 2) Keep the voltage difference less than 0.8V between AVDD3 and DVDD3 during the power up (0.8V is not a hard specification - a smaller delta between supplies is safer). If the above sequences are not practical then the sink current from the supply needs to be controlled or protection added externally. The max transient current (on the order of sec) for DVDD3 or AVDD3 pin is 500mA to avoid potential damage to the device or reduce its lifetime. Values for analog and clock input given in the Absolute Maximum Ratings are valid when the supplies are on. When the power supplies are off and the clock or analog inputs are still alive, the input voltage and current needs to be limited to avoid device damage. If the ADC supplies are off, the max/min continuous DC voltage is +/- 0.95 V and max DC current is 20 mA for each input pin (clock or analog), relative to ground. 0 fS = 400 MSPS PSRR - Power-Supply Rejection Ratio - dB -10 -20 -30 -40 AVDD5 -50 -60 -70 -80 AVDD3 -90 -100 -110 DVDD3 -120 100 k 1M 10 M 100 M 1G Frequency - Hz Figure 49. PSRR versus Supply Injected Frequency Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 29 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com Operational Lifetime It is important for applications that anticipate running continuously for long periods of time near the maximum-rated ambient temperature of +85C to consider the data shown in Figure 50. Referring to the Thermal Characteristics table, the worst-case operating condition with no airflow has a thermal rise of 23.7C/W. At approximately 2.5 W of normal power dissipation, at a maximum ambient of +85C with no airflow, the junction temperature of the ADS5474 reaches approximately +85C + 23.7C/W x 2.5 W = +144C. Being even more conservative and accounting for the maximum possible power dissipation that is ensured (2.797 W), the junction temperature becomes nearly +150C. As Figure 50 shows, this performance limits the expected lifetime of the ADS5474. Operation at +85C continuously may require airflow or an additional heatsink in order to decrease the internal junction temperature and increase the expected lifetime (because of electromigration failures). An airflow of 250 LFM (linear feet per minute) reduces the thermal resistance to 16.4C/W and, therefore, the maximum junction temperature to +131C, assuming a worst-case of 2.797 W and +85C ambient. The ADS5474 performance over temperature is quite good and can be seen starting in Figure 21. Though the typical plots show good performance at +100C, the device is only rated from -40C to +85C. For continuous operation at temperatures near or above the maximum, the expected primary negative effect is a shorter device lifetime because of the electromigration failures at high junction temperatures. The maximum recommended continuous junction temperature is +150C. Estimated Life - Years 1000 100 10 1 80 90 100 110 120 130 140 150 160 170 180 Continuous Junction Temperature - C Figure 50. Operating Life Derating Chart, Electromigration Fail Mode 30 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com Layout Information The evaluation board represents a good model of how to lay out the printed circuit board (PCB) to obtain the maximum performance from the ADS5474. Follow general design rules, such as the use of multilayer boards, a single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors. The analog input traces should be isolated from any external source of interference or noise, including the digital outputs as well as the clock traces. The clock signal traces should also be isolated from other signals, especially in applications such as high IF sampling where low jitter is required. Besides performance-oriented rules, care must be taken when considering the heat dissipation of the device. The thermal heatsink included on the bottom of the package should be soldered to the board as described in the PowerPad Package section. See the ADS5474 EVM User Guide (SLAU194) on the TI web site for the evaluation board schematic. PowerPAD Package The PowerPAD package is a thermally-enhanced, standard-size IC package designed to eliminate the use of bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using standard PCB assembly techniques, and can be removed and replaced using standard repair procedures. The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of the IC. This pad design provides an extremely low thermal resistance path between the die and the exterior of the package. The thermal pad on the bottom of the IC can then be soldered directly to the PCB, using the PCB as a heatsink. Assembly Process 1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in the Mechanical Data section (at the end of this data sheet). 2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils (0.013 in or 0.3302 mm) in diameter. The small size prevents wicking of the solder through the holes. 3. It is recommended to place a small number of 25 mil (0.025 in or 0.635 mm) diameter holes under the package, but outside the thermal pad area, to provide an additional heat path. 4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a ground plane). 5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground plane. The spoke pattern increases the thermal resistance to the ground plane. 6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area. 7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking. 8. Apply solder paste to the exposed thermal pad area and all of the package terminals. For more detailed information regarding the PowerPAD package and its thermal properties, see either the PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application report (SLMA002), both available for download at www.ti.com. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 31 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value. The injected frequency level is translated into dBFS, the spur in the output FFT is measured in dBFS, and the difference is the PSRR in dB. The measurement calibrates out the benefit of the board supply decoupling capacitors. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and in the first five harmonics. P SNR + 10log 10 S PN Clock Pulse Duration/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse duration) to the period of the clock signal, expressed as a percentage. SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSB. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD + 10log 10 PN ) PD Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. (4) Common-Mode Rejection Ratio (CMRR) CMRR measures the ability to reject signals that are presented to both analog inputs simultaneously. The injected common-mode frequency level is translated into dBFS, the spur in the output FFT is measured in dBFS, and the difference is the CMRR in dB. Effective Number of Bits (ENOB) ENOB is a measure in units of bits of converter performance as compared to the theoretical limit based on quantization noise: ENOB = (SINAD - 1.76)/6.02 (3) Gain Error Gain error is the deviation of the ADC actual input full-scale range from its ideal value, given as a percentage of the ideal input full-scale range. Integral Nonlinearity (INL) INL is the deviation of the ADC transfer function from a best-fit line determined by a least-squares curve fit of that transfer function. The INL at each analog input value is the difference between the actual transfer function and this best-fit line, measured in units of LSB. Offset Error Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode. Power-Supply Rejection Ratio (PSRR) PSRR is a measure of the ability to reject frequencies present on the power supply. 32 (5) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Temperature Drift Temperature drift (with respect to gain error and offset error) specifies the change from the value at the nominal temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters over the whole temperature range divided by TMIN - TMAX. Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first five harmonics (PD). P THD + 10log 10 S PD (6) THD is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion (IMD3) IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power of the worst spectral component at either frequency 2f1 - f2 or 2f2 - f1). IMD3 is given in units of either dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 ADS5474 SLAS525B - JULY 2007 - REVISED FEBRUARY 2012 www.ti.com REVISION HISTORY Changes from Revision A (August 2008) to Revision B Page * Changed 1.6pF to 2.3pF TYP Input capacitance in ELECTRICAL CHARACTERISTICS ................................................... 3 * Changed (where DRY equals the CLK frequency) to (where DRY equals 1/2 the CLK frequency) in Digital Outputs section ................................................................................................................................................................................. 28 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): ADS5474 33 PACKAGE OPTION ADDENDUM www.ti.com 2-Sep-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS5474IPFP ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR ADS5474IPFPG4 ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR ADS5474IPFPR ACTIVE HTQFP PFP 80 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR ADS5474IPFPRG4 ACTIVE HTQFP PFP 80 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS5474IPFPR Package Package Pins Type Drawing HTQFP PFP 80 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 15.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.0 1.5 20.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS5474IPFPR HTQFP PFP 80 1000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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