Reference
Timing
CLK
OVR D[13:0]
CLK
6
DRY
VREF
VIN
VIN TH1
5 5
S
DAC2ADC2
ADC3
S
DAC1
ADC1
DigitalErrorCorrection
+
+
DRY
OVR
A1 TH2 A2 A3TH3
ADS5474
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SLAS525B JULY 2007REVISED FEBRUARY 2012
14-Bit, 400-MSPS Analog-to-Digital Converter
Check for Samples: ADS5474
1FEATURES
23400-MSPS Sample Rate TQFP-80 PowerPADPackage
(14 mm ×14 mm footprint)
14-Bit Resolution, 11.2-Bits ENOB
Industrial Temperature Range:
1.4-GHz Input Bandwidth 40°C to +85°C
SFDR = 80 dBc at 230 MHz and 400 MSPS Pin-Similar/Compatible with 12-, 13-, and 14-Bit
SNR = 69.8 dBFS at 230 MHz and 400 MSPS Family:
2.2-VPP Differential Input Voltage ADS5463 and ADS5440/ADS5444
LVDS-Compatible Outputs
Total Power Dissipation: 2.5 W APPLICATIONS
Power Down Mode: 50 mW Test and Measurement Instrumentation
Offset Binary Output Format Software-Defined Radio
Output Data Transitions on the Rising and Data Acquisition
Falling Edges of a Half-Rate Output Clock Power Amplifier Linearization
On-Chip Analog Buffer, Track-and-Hold, and Communication Instrumentation
Reference Circuit Radar
DESCRIPTION
The ADS5474 is a 14-bit, 400-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and
3.3-V supply while providing LVDS-compatible digital outputs. This ADC is one of a family of 12-, 13-, and 14-bit
ADCs that operate from 210 MSPS to 500 MSPS. The ADS5474 input buffer isolates the internal switching of the
onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An
internal reference generator is also provided to simplify the system design.
Designed with a 1.4-GHz input bandwidth for the conversion of wide-bandwidth signals that exceed 400 MHz of
input frequency at 400 MSPS, the ADS5474 has outstanding low-noise performance and spurious-free dynamic
range over a large input frequency range.
The ADS5474 is available in an TQFP-80 PowerPAD package. The device is built on Texas Instruments
complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (40°C to
+85°C).
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©20072012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD TEMPERATURE
DESIGNATOR MARKING NUMBER MEDIA, QUANTITY
RANGE
ADS5474IPFP Tray, 96
HTQFP-80(2)
ADS5474 PFP 40°C to +85°C ADS5474I
PowerPAD ADS5474IPFPR Tape and Reel, 1000
(1) For the most current product and ordering information see the Package Option Addendum located at the end of this document, or see
the TI web site at www.ti.com.
(2) Thermal pad size: 6.15 mm ×6.15 mm (minimum), 7.5 mm ×7.5 mm (maximum).
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted. ADS5474 UNIT
AVDD5 to GND 6 V
Supply voltage AVDD3 to GND 5 V
DVDD3 to GND 5 V
Analog input to Valid when supplies are on and within normal ranges. See additional 0.3 to (AVDD5 + 0.3) V
GND information in the Power Supplies portion of the applications information
in the back of the datasheet regarding Clock and Analog Inputs when the
Clock input to GND 0.3 to (AVDD5 + 0.3) V
supplies are off.
CLK to CLK ±2.5 V
Digital data output to GND 0.3 to (DVDD3 + 0.3) V
Operating temperature range 40 to +85 °C
Maximum junction temperature +150 °C
Storage temperature range 65 to +150 °C
ESD, human-body model (HBM) 2 kV
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime are available upon
request.
THERMAL CHARACTERISTICS(1)
PARAMETER TEST CONDITIONS TYP UNIT
Soldered thermal pad, no airflow 23.7
RθJA (2) Soldered thermal pad, 150-LFM airflow 17.8 °C/W
Soldered thermal pad, 250-LFM airflow 16.4
RθJP (3) Bottom of package (thermal pad) 2.99 °C/W
(1) Using 36 thermal vias (6 ×6 array). See PowerPAD Package in the Application Information section.
(2) RθJA is the thermal resistance from the junction to ambient.
(3) RθJP is the thermal resistance from the junction to the thermal pad.
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RECOMMENDED OPERATING CONDITIONS ADS5474 UNIT
MIN NOM MAX
SUPPLIES
AVDD5 Analog supply voltage 4.75 5 5.25 V
AVDD3 Analog supply voltage 3.1 3.3 3.6 V
DVDD3 Output driver supply voltage 3 3.3 3.6 V
ANALOG INPUT
Differential input range 2.2 VPP
VCM Input common mode 3.1 V
DIGITAL OUTPUT (DRY, DATA, OVR)
Maximum differential output load 10 pF
CLOCK INPUT (CLK)
CLK input sample rate (sine wave) 20 400 MSPS
Clock amplitude, differential sine wave (see Figure 42) 0.5 5 VPP
Clock duty cycle (see Figure 46) 40 50 60 %
TAOperating free-air temperature 40 +85 °C
ELECTRICAL CHARACTERISTICS
Typical values at TA= +25°C: minimum and maximum values over full temperature range TMIN =40°C to TMAX = +85°C,
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, 1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted. ADS5474
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
Resolution 14 Bits
ANALOG INPUTS
Differential input range 2.2 VPP
Analog input common-mode voltage Self-biased; see VCM specification below 3.1 V
Input resistance (dc) Each input to VCM 500
Input capacitance Each input to GND 2.3 pF
Analog input bandwidth (3dB) 1.44 GHz
Common-mode signal <50 MHz
CMRR Common-mode rejection ratio 100 dB
(see Figure 27)
INTERNAL REFERENCE VOLTAGE
VREF Reference voltage 2.4 V
With internal VREF. Provided as an output
via the VCM pin for dc-coupled
Analog input common-mode voltage
VCM applications. If an external VREF is used, 2.9 3.1 3.3 V
reference output the VCM pin tracks as illustrated in
Figure 39
VCM temperature coefficient 0.8 mV/°C
DYNAMIC ACCURACY
No missing codes Assured
DNL Differential linearity error fIN = 70 MHz 0.99 ±0.7 1.5 LSB
INL Integral linearity error fIN = 70 MHz 3±1 3 LSB
Offset error 11 11 mV
Offset temperature coefficient 0.02 mV/°C
Gain error 5 5 %FS
Gain temperature coefficient 0.02 %FS/°C
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA= +25°C: minimum and maximum values over full temperature range TMIN =40°C to TMAX = +85°C,
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, 1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted. ADS5474
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
POWER SUPPLY
IAVDD5 5-V analog supply current 338 372 mA
IAVDD3 3.3-V analog supply current VIN = full-scale, fIN = 70 MHz, 185 201 mA
fS= 400 MSPS
3.3-V digital supply current
IDVDD3 75 83 mA
(includes LVDS)
Total power dissipation 2.5 2.797 W
Power-up time From turn-on of AVDD5 50 μs
From PWD pin switched from HIGH (PWD
Wake-up time active) to LOW (ADC awake) 5 μs
(see Figure 28)
Power-down power dissipation PWD pin = logic HIGH 50 350 mW
Power-supply rejection ratio,
PSRR 75 dB
AVDD5 supply
Power-supply rejection ratio, Without 0.1-μF board supply capacitors,
PSRR 90 dB
AVDD3 supply with <1-MHz supply noise (see Figure 49)
Power-supply rejection ratio,
PSRR 110 dB
DVDD3 supply
DYNAMIC AC CHARACTERISTICS
fIN = 30 MHz 70.3
fIN = 70 MHz 68.3 70.2
fIN = 130 MHz 70.1
fIN = 230 MHz 68 69.8
SNR Signal-to-noise ratio fIN = 351 MHz 69.1 dBFS
fIN = 451 MHz 68.4
fIN = 651 MHz 67.5
fIN = 751 MHz 66.6
fIN = 999 MHz 64.7
fIN = 30 MHz 88
fIN = 70 MHz 74 86
fIN = 130 MHz 80
fIN = 230 MHz 71 80
SFDR Spurious-free dynamic range fIN = 351 MHz 76 dBc
fIN = 451 MHz 71
fIN = 651 MHz 60
fIN = 751 MHz 55
fIN = 999 MHz 46
fIN = 30 MHz 89
fIN = 70 MHz 87
fIN = 130 MHz 90
fIN = 230 MHz 84
HD2 Second-harmonic fIN = 351 MHz 76 dBc
fIN = 451 MHz 71
fIN = 651 MHz 74
fIN = 751 MHz 70
fIN = 999 MHz 55
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA= +25°C: minimum and maximum values over full temperature range TMIN =40°C to TMAX = +85°C,
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, 1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted. ADS5474
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
DYNAMIC AC CHARACTERISTICS (continued)
fIN = 30 MHz 93
fIN = 70 MHz 86
fIN = 130 MHz 80
fIN = 230 MHz 80
HD3 Third-harmonic fIN = 351 MHz 85 dBc
fIN = 451 MHz 71
fIN = 651 MHz 60
fIN = 751 MHz 55
fIN = 999 MHz 46
fIN = 30 MHz 95
fIN = 70 MHz 93
fIN = 130 MHz 85
fIN = 230 MHz 85
Worst harmonic/spur fIN = 351 MHz 87 dBc
(other than HD2 and HD3) fIN = 451 MHz 87
fIN = 651 MHz 90
fIN = 751 MHz 87
fIN = 999 MHz 80
fIN = 30 MHz 86
fIN = 70 MHz 83
fIN = 130 MHz 78
fIN = 230 MHz 77
THD Total harmonic distortion fIN = 351 MHz 75 dBc
fIN = 451 MHz 68
fIN = 651 MHz 60
fIN = 751 MHz 55
fIN = 999 MHz 45
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA= +25°C: minimum and maximum values over full temperature range TMIN =40°C to TMAX = +85°C,
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, 1 dBFS differential input,
and 3-VPP differential clock, unless otherwise noted. ADS5474
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
DYNAMIC AC CHARACTERISTICS (continued)
fIN = 30 MHz 69.2
fIN = 70 MHz 67 68.9
fIN = 130 MHz 68.5
fIN = 230 MHz 65.5 68.2
SINAD Signal-to-noise and distortion fIN = 351 MHz 67.3 dBc
fIN = 451 MHz 64.8
fIN = 651 MHz 58.5
fIN = 751 MHz 54
fIN = 999 MHz 45.4
fIN1 = 69 MHz, fIN2 = 70 MHz, 93
each tone at 7 dBFS
fIN1 = 69 MHz, fIN2 = 70 MHz, 95
each tone at 16 dBFS
Two-tone SFDR dBFS
fIN1 = 297.5 MHz, fIN2 = 302.5 MHz, 85
each tone at 7 dBFS
fIN1 = 297.5 MHz, fIN2 = 302.5 MHz, 83
each tone at 16 dBFS
fIN = 70 MHz 10.8 11.2
ENOB Effective number of bits Bits
fIN = 230 MHz 10.6 10.9
RMS idle-channel noise Inputs tied to common-mode 1.8 LSB
DIGITAL OUTPUTS
VOD Differential output voltage (±) 247 350 454 mV
VOC Common-mode output voltage 1.125 1.375 V
DIGITAL INPUTS
VIH High level input voltage 2.0 V
VIL Low level input voltage 0.8 V
IIH High level input current PWD (pin 33) 1 μA
IIL Low level input current -1 μA
Input capacitance 2 pF
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N
CLK
D OVR[13:0],
N+1
N+5
tCLKL
tDRY
tDATA
tCLKH
ta
D[13:0], OVR
CLK
N+2
N+3
N+4
DRY
DRY(1)
NN+1N–1
Sample
N–1
Latency = 3.5 Clock Cycles
ADS5474
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SLAS525B JULY 2007REVISED FEBRUARY 2012
TIMING INFORMATION
(1) Polarity of DRY is undetermined. For further information, see the Digital Outputs section.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS(1)
Typical values at TA= +25°C: minimum and maximum values over full temperature range TMIN =40°C to TMAX = +85°C,
sampling rate = 400 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential
clock, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
taAperture delay 200 ps
Aperture jitter, rms Internal jitter of the ADC 103 fs
Latency 3.5 cycles
tCLK Clock period 2.5 50 ns
tCLKH Clock pulse duration, high 1 ns
tCLKL Clock pulse duration, low 1 ns
Zero crossing, 10-pF parasitic loading to GND on each
tDRY CLK to DRY delay(2) 1000 1400 1800 ps
output pin
Zero crossing, 10-pF parasitic loading to GND on each
tDATA CLK to DATA/OVR delay(2) 800 1400 2000 ps
output pin
tDATA tDRY, 10-pF parasitic loading to GND on each output
tSKEW DATA to DRY skew 500 0 500 ps
pin
tRISE DRY/DATA/OVR rise time 10-pF parasitic loading to GND on each output pin 500 ps
tFALL DRY/DATA/OVR fall time 10-pF parasitic loading to GND on each output pin 500 ps
(1) Timing parameters are assured by design or characterization, but not production tested.
(2) DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation
delay.
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Product Folder Link(s): ADS5474
22 23
D5
AVDD5
D5
AGND
D4
AVDD5
D4
AGND
D3
AVDD5
D3
AGND
D2
AVDD5
D2
AGND
DGND
VCM
DVDD3
AGND
D1
AVDD5
D1
AGND
D0
PWD
D0
AGND
NC
AVDD3
NC
AGND
NC
AVDD3
NC
AGND
OVR
AVDD3
OVR
AGND
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DVDD3
DRY
DGND
DRY
AVDD5
D13
NC
D13
NC
D12
VREF
D12
AGND
D11
AVDD5
D11
AGND
D10
CLK
D10
CLK
D9
AGND
D9
AVDD5
D8
AVDD5
D8
AGND
DVDD3
AIN
DGND
AIN
D7
AGND
D7
AVDD5
D6
AGND
D6
25 26 27 28
PFP PACKAGE
(TOP VIEW)
79 78 77 76 7580 74 72 71 7073
29 30 31 32 33
69 68
21
67 66 65 64
34
35
36 37 38 39 40
63 62 61
ADS5474
P0027-03
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
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PIN CONFIGURATION
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Table 2. TERMINAL FUNCTIONS
TERMINAL DESCRIPTION
NAME NO.
AIN 16 Differential input signal (positive)
AIN 17 Differential input signal (negative)
3, 8, 13, 14, 19, 21,
AVDD5 Analog power supply (5 V)
23, 25, 27, 31 Analog power supply (3.3 V) (Suggestion for 250 MSPS: leave option to connect to 5 V for
AVDD3 35, 37, 39 ADS5440/ADS5444 13-bit compatibility)
DVDD3 1, 51, 66 Digital and output driver power supply (3.3 V)
7, 9, 12, 15, 18, 20,
AGND 22, 24, 26, 28, 30, Analog Ground
32, 34, 36, 38, 40
(Power Pad) (not numbered) Power Pad for thermal relief, also Analog Ground
DGND 2, 52, 65 Digital Ground
CLK 10 Differential input clock (positive). Conversion is initiated on rising edge, digital outputs on falling edge.
CLK 11 Differential input clock (negative)
D0, D0 48, 47 LVDS digital output pair, least significant bit (LSB)
D1D12, 49, 50, 5364, LVDS digital output pairs
D1D12 6776
D13, D13 78, 77 LVDS digital output pair, most significant bit (MSB)
DRY, DRY 80, 79 Data ready LVDS output pair
No connect (pins 4 and 5 should be left floating; pins 43 to 46 are possible future bit additions for this
NC 4, 5, 4346 pinout and therefore can be connected to a digital bus or left floating)
Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale
OVR, OVR 42, 41 range.
Common-mode voltage output (3.1 V nominal). Commonly used in DC-coupled applications to set the
input signal to the correct common-mode voltage. A 0.1μF capacitor from VCM to AGND is
VCM 29 recommended, but not required.
(This pin is not used on the ADS5440,ADS5444, and ADS5463)
Power-down (active high). Device is in sleep mode when PWD pin is logic HIGH. ADC converter is
PWD 33 awake when PWD is logic LOW (grounded).
(This pin is not used on the ADS5440,ADS5444, and ADS5463)
Reference voltage input/output (2.4 V nominal). A 0.1μF capacitor from VREF to AGND is
VREF 6 recommended, but not required.
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Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 80 100 120 140 160 180 200
Amplitude dB-
SFDR=88.4dBc
SNR=70.3dBFS
SINAD=70.2dBFS
THD=86dBc
Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 80 100 120 140 160 180 200
Amplitude dB-
SFDR=86.6dBc
SNR=70.1dBFS
SINAD=69.9dBFS
THD=82.9dBc
Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 80 100 120 140 160 180 200
Amplitude dB-
SFDR=78.5dBc
SNR=70.1dBFS
SINAD=69.5dBFS
THD=77.4dBc
Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 80 100 120 140 160 180 200
Amplitude dB-
SFDR=79.7dBc
SNR=69.8dBFS
SINAD=69.2dBFS
THD=76.9dBc
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
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TYPICAL CHARACTERISTICS
At TA= +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude
=1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
FFT FOR 30 MHz INPUT SIGNAL FFT FOR 70 MHz INPUT SIGNAL
Figure 2. Figure 3.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
FFT FOR 130 MHz INPUT SIGNAL FFT FOR 230 MHz INPUT SIGNAL
Figure 4. Figure 5.
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Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 80 100 120 140 160 180 200
Amplitude dB-
SFDR=75.5dBc
SNR=69.2dBFS
SINAD=68.3dBFS
THD=74.7dBc
Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 80 100 120 140 160 180 200
Amplitude dB-
SFDR=71.4dBc
SNR=68.4dBFS
SINAD=65.8dBFS
THD=68.3dBc
Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 80 100 120 140 160 180 200
Amplitude dB-
SFDR=54.5dBc
SNR=66.6dBFS
SINAD=55.1dBFS
THD=54.4dBc
Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 80 100 120 140 160 180 200
Amplitude dB-
SFDR=46dBc
SNR=64.7dBFS
SINAD=46.4dBFS
THD=45.5dBc
ADS5474
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SLAS525B JULY 2007REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude
=1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
FFT FOR 351 MHz INPUT SIGNAL FFT FOR 451 MHz INPUT SIGNAL
Figure 6. Figure 7.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
FFT FOR 751 MHz INPUT SIGNAL FFT FOR 999 MHz INPUT SIGNAL
Figure 8. Figure 9.
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Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 80 100 120 140 160 180 200
Amplitude dB-
f =69MHz, 7dBFS
IN1 -
f =70MHz, 7dBFS
IN2 -
IMD3=97.3dBFS
SFDR=93.4dBFS
Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 80 100 120 140 160 180 200
Amplitude dB-
f =297.5MHz, 7dBFS
f =302.5MHz, 7dBFS
IMD3=85.1dBFS
SFDR=85dBFS
IN1
IN2
-
-
Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 200
Amplitude dB-
80 100 120
f =69MHz, 16dBFS
f =70MHz, 16dBFS
IMD3=98dBFS
SFDR=95.7dFBS
IN1
IN2
-
-
140 160 180
Frequency MHz-
0
-20
-40
-60
-80
-100
-120
0 20 40 60 200
Amplitude dB-
80 100 120
f =297.5MHz, 16dBFS
f =302.5MHz, 16dBFS
IMD3=94.4dBFS
SFDR=83.1dFBS
IN1
IN2
-
-
140 160 180
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude
=1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
TWO-TONE INTERMODULATION DISTORTION TWO-TONE INTERMODULATION DISTORTION
(FFT for 69 MHz and 70 MHz at 7 dBFS) (FFT for 297.5 MHz and 302.5 MHz at 7 dBFS)
Figure 10. Figure 11.
TWO-TONE INTERMODULATION DISTORTION TWO-TONE INTERMODULATION DISTORTION
(FFT for 69 MHz and 70 MHz at 16 dBFS) (FFT for 297.5 MHz and 302.5 MHz at 16 dBFS)
Figure 12. Figure 13.
12 Submit Documentation Feedback Copyright ©20072012, Texas Instruments Incorporated
Product Folder Link(s): ADS5474
Frequency Hz-
3
0
-3
-6
-9
-12
-15
-18
-21
10M 100M 1G 5G
NormalizedGain dB-
f =400MSPS
A = 0.38V
S
IN PP
±
Code
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0 2048 4096 6144 8192 10240 12288 14336 16384
DNL LSB-
f =400MSPS
S
f =70MHz
IN
Code
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0 2048 4096 6144 8192 10240 12288 14336 16384
INL LSB-
f =400MSPS
S
f =70MHz
IN
ADS5474
www.ti.com
SLAS525B JULY 2007REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude
=1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
NORMALIZED GAIN RESPONSE
vs
INPUT FREQUENCY DIFFERENTIAL NONLINEARITY
Figure 14. Figure 15.
INTEGRAL NONLINEARITY NOISE HISTOGRAM WITH INPUTS SHORTED
Figure 16. Figure 17.
Copyright ©20072012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): ADS5474
InputAmplitude dBFS-
120
100
80
60
40
20
0
-20
-40
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
ACPerformance dB-
f =400MSPS
S
f =70MHz
IN
SFDR(dBc)
SFDR(dBFS)
SNR(dBc)
SNR(dBFS)
InputAmplitude dBFS-
120
100
80
60
40
20
0
-20
-40
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
ACPerformance dB-
f =400MSPS
S
f =230MHz
IN
SFDR(dBc)
SFDR(dBFS)
SNR(dBc)
SNR(dBFS)
AVDD5 SupplyVoltage V- -
90
88
86
84
82
80
78
76
70
4.7 4.8 4.9 5.0 5.3
SFDR Spurious-FreeDynamicRange dBc- -
74
72
5.1 5.2
f =400MSPS
f =230MHz
S
IN
-40 C°
+25 C°
+40 C°+65 C°
+100 C°
+85 C°
0 C°
A dBFS
IN -
100
90
80
70
60
50
40
30
0
-100 -90 -80 -70 0
Performance dB-
20
10
-60 -50 -40 -30 -20 -10
2f f (dBc)-
1 2
2f f (dBc)
2 1
-
WorstSpur(dBc)
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude
=1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
AC PERFORMANCE AC PERFORMANCE
vs vs
INPUT AMPLITUDE (70 MHz Input Signal) INPUT AMPLITUDE (230 MHz Input Signal)
Figure 18. Figure 19.
TWO-TONE PERFORMANCE SFDR
vs vs
INPUT AMPLITUDE (f1= 297.5 MHz and f2= 302.5 MHz) AVDD5 OVER TEMPERATURE
Figure 20. Figure 21.
14 Submit Documentation Feedback Copyright ©20072012, Texas Instruments Incorporated
Product Folder Link(s): ADS5474
AVDD5 SupplyVoltage V- -
71.0
70.5
70.0
69.5
69.0
68.5
68.0
4.7 4.8 4.9 5.0 5.3
SNR Signal-to-NoiseRatio dBFS- -
5.1 5.2
f =400MSPS
f =230MHz
S
IN
- °40 C
+25 C°+40 C°
+65 C°
+100 C°
+85 C°
0 C°
AVDD3 SupplyVoltage V- -
90
88
86
84
82
80
78
76
70
3.0 3.1 3.2 3.3 3.6
SFDR Spurious-FreeDynamicRange dBc- -
74
72
3.4 3.5
f =400MSPS
f =230MHz
S
IN
- °40 C
+25 C°+40 C°
+65 C°
+100 C°
+85 C°
0 C°
AVDD3 SupplyVoltage V- -
71.0
70.5
70.0
69.5
69.0
68.5
68.0
3.0 3.1 3.2 3.3 3.6
SNR Signal-to-NoiseRatio dBFS- -
3.4 3.5
f =400MSPS
f =230MHz
S
IN
-40 C°
+25 C°
+40 C°+65 C°
+100 C°
+85 C°
0 C°
DVDD3 SupplyVoltage V- -
90
88
86
84
82
80
78
76
70
3.0 3.1 3.2 3.3 3.6
SFDR Spurious-FreeDynamicRange dBc- -
74
72
3.4 3.5
f =400MSPS
f =230MHz
S
IN
- °40 C +100 C°
0 C°
+40 C°
+65 C°
+85 C°
+25 C°
ADS5474
www.ti.com
SLAS525B JULY 2007REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude
=1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SNR SFDR
vs vs
AVDD5 OVER TEMPERATURE AVDD3 OVER TEMPERATURE
Figure 22. Figure 23.
SNR SFDR
vs vs
AVDD3 OVER TEMPERATURE DVDD3 OVER TEMPERATURE
Figure 24. Figure 25.
Copyright ©20072012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): ADS5474
DVDD3 SupplyVoltage V- -
71.0
70.5
70.0
69.5
69.0
68.5
68.0
3.0 3.1 3.2 3.3 3.6
SNR Signal-to-NoiseRatio dBFS--
3.4 3.5
f =400MSPS
f =230MHz
S
IN
- °40 C +100 C°
0 C°
+40 C°+65 C°
+85 C°
+25 C°
Frequency Hz-
0
-10
-20
-30
-40
-50
-60
-70
-130
100k 1M 10M 100M 1G 10G
CMRR Common-ModeRejectionRatio dB- -
-80
-90
-100
-110
-120
400MSPS
300MSPS
Time sm-
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
0 10 20 30 40 50 60 70 80 90 100
SNR dBFS-
Wakefrom5VSupply
WakefromPDWN
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude
=1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SNR CMRR
vs vs
DVDD3 OVER TEMPERATURE COMMON-MODE INPUT FREQUENCY
Figure 26. Figure 27.
ADC WAKEUP TIME
Figure 28.
16 Submit Documentation Feedback Copyright ©20072012, Texas Instruments Incorporated
Product Folder Link(s): ADS5474
70
70
70
70 69
69
69
69
68
68
68
68
66
67
67
SNR dBFS-
54 56 58 60 62 64 68 70
10 100 200 300
66
400 500 600
f InputFrequency MHz
IN - -
f SamplingFrequency MHz
S- -
400
350
300
250
200
150
100
40
ADS5474
www.ti.com
SLAS525B JULY 2007REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude
=1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SNR
vs
INPUT FREQUENCY AND SAMPLING FREQUENCY
Figure 29.
Copyright ©20072012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): ADS5474
SFDR dBc-
50 55 60 65 75 80 85 90
10 100 200
70
300 400 500 600
85
85
80
80
80
80 77
77
77
77
77 73
73
73
70
70
70
65
65
65 60
80
85
85
85
85
f InputFrequency MHz
IN - -
f SamplingFrequency MHz
S- -
400
350
300
250
200
150
100
40
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, sampling rate = 400 MSPS, 50% clock duty cycle, 3-VPP differential sinusoidal clock, analog input amplitude
=1 dBFS, AVDD5 = 5 V, AVDD3 = 3.3 V, and DVDD3 = 3.3 V, unless otherwise noted.
SFDR
vs
INPUT FREQUENCY AND SAMPLING FREQUENCY
Figure 30.
APPLICATIONS INFORMATION
Theory of Operation
The ADS5474 is a 14-bit, 400-MSPS, monolithic pipeline ADC. Its bipolar analog core operates from 5-V and
3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The conversion
process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is
captured by the input track-and-hold (T&H), and the input sample is converted sequentially by a series of lower
resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling
clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in
a data latency of 3.5 clock cycles, after which the output data are available as a 14-bit parallel word, coded in
offset binary format.
Input Configuration
The analog input for the ADS5474 consists of an analog pseudo-differential buffer followed by a bipolar transistor
T&H. The analog buffer isolates the source driving the input of the ADC from any internal switching and presents
a high impedance that is easy to drive at high input frequencies, compared to an ADC without a buffered input.
The input common-mode is set internally through a 500-resistor connected from 3.1 V to each of the inputs
(common-mode is ~2.4V on 12- and 13-bit members of this family). This configuration results in a differential
input impedance of 1 k.
18 Submit Documentation Feedback Copyright ©20072012, Texas Instruments Incorporated
Product Folder Link(s): ADS5474
500 W
500 W
Buffer
VCM
Buffer
1.6 pF
1.6pF GND
S0293-01
AIN
AIN
AVDD5
AVDD5
ADS5463/5474/54RF63
GND
GND
~ 2.5 nH Bond Wire
~ 2.5 nH Bond Wire
~ 0.5pF
Package
~ 0.5pF
Package
~ 200fF
BondPad
~ 200fF
BondPad
ADS5474
www.ti.com
SLAS525B JULY 2007REVISED FEBRUARY 2012
Figure 31. Analog Input Equivalent Circuit
For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings
symmetrically between (3.1 V + 0.55 V) and (3.1 V 0.55 V). This range means that each input has a maximum
signal swing of 1.1 VPP for a total differential input signal swing of 2.2 VPP. Operation below 2.2 VPP is allowable,
with the characteristics of performance versus input amplitude demonstrated in Figure 18 and Figure 19. For
instance, for performance at 1.1 VPP rather than 2.2 VPP, refer to the SNR and SFDR at 6 dBFS (0 dBFS =
2.2 VPP). The maximum swing is determined by the internal reference voltage generator, eliminating the need for
any external circuitry for this purpose.
Copyright ©20072012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): ADS5474
R
50
0
W
Z
50
0
W
ADS5474
AIN
AIN
R
200 W
ACSignal
Source
Mini-Circuits
JTX-4-10T
ADS5474
THS9001 AIN
AIN
VIN
VIN THS9001
1000pF 1000pF
39pF
50 W
50 W0.1 Fm
1000pF 1000pF
18 Hm
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
www.ti.com
The ADS5474 performs optimally when the analog inputs are driven differentially. The circuit in Figure 32 shows
one possible configuration using an RF transformer with termination either on the primary or on the secondary of
the transformer. In addition, the evaluation module is configured with two back-to-back transformers, also
demonstrating good performance. If voltage gain is required, a step-up transformer can be used.
Figure 32. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
In addition to the transformer configurations, Texas Instruments offers a wide selection of single-ended
operational amplifiers that can be selected depending on the application. An RF gain-block amplifier, such as
Texas Instruments' THS9001, can also be used for high-input-frequency applications. For large voltage gains at
intermediate-frequencies in the 50 MHz to 400 MHz range, the configuration shown in Figure 33 can be used.
The component values can be tuned for different intermediate frequencies. The example shown in Figure 33 is
located on the evaluation module and is tuned for an IF of 170 MHz. More information regarding this
configuration can be found in the ADS5474 EVM User Guide (SLAU194) and the THS9001 50-MHz to 350-MHz
Cascadeable Amplifier data sheet (SLOS426), both available for download at www.ti.com.
Figure 33. Using the THS9001 IF Amplifier With the ADS5474
20 Submit Documentation Feedback Copyright ©20072012, Texas Instruments Incorporated
Product Folder Link(s): ADS5474
18pF
AIN
AIN VCM
ADS5474
+5V
THS4509
CM
348 W
348 W
100 W
100 W
78.9 W
78.9 W49.9 W
VIN
From
50
Source
W
49.9 W
49.9 W
49.9 W
0.1 Fm0.1 Fm
0.22 Fm
0.22 Fm0.22 Fm
ADS5474
www.ti.com
SLAS525B JULY 2007REVISED FEBRUARY 2012
For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier such
as the THS4509 (shown in Figure 34) provides good harmonic performance and low noise over a wide range of
frequencies.
Figure 34. Using the THS4509 or THS4520 With the ADS5474
In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5474 by utilizing the VCM output pin of
the ADC. The 50-resistors and 18-pF capacitor between the THS4509 outputs and ADS5474 inputs (along
with the input capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (3 dB). Input
termination is accomplished via the 78.9-resistor and 0.22-μF capacitor to ground, in conjunction with the input
impedance of the amplifier circuit. A 0.22-μF capacitor and 49.9-resistor are inserted to ground across the
78.9-resistor and 0.22-μF capacitor on the alternate input to balance the circuit. Gain is a function of the
source impedance, termination, and 348-feedback resistor. See the THS4509 data sheet for further
component values to set proper 50-termination for other common gains. Because the ADS5474 recommended
input common-mode voltage is 3.1 V, the THS4509 operates from a single power-supply input with VS+ = 5 V and
VS= 0 V (ground). This configuration has the potential to slightly exceed the recommended output voltage from
the THS4509 of 3.6V due to the ADC input common-mode of 3.1V and the +0.55V full-scale signal. This will not
harm the THS4509 but may result in a degradation in the harmonic performance of the THS4509. An amplifier
with a wider recommended output voltage range is the THS4520, which is optimized for low noise and low
distortion in the range of frequencies up to ~20MHz. Applications that are not sensitive to harmonic distortion
could consider either device at higher frequencies.
Copyright ©20072012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): ADS5474
ExternalVREFApplied V-
1.0
0.5
0
-0.5
-1.0
-1.5
-3.0
2.2 2.3 2.4 2.5 3.1
NormalizedGainAdjustment dB-
2.6 2.7 2.8
f =400MSPS
f =70MHz
A =< 1dBFS
S
IN
IN -
2.9 3.0
BestFit:
y= 3.14x+7.5063-
-2.0
-2.5
ExternalVREFApplied V-
90
80
70
60
50
40
2.05 2.15 2.25 2.35 2.45 3.15
SFDR Spurious-FreeDynamicRange dBc- -
f =400MSPS
f =70MHz
S
IN
2.55 2.65 2.75 2.85 2.95 3.05
A = 6dBFS-
IN
A = 4dBFS-
IN
A = 3dBFS-
IN
A = 5dBFS-
IN
A = 2dBFS-
IN
A = 1dBFS-
IN
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
www.ti.com
External Voltage Reference
For systems that require the analog signal gain to be adjusted or calibrated, this can be performed by using an
external reference. The dependency on the signal amplitude to the value of the external reference voltage is
characterized typically by Figure 35 (VREF = 2.4 V is normalized to 0 dB as this is the internal reference
voltage). As can be seen in the linear fit, this equates to approximately 0.3 dB of signal adjustment per 100 mV
of reference adjustment. The range of allowable variation depends on the analog input amplitude that is applied
to the inputs and the desired spectral performance, as can be seen in the performance versus external reference
graphs in Figure 36 and Figure 37. As the applied analog signal amplitude is reduced, more variation in the
reference voltage is allowed in the positive direction (which equates to a reduction in signal amplitude), whereas
an adjustment in reference voltage below the nominal 2.4 V (which equates to an increase in signal amplitude) is
not recommended below approximately 2.35 V. The power consumption versus reference voltage and operating
temperature should also be considered, especially at high ambient temperatures, because the lifetime of the
device is affected by internal junction temperature, see Figure 50.
For dc-coupled applications that use the VCM pin of the ADS5474 as the common mode of the signal in the
analog signal gain path prior to the ADC inputs, the information in Figure 39 is useful to consider versus the
allowable common-mode range of the device that is receiving the VCM voltage, such as an operational amplifier.
Because it is pin-compatible, it is important to note that the ADS5463 does not have a VCM pin and primarily
uses the VREF pin to provide the common-mode voltage in dc-coupled applications. The ADS5463 (VCM = 2.4
V) and ADS5474 (VCM = 3.1V) do not have the same common-mode voltage. To create a board layout that may
accommodate both devices in dc-coupled applications, route VCM and VREF both to a common point that can
be selected via a switch, jumper, or a 0 resistor.
Figure 35. Signal Gain Adjustment versus External Figure 36. SFDR versus External VREF and AIN
Reference (VREF)
22 Submit Documentation Feedback Copyright ©20072012, Texas Instruments Incorporated
Product Folder Link(s): ADS5474
ExternalVREFApplied V-
75
70
65
60
55
50
45
40
2.05 2.15 2.25 2.35 2.45 3.15
SNR Signal-to-NoiseRatio V- -
f =400MSPS
f =70MHz
S
IN
2.55 2.65 2.75 2.85 2.95 3.05
A = 4dBFS-
IN
A = 3dBFS-
IN
A = 2dBFS-
IN
A = 1dBFS-
IN A = 5dBFS-
IN
A = 6dBFS-
IN
ExternalVREFApplied V-
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
2.05 2.15 2.25 2.35 2.45 3.15
Power W-
f =400MSPS
f =70MHz
S
IN
2.55 2.65 2.75 2.85 2.95 3.05
ExternalVREFApplied V-
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
2.8
2.05 2.15 2.25 2.35 2.45 3.15
VCMPinOutputVoltage V-
3.0
2.9
f =400MSPS
f =70MHz
S
IN
2.55 2.65 2.75 2.85 2.95 3.05
ADS5474
www.ti.com
SLAS525B JULY 2007REVISED FEBRUARY 2012
Figure 37. SNR versus External VREF and AIN Figure 38. Total Power Consumption versus
External VREF
Figure 39. VCM Pin Output versus External VREF
Copyright ©20072012, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): ADS5474
1000 W
~ 2.4 V
CLK
CLK
AVDD5
AVDD5
1000 W
GND
ADS5474
GND
GND
~ 2.5 nH Bond Wire
~ 2.5 nH Bond Wire
Parasitic
~0.2pF
Parasitic
~0.2pF
S0292-04
Internal
Clock
Buffer
~ 0.5pF
Package
~ 0.5pF
Package
~ 200fF
BondPad
~ 200fF
BondPad
CLK
ADS5474
CLK
SquareWaveor
SineWave
0.01 Fm
0.01 Fm
ClockAmplitude V-PP
90
85
80
75
70
65
60
0 0.5 1.0 1.5 5.0
ACPerformance dB-
2.0 2.5 3.0
f =400MSPS
f =230MHz
S
IN
3.5 4.0 4.5
SFDR(dBc)
SNR(dBFS)
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
www.ti.com
Clock Inputs
The ADS5474 clock input can be driven with either a differential clock signal or a single-ended clock input. The
characterization of the ADS5474 is typically performed with a 3-VPP differential clock, but the ADC performs well
with a differential clock amplitude down to ~0.5 VPP, as shown in Figure 42. The clock amplitude becomes more
of a factor in performance as the analog input frequency increases. In low-input-frequency applications, where
jitter may not be a big concern, the use of a single-ended clock could save cost and board space without much
performance tradeoff. When clocked with this configuration, it is best to connect CLK to ground with a 0.01-μF
capacitor, while CLK is ac-coupled with a 0.01-μF capacitor to the clock source, as shown in Figure 41.
Figure 40. Clock Input Circuit
Figure 41. Single-Ended Clock Figure 42. AC Performance versus Clock Level
24 Submit Documentation Feedback Copyright ©20072012, Texas Instruments Incorporated
Product Folder Link(s): ADS5474
CLK
ADS5474
CLK
0.1 Fm
Clock
Source
ClockCommonMode V-
90
85
80
75
70
65
50
0 1 5
SFDR Spurious-FreeDynamicRange dBc--
2 3 4
60
55 f =400MSPS
V =3V
S
CLK PP
230MHz
351MHz
70MHz 10MHz
ClockCommonMode V-
75
70
65
50
0 1 5
SNR Signal-to-NoiseRatio dBFS- -
2 3 4
60
55
f =400MSPS
V =3V
S
CLK PP
230MHz
351MHz 70MHz
10MHz
ADS5474
www.ti.com
SLAS525B JULY 2007REVISED FEBRUARY 2012
For jitter-sensitive applications, the use of a differential clock has some advantages at the system level. The
differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a
differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications
because the board level clock jitter is superior.
Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. In
the case of a sinusoidal clock, larger amplitudes result in higher clock slew rates and reduces the impact of clock
noise on jitter. At high analog input frequencies, the sampling process is sensitive to jitter. And at slow clock
frequencies, a small amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR
degradation. Figure 43 demonstrates a recommended method for converting a single-ended clock source into a
differential clock; it is similar to the configuration found on the evaluation board and was used for much of the
characterization. See also Clocking High Speed Data Converters (SLYT075) for more details.
Figure 43. Differential Clock
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kresistors. It is
recommended to use ac coupling, but if this scheme is not possible, the ADS5474 features good tolerance to
clock common-mode variation (as shown in Figure 44 and Figure 45). Additionally, the internal ADC core uses
both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided.
Performance degradation as a result of duty cycle can be seen in Figure 46.
Figure 44. SFDR versus Clock Common Mode Figure 45. SNR versus Clock Common Mode
Copyright ©20072012, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): ADS5474
ClockDutyCycle %-
90
85
70
65
60
55
50
20 30 40 50 80
SFDR Spurious-FreeDynamicRange dBc- -
60 70
80
75
f =400MSPS
ClockInput=3V
S
PP
f =10MHz
IN f =70MHz
IN
f =230MHz
IN
f =300MHz
IN
SNR(dBc)= 20 LOG10(2 f j )- p ´´ ´ ´
IN TOTAL
j =(j +j )
TOTAL ADC CLOCK
2 1/22
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
www.ti.com
Figure 46. SFDR vs Clock Duty Cycle
The ADS5474 is capable of achieving 69.2 dBFS SNR at 350 MHz of analog input frequency. In order to achieve
the SNR at 350 MHz the clock source rms jitter must be at least 144 fsec in order for the total rms jitter to be 177
fsec. A summary of maximum recommended rms clock jitter as a function of analog input frequency is provided
in Table 3. The equations used to create the table are also presented.
Table 3. Recommended RMS Clock Jitter
MAXIMUM CLOCK
INPUT FREQUENCY MEASURED SNR TOTAL JITTER JITTER
(MHz) (dBc) (fsec rms) (fsec rms)
30 69.3 1818 1816
70 69.1 798 791
130 69.1 429 417
230 68.8 251 229
350 68.2 177 144
450 67.4 151 110
750 65.6 111 42
1000 63.7 104 14
Equation 1 and Equation 2 are used to estimate the required clock source jitter.
(1)
(2)
where:
jTOTAL = the rms summation of the clock and ADC aperture jitter;
jADC = the ADC internal aperture jitter which is located in the data sheet;
jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
fIN = the analog input frequency.
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
Application Note SLWA034,Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
26 Submit Documentation Feedback Copyright ©20072012, Texas Instruments Incorporated
Product Folder Link(s): ADS5474
Thisisanexampleblockdiagram.
Low-JitterClockDistribution
ADC
ADS5474
VCXO
REF
CDC
(ClockDistributionChip)
CDCM7005
800MHz(totransmitDAC)
100MHz(toDSP)
200MHz(toFPGA)
ToOther
BoardMaster
ReferenceClock
(highorlowjitter)
10MHz 400MHz
Low-JitterOscillator
800MHz
BPF
LVCMOS
LVPECL
or
LVCMOS
XFMR
AMP
CLKIN
CLKIN
¼
AMPand/orBPFareOptional
ADS5474
www.ti.com
SLAS525B JULY 2007REVISED FEBRUARY 2012
Devices, on the Texas Instruments web site. Recommended clock distribution chips (CDCs) are the TI
CDC7005, the CDCM7005 and CDCE72010. Depending on the jitter requirements, a band pass filter (BPF) is
sometimes required between the CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude
to be too low for the ADC, or the clock source amplitude is too low to begin with, an inexpensive amplifier can be
placed between the CDC and the BPF.
Figure 47 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCM7005 with
the clock signal path optimized for maximum amplitude and minimum jitter. This type of conditioning might
generally be well-suited for use with greater than 150 MHz of input frequency. The jitter of this setup is difficult to
estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost
amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter
provided by the CDC is still not adequate. The total jitter at the CDCM7005 output depends largely on the phase
noise of the VCXO selected, as well as the CDCM7005, and typically has 50100 fs of rms jitter. If it is
determined that the jitter from the CDCM7005 with a VCXO is sufficient without further conditioning, it is possible
to clock the ADS5474 directly from the CDCM7005 using differential LVPECL outputs, as illustrated in Figure 48
(see the CDCM7005 data sheet for the exact schematic). This scenario may be more suitable for less than 150
MHz of input frequency where jitter is not as critical. A careful analysis of the required jitter is recommended
before determining the proper approach.
Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 47. Optimum Jitter Clock Circuit
Copyright ©20072012, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): ADS5474
Thisisanexampleblockdiagram.
Low-JitterClockDistribution
ADC
ADS5474
VCXO
REF
CDC
(ClockDistributionChip)
CDCM7005
800MHz(totransmitDAC)
100MHz(toDSP)
200MHz(toFPGA)
ToOther
BoardMaster
ReferenceClock
(highorlowjitter)
10MHz
400MHz
Low-JitterOscillator
800MHz
LVPECL
LVPECL
or
LVCMOS
CLKIN
CLKIN
¼
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
www.ti.com
Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 48. Acceptable Jitter Clock Circuit
Digital Outputs
The ADC provides 14 LVDS-compatible, offset binary data outputs (D13 to D0; D13 is the MSB and D0 is the
LSB), a data-ready signal (DRY), and an over-range indicator (OVR). It is recommended to use the DRY signal
to capture the output data of the ADS5474. DRY is source-synchronous to the DATA/OVR outputs and operates
at the same frequency, creating a half-rate DDR interface that updates data on both the rising and falling edges
of DRY. It is recommended that the capacitive loading on the digital outputs be minimized. Higher capacitance
shortens the data-valid timing window. The values given for timing (see Figure 1) were obtained with a measured
10-pF parasitic board capacitance to ground on each LVDS line (or 5-pF differential parasitic capacitance). When
setting the time relationship between DRY and DATA at the receiving device, it is generally recommended that
setup time be maximized, but this partially depends on the setup and hold times of the device receiving the
digital data (like an FPGA or Field Programmable Field Array). Since DRY and DATA are coincident, it will likely
be necessary to delay either DRY or DATA such that setup time is maximized.
Referencing Figure 1, the polarity of DRY with respect to the sample N data output transition is undetermined
because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a
frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N and
the polarity of DRY could invert when power is cycled off/on or when the power-down pin is cycled. Data capture
from the transition and not the polarity of DRY is recommended, but not required. If the synchronization of
multiple ADS5474 devices is required, it might be necessary to use a form of the CLKIN signal rather than DRY
to capture the data.
The DRY frequency is identical on the ADS5474 and ADS5463 (where DRY equals ½the CLK frequency), but
different than it is on the pin-similar ADS5444/ADS5440 (where DRY equals the CLK frequency). The LVDS
outputs all require an external 100-load between each output pair in order to meet the expected LVDS voltage
levels. For long trace lengths, it may be necessary to place a 100-load on each digital output as close to the
ADS5474 as possible and another 100-differential load at the end of the LVDS transmission line to provide
matched impedance and avoid signal reflections. The effective load in this case reduces the LVDS voltage levels
by half.
The OVR output equals a logic high when the 14-bit output word attempts to exceed either all 0s or all 1s. This
flag is provided as an indicator that the analog input signal exceeded the full-scale input limit of approximately
2.2 VPP (±gain error). The OVR indicator is provided for systems that use gain control to keep the analog input
signal within acceptable limits.
28 Submit Documentation Feedback Copyright ©20072012, Texas Instruments Incorporated
Product Folder Link(s): ADS5474
Frequency Hz-
0
-10
-20
-30
-40
-50
-60
-70
-120
100k 1M 10M 100M 1G
PSRR Power-SupplyRejectionRatio dB--
-80
-90
-100
-110
f =400MSPS
S
AVDD5
AVDD3
DVDD3
ADS5474
www.ti.com
SLAS525B JULY 2007REVISED FEBRUARY 2012
Power Supplies
The ADS5474 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5
and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power
supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched
supplies tend to generate more noise components that can be coupled to the ADS5474. However, the PSRR
value and the plot shown in Figure 49 were obtained without bulk supply decoupling capacitors. When bulk (0.1
μF) decoupling capacitors are used, the board-level PSRR is much higher than the stated value for the ADC. The
user may be able to supply power to the device with a less-than-ideal supply and still achieve good performance.
It is not possible to make a single recommendation for every type of supply and level of decoupling for all
systems. If the noise characteristics of the available supplies are understood, a study of the PSRR data for the
ADS5474 may provide the user with enough information to select noisy supplies if the performance is still
acceptable within the frequency range of interest. The power consumption of the ADS5474 does not change
substantially over clock rate or input frequency as a result of the architecture and process. The DVDD3 PSRR is
superior to both the AVDD5 and AVDD3 so was not graphed.
Because there are two diodes connected in reverse between AVDD3 and DVDD3 internally, a power-up
sequence is recommended. When there is a delay in power up between these two supplies, the one that lags
could have current sinking through an internal diode before it powers up. The sink current can be large or small
depending on the impedance of the external supply and could damage the device or affect the supply source.
The best power up sequence is one of the following options (regardless of when AVDD5 powers up):
1) Power up both AVDD3 and DVDD3 at the same time (best scenario), OR
2) Keep the voltage difference less than 0.8V between AVDD3 and DVDD3 during the power up (0.8V is not a
hard specification - a smaller delta between supplies is safer).
If the above sequences are not practical then the sink current from the supply needs to be controlled or
protection added externally. The max transient current (on the order of μsec) for DVDD3 or AVDD3 pin is 500mA
to avoid potential damage to the device or reduce its lifetime.
Values for analog and clock input given in the Absolute Maximum Ratings are valid when the supplies are on.
When the power supplies are off and the clock or analog inputs are still alive, the input voltage and current needs
to be limited to avoid device damage. If the ADC supplies are off, the max/min continuous DC voltage is +/- 0.95
V and max DC current is 20 mA for each input pin (clock or analog), relative to ground.
Figure 49. PSRR versus Supply Injected Frequency
Copyright ©20072012, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): ADS5474
ContinuousJunctionTemperature C°-
1000
100
10
1
80 90 100 110 120 130 140 150 160 170 180
EstimatedLife Years-
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
www.ti.com
Operational Lifetime
It is important for applications that anticipate running continuously for long periods of time near the
maximum-rated ambient temperature of +85°C to consider the data shown in Figure 50. Referring to the Thermal
Characteristics table, the worst-case operating condition with no airflow has a thermal rise of 23.7°C/W. At
approximately 2.5 W of normal power dissipation, at a maximum ambient of +85°C with no airflow, the junction
temperature of the ADS5474 reaches approximately +85°C + 23.7°C/W ×2.5 W = +144°C. Being even more
conservative and accounting for the maximum possible power dissipation that is ensured (2.797 W), the junction
temperature becomes nearly +150°C. As Figure 50 shows, this performance limits the expected lifetime of the
ADS5474. Operation at +85°C continuously may require airflow or an additional heatsink in order to decrease the
internal junction temperature and increase the expected lifetime (because of electromigration failures). An airflow
of 250 LFM (linear feet per minute) reduces the thermal resistance to 16.4°C/W and, therefore, the maximum
junction temperature to +131°C, assuming a worst-case of 2.797 W and +85°C ambient.
The ADS5474 performance over temperature is quite good and can be seen starting in Figure 21. Though the
typical plots show good performance at +100°C, the device is only rated from 40°C to +85°C. For continuous
operation at temperatures near or above the maximum, the expected primary negative effect is a shorter device
lifetime because of the electromigration failures at high junction temperatures. The maximum recommended
continuous junction temperature is +150°C.
Figure 50. Operating Life Derating Chart, Electromigration Fail Mode
30 Submit Documentation Feedback Copyright ©20072012, Texas Instruments Incorporated
Product Folder Link(s): ADS5474
ADS5474
www.ti.com
SLAS525B JULY 2007REVISED FEBRUARY 2012
Layout Information
The evaluation board represents a good model of how to lay out the printed circuit board (PCB) to obtain the
maximum performance from the ADS5474. Follow general design rules, such as the use of multilayer boards, a
single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors. The analog input
traces should be isolated from any external source of interference or noise, including the digital outputs as well
as the clock traces. The clock signal traces should also be isolated from other signals, especially in applications
such as high IF sampling where low jitter is required. Besides performance-oriented rules, care must be taken
when considering the heat dissipation of the device. The thermal heatsink included on the bottom of the package
should be soldered to the board as described in the PowerPad Package section. See the ADS5474 EVM User
Guide (SLAU194) on the TI web site for the evaluation board schematic.
PowerPAD Package
The PowerPAD package is a thermally-enhanced, standard-size IC package designed to eliminate the use of
bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using
standard PCB assembly techniques, and can be removed and replaced using standard repair procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC. This pad design provides an extremely low thermal resistance path between the die and the exterior of
the package. The thermal pad on the bottom of the IC can then be soldered directly to the PCB, using the PCB
as a heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in
the Mechanical Data section (at the end of this data sheet).
2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils (0.013 in or
0.3302 mm) in diameter. The small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25 mil (0.025 in or 0.635 mm) diameter holes under the
package, but outside the thermal pad area, to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a
ground plane).
5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either the
PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application
report (SLMA002), both available for download at www.ti.com.
Copyright ©20072012, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): ADS5474
SNR +10log10 PS
PN
SINAD +10log10 PS
PN)PD
THD +10log10 PS
PD
ADS5474
SLAS525B JULY 2007REVISED FEBRUARY 2012
www.ti.com
DEFINITION OF SPECIFICATIONS The injected frequency level is translated into dBFS,
the spur in the output FFT is measured in dBFS, and
Analog Bandwidth the difference is the PSRR in dB. The measurement
The analog input frequency at which the power of the calibrates out the benefit of the board supply
fundamental is reduced by 3 dB with respect to the decoupling capacitors.
low-frequency value. Signal-to-Noise Ratio (SNR)
Aperture Delay SNR is the ratio of the power of the fundamental (PS)
The delay in time between the rising edge of the input to the noise floor power (PN), excluding the power at
sampling clock and the actual time at which the dc and in the first five harmonics.
sampling occurs.
Aperture Uncertainty (Jitter) (4)
The sample-to-sample variation in aperture delay. SNR is either given in units of dBc (dB to carrier)
Clock Pulse Duration/Duty Cycle when the absolute power of the fundamental is used
The duty cycle of a clock signal is the ratio of the time as the reference, or dBFS (dB to full-scale) when the
the clock signal remains at a logic high (clock pulse power of the fundamental is extrapolated to the
duration) to the period of the clock signal, expressed converter full-scale range.
as a percentage. Signal-to-Noise and Distortion (SINAD)
Differential Nonlinearity (DNL) SINAD is the ratio of the power of the fundamental
An ideal ADC exhibits code transitions at analog input (PS) to the power of all the other spectral components
values spaced exactly 1 LSB apart. DNL is the including noise (PN) and distortion (PD), but excluding
deviation of any single step from this ideal value, dc.
measured in units of LSB.
Common-Mode Rejection Ratio (CMRR)
CMRR measures the ability to reject signals that are (5)
presented to both analog inputs simultaneously. The SINAD is either given in units of dBc (dB to carrier)
injected common-mode frequency level is translated when the absolute power of the fundamental is used
into dBFS, the spur in the output FFT is measured in as the reference, or dBFS (dB to full-scale) when the
dBFS, and the difference is the CMRR in dB. power of the fundamental is extrapolated to the
Effective Number of Bits (ENOB) converter full-scale range.
ENOB is a measure in units of bits of converter Temperature Drift
performance as compared to the theoretical limit Temperature drift (with respect to gain error and
based on quantization noise: offset error) specifies the change from the value at
ENOB = (SINAD 1.76)/6.02 (3) the nominal temperature to the value at TMIN or TMAX.
It is computed as the maximum variation the
Gain Error parameters over the whole temperature range divided
Gain error is the deviation of the ADC actual input by TMIN TMAX.
full-scale range from its ideal value, given as a
percentage of the ideal input full-scale range. Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
Integral Nonlinearity (INL) to the power of the first five harmonics (PD).
INL is the deviation of the ADC transfer function from
a best-fit line determined by a least-squares curve fit
of that transfer function. The INL at each analog input (6)
value is the difference between the actual transfer
function and this best-fit line, measured in units of THD is typically given in units of dBc (dB to carrier).
LSB. Two-Tone Intermodulation Distortion (IMD3)
Offset Error IMD3 is the ratio of the power of the fundamental (at
Offset error is the deviation of output code from frequencies f1, f2) to the power of the worst spectral
mid-code when both inputs are tied to component at either frequency 2f1f2or 2f2f1).
common-mode. IMD3 is given in units of either dBc (dB to carrier)
when the absolute power of the fundamental is used
Power-Supply Rejection Ratio (PSRR) as the reference, or dBFS (dB to full-scale) when the
PSRR is a measure of the ability to reject frequencies power of the fundamental is extrapolated to the
present on the power supply. converter full-scale range.
32 Submit Documentation Feedback Copyright ©20072012, Texas Instruments Incorporated
Product Folder Link(s): ADS5474
ADS5474
www.ti.com
SLAS525B JULY 2007REVISED FEBRUARY 2012
REVISION HISTORY
Changes from Revision A (August 2008) to Revision B Page
Changed 1.6pF to 2.3pF TYP Input capacitance in ELECTRICAL CHARACTERISTICS ................................................... 3
Changed (where DRY equals the CLK frequency) to (where DRY equals ½the CLK frequency) in Digital Outputs
section ................................................................................................................................................................................. 28
Copyright ©20072012, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): ADS5474
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS5474IPFP ACTIVE HTQFP PFP 80 96 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
ADS5474IPFPG4 ACTIVE HTQFP PFP 80 96 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
ADS5474IPFPR ACTIVE HTQFP PFP 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
ADS5474IPFPRG4 ACTIVE HTQFP PFP 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Sep-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS5474IPFPR HTQFP PFP 80 1000 330.0 24.4 15.0 15.0 1.5 20.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS5474IPFPR HTQFP PFP 80 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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