1
Aug. 2009
GND
HIN
LIN
CIN
Vref
+
–
FO_RST
Interlock
& Noise Filter
UV
Pulse
Generator
Protection
Logic
VB
VS
VCC
LPOUT
LNOUT1
LNOUT2
VNO
FO
HPOUT
HNOUT1
HNOUT2
Filter
Logic
Filter
Filter
VREG
Vref
V
CC
Vreg
NC
NC
VB
HPOUT
HNOUT1
HNOUT2
VS
NC
NC
NC
NC
NC
NC
HIN
LIN
FO_RST
CIN
GND
FO
VCC
LPOUT
LNOUT1
LNOUT2
VNO
1 12
24 13
APPLICATIONS
Power MOSFET and IGBT gate driver for Medium and Mi-
cro inverter or general purpose.
FEATURES
¡Floating supply voltage up to 1200V
¡Low quiescent power supply current
¡Separate sink and source current output up to ±1A (typ)
¡
Active Miller effect clamp NMOS with sink current up to –1A (typ)
¡Input noise filters
¡Over-current detection and output shutdown
¡High side under voltage lockout
¡FO pin which can input and output Fault signals to commu-
nicate with controllers and synchronize the shut down with
other phases
¡Pb-free
¡24-Lead SSOP package
DESCRIPTION
M81019FP is high voltage Power MOSFET and IGBT gate
driver for half bridge applications.
BLOCK DIAGRAM
PIN CONFIGURATION (TOP VIEW)
Outline: 24P2Q
MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
2
Aug. 2009
V
V
V
V
V
V
V
V
V
V
V/ns
W
mW/°C
°C/W
°C
°C
°C
V
V
V
V
V
V
V
V
V
V
VS+13.5
–5
13.5
VS
13.5
–0.5
VNO
0
0
0
VS+15
—
15
—
—
—
—
5
—
—
VS+20
900
20
VS+20
20
5
VCC
VCC
VCC
5
ABSOLUTE MAXIMUM RATINGS
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating supply voltage
High side output voltage
Low side fixed supply voltage
Power ground
Low side output voltage
Logic input voltage
FO input/output voltage
CIN input voltage
Symbol UnitParameter Test conditions Limits
Min. Typ. Max.
VBS > 13.5V
VBS = VB–VS
HIN, LIN, FO_RST
VB
VS
VBS
VHO
VCC
VNO
VLO
VIN
VFO
VCIN
–0.5 ~ 1224
VB–24 ~ VB+0.5
–0.5 ~ 24
VS–0.5 ~ VB+0.5
–0.5 ~ 24
VCC–24 ~ VCC+0.5
VNO–0.5 ~ VCC+0.5
–0.5 ~ VCC+0.5
–0.5 ~ VCC+0.5
–0.5 ~ VCC+0.5
±50
1.6
16
60
–40 ~ 125
–40 ~ 100
–40 ~ 125
VBS = VB–VS
HIN, LIN, FO_RST
Ta = 25°C, On PCB
Ta > 25°C, On PCB
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating supply voltage
High side output voltage
Low side fixed supply voltage
Power ground
Low side output voltage
Logic input voltage
FO input/output voltage
CIN input voltage
Allowable offset voltage slew rate
Package power dissipation
Linear derating factor
Junction-case thermal resistance
Junction temperature
Operation temperature
Storage temperature
VB
VS
VBS
VHO
VCC
VNO
VLO
VIN
VFO
VCIN
dVS/dt
Pd
K q
Rth(j-c)
Tj
Topr
Tstg
Symbol Parameter Test conditions Ratings Unit
MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
Absolute maximum ratings indicate limitation beyond which destruction of device may occur. All voltage parameters are
absolute voltage reference to GND unless otherwise specified.
RECOMMENDED OPERATING CONDITIONS
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to GND unless otherwise specified.
Note : For proper operation, the device should be used within the recommend conditions.
THERMAL DERATING FACTOR CHARACTERISTIC
Ambience Temperature (°C)
Package Power Dissipation Pd (W)
0255075100 125 150
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
3
Aug. 2009
TYPICAL CONNECTION
MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
Note: If HVIC is working in high noise environment, it is recommended to connect a 1nF ceramic capacitor (CFO) to FO pin.
DC BUS
Voltage
DC+
DC-
M81019FP
Vout
Cboot
C
CIN
R
GOFF
5V~15V
15V
V
CC
V
B
V
S
V
NO
HPOUT
LPOUT
LNOUT1
LNOUT2
HNOUT1
HNOUT2
HIN
Rboot Dboot
LIN
FO_RST
FO
GND
CIN
R
GON
R
FO
C
FO
R
GOFF
R
GON
HOUT
LOUT
Rshunt
R
CIN
Other
Phases
MCU/DSP
Controller
4
Aug. 2009
MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
µA
mA
mA
V
V
V
V
mA
mA
ns
V
V
ns
V
V
V
V
V
V
µs
V
V
A
A
A
Ω
Ω
Ω
µs
µs
µs
µs
ns
ns
ns
ns
—
—
—
14.5
—
4.0
—
0.6
–0.01
80
2.0
6.0
—
—
4.0
—
10.5
10
0.2
4
0.4
4
—
—
—
—
—
—
1
0.9
1
0.9
—
—
—
—
—
0.5
1
—
—
—
—
1
0
200
3.4
7.6
400
0.4
—
—
11.3
10.8
0.5
8
0.5
5.5
1
–1
–1
15
15
15
1.27
1.21
1.39
1.19
40
40
80
180
1.0
0.8
1.5
—
0.5
—
0.6
1.4
0.01
500
5
9
—
0.95
—
0.6
12.1
11.6
0.8
16
0.6
7.5
—
—
—
—
—
—
1.8
1.8
1.9
1.7
—
—
—
—
High side leakage current
VBS quiescent supply current
VCC quiescent supply current
High level output voltage
Low level output voltage
High level input threshold voltage
Low level input threshold voltage
High level input bias current
Low level input bias current
Input signals filter time
High side active Miller clamp NMOS
input threshold voltage
Low side active Miller clamp NMOS
input threshold voltage
Active Miller clamp NMOS filter time
Low level FO output voltage
High level FO input threshold voltage
Low level FO input threshold voltage
VBS supply UV reset voltage
VBS supply UV trip voltage
VBS supply UV hysteresis voltage
VBS supply UV filter time
CIN trip voltage
POR trip voltage
Output high level short circuit pulsed current
Output low level short circuit pulsed current
Active Miller clamp NMOS output
low level short circuit pulsed current
Output high level on resistance
Output low level on resistance
Active Miller clamp NMOS output
low level on resistance
High side turn-on propagation delay
High side turn-off propagation delay
Low side turn-on propagation delay
Low side turn-off propagation delay
Output turn-on rise time
Output turn-off fall time
Delay matching, high side turn-on
and low side turn-off
Delay matching, high side turn-off
and low side turn-on
Symbol UnitParameter Test conditions Limits
Min. Typ. Max.
VB = VS = 1200V
HIN = LIN = 0V
HIN = LIN = 0V
IO = –20mA, HPOUT, LPOUT
IO = 20mA, HNOUT1, LNOUT1
HIN, LIN, FO_RST
HIN, LIN, FO_RST
VIN = 5V
VIN = 0V
HIN, LIN, FO_RST, FO
VIN = 0V
VIN = 0V
VIN = 0V
IFO = 1mA
VBSuvh = VBSuvr–VBSuvt
HPOUT (LPOUT) = 0V, HIN = 5V, PW < 5µs
HNOUT1 (LNOUT1) = 15V, LIN = 5V, PW < 5µs
HNOUT2 (LNOUT2) = 15V, LIN = 5V,
PW < 5µs
IO = –1A, ROH = (VOH–VO) /IO
IO = 1A, ROL1 = VO/IO
IO = 1A, ROL2 = VO/IO
HPOUT short to HNOUT1 and HNOUT2, CL = 1nF
HPOUT short to HNOUT1 and HNOUT2, CL = 1nF
LPOUT short to LNOUT1 and LNOUT2, CL = 1nF
LPOUT short to LNOUT1 and LNOUT2, CL = 1nF
CL = 1nF
CL = 1nF
tdLH (HO)-tdHL (LO)
tdLH (LO)-tdHL (HO)
IFS
IBS
ICC
VOH
VOL
VIH
VIL
IIH
IIL
tFilter
VHNO2
VLNO2
tVNO2
VOLFO
VIHFO
VILFO
VBSuvr
VBSuvt
VBSuvh
tVBSuv
VCIN
VPOR
IOH
IOL1
IOL2
ROH
ROL1
ROL2
tdLH(HO)
tdHL(HO)
tdLH(LO)
tdHL(LO)
tr
tf
∆tdLH
∆tdHL
ELECTRICAL CHARACTERISTICS (Ta=25°C, VCC=VBS (=VB–VS)=15V, unless otherwise specified)
Note: Typ is not specified.
5
Aug. 2009
MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
FUNCTION TABLE (Q: Keep previous status)
Interlock active
CIN tripping when LIN=H
CIN not tripping when LIN=L
Output shuts down when FO=L
VCC power reset
VBS power reset
VBS power reset is tripping when LIN=H
H→L
H→L
L→H
L→H
X
X
X
X
X
X
HIN Behavioral status
LIN VBS/UV
V
CC
/
POR
HOUT LOUT
L
H
L
H
H
L
X
X
L
H
H
H
H
H
X
X
X
X
L
L
H
H
H
H
H
H
H
L
H
H
L
L
H
Q
L
Q
L
L
L
L
L
H
L
Q
L
Q
L
L
L
H
Note1 : “L” status of VBS/UV indicates a high side UV condition; “L” status of VCC/POR indicates a VCC power reset condition.
Note2 : In the case of both input signals (HIN and LIN) are “H”, output signals (HOUT and LOUT) keep previous status.
Note3 : X (HIN) : L→H or H→L. Other : H or L.
Note4 : Output signal (HOUT) is triggered by the edge of input signal.
FO
(Output)
H
H
H
H
L
H
L
H
H
H
FO_RST
L
L
L
L
X
X
X
X
L
L
CIN
L
L
L
L
H
H
X
X
L
L
FO
(Input)
–
–
–
–
–
–
L
–
–
–
FUNCTIONAL DESCRIPTION
1. INPUT/OUTPUT TIMING DIAGRAM
LIN
HIN
HOUT
LOUT 90% 90%
90% 90%
10% 10%
10% 10%
tdLH(HO)
50% 50%
tdHL(LO)
tf
tr
tr
∆tdLH ∆tdHL
tf
tdLH(LO)
tdHL(HO)
HIN
HOUT
6
Aug. 2009
MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
Note1 : Delay times between input and output signals are not shown in the figure above.
Note2 : The minimum FO_RST pulse width should be more than 500ns (because of FO_RST input filter circuit).
3. SHORT CIRCUIT PROTECTION TIMING DIAGRAM
When an over-current is detected by exceeding the threshold at the CIN and LIN is at high level at the same time, the
short circuit protection will get active and shutdown the outputs while FO will issue a low level (indicating a fault signal).
The fault output latch is reset by a high level signal at FO_RST pin and then FO will return to high level while the output
of the driver will respond to the following active input signal.
HIN
LIN
CIN
FO_RST
HOUT
LOUT
FO
HIN
LIN
HOUT
LOUT
2. INPUT INTERLOCK TIMING DIAGRAM
When the input signals (HIN/LIN) are high level at the same time, the outputs (HOUT/LOUT) keep their previous status.
But if signals (HIN/LIN) are going to high level simultaneously, HIN signals will get active and cause HOUT to enter “H” status.
Note1: The minimum input pulse width at HIN/LIN should be to more than 500ns (because of HIN/LIN input noise filter circuit).
Note2: If a high-high status of input signals (HIN/LIN) is ended with only one input signal entering low level and another still being in high level, the output will
enter high-low status after the delay match time (not shown in the figure above).
Note3: Delay times between input and output signals are not shown in the figure above.
7
Aug. 2009
MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
Note1: Delay times between input and output signals are not shown in the figure above.
Note2: The minimum FO pulse width should be more than 500ns (because of FO input filter circuit).
4. FO INPUT TIMING DIAGRAM
When FO is pulled down to low level in case the FO of other phases becomes low level (fault happened) or the MCU/
DSP sets FO to low level, the outputs (HOUT, LOUT) of the driver will be shut down. As soon as FO goes high again,
the output will respond to the following active input signal.
Note1: Delay times between input and output signals are not shown in the figure above.
5. LOW SIDE VCC SUPPLY POWER RESET SEQUENCE
When the VCC supply voltage is lower than power reset trip voltage, the power reset gets active and the outputs (HOUT/
LOUT) become “L”. As soon as the VCC supply voltage goes higher than the power reset trip voltage, the outputs will
respond to the following active input signals.
HIN
LIN
FO
HOUT
LOUT
V
CC
HIN
V
POR
voltage
LIN
HOUT
LOUT
8
Aug. 2009
MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
Note1: Delay times between input and output signals are not shown in the figure above.
6. HIGH SIDE VBS SUPPLY UNDER VOLTAGE LOCKOUT SEQUENCE
When VBS supply voltage drops below the VBS supply UV trip voltage and the duration in this status exceeds the VBS
supply UV filter time, the output of the high side is locked. As soon as the VBS supply voltage rises above the VBS supply UV
reset voltage, the output will respond to the following active HIN signal.
7. POWER START-UP SEQUENCE
At power supply start-up the following sequence is recommended when bootstrap supply topology is used.
(1). Apply VCC.
(2). Make sure that FO is at high level.
(3). Set LIN to high level and HIN to low
level so that bootstrap capacitor could
be charged.
(4). Set LIN to low level.
Note: If two power supply are used for supplying
Note: VCC and VBS individually, it is recommended
Note: to set VCC first and then set VBS.
VBSuvt
VBSuvrVBSuvr
VBS supply UV
hysteresis voltage
VBS
HIN
LIN
HOUT
LOUT
VBS supply UV filter time
V
CC
FO
HIN
LIN
LOUT
9
Aug. 2009
MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
8. ACTIVE MILLER EFFECT CLAMP NMOS OUTPUT TIMING DIAGRAM
The structure of the output driver stage is shown in following figure. This circuit structure employs a solution for the problem
of the Miller current through Cres in IGBT switching applications. Instead of driving the IGBT gate to a negative voltage to
increase the safety margin, this circuit structure uses a NMOS to establish a low impedance path to prevent the self-turn-on
due to the parasitic Miller capacitor in power switches.
When HIN/LIN is at low level and the voltage of the VOUT (IGBT gate voltage) is below active Miller effect clamp NMOS
input threshold voltage, the active Miller effect clamp NMOS is being turned on and opens a low resistive path for the Miller
current through Cres.
P1 ON P1 OFF
N1 ON
N2 ON
N1 OFF
P1 ON
N1 OFF
N2 OFF N2 OFF
TW
Active Miller effect clamp
NMOS input threshold
Active Miller effect clamp NMOS
keeps turn-on if TW does not exceed
active Miller clamp NMOS filter time
VIN
VPG
VN1G
VOUT
VN2G
Cres
high dv/dt
P1
V
OUT
V
S
/V
NO
V
N2G
V
PG
/V
N1G
V
IN
=0
(from HIN/LIN)
Active Miller Effect
Clamp NMOS
Cies
N2
N1
V
BS
/V
CC
10
Aug. 2009
MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
PACKAGE OUTLINE
SSOP24-P-300-0.80
Weight(g)
–
JEDEC Code
0.2
EIAJ Package Code Lead Material
Cu Alloy
24P2Q-A
Symbol Min Nom Max
A
A2
b
c
D
E
L
L1
y
Dimension in Millimeters
HE
A1
I2
–
–
.30
0
.180
.010
.25
–
.57
.40
–
–
–
.271
.10
–
.81
.350
.20
.110
.35
.80
.87
.60
.251
–
.627
–
.20
.12
–
.450
.250
.210
.45
–
.18
.80
–
.10
–
b2–.50–
–
0°–8°
e
e1
24 13
12
1
HE
E
D
ey
F
A
A2A1
L1
L
c
eb2
e1
I2
Recommended Mount Pad
Detail F
–
–
Z1
0.65
–
–
0.8
z
Detail G
z
Z1
b
G
INTERNAL DIODE CLAMP CIRCUITS FOR INPUT AND OUTPUT PINS
VCC
VCC
HIN
LIN
FO_RST
LPOUT
LNOUT1
LNOUT2
GND
5K
GND
VCC
CIN
FO
GND
VB
HPOUT
VS
VCC
VNO
GND
VB
HNOUT1
HNOUT2
