0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.05
Output Current (A)
Efficiency (%)
VO= 5 V, fsw = 100 kHz, EN Floating
VO= 3.3 V, fsw = 400 kHz
VIN = 10 V
G000
TPS54062
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SLVSAV1B –MAY 2011–REVISED AUGUST 2012
4.7V to 60V Input, 50mA Synchronous Step-Down Converter with Low IQ
Check for Samples: TPS54062
1FEATURES DESCRIPTION
The TPS54062 device is a 60 V, 50-mA, synchronous
2• Integrated High Side and Low Side MOSFET step-down converter with integrated high side and low
• Peak Current Mode Control side MOSFETs. Current mode control provides
• Diode Emulation for Improved Light Load simple external compensation and flexible component
Efficiency selection. The non-switching supply current is 89 µA.
Using the enable pin, shutdown supply current is
• 89 µA (typical) Operating Quiescent Current reduced to 1.7 µA.
• 100 kHz to 400 kHz Adjustable Switching Under voltage lockout is internally set at 4.5 V, but
Frequency can be increased using the accurate enable pin
• Synchronizes to External Clock threshold. The output voltage startup ramp is
• Internal Slow Start controlled by the internal slow start time.
• 0.8 V ±2% Voltage Reference Adjustable switching frequency range allows
• Stable with Ceramic Output Capacitors or Low efficiency and external component size to be
Cost Aluminum Electrolytic optimized. Frequency fold back and thermal
shutdown protects the part during an overload
• Cycle-by-Cycle Current Limit, Thermal and condition.
Frequency Fold Back Protection
• MSOP-8 and 3mm x 3mm VSON-8 Packages
APPLICATIONS
• Low Power Standby or Bias Voltage Supplies
• 4-20 mA Current-Loop Powered Sensors
• Industrial Process Control, Metering, and
Security Systems
• High Voltage Linear Regulator Replacement
spacer
SIMPLIFIED SCHEMATIC EFFICIENCY
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SwitcherPro is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
2
Thermal
Pad (9)
COMP 36
1
4
7
8
5
EN
GND
PH
VSENSE
VIN
BOOT
RT/CLK
See appended
Mechanical
Data for
size and shape
1
2
3
45
6
7
8
BOOT
VIN
PH
GND
COMP
VSENSE
EN
RT/CLK
TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. ORDERING INFORMATION(1)
TJPACKAGE PART NUMBER(2)
MSOP-8 DGK TPS54062DGK
–40°C to 125°C VSON-8 DRB TPS54062DRB
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The DGK and DRB packages are also available taped and reeled. Add an R suffix to the device type (i.e., TPS54062DGKR).
PIN CONFIGURATION PIN CONFIGURATION
MSOP-8 PACKAGE VSON-8 PACKAGE
(TOP VIEW) (BOTTOM VIEW)
PIN FUNCTIONS
PIN DESCRIPTION
NAME NUMBER
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum
BOOT 1 required by the output device, the output is forced to switch off until the capacitor is refreshed.
VIN 2 Input supply voltage, 4.7 V to 60 V.
Enable pin, internal pull-up current source. Pull below 1.14 V to disable. Float to enable. Adjust the input
EN 3 undervoltage lockout with two resistors, see the Enable and Adjusting Undervoltage Lockout section.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a
RT/CLK 4 mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the
pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-
enabled and the mode returns to a resistor frequency programming.
VSENSE 5 Inverting input of the transconductance (gm) error amplifier.
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
COMP 6 components to this pin.
GND 7 Ground
PH 8 The source of the internal high-side power MOSFET and drain of the internal low side MOSFET
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
Thermal Pad 9 VSON-8 package only.
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Product Folder Link(s): TPS54062
ERROR
AMPLIFIER
Boot
Charge
Boot
UVLO
UVLO
Current
Sense
Oscillator
with PLL
Frequency
Shift
Deadtime
Control Logic
Slope
Compensation
PWM
Comparator
Minimum
Clamp
Maximum
Clamp
REFERENCE
DAC
VSENSE
COMP
RT/CLK
PH
BOOT
VIN
GND
Thermal
Shutdown
EN
Enable
Comparator
Shutdown
Logic
Shutdown
Enable
Threshold
Shutdown
OV
DRV
REG
ZX
detect
TPS54062
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SLVSAV1B –MAY 2011–REVISED AUGUST 2012
FUNCTIONAL BLOCK DIAGRAM
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) VALUE UNIT
MIN MAX
VIN –0.3 62 V
EN –0.3 8 V
PH-BOOT 8 V
BOOT 70 V
Voltage VSENSE –0.3 6 V
COMP –0.3 3 V
PH –0.6 62 V
PH, 10ns Transient –2 62 V
RT/CLK –0.3 6 V
VIN Internally Limited A
EN 100 µA
BOOT 100 mA
Current VSENSE 10 µA
COMP 100 µA
PH Internally Limited A
RT/CLK 200 µA
(HBM) QSS 009-105 (JESD22-A114A) 2 kV
Electrostatic discharge (CDM) QSS 009-147 (JESD22-C101B.01) 500 V
Operating junction temperature –40 125 ºC
Storage temperature –65 150 ºC
(1) The Absolute Maximum Ratings specified in this section will apply to all specifications of this document unless otherwise noted. These
specifications will be interpreted as the conditions which may damage the device with a single occurrence.
THERMAL INFORMATION TPS54062
THERMAL METRIC(1) UNITS
MSOP-8 VSON-8
θJA Junction-to-ambient thermal resistance 127.1 40.2
θJCtop Junction-to-case (top) thermal resistance 33.4 49.7
θJB Junction-to-board thermal resistance 80 15.7 °C/W
ψJT Junction-to-top characterization parameter 1 0.6
ψJB Junction-to-board characterization parameter 79 15.9
θJCbot Junction-to-case (bottom) thermal resistance n/a 4.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
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TPS54062
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SLVSAV1B –MAY 2011–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS(1)
TEST CONDITIONS: TJ= –40°C to 125°C, VIN = 4.7 To 60 V ( (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage VIN 4.7 60 V
Shutdown supply current EN = 0V 1.7 µA
Iq Operating – Non switching VSENSE = 0.9V, VIN = 12V 89 110 µA
ENABLE AND UVLO (EN PIN)
Rising 1.24 1.4 V
Enable threshold Falling 1 1.14 V
Enable threshold +50 mV –4.7 µA
Input current Enable threshold –50 mV –1.2 µA
Hysteresis 3.5 µA
Enable to start switching time 450 µs
VIN
VIN start voltage VIN rising 4.53 V
VOLTAGE REFERENCE
Voltage reference 1mA < IOUT < Minimum Current Limit 0.784 0.8 0.816 V
HIGH-SIDE MOSFET
Switch resistance BOOT-PH = 5.7V 1.5 2.8 Ω
LOW-SIDE MOSFET
Switch resistance VIN = 12V 0.8 1.5 Ω
ERROR AMPLIFIER
Input Current VSENSE pin 20 nA
Error amp gm –2µA < I(COMP) < 2µA, V(COMP) = 1V 102 µMhos
EA gm during slow start –2µA < I(COMP) < 2µA, V(COMP) = 1V, VSENSE = 0.4V 26 µMhos
Error amp dc gain VSENSE = 0.8V 1000 V/V
Min unity gain bandwidth 0.5 MHz
Error amp source/sink V(COMP) = 1V, 100 mV Overdrive ±8 µA
Start Switching Threshold 0.57 V
COMP to Iswitch gm 0.65 A/V
CURRENT LIMIT
High side sourcing current limit VIN = 12V BOOT-PH = 5.7V 75 134 mA
threshold
Zero cross detect current –0.7 mA
THERMAL SHUTDOWN
Thermal shutdown 146 C
RT/CLK
Operating frequency using RT mode 100 400 kHz
Switching frequency R(RT/CLK) = 510kΩ192 240 288 kHz
Minimum CLK pulse width 40 ns
RT/CLK voltage R(RT/CLK) = 510kΩ0.53 V
RT/CLK high threshold 1.3 V
RT/CLK low threshold 0.5 V
RT/CLK falling edge to PH rising Measure at 240 kHz with RT resistor in series 100 200 ns
edge delay
PLL lock in time Measure at 240 kHz 100 µs
PLL frequency range 300 400 kHz
(1) The Electrical Ratings specified in this section will apply to all specifications in this document unless otherwise noted. These
specifications will be interpreted as conditions that will not degrade the device’s parametric or functional specifications for the life of the
product containing it.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
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TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
ELECTRICAL CHARACTERISTICS(1) (continued)
TEST CONDITIONS: TJ= –40°C to 125°C, VIN = 4.7 To 60 V ( (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
PH
Minimum On time Measured at 50% to 50% of VIN IOUT = 50mA 120 ns
Dead time VIN = 12V, IOUT = 50mA, One transition 30 ns
BOOT
BOOT to PH regulation voltage VIN = 12V 5.7 V
BOOT-PH UVLO 2.9 V
INTERNAL SLOW START TIME
Slow start time fSW = 240kHz, RT = 510kΩ, 10% to 90% 4.1 ms
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200
210
220
230
240
250
260
270
280
−50 −25 0 25 50 75 100 125
Temperature (°C)
Oscillator Frequency (kHz)
VIN = 12V
RT = 510kΩ
G004
0
50
100
150
200
250
300
350
400
300 425 550 675 800 925 1050 1175 1300
Timing Resistance (kΩ)
Oscillator Frequency (kHz)
VIN = 12V
G006
0.0
12.5
25.0
37.5
50.0
62.5
75.0
87.5
100.0
0 100 200 300 400 500 600 700 800 900
Feedback Voltage (mV)
% of Normal Fsw
VSENSE Rising
VSENSE Falling
VIN = 12V
G005
0.792
0.794
0.796
0.798
0.800
0.802
0.804
0.806
0.808
−50 −25 0 25 50 75 100 125
Temperature (°C)
Voltage Reference (V)
VIN = 12V
G003
0.5
1.0
1.5
2.0
2.5
3.0
−50 −25 0 25 50 75 100 125
Temperature (°C)
Resistance (Ω)
VIN = 4.7V
VIN = 12V
VIN = 60V
G001
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
−50 −25 0 25 50 75 100 125
Temperature (°C)
Resistance (Ω)
VIN = 4.7V
VIN = 12V
VIN = 60V
G002
TPS54062
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SLVSAV1B –MAY 2011–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS
SPACER
Figure 1. High Side RDS(on) vs Temperature Figure 2. Low Side RDS(on) vs Temperature
Figure 3. VREF Voltage vs Temperature Figure 4. Frequency vs VSENSE Voltage
Figure 5. Frequency vs Temperature Figure 6. Frequency vs RT/CLK Resistance
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−2.0
−1.8
−1.6
−1.4
−1.2
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0 5 10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
Enable Current (µA)
G016
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
Shutdown Current (µA)
TJ = 125°C
TJ = 25°C
TJ = −40°C
G009
−3.60
−3.55
−3.50
−3.45
−3.40
−3.35
−3.30
−3.25
−3.20
−50 −25 0 25 50 75 100 125
Junction Temperature (°C)
Enable Hysteresis Current (µA)
VIN = 12V
G015
4.05
4.10
4.15
4.20
4.25
4.30
4.35
4.40
4.45
4.50
−50 −25 0 25 50 75 100 125
Junction Temperature (°C)
Input Voltage (V)
UVLO Start
UVLO Stop
G012
0
20
40
60
80
100
120
140
−50 −25 0 25 50 75 100 125
Temperature (°C)
Transconductance (µA)
VIN = 12V
G007
1.12
1.14
1.16
1.18
1.20
1.22
1.24
1.26
−50 −25 0 25 50 75 100 125
Junction Temperature (°C)
Enable Voltage (V)
VENA Rising
VENA Falling
VIN = 12V
G013
TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 7. Error Amp Transconductance vs Temperature Figure 8. Enable Pin Voltage vs Temperature
Figure 9. Enable Pin Hysteresis Current Figure 10. Input Voltage (UVLO) vs Temperature
vs Temperature
Figure 11. Enable Pin Pull Up Current vs Input Voltage Figure 12. Shutdown Supply Current (VIN) vs Input Voltage
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100
110
120
130
140
150
160
170
0 5 10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
Current Limit Threshold (mA)
TJ = −40°C
TJ = 25°C
TJ = 125°C
G018
0
20
40
60
80
100
120
140
0 1 2 3 4 5
Input Voltage (V)
Supply Current (µA)
TJ = 125°C
TJ = 25°C
TJ = −40°C
G010
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
−50 −25 0 25 50 75 100 125
Junction Temperature (°C)
SS Time (ms)
FSW = 240KHz
G025
84
86
88
90
92
94
96
98
0 5 10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
Supply Current (µA)
TJ = 125°C
TJ = −40°C
TJ = 25°C
Non−Switching
G008
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
0 1 2 3 4 5
Input Voltage (V)
Supply Current (µA)
TJ = 125°C
TJ = 25°C
TJ = −40°C
G011
TPS54062
www.ti.com
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Figure 13. Supply Current (VIN pin) vs Input Voltage Figure 14. Supply Current (VIN pin)
vs Input Voltage (0V to VSTART) EN Pin Low
Figure 15. Supply Current (VIN pin) vs Figure 16. Slow Start Time vs Temperature
Input Voltage (0V to VSTART) EN Pin Open
Figure 17. Current Limit vs
Input Voltage
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TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
OVERVIEW
The TPS54062 device is a 60 V, 50 mA, step-down (buck) regulator with an integrated high side and low side n-
channel MOSFET. To improve performance during line and load transients the device implements a constant
frequency, current mode control which reduces output capacitance and simplifies external frequency
compensation design.
The switching frequency of 100 kHz to 400 kHz allows for efficiency and size optimization when selecting the
output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The
device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch
turn on to a falling edge of an external system clock.
The TPS54062 has a default start up voltage of approximately 4.5V. The EN pin has an internal pull-up current
source that can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external
resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device will
operate. The operating current is 89uA when not switching and under no load. When the device is disabled, the
supply current is 1.7µA.
The integrated 1.5Ωhigh side MOSFET and 0.8Ωlow side MOSFET allows for high efficiency power supply
designs capable of delivering 50 milliamperes of continuous current to a load.
The TPS54062 reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor
voltage is monitored by an UVLO circuit and will turn the high side MOSFET off when the boot voltage falls
below a preset threshold. The TPS54062 can operate at high duty cycles because of the boot UVLO. The output
voltage can be stepped down to as low as the 0.8 V reference.
The TPS54062 has an internal output OV protection that disables the high side MOSFET if the output voltage is
109% of the nominal output voltage.
The TPS54062 reduces external component count by integrating the slow start time using a reference DAC
system.
The TPS54062 resets the slow start times during overload conditions with an overload recovery circuit. The
overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage once a
fault condition is removed. A frequency foldback circuit reduces the switching frequency during startup and
overcurrent fault conditions to help control the inductor current.
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V 0.8 V
OUT
R = R
HS LS 0.8 V
-
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ç ÷
è ø
TPS54062
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SLVSAV1B –MAY 2011–REVISED AUGUST 2012
DETAILED DESCRIPTION
Fixed Frequency PWM Control
The TPS54062 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the level set by the
COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output
current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a
maximum level.
Slope Compensation Output Current
The TPS54062 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-
harmonic oscillations.
Error Amplifier
The TPS54062 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the internal slow start voltage or the internal 0.8 V voltage reference. The
transconductance (gm) of the error amplifier is 102 µA/V during normal operation. During the slow start
operation, the transconductance is a fraction of the normal operating gm. The frequency compensation
components (capacitor, series resistor and capacitor) are added to the COMP pin to ground.
Voltage Reference
The voltage reference system produces a precise ±2 voltage reference over temperature by scaling the output of
a temperature stable band-gap circuit
Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Start with a 10kΩfor the RLS resistor and use the Equation 1 to
calculate RHS.
(1)
Enable and Adjusting Undervoltage Lockout
The TPS54062 is enabled when the VIN pin voltage rises above 4.53 V and the EN pin voltage exceeds the EN
rising threshold of 1.24 V. The EN pin has an internal pull-up current source, I1, of 1.2 µA that provides the
default enabled condition when the EN pin floats.
If an application requires a higher input undervoltage lockout (UVLO) threshold, use the circuit shown in
Figure 18 to adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.24 V,
an additional 3.5 µA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled below
1.14 V, the 3.5 µA Ihys current is removed. This additional current facilitates adjustable input voltage hysteresis.
Use Equation 2 to calculate RUVLO1 for the desired input start and stop voltages . Use Equation 3 to similarly
calculate RUVLO2.
In applications designed to start at relatively low input voltages (e.g., from 4.7 V to 10V) and withstand high input
voltages (e.g., from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute maximum
voltage of 8 V during the high input voltage condition. It is recommended to use a zener diode to clamp the pin
voltage below the absolute maximum rating.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
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T
SW
0.9967
116720
R (k ) = (kHz)f
W
ENAFALLING
START STOP
ENARISING
UVLO
ENAFALLING
HYS
ENARISING
V
V V
V
R 1 =
V
I1 × 1 + I
V
æ ö -
ç ÷
è ø
æ ö
-
ç ÷
è ø
TPS54062
i
VIN
R 1
UVLO
EN
Optional
VEN
ihys1
R 2
UVLO
TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
Figure 18. Adjustable Undervoltage Lock Out
(2)
(3)
Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54062 is adjustable over a wide range from approximately 100 kHz to 400
kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.53 V and must have a resistor
to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use
Equation 4. To reduce the solution size one would typically set the switching frequency as high as possible, but
tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be
considered. The minimum controllable on time is typically 130ns and limits the maximum operating input voltage.
The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of
the maximum switching frequency is located below.
(4)
Selecting the Switching Frequency
The TPS54062 implements current mode control which uses the COMP pin voltage to turn off the high side
MOSFET on a cycle-by-cycle basis. Each cycle the switch current and COMP pin voltage are compared, when
the peak switch current intersects the COMP voltage, the high side switch is turned off. During overcurrent
conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high,
increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current
limit.
To increase the maximum operating switching frequency at high input voltages the TPS54062 implements a
frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on
VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during
normal startup and fault conditions. Since the device can only divide the switching frequency by 8, there is a
maximum input voltage limit in which the device operates and still have frequency shift protection. During short-
circuit events (particularly with high input voltage applications), the control loop has a finite minimum controllable
on time and the output has a low voltage. During the switch on time, the inductor current ramps to the peak
current limit because of the high input voltage and minimum on time. During the switch off time, the inductor
would normally not have enough off time and output voltage for the inductor to ramp down by the ramp up
amount. The frequency shift effectively increases the off time allowing the current to ramp down.
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RT/CLK
TPS54062
Clock
Source
PLL
RT
RT/CLK
TPS54062
Hi-Z
Clock
Source
PLL
RT
OUTSC LS CL DC CL
SW
ON IN CL HS CL LS
V + R × I + R I
div
(shift) = ×
t V I R + I R
f
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´
ç ÷ ç ÷
- ´ ´
è ø è ø
OUT LS O DC O
SW
ON IN O HS O LS
V + R I + R I
1
(maxskip) = t V I R + I R
fæ ö æ ö
´ ´
´
ç ÷ ç ÷
- ´ ´
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TPS54062
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SLVSAV1B –MAY 2011–REVISED AUGUST 2012
(5)
(6)
Where:
IO= Output current
ICL = Current Limit
VIN = Input Voltage
VOUT = Output Voltage
VOUTSC Output Voltage during short
RDC = Inductor resistance
RHS = High side MOSFET resistance
RLS = Low side MOSFET resistance
ton = Controllable on time
fdiv = Frequency divide (equals 1, 2, 4, or 8)
How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through one of the circuit networks shown in
Figure 19. The square wave amplitude must transition lower than 0.5 V and higher than 1.3V on the RT/CLK pin
and have an on time greater than 40 ns and an off time greater than 40ns. The synchronization frequency range
is 300 kHz to 400 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal.
The external synchronization circuit should be designed in such a way that the device will have the default
frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is
recommended to use a frequency set resistor connected as shown in Figure 19 through another resistor (e.g.,
50Ω) to ground for clock signal that are not Hi-Z or 3-state during the off state. The sum of the resistance should
set the switching frequency close to the external CLK frequency. It is recommended to ac couple the
synchronization signal through a 10pF ceramic capacitor to RT/CLK pin. The first time the CLK is pulled above
the CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5 V voltage
source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal.
Since there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with
the external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or
decrease the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds. When
the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5V voltage and the resistor will then set the switching frequency. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The
device implements a digital frequency shift to enable synchronizing to an external clock during normal startup
and fault conditions.
Figure 19. Synchronizing to a System Clock
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+
TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
Overvoltage Transient Protection
The TPS54062 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients on power supply designs with low value
output capacitance. For example, when the power supply output is overloaded the error amplifier compares the
actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal
reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error
amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed,
the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In some
applications, the power supply output voltage can respond faster than the error amplifier output can respond, this
actuality leads to the possibility of an output overshoot.
The OVTP feature minimizes the output overshoot, when using a low value output capacitor, by implementing a
circuit to compare the VSENSE pin voltage to OVTP threshold which is 109% of the internal voltage reference. If
the VSENSE pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing
current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than
the OVTP threshold, the high side MOSFET is allowed to turn on at the next clock cycle.
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 146°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 146°C, the device reinitiates the power up sequence
by restarting the internal slow start.
DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE No.1
Figure 20. Application Schematic
This example details the design of a continuous conduction mode (CCM) switching regulator design using
ceramic output capacitors. If a low output current design is needed go to the design procedure Number 2. A few
parameters must be known in order to start the design process. These parameters are typically determined at the
system level. For this example, we will start with the following known parameters:
Output Voltage 3.3V
Transient Response 0 to 50mA load step ΔVOUT = 4%
Maximum Output Current 50mA
Input Voltage 24 V nom. 8V to 60V
Output Voltage Ripple 0.5% of VOUT
Start Input Voltage (rising VIN) 7.88V
Stop Input Voltage (falling VIN) 6.66V
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RIPPLE
L OUT
I
I peak = I + 2
( ) 2
OUT IN OUT
2
L O
IN O SW
V V max V
1
I rms = I +
12 V max L f
æ ö
´ -
´ç ÷
ç ÷
´ ´
è ø
( )
OUT IN OUT
RIPPLE
IN O SW
V V max V
I
V max L f
´ -
³´ ´
IN OUT OUT
O
O IN SW
V max V V
L min
Kind I V max f
æ ö
-
³ ´
ç ÷
´ ´
è ø
TPS54062
www.ti.com
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the
highest switching frequency possible since this will produce the smallest solution size. The high switching
frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of
the internal power switch, the input voltage and the output voltage and the frequency shift limitation.
Equation 5 and Equation 6 must be used to find the maximum switching frequency for the regulator, choose the
lower value of the two equations. Switching frequencies higher than these values will result in pulse skipping or
the lack of overcurrent protection during a short circuit. The typical minimum on time, tonmin, is 130ns for the
TPS54062. For this example, the output voltage is 3.3V and the maximum input voltage is 60 V, which allows for
a maximum switch frequency up to 400 kHz when including the inductor resistance, on resistance and diode
voltage in Equation 5 or Equation 6. To ensure overcurrent runaway is not a concern during short circuits in your
design use Equation 6 to determine the maximum switching frequency. With a maximum input voltage of 60V,
inductor resistance of 3.7 Ω, high side switch resistance of 2.3 Ω, low side switch resistance of 1.1Ω, a current
limit value of 120 mA and a short circuit output voltage of 0.1 V.
The maximum switching frequency is 400 kHz in both cases and a switching frequency of 400 kHz is used. To
determine the timing resistance for a given switching frequency, use Equation 4. The switching frequency is set
by resistor R3 shown in Figure 20. R3 is calculated to be 298 kΩ. A standard value of 301 kΩis used.
Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 7. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be
filtered by the output capacitor. Therefore, choosing high inductor ripple currents will impact the selection of the
output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor
ripple current. In general, the inductor ripple value is at the discretion of the designer; however, the following
guidelines may be used. Typically it is recommended to use KIND values in the range of 0.2 to 0.4; however, for
designs using low ESR output capacitors such as ceramics and low output currents, a value as high as KIND = 1
may be used. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side.
This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this
design example, use KIND = 0.8 and the minimum inductor value is calculated to be 195 µH. For this design, a
near standard value was chosen: 220 µH. For the output filter inductor, it is important that the RMS current and
saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 9
and Equation 10.
For this design, the RMS inductor current is 50 mA and the peak inductor current is 68 mA. The chosen inductor
is a Coilcraft LPS4018-224ML. It has a saturation current rating of 235 mA and an RMS current rating of 200 mA.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value. The current flowing through the inductor is the inductor
ripple current plus the output current. During power up, faults or transient load conditions, the inductor current
can increase above the calculated peak inductor current level calculated above. In transient conditions, the
inductor current can increase up to the switch current limit of the device. For this reason, the most conservative
approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit
rather than the peak inductor current.
(7)
(8)
(9)
(10)
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RIPPLE
O
RIPPLE SW
I1
C 1
V 8 f
æ ö
³ ´ ç ÷
´
è ø
( )
OUT IN OUT
O
IN O SW
V V max V
1
IC rms =
V max L
12 f
æ ö
´ -
´ç ÷
ç ÷
´ ´
è ø
TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor will
determine the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator also will temporarily not be able to
supply sufficient output current if there is a large, fast increase in the current needs of the load such as
transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop
to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only
allowing a tolerable amount of droop in the output voltage. Equation 14 shows the minimum output capacitance
necessary to accomplish this. Where ΔIout is the change in output current, ƒsw is the regulators switching
frequency and ΔVout is the allowable change in the output voltage.
For this example, the transient load response is specified as a 4% change in Vout for a load step from 0A (no
load) to 50 mA (full load). For this example, ΔIOUT = 0.05-0 = 0.05 and ΔVOUT = 0.04 × 3.3 = 0.132.
Using these numbers gives a minimum capacitance of 1.89 µF. This value does not take the ESR of the output
capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to
ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken
into account. The low side FET of the regulator emulates a diode so it can not sink current so any stored energy
in the inductor will produce an output voltage overshoot when the load current rapidly decreases, see Figure 26.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high
load current to a lower load current. The excess energy that gets stored in the output capacitor will increase the
voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these
transient periods. Equation 13 is used to calculate the minimum capacitance to keep the output voltage
overshoot to a desired value. Where L is the value of the inductor, IOH is the output current under heavy load, IOL
is the output under light load, VF is the final peak output voltage, and Vi is the initial capacitor voltage. For this
example, the worst case load step will be from 50 mA to 0A. The output voltage will increase during this load
transition and the stated maximum in our specification is 4% of the output voltage. This will make VF = 1.04 × 3.3
= 3.432 V. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in
Equation 14 yields a minimum capacitance of 0.619 µF.
Equation 12 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fSW is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. Equation 13 yields 0.671 µF. Equation 15 calculates the maximum ESR an output
capacitor can have to meet the output voltage ripple specification. Equation 15 indicates the ESR should be less
than 0.466Ω.
The most stringent criteria for the output capacitor is 1.89 µF of capacitance to keep the output voltage in
regulation during an load transient.
Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase
this minimum value. For this example, 10 µF, 10V X5R ceramic capacitor with 0.003 Ωof ESR will be used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the Root Mean Square (RMS) value of the maximum ripple current.
Equation 11 can be used to calculate the RMS ripple current the output capacitor needs to support. For this
application, Equation 11 yields 10.23 mA.
(11)
(12)
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O
IN
IN SW
I0.25
CV ripple f
æ ö
³ ´ ç ÷
è ø
( )
IN OUT
OUT
IN OUT
IN IN
V min V
V
IC rms = I
V min V Min
-
´ ´
RIPPLE
C
RIPPLE
V
R
I
£
O
O
SW
I2
C 3
Vf
³
D
( )
( )
2 2
O
O O 22
O O
I 0
C 2 L
V + V V
-
³ ´
D -
TPS54062
www.ti.com
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
(13)
(14)
(15)
Input capacitor
The TPS54062 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 1µF of
effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a rms current rating greater than the maximum rms input current of the TPS54062. The
input rms current can be calculated using Equation 16. The value of a ceramic capacitor varies significantly over
temperature and the amount of dc bias applied to the capacitor. The capacitance variations due to temperature
can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic
dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume
ratio and are fairly stable over temperature. The output capacitor must also be selected with the dc bias taken
into account. The capacitance value of a capacitor decreases as the dc bias across a capacitor increases. For
this example design, a ceramic capacitor with at least a 100 V voltage rating is required to support the maximum
input voltage. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using rearranging Equation 17.
Using the design example values, Ioutmax = 50 mA, CIN = 2.2 µF, ƒSW = 400 kHz, yields an input voltage ripple
of 14.2 mV and a rms input ripple current of 24.6 mA.
(16)
(17)
Bootstrap Capacitor Selection
A 0.01-µF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10V
or higher voltage rating.
Under Voltage Lock Out Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54062. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 7.88 V (enabled). After the regulator starts switching, it should
continue to do so until the input voltage falls below 6.66 V (UVLO stop). The programmable UVLO and enable
voltages are set using a resistor divider between Vin and ground to the EN pin. Equation 2 through Equation 3
can be used to calculate the resistance values necessary. For the example application, a 174 kΩresistor
between Vin and EN and a 31.6 kΩresistor between EN and ground are required to produce the 7.88 and 6.66
volt start and stop voltages.
Output Voltage and Feedback Resistors Selection
For the example design, 10 kΩwas selected for RLS. Using Equation 1, RHS is calculated as 31.25 kΩ. The
nearest standard 1% resistor is 31.6 kΩ.
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SW
1
C6 =
R4 f´ ´ p
C O
R C
C6 =
R4
´
POLE
1
C5 =
2 R4 f´ ´ ´p
CO O O
REF
2 C V
R4 = gmps V gmea
f´ ´ ´
´
´
p
f
f f
æ ö
´
ç ÷
è ø
0.5
sw
co2(Hz) = pole
2
( )
f f f´0. 5
co1(Hz) = zero pole
C O
1
zero(Hz) = R C 2
f
p´ ´ ´
OO
O
1
pole(Hz) = VC 2
I
f
p´ ´ ´
TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
Closing the Loop
There are several methods used to compensate DC/DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency
used in the calculations. This method assume the crossover frequency is between the modulator pole and the
ESR zero and the ESR zero is at least 10 times greater the modulator pole. Use SwitcherPro™ software for a
more accurate design.
To get started, the modulator pole, fpole, and the ESR zero, fzero must be calculated using Equation 18 and
Equation 19. For Cout, use a derated value of 8.9 µF. Use Equation 21 and Equation 22, to estimate a starting
point for the crossover frequency, fco, to design the compensation. For the example design, fpole is 271 Hz and
fzero is 5960 kHz.
Equation 21 is the geometric mean of the modulator pole and the esr zero and Equation 22 is the mean of
modulator pole and the switching frequency. Equation 21 yields 40.29 kHz and Equation 22 gives 7.36 kHz. Use
a frequency near the lower value of Equation 21 or Equation 22 for an initial crossover frequency.
For this example, fco is 7.8 kHz. Next, the compensation components are calculated. A resistor in series with a
capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the
compensating pole.
To determine the compensation resistor, R4, use Equation 22. Assume the power stage transconductance,
gmps, is 0.65 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are
3.3 V, 0.8 V and 102 µA/V, respectively.
R4 is calculated to be 27.1 kΩ, use the nearest standard value of 27.4 kΩ. Use Equation 23 to set the
compensation zero to the modulator pole frequency. Equation 23 yields 0.021.4 µF for compensating capacitor
C5, a 0.022 µF is used on the board. Use the larger value of Equation 24 and Equation 25 to calculate the C6
value, to set the compensation pole. Equation 25yields 29 pF so the nearest standard of 27 pF is used.
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
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Product Folder Link(s): TPS54062
−0.20
−0.15
−0.10
−0.05
0.00
0.05
0.10
0.15
0.20
0 0.01 0.02 0.03 0.04 0.05
Output Current (A)
Output Voltage Normalized (%)
VIN = 24V
G033
−0.10
−0.08
−0.06
−0.04
−0.02
0.00
0.02
0.04
0.06
0.08
0.10
8 12 16 20 24 28 32 36 40 44 48 52 56 60
Input Voltage (V)
Output Voltage Normalized (%)
IOUT = 25mA
G035
10 100 1000 10000 100000 1000000
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
−180
−150
−120
−90
−60
−30
0
30
60
90
120
150
180
Frequency (Hz)
Gain (dB)
Phase (°)
Gain
Phase
G031
0
10
20
30
40
50
60
70
80
90
100
0 0.01 0.02 0.03 0.04 0.05
Output Current (A)
Efficiency (%)
VIN = 10V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 60V
VOUT = 3.3V
fSW = 400kHz
G040
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1
Output Current (A)
Efficiency (%)
VIN = 10V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 60V
VOUT = 3.3V
fSW = 400kHz
G041
TPS54062
www.ti.com
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
Characteristics
SPACER
Figure 21. Efficiency vs Output Current Figure 22. Efficiency vs Output Current
Figure 23. Gain vs Phase Figure 24. Output Voltage vs Input Voltage
Figure 25. Output Voltage vs Output Current
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V = 10 mV / div (ac coupled)
IN
PH = 20 V / div
Time = 2 µsec / div
Inductor Current = 100 mA / div
V = 10 mV / div (ac coupled)
IN
PH = 20 V / div
Time = 2 µsec / div
Inductor Current = 100 mA / div
V = 10 V / div
IN
EN = 2 V / div
Time = 2 msec / div
V = 2 V / div
OUT
V = 10 V / div
IN
EN = 2 V / div
Time = 2 msec / div
V = 2 V / div
OUT
I = 20 mA / div
OUT
Time = 1 msec / div
V = 50 mV / div (ac coupled)
OUT
V = 100 mV / div (ac coupled)
OUT
V = 10 V / div
IN
Time = 20 msec / div
TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
Figure 26. Load Transient Figure 27. Line Transient
Figure 28. Startup with ENA Figure 29. Startup with VIN
Figure 30. Input Ripple in DCM Figure 31. Input Ripple in CCM
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V = 10 mV / div (ac coupled)
OUT
PH = 20 V / div
Time = 2 µsec / div
Inductor Current = 100 mA / div
V = 10 mV / div (ac coupled)
OUT
PH = 20 V / div
Time = 50 µsec / div
Inductor Current = 100 mA / div
V = 10 mV / div (ac coupled)
IN
PH = 20 V / div
Time = 50 µsec / div
Inductor Current = 100 mA / div
V = 10 mV / div (ac coupled)
OUT
PH = 20 V / div
Time = 2 µsec / div
Inductor Current = 100 mA / div
TPS54062
www.ti.com
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
Figure 32. Input Ripple Skip Figure 33. Output Ripple in DCM
Figure 34. Output Ripple in CCM Figure 35. Output Ripple Skip
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TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
DESIGN GUIDE – STEP-BY-STEP PROCEDURE Number 2
Figure 36. DCM Application Schematic
For Designing an Efficient, Low Output Current Power Supply at a Fixed Switching Frequency
This example details the design of a low output current, fixed switching regulator design using ceramic output
capacitors. A few parameters must be known in order to start the design process. These parameters are typically
determined at the system level. For this example, we will start with the following known parameters:
Output Voltage 3.3 V
Transient Response 0 to 15 mA load step ΔVOUT = 4%
Maximum Output Current 10 mA
Minimum Output Current 3 mA
Input Voltage 24 V nom. 10 V to 40 V
Output Voltage Ripple 0.5% of VOUT
Switching Frequency 100 kHz
Start Input Voltage (rising VIN) 9 V
Stop Input Voltage (falling VIN) 8 V
It is most desirable to have a power supply that is efficient and has a fixed switching frequency at low output
currents. A fixed frequency power supply will have a predictable output voltage ripple and noise. Using a
traditional continuous conduction mode (CCM) design method to calculate the output inductor will yield a large
inductance for a low output current supply. Using a CCM inductor will result in a large sized supply or will affect
efficiency from the large dc resistance an alternative is to operate in discontinuous conduction mode (DCM). Use
the procedure below to calculate the components values for designing a power supply operating in discontinuous
conduction mode. The advantage of operating a power supply in DCM for low output current is the fixed
switching frequency, lower output inductance, and lower dc resistance on the inductor. Use the frequency shift
and skip equations to estimate the maximum switching frequency.
The TPS54062 is designed for applications which require a fixed operating frequency and low output voltage
ripple at low output currents, thus, the TPS54062 does not have a pulse skip mode at light loads. Since the
device has a minimum controllable on time, there is an output current at which the power supply will pulse skip.
To ensure that the supply does not pulse skip at output current of the application the inductor value will be need
to be selected greater than a minimum value. The minimum inductance needed to maintain a fixed switching
frequency at the minimum load is calculated to be 0.9mH using Equation 26. Since the equation is ideal and was
derived without losses, assume the minimum controllable light load on time, tonminll, is 350ns. To maintain DCM
operation the inductor value and output current need to stay below a maximum value. The maximum inductance
is calculated to be 1.42mH using Equation 27. A 744062102 inductor from Wurth Elektronik is selected. If CCM
operation is necessary, use the previous design procedure.
22 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS54062
O
IN
IN SW
I0.25
C
V RIPPLE f
æ ö
³ ´ ç ÷
è ø
0.5
2
CIN L
D1 D1
I rms = I peak 3 4
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RIPPLE
C
L
V
RI peak
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O
CO
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Vf
³
D
( )
( )
2 2
O O 22
O
O
Io 0
C 2 L
V + V V
-
³ ´
D -
L
O
RIPPLE SW
I peak D1 + D2
C 1 V 8 f
æ ö
£ ´ ç ÷
´
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0.5
2
CO L
D1 + D2 D1 + D2
I rms = I peak 3 4
æ ö
æ ö æ ö
ç ÷
´ -
ç ÷ ç ÷
ç ÷
è ø è ø
è ø
0.5
L L
D1 + D2
I rms = I peak 3
æ ö
´ç ÷
è ø
S O
O
V V
D2 = D1
V
æ ö
-´
ç ÷
è ø
( )
0.5
O O O SW
S S O
2 V I L
D1 =
V V V
f
æ ö
´ ´ ´ ´
ç ÷
ç ÷
´ -
è ø
( ) 0.5
O O S O
L
S O SW
2 V I max V max V
I peak = V max L f
æ ö
´ ´ ´ -
ç ÷
ç ÷
´ ´
è ø
S O O
O
S SW O
V min V V 1
L max
2 V min If
æ ö
-
æ ö
£ ´ ´
ç ÷
ç ÷ ´
è ø è ø
2
S O S O
O SW
O O
V max V V max t nmin
L min
V 2 I min x f
æ ö
-æ ö
³ ´ ´
ç ÷ ç ÷
è ø
è ø
TPS54062
www.ti.com
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
Use Equation 28, to make sure the minimum current limit on the high side power switch is not exceeded at the
maximum output current. The peak current is calculated as 23.9mA and is lower than the 134 mA current limit.
To determine the rms current for the inductor and output capacitor, it is necessary to calculate the duty cycle.
The duty cycle, D1, for a step down regulator in DCM is calculated in Equation 29. D1 is the portion of the
switching cycle the high side power switch is on, and is calculated to be 0.1153. D2 is the portion of the switching
cycle the low side power switch is on, and is calculated to be 0.7253.
Using the Equation 31 and Equation 32, the rms current of the inductor and output capacitor are calculated, to be
12.8mA and 7.6mA respectively. Select components that ratings exceed the calculated rms values. Calculate the
output capacitance using the Equation 33 to Equation 35 and use the largest value, Vripple is the steady state
voltage ripple and deltaV is voltage change during a transient. A minimum of 1.5 µF capacitance is calculated.
Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which increases this
minimum value. For this example, a 22 µF 6.3 V X7R ceramic capacitor with 5mΩESR is used. To have a low
output ripple power supply use a low esr capacitor. Use Equation 36 to estimate the maximum esr for the output
capacitor. Equation 37 and Equation 38 estimate the rms current and capacitance for the input capacitor. An rms
current of 3.7 mA and capacitance of 0.2 µF is calculated. A 1 µF 100V/X7R ceramic is used for this example.
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TPS54062
POLE2
COMP SW
1
C =
Rfp´ ´
C O
POLE1
COMP
R C
C =
R
´
COMP
COMP
1
C =
2 R Kdcm Fmp´ ´ ´ ´
V
CO O
COMP V
REF
POLE gmea
R = Kdcm Fm x
fx
x x f
( )0.5
CO2 SW POLE
(Hz) =f f f´
( )0.5
CO1 ZERO POLE
(Hz) =f f f´
ZERO
C O
1
(Hz) = R C 2
f
p´ ´ ´
O
S
POLE
O O
O
O S
V
2V
1
(Hz) = V V
C 2 1
I V
f
p
æ ö
-
ç ÷
ç ÷
´ç ÷
´ ´ ´ -
ç ÷
è ø
S O
O SW
gmps
Fm = V V + 0.277
Lf
æ ö
-
ç ÷
´
è ø
( )
O S O
S O
O
O
V V V
2
Kdcm =
D1
Rdc
V 2 + V
V
I
´ -
´æ ö
ç ÷
ç ÷
´ -
ç ÷
ç ÷
è ø
ZERO
POLE
s
1 + 2
Gdcm(s) Fm Kdcm s
1 + 2
f
f
p
p
´ ´
» ´ ´
´ ´
TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
Closing the Feedback Loop
The method presented here is easy to calculate and includes the effect of the slope compensation that is internal
to the device. This method assumes the crossover frequency is between the modulator pole and the esr zero
and the esr zero is at least 10 times greater the modulator pole. Once the output components are determined,
use the equations below to close the feedback loop. A current mode controlled power supply operating in DCM
has a transfer function which has an esr zero and pole as shown in Equation 39. To calculate the current mode
power stage gain, first calculate, Kdcm, DCM gain, and Fm, modulator gain, in Equation 40 and Equation 41.
Kdcm and Fm are 26.3 and 1.34 respectively. The location of the pole and esr zero are calculated using
Equation 42 and Equation 43 . The pole and zero are 67 Hz and 2 MHz, respectively. Use the lower value of
Equation 44 and Equation 45 as a starting point for the crossover frequency. Equation 44 is the geometric mean
of the power stage pole and the esr zero and Equation 45 is the mean of power stage pole and the switching
frequency. The crossover frequency is chosen as 2.5 kHz from Equation 45.
To determine the compensation resistor, RCOMP, use Equation 46. Assume the power stage transconductance,
gmps, is 0.65 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are
3.3 V, 0.8 V and 102 µA/V, respectively. RCOMP is calculated to be 32.7 kΩ, use the nearest standard value of
32.4 kΩ. Use Equation 47 to set the compensation zero to the modulator pole frequency. Equation 47 yields 139
nF for compensating capacitor CCOMP, a 330 nF is used on the board. Use the larger value of Equation 48 or
Equation 49 to calculate the CPOLE, to set the compensation pole. Equation 49 yields 98 pF so the nearest
standard of 100 pF is used.
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
24 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS54062
−0.25
−0.20
−0.15
−0.10
−0.05
0.00
0.05
0.10
0.15
0.20
0.25
0 10 20 30 40 50
Input Voltage (V)
Output Voltage Normalized (%)
IOUT = 7.5mA
G023
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0 0.01 0.02 0.03 0.04 0.05
Output Current (A)
Output Voltage Normalized (%)
VIN = 24V
VOUT = 3.3V
G022
10 100 1000 10000 100000
−40
−30
−20
−10
0
10
20
30
40
−180
−135
−90
−45
0
45
90
135
180
Frequency (Hz)
Gain (dB)
Phase (°)
Gain
Phase
VIN = 24V
IOUT = 5ma
G018
0
10
20
30
40
50
60
70
80
90
100
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
Output Current (A)
Efficiency (%)
VIN = 10V
VIN = 24V
VIN = 40V
VOUT =3.3V
G020
0
10
20
30
40
50
60
70
80
90
100
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
Output Current (A)
Efficiency (%)
VIN = 10V
VIN = 24V
VIN = 40
VOUT = 5V
G021
TPS54062
www.ti.com
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
Characteristics
SPACER
Figure 37. Efficiency vs Output Current Figure 38. Efficiency vs Output Current
Figure 39. Gain vs Phase Figure 40. Output Voltage vs Output Current
Figure 41. Output Voltage vs Input Voltage Figure 42. Load Transient
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS54062
TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
Figure 43. Unload Transient Figure 44. Startup With ENA
Figure 45. Startup With VIN Figure 46. Prebias Startup With ENA
Figure 47. Prebias Startup With VIN Figure 48. Input and Output Ripple in DCM
26 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS54062
VSENSE
COMP
GND
PH
BOOT
VIN
EN
RT/CLK
Frequency Set
Resistor
Boot
Capacitor
Input
Capacitor
Output
Capacitor
VOUT
Output
Inductor
Compensation
Network
Feedback
Resistors
UVLO
Adjust
Resistor
VIN
GND
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Signal VIA
TPS54062
www.ti.com
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
Figure 49. Input and Output Ripple in CCM
Layout
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed
to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the GND pin. See
Figure 50 for a PCB layout example. Since the PH connection is the switching node and output inductor should
be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive
coupling. The RT/CLK pin is sensitive to noise. so the RT resistor should be located as close as possible to the
IC and routed with minimal lengths of trace. The additional external components can be placed approximately as
shown. It may be possible to obtain acceptable performance with alternate PCB layouts; however; this layout has
been shown to produce good results and is meant as a guideline.
Figure 50. PCB Layout Example
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPS54062
TPS54062
SLVSAV1B –MAY 2011–REVISED AUGUST 2012
www.ti.com
REVISION HISTORY
Changes from Original (May 2011) to Revision A Page
• Changed Features Item From: MSOP8 and WSON8 Packages To: MSOP-8 and 3 mm x 3 mm VSON-8 Packages ....... 1
• Changed the Efficiency Graph .............................................................................................................................................. 1
• Added the ORDERING INFORMATION table ...................................................................................................................... 2
• Added the VSON (DRB-8 Pin) Package ............................................................................................................................... 2
• Added Thermal Pad information to the Pin Functions table ................................................................................................. 2
• Changed the RT/CLK pin Description ................................................................................................................................... 2
• Added VSON-8 Pins values to the Thermal Information table ............................................................................................. 4
• Changed the PLL lock in time Unit of Measure From: µA To: µs ......................................................................................... 5
• Changed Equation 22 ......................................................................................................................................................... 18
• Changed the Efficiency vs Output Current Graphs, Figure 21 and Figure 22 .................................................................... 19
Changes from Revision A (October 2011) to Revision B Page
• Added features Item: Diode Emulation for Improved Light Load Efficiency ......................................................................... 1
• Changed Features Item From: 100 kHz to 400 kHz Switching Frequency To: 100 kHz to 400 kHz Adjustable
Switching Frequency ............................................................................................................................................................. 1
• Changed the Efficiency Graph .............................................................................................................................................. 1
• Changed VSON-8 package graphic to clarify ThermalPAD area ......................................................................................... 2
• Changed the EN pin MAX value From: 5 V To: 8 V ............................................................................................................. 4
• Changed the Enable and Adjusting Undervoltage Lockout section ................................................................................... 11
• Changed Equation 22 through Equation 25 ....................................................................................................................... 18
28 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS54062
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS54062DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54062DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54062DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS54062DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS54062DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS54062DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54062DGKR VSSOP DGK 8 2500 370.0 355.0 55.0
TPS54062DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS54062DRBT SON DRB 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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