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Application Note 1919
ISL8115DEMO1Z Synchronous Buck Converter User
Guide
Introduction
The ISL8115DEMO1Z is a compact reference design
Synchronous Buck Converter (28.19mmx16.89mm)
implementing Intersil’s wide input range PWM controller
ISL8115. Utilizing voltage mode control with input
feed-forward, the ISL8115DEMO1Z maintains a constant loop
gain for optimal transient response, especially for applications
with a wide input voltage range. For a more detailed
description of the ISL8115 functionality, refer to the ISL8115
datasheet.
This user guide includes the test setup, typical performance
waveforms, schematic, layout and bill of materials (BOM).
Specifications
Key Features
•Small, compact design
• Fast transient response
- Voltage-mode PWM leading-edge modulation with
nonlinear control
-Input voltage feed-forward
• Integrated 5V high speed 4A MOSFET gate drivers
- Internal bootstrap diode
• Oscillator programmable from 150kHz to 1.5MHz
- Frequency synchronization to external clock signal
• Diode emulation mode for light load efficiency improvement
• Output OVP/UVP; OCP and OTP
•Adjustable soft-start
• Prebias start-up function
• Excellent output voltage regulation
- 0.6V ±1.0% internal reference (-40°C~+125°C)
- 0.6V ±0.7% internal reference (-40°C~+105°C)
- Differential voltage sensing
References
•ISL8115 datasheet
Recommended Equipment
• Input power source up to 36V supply voltage with 125W
power supply ability
• Electronic load with 100W power sinking ability
• Voltmeters and ammeters
• 100MHz quad-trace oscilloscope
TABLE 1. DEMONSTRATION BOARD ELECTRICAL SPECIFICATIONS
SPEC DESCRIPTION MIN TYP MAX UNIT
VIN Input voltage range 16 24 36 V
VOUT Output voltage 5 V
IOUT Output rated current 10 A
IOC Overcurrent threshold 13 A
fsw Switching frequency 600 kHz
Input UVP Rising threshold 15 V
Falling threshold 14.2 V
ηEfficiency at 24V input full
load (10A)
90.12 %
FIGURE 1. ISL8115DEMO1Z DEMONSTRATION BOARD
Ordering Information
PART NUMBER DESCRIPTION
ISL8115DEMO1Z Demonstration Board for ISL8115
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2014, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
March 11, 2015
AN1919.2
Application Note 1919
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Quick Test Setup
1. Ensure that the demonstration board is correctly connected to
the power supply and the electronic load prior to applying any
power. Refer to Figure 2 for proper setup.
2. Set the input voltage to 24V, turn on the power supply and
observe output voltage. The output voltage variation should
be within 5%.
3. Adjust load current within 10A. The output voltage variation
should be within 5%.
4. Use oscilloscope to observe output ripple voltage and phase
node ringing. For accurate measurement, refer to Figure 3 for
proper setup.
Probe Setup
Design Guide
The ISL8115DEMO1Z is optimized for 16V to 36V input voltage
range. However, the evaluation board can be modified to support
multiple applications due to the customer’s requirements. Refer
to the ISL8115 datasheet for detailed information.
Quick modify to 12V input application, Table 2 can be followed.
Some other modifications need to be made at the same time if
best performance is expected.
Output Voltage Adjustment
The output voltage can be set by the resistors R4 and R1. In order
to keep the existing compensation parameters unchanged,
adjust R4 to set the output voltage by the following Equation 1:
The VMON monitors the output for UVP and OVP, the resistor
divider value of R11/R8 should be the same with the R1/R4.
Synchronization
The ISL8115DEMOZ board can be synchronized with an external
clock. Applying a clock signal (10% to 90% duty cycle) in the
range of 150kHz to 1.5MHz to the FSET pin makes the internal
frequency synchronized with the external clock. Please remove
R27 when the synchronized function is implemented.
FIGURE 2. ISL8115DEMO1Z TEST SETUP
FIGURE 3. OSCILLOSCOPE PROBE SETUP
TABLE 2. 12V APPLICATION
VIN R35
12V 71.5k
(EQ. 1)
R4
0.6V R1
VOUT 0.6V–
----------------------------------
=
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Typical Performance Curves Unless otherwise specified, the input voltage is 28V.
FIGURE 4. EFFICIENCY vs LOAD CURRENT AT CCM MODE FIGURE 5. EFFICIENCY vs LOAD CURRENT AT DEM MODE
FIGURE 6. VOUT LOAD REGULATION AT CCM MODE FIGURE 7. VOUT LOAD REGULATION AT DEM MODE
FIGURE 8. LINE REGULATION AT NO LOAD CCM MODE FIGURE 9. LINE REGULATION AT NO LOAD DEM MODE
65
70
75
80
85
90
95
1 2 3 4 5 6 7 8 9 10
EFFICIENCY (%)
OUTPUT CURRENT (A)
75 VIN = 24V
VIN = 36V
VIN = 16V
5
15
25
35
45
55
65
75
85
95
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
EFFICIENCY (%)
OUTPUT CURRENT (A)
VIN = 36V
VIN = 16V
VIN = 24V
123456789
10
0
5.0330
5.0335
5.0340
5.0345
5.0350
5.0355
5.0360
5.0365
5.0370
LOAD CURRENT (A)
VOUT (V)
VIN = 24V
0 123 45678910
VIN = 24V
LOAD CURRENT (A)
VOUT (V)
5.0330
5.0340
5.0350
5.0360
5.0370
5.0380
5.0390
5.033
5.034
5.034
5.035
5.035
5.036
5.036
5.037
5.037
5.038
5.038
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
NO LOAD
VIN (V)
VOUT (V)
5.030
5.032
5.033
5.034
5.035
5.036
5.037
5.038
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
5.031
NO LOAD
VIN (V)
VOUT (V)
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FIGURE 10. LINE REGULATION AT FULL LOAD CCM MODE FIGURE 11. LINE REGULATION AT FULL LOAD DEM MODE
FIGURE 12. OUTPUT VOLTAGE RIPPLE AT 10A LOAD CONDITION
FIGURE 13. LOAD TRANSIENT 0A TO 5A; 2A/µs AT CCM FIGURE 14. LOAD TRANSIENT 5A TO 10A; 2A/µs AT CCM
Typical Performance Curves Unless otherwise specified, the input voltage is 28V. (Continued)
5.031
5.032
5.033
5.034
5.035
5.036
5.037
5.038
16 18 20 22 24 26 28 30 32 34 36
FULL LOAD 10A
VIN (V)
VOUT (V)
5.029
5.030
5.031
5.032
5.033
5.034
5.035
5.036
5.037
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VIN (V)
VOUT (V)
FULL LOAD 10A
OUTPUT LOAD 5A/DIV
10µs/DIV
VOUT 20mV/DIV
OUTPUT LOAD 5A/DIV
V
OUT
100mV/DIV
100µs/DIV
100mV/DIV
VOUT
OUTPUT LOAD
100µs/DIV
5A/DIV
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FIGURE 15. START-UP AT 0A LOAD CONDITION FIGURE 16. START-UP AT 10A LOAD CONDITION
FIGURE 17. SHUTDOWN AT 0A LOAD CONDITION FIGURE 18. SHUTDOWN AT 10A LOAD CONDITION
FIGURE 19. OVERCURRENT PROTECTION AT 12.6A LOAD FIGURE 20. SHORT PROTECTION
Typical Performance Curves Unless otherwise specified, the input voltage is 28V. (Continued)
2msDIV
5A/DIV
OUTPUT LOAD
VOUT 2V/DIV
2V/DIV
VOUT
2ms/DIV
OUTPUT LOAD 5A/DIV
OUTPUT LOAD 5A/DIV
2V/DIV
100µs/DIV
VOUT
VOUT
OUTPUT LOAD
500µs/DIV
5A/DIV
2V/DIV
V
OUT
500mV/DIV
5A/DIV
OUTPUT LOAD
OUTPUT LOAD
20V/DIV
PH
5ms/DIV
5ms/DIV
VOUT 1V/DIV
5A/DIV
OUTPUT LOAD
PH 50V/DIV
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Schematic
FIGURE 21. ISL8115DEMO1Z SCHEMATIC
C24
100uF
C26
100uF
C23
100uF
C11
1uF
C25
100uF
C15
1uF
VOUT
U1
ISL8115
ISET
19
ISHARE
20
RGND
16
RAMP
5
PL L_ CO MP
21
VIN
7
CONF
22
SS
24
CLKOUT
23
FB
17
VCC
3
EN
2
ISENB
14
VMON 15
FSET
1
PGOOD
4
VFF
6
UGATE
9
PHASE
10
PV CC
11
LG AT E
12
ISEN A
13
BOOT
8
COMP 18
GND
25
R14
2
C21
2. 2 u F
R20
30 K
C16 0.22uF
C20
4.7uF
R36
46. 4K
C22
2. 2u F
R27
40. 2K
R26
18.2K
R23
73 2
R4 2K
C19
390pF
R21
5. 1 1 K
C14
2.2nF
C4
470p
C17
47nF
R8
2K
TP 1
VIN
1
R29
10k
TP 2
GND
1
R34
2.2
PVCC
R39
10k
TP3
VOUT
1
TP4
GND
1
R9
0
C36
DNP
R35
113k
R40
10 k
R12
2k
Upper MOS: BSC039N06NS
Lower MOS: BSC039N06NS
Q2
3
1
2
4
5
Q4
3
1
2
4
5
5V/10A
C1
2.2nF
R28
9.1k
L1
2.4uH 21
744325240
2.4uH 14A 4.8mohm
R17
4.22k
R1
14.7k
R11
14.7k
R3
13 3
C3
1. 8n
R2
16 . 5 k
C2
33 p
Av erag e OCP: 12. 8A
Peak current limit: 13A
PVCC
DEMO1Z
Input: 16V - 3 6V Output: 5V/ 10A
Frequency: 600KHz
in put ri sing s hr esho ld: 15 V
in put fa llin g sh resh old: 1 4. 2V
C30
10uF
C29
10uF
R22
0
C35
10 0u F
16 - 36V
Application Note 1919
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Bill of Materials
ITEM QTY REFERENCE VALUE DESCRIPTION MANUFACTURER PART NUMBER
1 2 C1, C14 2.2nF CAP CER 2200pF 25V 10% X7R 0402 Generic Generic
2 1 C2 33pF CAP CER 33pF 50V 5% NP0 0402 Generic Generic
3 1 C3 1.8nF CAP CER 1800pF 50V 10% X7R 0402 Generic Generic
4 1 C4 470pF CAP CER 470pF 50V 10% X7R 0402 Generic Generic
5 2 C11, C15 1µF CAP CER 1µF 10V 10% X5R 0603 Generic Generic
7 1 C16 0.22µF CAP CER 0.22µF 16V 10% X7R 0402 Generic Generic
8 1 C17 47nF CAP CER 0.047µF 25V 10% X7R 0402 Generic Generic
9 1 C19 390pF CAP CER 390pF 50V 10% X7R 0402 Generic Generic
10 1 C20 4.7µF CAP CER 4.7µF 6.3V 10% X5R 0805 Generic Generic
11 1 C21 2.2µF CAP CER 2.2µF 50V 10% X7R 1210 TDK C3225X7R1H225K
12 1 C22 2.2µF CAP CER 2.2µF 6.3V 20% X5R 0603 Generic Generic
13 4 C23, C24, C25,
C26
100µF CAP CER 100µF 6.3V 20% X5R 1210 TDK C3225X5R0J107M250AC
14 2 C29, C30 10µF CAP CER 10µF 50V 10% X5R 1206 TDK C3216X5R1H106K160AB
15 1 C35 100µF CAP ALUM 100µF 50V 20% SMD Nichicon PCV1H101MCL2GS
16 1 C36 DNP CAP 220µF 6.3V Panasonic 6TPF220M5L
17 1 L1 2.4µH INDUCTOR POWER 2.4µH 31.5A SMD WE-Midcom 744325240
18 2 Q2, Q4 BSC039N06NS MOSFET N-CH 60V 19A TDSON-8 Infineon BSC039N06NS
19 2 R1, R11 14.7k RES 14.7kΩ 1/16W 1% 0402 SMD Generic Generic
20 1 R2 16.5k RES 16.5kΩ 1/16W 1% 0402 SMD Generic Generic
21 1 R3 133 RES 133Ω 1/16W 1% 0402 SMD Generic Generic
22 3 R4, R8, R12 2k RES 2.00kΩ 1/16W 1% 0402 SMD Generic Generic
23 2 R9, R22 0 RES 0.0Ω 1/16W JUMP 0402 SMD Generic Generic
24 1 R14 2 RES 2.00Ω 1/4W 1% 1206 SMD Generic Generic
25 1 R17 4.22k RES 4.22kΩ 1/16W 1% 0402 SMD Generic Generic
26 1 R20 30k RES 30kΩ 1/16W 1% 0402 SMD Generic Generic
27 1 R21 5.11k RES 5.11kΩ 1/16W 1% 0402 SMD Generic Generic
28 1 R23 732 RES 732Ω 1/16W 1% 0402 SMD Generic Generic
29 1 R26 18.2k RES 18.2kΩ 1/16W 1% 0402 SMD Generic Generic
30 1 R27 40.2k RES 40.2kΩ 1/16W 1% 0402 SMD Generic Generic
31 1 R28 9.1k RES 9.1kΩ 1/16W 1% 0402 SMD Generic Generic
32 3 R29, R39, R40 10k RES 10kΩ 1/16W 1% 0402 SMD Generic Generic
33 1 R34 2.2 RES 2.2Ω 1/16W 1% 0402 SMD Generic Generic
34 1 R35 113k RES 113kΩ 1/16W 1% 0402 SMD Generic Generic
Application Note 1919
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March 11, 2015
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Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the document is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
FIGURE 26. LAYER 3
FIGURE 27. BOTTOM LAYER
PCB Layout (Continued)
