MT41J64M16JT-15E:GTR - Micron Technology

DDR3 SDRAM

MT41J256M4 – 32 Meg x 4 x 8 banks

MT41J128M8 – 16 Meg x 8 x 8 banks

MT41J64M16 – 8 Meg x 16 x 8 banks

Features

•V

DD = VDDQ = 1.5V ±0.075V

• 1.5V center-terminated push/pull I/O

• Differential bidirectional data strobe

•8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS READ latency (CL)

• POSTED CAS ADDITIVE latency (AL)

• Programmable CAS WRITE latency (CWL) based on

tCK

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

•T

C of 0°C to 95°C

– 64ms, 8192 cycle refresh at 0°C to 85°C

– 32ms, 8192 cycle refresh at 85°C to 95°C

• Self refresh temperature (SRT)

• Automatic self refresh (ASR)

• Write leveling

• Multipurpose register

• Output driver calibration

Options1Marking

• Configuration

– 256 Meg x 4 256M4

– 128 Meg x 8 128M8

– 64 Meg x 16 64M16

• FBGA package (Pb-free) – x4, x8

– 78-ball (8mm x 11.5mm) Rev. G JP

– 78-ball (8mm x 10.5mm) Rev. J DA

• FBGA package (Pb-free) – x16

– 96-ball (8mm x 14mm) Rev. G, J JT

• Timing – cycle time

– 938ps @ CL = 14 (DDR3-2133) -093

– 1.07ns @ CL = 13 (DDR3-1866) -107

– 1.25ns @ CL = 11 (DDR3-1600) -125

– 1.5ns @ CL = 9 (DDR3-1333) -15E

– 1.87ns @ CL = 7 (DDR3-1066) -187E

• Operating temperature

– Commercial (0°C ≤ TC ≤ +95°C) None

– Industrial (–40°C ≤ TC ≤ +95°C) IT

• Revision :G / :J

Note: 1. Not all options listed can be combined to

define an offered product. Use the part

catalog search on http://www.micron.com

for available offerings.

Table 1: Key Timing Parameters

Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)

-0931, 2, 3, 4 2133 14-14-14 13.09 13.09 13.09

-1071, 2, 3 1866 13-13-13 13.91 13.91 13.91

-1251, 2 1600 11-11-11 13.75 13.75 13.75

-15E11333 9-9-9 13.5 13.5 13.5

187E 1066 7-7-7 13.1 13.1 13.1

Notes: 1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

3. Backward compatible to 1600, CL = 11 (-125).

4. Backward compatible to 1866, CL = 13 (-107).

1Gb: x4, x8, x16 DDR3 SDRAM

Features

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 256 Meg x 4 128 Meg x 8 64 Meg x 16

Configuration 32 Meg x 4 x 8 banks 16 Meg x 8 x 8 banks 8 Meg x 16 x 8 banks

Refresh count 8K 8K 8K

Row addressing 16K (A[13:0]) 16K (A[13:0]) 8K (A[12:0])

Bank addressing 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0])

Column addressing 2K (A[11, 9:0]) 1K (A[9:0]) 1K (A[9:0])

Page Size 1KB 1KB 2KB

Figure 1: DDR3 Part Numbers

Package

78-ball 8mm x 11.5mm FBGA

78-ball 8mm x 10.5mm FBGA

96-ball 8mm x 14mm FBGA

Mark

Rev.

G,J

Example Part Number: MT41J64M16JT-125:J

Configuration

256 Meg x 4

128 Meg x 8

64 Meg x 16

256M4

128M8

64M16

Speed Grade

tCK = 0.938ns, CL = 14

tCK = 1.071ns, CL = 13

tCK = 1.25ns, CL = 11

tCK = 1.25ns, CL = 10

tCK = 1.5ns, CL = 9

tCK = 1.87ns, CL = 7

-093

-107

-125

-125E

-15E

-187E

Configuration

MT41J Package Speed

Revision

Revision:G/:J

Temperature

Commercial

Industrial temperature

None

Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on

http://www.micron.com for available offerings.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the

part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:

http://www.micron.com.

1Gb: x4, x8, x16 DDR3 SDRAM

Features

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 2Micron Technology, Inc. reserves the right to change products or specifications without notice.

Contents

State Diagram ................................................................................................................................................ 11

Functional Description ................................................................................................................................... 12

Industrial Temperature ............................................................................................................................... 12

Automotive Temperature ............................................................................................................................ 12

General Notes ............................................................................................................................................ 13

Functional Block Diagrams ............................................................................................................................. 14

Ball Assignments and Descriptions ................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 25

Electrical Specifications .................................................................................................................................. 29

Absolute Ratings ......................................................................................................................................... 29

Input/Output Capacitance .......................................................................................................................... 30

Thermal Characteristics .................................................................................................................................. 31

Electrical Specifications – IDD Specifications and Conditions ............................................................................ 33

Electrical Characteristics – IDD Specifications .................................................................................................. 44

Electrical Specifications – DC and AC .............................................................................................................. 46

DC Operating Conditions ........................................................................................................................... 46

Input Operating Conditions ........................................................................................................................ 46

AC Overshoot/Undershoot Specification ..................................................................................................... 49

Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 53

Slew Rate Definitions for Differential Input Signals ...................................................................................... 55

ODT Characteristics ....................................................................................................................................... 56

ODT Resistors ............................................................................................................................................ 57

ODT Sensitivity .......................................................................................................................................... 58

ODT Timing Definitions ............................................................................................................................. 58

Output Driver Impedance ............................................................................................................................... 62

34 Ohm Output Driver Impedance .............................................................................................................. 63

34 Ohm Driver ............................................................................................................................................ 64

34 Ohm Output Driver Sensitivity ................................................................................................................ 65

Alternative 40 Ohm Driver .......................................................................................................................... 66

40 Ohm Output Driver Sensitivity ................................................................................................................ 66

Output Characteristics and Operating Conditions ............................................................................................ 68

Reference Output Load ............................................................................................................................... 70

Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 71

Slew Rate Definitions for Differential Output Signals .................................................................................... 72

Speed Bin Tables ............................................................................................................................................ 73

Electrical Characteristics and AC Operating Conditions ................................................................................... 78

Command and Address Setup, Hold, and Derating ........................................................................................... 98

Data Setup, Hold, and Derating ...................................................................................................................... 106

Commands – Truth Tables ............................................................................................................................. 115

Commands ................................................................................................................................................... 118

DESELECT ................................................................................................................................................ 118

NO OPERATION ........................................................................................................................................ 118

ZQ CALIBRATION LONG ........................................................................................................................... 118

ZQ CALIBRATION SHORT .......................................................................................................................... 118

ACTIVATE ................................................................................................................................................. 118

READ ........................................................................................................................................................ 118

WRITE ...................................................................................................................................................... 119

PRECHARGE ............................................................................................................................................. 120

REFRESH .................................................................................................................................................. 120

SELF REFRESH .......................................................................................................................................... 121

1Gb: x4, x8, x16 DDR3 SDRAM

Features

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 3Micron Technology, Inc. reserves the right to change products or specifications without notice.

DLL Disable Mode ..................................................................................................................................... 122

Input Clock Frequency Change ...................................................................................................................... 126

Write Leveling ............................................................................................................................................... 128

Write Leveling Procedure ........................................................................................................................... 130

Write Leveling Mode Exit Procedure ........................................................................................................... 132

Initialization ................................................................................................................................................. 133

Mode Registers .............................................................................................................................................. 135

Mode Register 0 (MR0) ................................................................................................................................... 136

Burst Length ............................................................................................................................................. 136

Burst Type ................................................................................................................................................. 137

DLL RESET ................................................................................................................................................ 138

Write Recovery .......................................................................................................................................... 138

Precharge Power-Down (Precharge PD) ...................................................................................................... 139

CAS Latency (CL) ....................................................................................................................................... 139

Mode Register 1 (MR1) ................................................................................................................................... 140

DLL Enable/DLL Disable ........................................................................................................................... 140

Output Drive Strength ............................................................................................................................... 141

OUTPUT ENABLE/DISABLE ...................................................................................................................... 141

TDQS Enable ............................................................................................................................................. 141

On-Die Termination .................................................................................................................................. 142

WRITE LEVELING ..................................................................................................................................... 142

POSTED CAS ADDITIVE Latency ................................................................................................................ 142

Mode Register 2 (MR2) ................................................................................................................................... 143

CAS Write Latency (CWL) ........................................................................................................................... 144

AUTO SELF REFRESH (ASR) ....................................................................................................................... 144

SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 145

SRT vs. ASR ............................................................................................................................................... 145

DYNAMIC ODT ......................................................................................................................................... 145

Mode Register 3 (MR3) ................................................................................................................................... 146

MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 146

MPR Functional Description ...................................................................................................................... 147

MPR Register Address Definitions and Bursting Order ................................................................................. 148

MPR Read Predefined Pattern .................................................................................................................... 154

MODE REGISTER SET (MRS) Command ........................................................................................................ 154

ZQ CALIBRATION Operation ......................................................................................................................... 155

ACTIVATE Operation ..................................................................................................................................... 156

READ Operation ............................................................................................................................................ 158

WRITE Operation .......................................................................................................................................... 169

DQ Input Timing ....................................................................................................................................... 177

PRECHARGE Operation ................................................................................................................................. 179

SELF REFRESH Operation .............................................................................................................................. 179

Extended Temperature Usage ........................................................................................................................ 181

Power-Down Mode ........................................................................................................................................ 182

RESET Operation ........................................................................................................................................... 190

On-Die Termination (ODT) ............................................................................................................................ 192

Functional Representation of ODT ............................................................................................................. 192

Nominal ODT ............................................................................................................................................ 192

Dynamic ODT ............................................................................................................................................... 194

Dynamic ODT Special Use Case ................................................................................................................. 194

Functional Description .............................................................................................................................. 194

Synchronous ODT Mode ................................................................................................................................ 200

ODT Latency and Posted ODT .................................................................................................................... 200

1Gb: x4, x8, x16 DDR3 SDRAM

Features

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Timing Parameters .................................................................................................................................... 200

ODT Off During READs .............................................................................................................................. 203

Asynchronous ODT Mode .............................................................................................................................. 205

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 207

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 209

Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 211

1Gb: x4, x8, x16 DDR3 SDRAM

Features

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 5Micron Technology, Inc. reserves the right to change products or specifications without notice.

List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 1

Table 2: Addressing ......................................................................................................................................... 2

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 19

Table 4: 86-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 21

Table 5: 96-Ball FBGA – x16 Ball Descriptions ................................................................................................. 23

Table 6: Absolute Maximum Ratings .............................................................................................................. 29

Table 7: DDR3 Input/Output Capacitance ...................................................................................................... 30

Table 8: Thermal Characteristics .................................................................................................................... 31

Table 9: Timing Parameters Used for IDD Measurements – Clock Units ............................................................ 33

Table 10: IDD0 Measurement Loop .................................................................................................................. 34

Table 11: IDD1 Measurement Loop .................................................................................................................. 35

Table 12: IDD Measurement Conditions for Power-Down Currents ................................................................... 36

Table 13: IDD2N and IDD3N Measurement Loop ................................................................................................ 37

Table 14: IDD2NT Measurement Loop .............................................................................................................. 37

Table 15: IDD4R Measurement Loop ................................................................................................................ 38

Table 16: IDD4W Measurement Loop ............................................................................................................... 39

Table 17: IDD5B Measurement Loop ................................................................................................................ 40

Table 18: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 .................................................................... 41

Table 19: IDD7 Measurement Loop .................................................................................................................. 42

Table 20: IDD Maximum Limits – Die Rev. G .................................................................................................... 44

Table 21: IDD Maximum Limits – Die Rev. J ..................................................................................................... 45

Table 22: DC Electrical Characteristics and Operating Conditions ................................................................... 46

Table 23: DC Electrical Characteristics and Input Conditions .......................................................................... 46

Table 24: Input Switching Conditions ............................................................................................................. 47

Table 25: Control and Address Pins ................................................................................................................ 49

Table 26: Clock, Data, Strobe, and Mask Pins .................................................................................................. 49

Table 27: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .................................................. 50

Table 28: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS - DQS# ............................................... 52

Table 29: Single-Ended Input Slew Rate Definition .......................................................................................... 53

Table 30: Differential Input Slew Rate Definition ............................................................................................. 55

Table 31: On-Die Termination DC Electrical Characteristics ............................................................................ 56

Table 32: RTT Effective Impedances ................................................................................................................ 57

Table 33: ODT Sensitivity Definition .............................................................................................................. 58

Table 34: ODT Temperature and Voltage Sensitivity ........................................................................................ 58

Table 35: ODT Timing Definitions .................................................................................................................. 59

Table 36: Reference Settings for ODT Timing Measurements ........................................................................... 59

Table 37: 34 Ohm Driver Impedance Characteristics ....................................................................................... 63

Table 38: 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ....................................................... 64

Table 39: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.5V ................................................................ 64

Table 40: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.575V ............................................................. 64

Table 41: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.425V ............................................................. 65

Table 42: 34 Ohm Output Driver Sensitivity Definition .................................................................................... 65

Table 43: 34 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 65

Table 44: 40 Ohm Driver Impedance Characteristics ....................................................................................... 66

Table 45: 40 Ohm Output Driver Sensitivity Definition .................................................................................... 66

Table 46: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 67

Table 47: Single-Ended Output Driver Characteristics ..................................................................................... 68

Table 48: Differential Output Driver Characteristics ........................................................................................ 69

Table 49: Single-Ended Output Slew Rate Definition ....................................................................................... 71

Table 50: Differential Output Slew Rate Definition .......................................................................................... 72

1Gb: x4, x8, x16 DDR3 SDRAM

Features

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Table 51: DDR3-1066 Speed Bins ................................................................................................................... 73

Table 52: DDR3-1333 Speed Bins ................................................................................................................... 74

Table 53: DDR3-1600 Speed Bins ................................................................................................................... 75

Table 54: DDR3-1866 Speed Bins ................................................................................................................... 76

Table 55: DDR3-2133 Speed Bins ................................................................................................................... 77

Table 56: Electrical Characteristics and AC Operating Conditions .................................................................... 78

Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 88

Table 58: Command and Address Setup and Hold Values Referenced – AC/DC-Based ...................................... 98

Table 59: Derating Values for tIS/tIH – AC175/DC100-Based ............................................................................ 99

Table 60: Derating Values for tIS/tIH – AC150/DC100-Based ............................................................................ 99

Table 61: Derating Values for tIS/tIH – AC135/DC100-Based ........................................................................... 100

Table 62: Derating Values for tIS/tIH – AC125/DC100-Based ........................................................................... 100

Table 63: Minimum Required Time tVAC Above VIH(AC) or Below VIL(AC)for Valid Transition .............................. 101

Table 64: DDR3 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ......................... 106

Table 65: Derating Values for tDS/tDH – AC175/DC100-Based ........................................................................ 107

Table 66: Derating Values for tDS/tDH – AC150/DC100-Based ........................................................................ 107

Table 67: Derating Values for tDS/tDH – AC135/DC100-Based at 1V/ns ........................................................... 108

Table 68: Derating Values for tDS/tDH – AC135/DC100-Based at 2V/ns ........................................................... 109

Table 69: Required Minimum Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition ......................... 110

Table 70: Truth Table – Command ................................................................................................................. 115

Table 71: Truth Table – CKE .......................................................................................................................... 117

Table 72: READ Command Summary ............................................................................................................ 119

Table 73: WRITE Command Summary .......................................................................................................... 119

Table 74: READ Electrical Characteristics, DLL Disable Mode ......................................................................... 125

Table 75: Write Leveling Matrix ..................................................................................................................... 129

Table 76: Burst Order .................................................................................................................................... 138

Table 77: MPR Functional Description of MR3 Bits ........................................................................................ 147

Table 78: MPR Readouts and Burst Order Bit Mapping ................................................................................... 148

Table 79: Self Refresh Temperature and Auto Self Refresh Description ............................................................ 181

Table 80: Self Refresh Mode Summary ........................................................................................................... 181

Table 81: Command to Power-Down Entry Parameters .................................................................................. 182

Table 82: Power-Down Modes ....................................................................................................................... 183

Table 83: Truth Table – ODT (Nominal) ......................................................................................................... 193

Table 84: ODT Parameters ............................................................................................................................ 193

Table 85: Write Leveling with Dynamic ODT Special Case .............................................................................. 194

Table 86: Dynamic ODT Specific Parameters ................................................................................................. 195

Table 87: Mode Registers for RTT,nom ............................................................................................................. 195

Table 88: Mode Registers for RTT(WR) ............................................................................................................. 196

Table 89: Timing Diagrams for Dynamic ODT ................................................................................................ 196

Table 90: Synchronous ODT Parameters ........................................................................................................ 201

Table 91: Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 206

Table 92: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period ................................... 208

1Gb: x4, x8, x16 DDR3 SDRAM

Features

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 7Micron Technology, Inc. reserves the right to change products or specifications without notice.

List of Figures

Figure 1: DDR3 Part Numbers .......................................................................................................................... 2

Figure 2: Simplified State Diagram ................................................................................................................. 11

Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 14

Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 15

Figure 5: 64 Meg x 16 Functional Block Diagram ............................................................................................. 15

Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16

Figure 7: 86-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 17

Figure 8: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 18

Figure 9: 78-Ball FBGA – x4, x8 (JP) ................................................................................................................ 25

Figure 10: 78-Ball FBGA – x4, x8 (HX) ............................................................................................................. 26

Figure 11: 78-Ball FBGA – x4, x8; (DA) ............................................................................................................. 27

Figure 12: 96-Ball FBGA – x16 (JT) .................................................................................................................. 28

Figure 13: Thermal Measurement Point ......................................................................................................... 32

Figure 14: Input Signal .................................................................................................................................. 48

Figure 15: Overshoot ..................................................................................................................................... 49

Figure 16: Undershoot ................................................................................................................................... 49

Figure 17: VIX for Differential Signals .............................................................................................................. 51

Figure 18: Single-Ended Requirements for Differential Signals ........................................................................ 51

Figure 19: Definition of Differential AC-Swing and tDVAC ............................................................................... 52

Figure 20: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 54

Figure 21: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 55

Figure 22: ODT Levels and I-V Characteristics ................................................................................................ 56

Figure 23: ODT Timing Reference Load .......................................................................................................... 59

Figure 24: tAON and tAOF Definitions ............................................................................................................ 60

Figure 25: tAONPD and tAOFPD Definitions ................................................................................................... 60

Figure 26: tADC Definition ............................................................................................................................. 61

Figure 27: Output Driver ................................................................................................................................ 62

Figure 28: DQ Output Signal .......................................................................................................................... 69

Figure 29: Differential Output Signal .............................................................................................................. 70

Figure 30: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 70

Figure 31: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 71

Figure 32: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 72

Figure 33: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 102

Figure 34: Nominal Slew Rate for tIH (Command and Address – Clock) ........................................................... 103

Figure 35: Tangent Line for tIS (Command and Address – Clock) .................................................................... 104

Figure 36: Tangent Line for tIH (Command and Address – Clock) .................................................................... 105

Figure 37: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 111

Figure 38: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 112

Figure 39: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 113

Figure 40: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 114

Figure 41: Refresh Mode ............................................................................................................................... 121

Figure 42: DLL Enable Mode to DLL Disable Mode ........................................................................................ 123

Figure 43: DLL Disable Mode to DLL Enable Mode ........................................................................................ 124

Figure 44: DLL Disable tDQSCK .................................................................................................................... 125

Figure 45: Change Frequency During Precharge Power-Down ........................................................................ 127

Figure 46: Write Leveling Concept ................................................................................................................. 128

Figure 47: Write Leveling Sequence ............................................................................................................... 131

Figure 48: Write Leveling Exit Procedure ....................................................................................................... 132

Figure 49: Initialization Sequence ................................................................................................................. 134

Figure 50: MRS to MRS Command Timing (tMRD) ......................................................................................... 135

1Gb: x4, x8, x16 DDR3 SDRAM

Features

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1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 8Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 51: MRS to nonMRS Command Timing (tMOD) .................................................................................. 136

Figure 52: Mode Register 0 (MR0) Definitions ................................................................................................ 137

Figure 53: READ Latency .............................................................................................................................. 139

Figure 54: Mode Register 1 (MR1) Definition ................................................................................................. 140

Figure 55: READ Latency (AL = 5, CL = 6) ....................................................................................................... 143

Figure 56: Mode Register 2 (MR2) Definition ................................................................................................. 144

Figure 57: CAS Write Latency ........................................................................................................................ 144

Figure 58: Mode Register 3 (MR3) Definition ................................................................................................. 146

Figure 59: Multipurpose Register (MPR) Block Diagram ................................................................................. 147

Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 150

Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 151

Figure 62: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 152

Figure 63: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 153

Figure 64: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 155

Figure 65: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 156

Figure 66: Example: tFAW ............................................................................................................................. 157

Figure 67: READ Latency .............................................................................................................................. 158

Figure 68: Consecutive READ Bursts (BL8) .................................................................................................... 160

Figure 69: Consecutive READ Bursts (BC4) .................................................................................................... 160

Figure 70: Nonconsecutive READ Bursts ....................................................................................................... 161

Figure 71: READ (BL8) to WRITE (BL8) .......................................................................................................... 161

Figure 72: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 162

Figure 73: READ to PRECHARGE (BL8) .......................................................................................................... 162

Figure 74: READ to PRECHARGE (BC4) ......................................................................................................... 163

Figure 75: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 163

Figure 76: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 163

Figure 77: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 165

Figure 78: Data Strobe Timing – READs ......................................................................................................... 166

Figure 79: Method for Calculating tLZ and tHZ ............................................................................................... 167

Figure 80: tRPRE Timing ............................................................................................................................... 167

Figure 81: tRPST Timing ............................................................................................................................... 168

Figure 82: tWPRE Timing .............................................................................................................................. 170

Figure 83: tWPST Timing .............................................................................................................................. 170

Figure 84: WRITE Burst ................................................................................................................................ 171

Figure 85: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 172

Figure 86: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 172

Figure 87: Nonconsecutive WRITE to WRITE ................................................................................................. 173

Figure 88: WRITE (BL8) to READ (BL8) .......................................................................................................... 173

Figure 89: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 174

Figure 90: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 175

Figure 91: WRITE (BL8) to PRECHARGE ........................................................................................................ 176

Figure 92: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 176

Figure 93: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 177

Figure 94: Data Input Timing ........................................................................................................................ 178

Figure 95: Self Refresh Entry/Exit Timing ...................................................................................................... 180

Figure 96: Active Power-Down Entry and Exit ................................................................................................ 184

Figure 97: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 185

Figure 98: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 185

Figure 99: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 186

Figure 100: Power-Down Entry After WRITE .................................................................................................. 186

Figure 101: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 187

Figure 102: REFRESH to Power-Down Entry .................................................................................................. 187

1Gb: x4, x8, x16 DDR3 SDRAM

Features

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 9Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 103: ACTIVATE to Power-Down Entry ................................................................................................. 188

Figure 104: PRECHARGE to Power-Down Entry ............................................................................................. 188

Figure 105: MRS Command to Power-Down Entry ......................................................................................... 189

Figure 106: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 189

Figure 107: RESET Sequence ......................................................................................................................... 191

Figure 108: On-Die Termination ................................................................................................................... 192

Figure 109: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 197

Figure 110: Dynamic ODT: Without WRITE Command .................................................................................. 197

Figure 111: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 198

Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 199

Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 199

Figure 114: Synchronous ODT ...................................................................................................................... 201

Figure 115: Synchronous ODT (BC4) ............................................................................................................. 202

Figure 116: ODT During READs .................................................................................................................... 204

Figure 117: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 206

Figure 118: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 208

Figure 119: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 210

Figure 120: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 212

Figure 121: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 212

1Gb: x4, x8, x16 DDR3 SDRAM

Features

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State Diagram

Figure 2: Simplified State Diagram

SRX = Self refresh exit

WRITE = WR, WRS4, WRS8

WRITE AP = WRAP, WRAPS4, WRAPS8

ZQCL = ZQ LONG CALIBRATION

ZQCS = ZQ SHORT CALIBRATION

Bank

active

ReadingWriting

Activating

Refreshing

Self

refresh

Idle

Active

power-

down

calibration

From any

state

Power

applied Reset

procedure

Power

Initial-

ization

MRS, MPR,

write

leveling

Precharge

power-

down

Writing Reading

Automatic

sequence

Command

sequence

Precharging

READ

READ READ

READ AP

PRE, PREA

PRE, PREA PRE, PREA

WRITE

CKE L CKE L

CKE L

WRITE

WRITE AP

PDE

PDX

SRX

SRE

REF

MRS

ACT

RESET

ZQCL

ZQCL/ZQCS

ACT = ACTIVATE

MPR = Multipurpose register

MRS = Mode register set

PDE = Power-down entry

PDX = Power-down exit

PRE = PRECHARGE

PREA = PRECHARGE ALL

READ = RD, RDS4, RDS8

READ AP = RDAP, RDAPS4, RDAPS8

REF = REFRESH

RESET = START RESET PROCEDURE

SRE = Self refresh entry

1Gb: x4, x8, x16 DDR3 SDRAM

State Diagram

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Functional Description

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.

The double data rate architecture is an 8n-prefetch architecture with an interface de-

signed to transfer two data words per clock cycle at the I/O pins. A single read or write

operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-

cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-

half-clock-cycle data transfers at the I/O pins.

The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data

for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the

data strobes.

The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK

going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, com-

mand, and address signals are registered at every positive edge of CK. Input data is reg-

istered on the first rising edge of DQS after the WRITE preamble, and output data is ref-

erenced on the first rising edge of DQS after the READ preamble.

Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a se-

lected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVATE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with

the ACTIVATE command are used to select the bank and row to be accessed. The ad-

dress bits registered coincident with the READ or WRITE commands are used to select

the bank and the starting column location for the burst access.

The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be

enabled to provide a self-timed row precharge that is initiated at the end of the burst

access.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM

allows for concurrent operation, thereby providing high bandwidth by hiding row pre-

charge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

Industrial Temperature

The industrial temperature (IT) device requires that the case temperature not exceed

–40°C or 95°C. JEDEC specifications require the refresh rate to double when TC exceeds

85°C; this also requires use of the high-temperature self refresh option. Additionally,

ODT resistance and the input/output impedance must be derated when TC is < 0°C or

>95°C.

Automotive Temperature

The automotive temperature (AT) device requires that the case temperature not exceed

–40°C or 105°C. JEDEC specifications require the refresh rate to double when TC exceeds

85°C; this also requires use of the high-temperature self refresh option. Additionally,

ODT resistance and the input/output impedance must be derated when TC is < 0°C or >

95°C.

1Gb: x4, x8, x16 DDR3 SDRAM

Functional Description

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL enable mode of operation (normal operation).

• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be

interpreted as any and all DQ collectively, unless specifically stated otherwise.

• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as

DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.

• Complete functionality may be described throughout the document; any page or dia-

gram may have been simplified to convey a topic and may not be inclusive of all re-

quirements.

• Any specific requirement takes precedence over a general statement.

• Any functionality not specifically stated is considered undefined, illegal, and not sup-

ported, and can result in unknown operation.

• Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4,

x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4,

x8).

• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a

single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer

to the Dynamic ODT Special Use Case section.

• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be

used, use the lower byte for data transfers and terminate the upper byte as noted:

– Connect UDQS to ground via 1kΩ* resistor.

– Connect UDQS# to VDD via 1kΩ* resistor.

– Connect UDM to VDD via 1kΩ* resistor.

– Connect DQ[15:8] individually to either VSS, VDD, or VREF via 1kΩ resistors,* or float

DQ[15:8].

*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.

1Gb: x4, x8, x16 DDR3 SDRAM

Functional Description

PDF: 09005aef826aa906

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Functional Block Diagrams

DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally

configured as an 8-bank DRAM.

Figure 3: 256 Meg x 4 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[13:0]

BA[2:0]

Address

256

(x32)

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(16,384 x 256 x 32)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To pull-up/pull-down

networks

READ

drivers DQ[3:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

CK, CK#

DQS, DQS#

ZQ CAL

CS#

RZQ

CK, CK#

RAS#

WE#

CAS#

ODT

CKE

RESET#

CK, CK#

DLL

DQ[3:0]

(1 . . . 4)

(1, 2)

sw1 sw2

VDDQ/2

RTT,nom RTT(WR)

sw1 sw2

VDDQ/2

RTT,nom RTT(WR)

sw1 sw2

VDDQ/2

RTT,nom RTT(WR)

OTF

BC4 (burst chop)

BC4

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

ODT

control

SSQ

A12

OTF

BC4

1Gb: x4, x8, x16 DDR3 SDRAM

Functional Block Diagrams

PDF: 09005aef826aa906

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Figure 4: 128 Meg x 8 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[13:0]

BA[2:0]

Address

8,192

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(16,384 x 128 x 64)

Bank 0

row-

address

latch

and

decoder

16,384

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

DQS, DQS#

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

READ

drivers DQ[7:0]

READ

FIFO

and

data

MUX

Data

Bank 1

Bank 2

Bank 3

DM/TDQS

(shared pin)

TDQS#

CK, CK#

DQS, DQS#

ZQ CAL

RZQ

CK, CK#

RAS#

WE#

CAS#

CS#

ODT

CKE

RESET#

CK, CK#

DLL

DQ[7:0]

DQ8

(1 . . . 8)

(1, 2)

sw1 sw2

VDDQ/2

RTT,nom RTT(WR)

sw1 sw2

VDDQ/2

RTT,nom RTT(WR)

sw1 sw2

VDDQ/2

RTT,nom RTT(WR)

BC4 (burst chop)

BC4

WRITE

drivers

and

input

logic

Data

interface

Column 2

(select upper or

lower nibble for BC4)

(128

x64)

ODT

control

SSQ

A12

OTF

Figure 5: 64 Meg x 16 Functional Block Diagram

Bank 5

Bank 6

Bank 7

Bank 4

Bank 7

Bank 4

Bank 5

Bank 6

Row-

address

MUX

Control

logic

Column-

address

counter/

latch

Mode registers

Command

decode

A[12:0]

BA[2:0]

Address

(128

x128)

16,384

I/O gating

DM mask logic

Column

decoder

Bank 0

memory

array

(8192 x 128 x 128)

Bank 0

row-

address

latch

and

decoder

8,192

Sense amplifiers

Bank

control

logic

Bank 1

Bank 2

Bank 3

Refresh

counter

128

LDQS, LDQS#, UDQS, UDQS#

Column 0, 1, and 2

Columns 0, 1, and 2

ZQCL, ZQCS

To ODT/output drivers

BC4

READ

drivers DQ[15:0]

READ

FIFO

and

data

MUX

Data

BC4 (burst chop)

Bank 1

Bank 2

Bank 3

LDM/UDM

CK, CK#

LDQS, LDQS#

UDQS, UDQS#

ZQ CAL

RZQ

ODT

CKE

CK, CK#

RAS#

WE#

CAS#

CS#

RESET#

CK, CK#

DLL

DQ[15:0]

(1 . . . 16)

(1 . . . 4)

(1, 2)

sw1 sw2

VDDQ/2

RTT,nom RTT(WR)

BC4

sw1 sw2

VDDQ/2

RTT,nom RTT(WR)

sw1 sw2

VDDQ/2

RTT,nom RTT(WR)

Column 2

(select upper or

lower nibble for BC4)

Data

interface

WRITE

drivers

and

input

logic

ODT

control

SSQ

A12

OTF

1Gb: x4, x8, x16 DDR3 SDRAM

Functional Block Diagrams

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Ball Assignments and Descriptions

Figure 6: 78-Ball FBGA – x4, x8 (Top View)

1234 67895

VSS

VDDQ

VSSQ

VREFDQ

ODT

VSS

VDD

VSS

VDD

VSS

VDD

VSSQ

DQ2

NF, DQ6

VDDQ

VSS

VDD

CS#

BA0

RESET#

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

VDD

NF, DQ7

CK#

A10/AP

A12/BC#

A11

VDD

VDDQ

VSSQ

VDDQ

CKE

VSS

VDD

VSS

VDD

VSS

VSSQ

DQ3

VSS

NF, DQ5

VSS

VDD

VREFCA

BA1

Notes: 1. Ball descriptions listed in Table 3 (page 19) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

1Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 7: 86-Ball FBGA – x4, x8 (Top View)

1234 67895

VSS

VDDQ

VSSQ

VREFDQ

ODT

VSS

VDD

VSS

VDD

VSS

VDD

VSSQ

DQ2

NF, DQ6

VDDQ

VSS

VDD

CS#

BA0

RESET#

DQ0

DQS

DQS#

NF, DQ4

RAS#

CAS#

WE#

BA2

A13

NF, NF/TDQS#

DM, DM/TDQS

DQ1

VDD

NF, DQ7

CK#

A10/AP

A12/BC#

A11

VDD

VDDQ

VSSQ

VDDQ

CKE

VSS

VDD

VSS

VDD

VSS

VSSQ

DQ3

VSS

NF, DQ5

VSS

VDD

VREFCA

BA1

Notes: 1. Ball descriptions listed in Table 4 (page 21) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 4).

1Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Figure 8: 96-Ball FBGA – x16 (Top View)

1234 67895

VSS

VDD

VSS

NC CS#

BA0

RESET#

NC VSS

VREFDQ VDDQ DQ4

RAS#

CAS#

WE#

BA2

VSSQ

VSSQ VDD VSS

VDDQ DQ2 LDQS

DQ6 LDQS#

VDDQ

VDDQ DQ13 DQ15

DQ11 DQ9

VDDQ UDM

VSS VSSQ DQ0

ODT VDD

VDD

A11

A10/AP ZQ

VREFCA

BA1

CK VSS

DQ7 DQ5 VDDQ

CKE

VSS

VDD

VSS

VDD

VSS

VDD

DQ8

UDQS# DQ14 VSSQ

DQ1 DQ3 VSSQ

VSS VSSQ

UDQS

DQ12 VDDQ VSS

DQ10 VDDQ

VSSQ VDD

LDM VSSQ VDDQ

CK# VDD

A12/BC#

Notes: 1. Ball descriptions listed in Table 5 (page 23) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 5).

1Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A0, A1, A2, A3, A4,

A5, A6, A7, A8, A9,

A10/AP, A11, A12/

BC#, A13

Input Address inputs: Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank (A10

LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also pro-

vide the op-code during a LOAD MODE command. Address inputs are referenced to

VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 115).

BA0, BA1, BA2 Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE,

or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0,

MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are

referenced to VREFCA.

CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of CK#.

Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal

circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is

dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE

LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks

idle), or active power-down (row active in any bank). CKE is synchronous for

power-down entry and exit and for self refresh entry. CKE is asynchronous for self re-

fresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled dur-

ing POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during

SELF REFRESH. CKE is referenced to VREFCA.

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to VREFCA.

DM Input Input data mask: DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access. Although

the DM ball is input-only, the DM loading is designed to match that of the DQ and

DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8.

ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,

and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored

if disabled via the LOAD MODE command. ODT is referenced to VREFCA.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to VREFCA.

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input

receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and

DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous.

DQ0, DQ1, DQ2,

DQ3

I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are

referenced to VREFDQ.

1Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)

Symbol Type Description

DQ0, DQ1, DQ2,

DQ3, DQ4, DQ5,

DQ6, DQ7

I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are

referenced to VREFDQ.

DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write

data. Center-aligned to write data.

TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is

enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resist-

ance.

VDD Supply Power supply: 1.5V ±0.075V.

VDDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immuni-

ty.

VREFCA Supply Reference voltage for control, command, and address: VREFCA must be

maintained at all times (including self refresh) for proper device operation.

VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self

refresh) for proper device operation.

VSS Supply Ground.

VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.

ZQ Reference External reference ball for output drive calibration: This ball is tied to an

external 240Ω resistor (RZQ), which is tied to VSSQ.

NC – No connect: These balls should be left unconnected (the ball has no connection to

the DRAM or to other balls).

NF – No function: When configured as a x4 device, these balls are NF. When configured as

a x8 device, these balls are defined as TDQS#, DQ[7:4].

1Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

PDF: 09005aef826aa906

1Gb_DDR3_SDRAM.pdf - Rev. L 09/12 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 4: 86-Ball FBGA – x4, x8 Ball Descriptions

Symbol Type Description

A0, A1, A2, A3, A4,

A5, A6, A7, A8, A9