Rev 0.6 / Dec. 2009 1
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
32Gb NAND Flash
H27UBG8T2A
Rev 0.6 / Dec. 2009 2
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Document Title
32Gbit (4096 M x 8 bit) NAND Flash Memory
Revision History
Revision
No. History Draft Date Remark
0.0 Initial Draft. May. 22. 2009 Preliminary
0.1 Update PKG outline.
Add Marking Information .
Jun. 17. 2009 Preliminary
0.2 Update PKG Information.
Update Multi Plane Cache Program.
Jul. 16. 2009 Preliminary
0.3
Correct Multi Plane Cache Program Operation Timings (Figure 22)
Correct Random Data Input Timings (Figure 24)
Update PKG Mechanical Data (Figure 2-1)
Correct Restriction read status in multi plane operation (Figure 63)
Aug. 31. 2009 Preliminary
0.4 Correct7.5 Restriction of Read Status Value in Multi Plane Operation
Correct7.6. Page Program Failure
Sep. 21. 2009 Preliminary
0.5 Correct4.3 Multi Plane Page Read Oct. 5. 2009 Preliminary
0.6
Change 52-VLGA Contact, X8 Device (Figure 2)
Update PKG Mechanical Data (Figure 2-1)
Update Pin Description of CE#
Change Endurance
Change AC Timing Characteristics (tRC, tRP, tWC, tWP, tCLS, tCS, tALS,
tDS, tREA, tADL)
Update Read ID table (3rd Byte)
Change Bad Block Management
Dec. 14. 2009 Preliminary
Rev 0.6 / Dec. 2009 3
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Product Feature
â– Multilevel Cell technology
â– Supply Voltage
- 3.3V device : Vcc = 2.7 V ~ 3.6 V
Vcc = 2.7 V ~ 3.6 V
â– Organization
- Page size : 8,640 Bytes(8192+448 bytes)
- Block size : 256 pages(2M+112K bytes)
- Plane size : 1,024 blocks
â– Page Read Time
- Random Access: 200 ㎲ (Max.)
- Sequential Access : 25 ㎱ (Min.)
â– Write Time
- Page program : 1600 ㎲ (Typ.)
- Block erase : 2.5 ㎳ (Typ.)
â– Operating Current
- Read
- Program
- Erase
- Standby
â– Hardware Data Protection
- Program/Erase locked during power transitions
â– Endurance
- 3,000 P/E cycles (with 24 bit/ 1,024byte ECC)
â– Data Retention
- 10 Years
â– Package
- TSOP (12x20)
- LGA (14x18)
â– Unique ID for copyright protection
Rev 0.6 / Dec. 2009 4
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
1. SUMMARY DESCRIPTION
The product part NO.(H27UBG8T2A) is a single 3.3V 32Gbit NAND flash memory. The Device contains 2 planes in a single
die. Each plane is made up of the 1024 blocks. Each block consists of 256 programmable pages. Each page contains 8,640
bytes. The pages are subdivided into an 8192-bytes main data storage area with a spare 448-byte district.
Page program operation can be performed in typical 1,600us, and a single block can be erased in typical 2.5ms. On-chip
control logic unit automates erase and program operations to maximize cycle endurance. E/W endurance is stipulated at
3,000 cycles when using relevant ECC and Error management.
The H27UBG8T2A is a best solution for applications requiring large nonvolatile storage memory.
1.1. Product List
Table 1
PART NUMBER ORGANIZATION Vcc RANGE PACKAGE
H27UBG8T2A X8 2.7V ~ 3.6V 48 - TSOP1
52 - LGA
Rev 0.6 / Dec. 2009 5
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
NC
NC
NC
NC
NC
NC
R/B
RE
CE
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
Vcc
Vss
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
12
13
37
36
25
481
24
NAND Flash
TSOP1
(x8)
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1.2. Packaging Information
â– Figure 1. 48-TSOP1 Contact, x8 Device
48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Symbol millimeters
Min Typ Max
A1.200
A1 0.050 0.150
A2 0.980 1.030
B 0.170 0.250
C 0.100 0.200
CP 0.100
D 11.910 12.000 12.120
E 19.900 20.000 20.100
E1 18.300 18.400 18.500
e 0.500
L 0.500 0.680
alpha 0 5
â– Figure 1-1. 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
Rev 0.6 / Dec. 2009 6
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
NC
NC
NC
NC
NC
NC
NC
NC
VCC
NC
/WE
/WP VSS
IO0
IO1
IO2 IO6
IO7
IO5
IO4
VSS
IO3
R/B
NC
NC NC
NC
NC
NC VCC
NC
VSS
VSS
VCC
VCC
NC CLE
ALE
/CE
/RE
NC
NC NC
NC
NC
NC
NC
VSS
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
12345
67
08
OA
OB
OC
OD
OE
OF
NC
NC
NC
â– Figure 2. 52-VLGA Contact, x8 Device
Rev 0.6 / Dec. 2009 7
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
52-VLGA, 14 x 18mm, Package Mechanical Data
Symbol millimeters
Min Typ Max
A 17.90 18.00 18.10
A1 13.00
A2 12.00
B 13.90 14.00 14.10
B1 10.00
B2 6.00
C1.00
C1 1.50
C2 2.00
D1.00
D1 1.00
E 0.80 0.90 1.00
CP1 0.65 0.70 0.75
CP2 0.95 1.00 1.05
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â– Figure 2-1. 52-VLGA, 14 x 18mm, Package Outline (Top view through package)
Rev 0.6 / Dec. 2009 8
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
VCC
VSS
WP#
CLE
ALE
RE#
WE#
CE# I/O0~I/O7
R/B#
I/O7~I/O0 Data Input / Outputs
CLE Command Latch Enable
ALE Address Latch Enable
CE# Chip Enable
RE# Read Enable
R/B# Ready / Busy
WE# Write Enable
WP# Write Protect
VCC Power Supply
VSS Ground
NC No Connection
Pin Diagram
â– Figure 3. Pin Diagram
Pin Names
Rev 0.6 / Dec. 2009 9
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
1.3. PIN DESCRIPTION
Notes:
A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges
from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.
Pin Name Description
I/O0-I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to COMMAND LATCH cycle, ADDRESS INPUT cycle, and DATA in-out cycles during read / write
operations. The I/O pins float to High-Z when the device is deselected or the outputs are disabled.
CLE
COMMAND LATCH ENABLE
This input activates the latching of the I/O inputs inside the Command Register on the Rising edge of Write Enable
(WE#).
ALE ADDRESS LATCH ENABLE
This input activates the latching of the I/O inputs inside the Address Register on the Rising edge of Write Enable (WE#).
CE#
CHIP ENABLE
This input controls the selection of the device. When the device is busy, CE# low does not deselect the memory. The
device goes into Stand-by mode when CE# goes High during 10us in Ready state. The CE# signal is ignored when
device is in Busy state, and will not enter Standby mode even if the CE# goes high.
WE# WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The I/O inputs are latched on the rise edge of WE#.
RE#
READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after
the falling edge of RE# which also increments the internal column address counter by one.
WP#
WRITE PROTECT
The WP# pin, when Low, provides a hardware protection against undesired write operations. Hardware Write Protection
is activated when the Write Protect pin is low. In this condition modify operation do not start and the content of the
memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protection even during the power
up phases.
R/B# READY / BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
Vcc SUPPLY VOLTAGE
The VCC supplies the power for all the operations. (Read, Write, and Erase).
Vss GROUND
NC NO CONNECTED
Rev 0.6 / Dec. 2009 10
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
X Decoder
Address
register
ALE
CLE
CE#
WE#
RE#
WP#
Command
Interface Logic
Program/Erase
Controller
HV generation
Y Decoder
Address
register
Command
register
IO Buffer & latch
X
D
E
C
O
D
E
R
NAND FLASH
Memory Array
1 Device =
(8,192 + 448) bytes x 256pages x 2048 blocks
= 36,238,786 kbits
Data Register & Sense Amp
Column Decoder
Vcc
Vss
Global data
buffer Output Driver
A14-A32
A0-A13
I/O<7:0>
1.4. Block Diagram
â– Figure 4. Block diagram
Rev 0.6 / Dec. 2009 11
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
1.5. Array Organization
â– Figure 5. Array organization
1.6. Addressing
Notes:
1. L must be set to Low.
2. The device ignores any additional address input cycle than required.
3. The Address consists of column address (A0~A13), page address (A14 ~ A21), plane address (A22), and
block address (A23 ~ the last address).
Bus cycle I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
1st Cycle A0 A1 A2 A3 A4 A5 A6 A7
2nd Cycle A8 A9 A10 A11 A12 A13 L(1) L(1)
3rd Cycle A14 A15 A16 A17 A18 A19 A20 A21
4th Cycle A22 A23 A24 A25 A26 A27 A28 A29
5th Cycle A30 A31 A32 L(1) L(1) L(1) L(1) L(1)
Rev 0.6 / Dec. 2009 12
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
1.7. Command Set
FUNCTION 1st
Cycle
Number of
Address
cycles
Data
input
cycles
2nd
Cycle
Number
of
Address
cycles
Data
input
cycles
3rd
Cycle
Acceptable
command
during busy
PAGE READ 00h 5 - 30h - - - No
READ FOR COPY-BACK 00h 5 - 35h - - - No
RANDOM DATA OUTPUT1) 05h 2 - E0h - - - No
SINGLE/multi plane CACHE READ5) 31h - - - - - - No
SINGLE/multi plane CACHE READ END5) 3Fh - - - - - - No
READ ID 90h 1 - - - - - No
READ STATUS REGISTER 70h - - - - - - Yes
PAGE PGM (start) / CACHE PGM 5)(end) 80h 5 Yes 10h - - - No
RANDOM DATA INPUT 1) 85h 2 Yes - - - - No
COPY-BACK PGM 85h 5 option 10h - - - No
CACHE PGM (start) 5) 80h 5 Yes 15h - - - No
BLOCK ERASE 60h 3 - D0h - - - No
RESET FFh - - - - - Yes
multi plane PAGE READ 60h 3 - 60h 3 - 30h No
multi plane CACHE READ START5) 60h 3 - 60h 3 - 30h/33h No
multi plane READ FOR COPY-BACK 60h 3 - 60h 3 - 35h No
multi plane BLOCK ERASE 60h 3 - 60h 3 - D0h No
multi plane DATA OUTPUT 1) 3) 00h 5 - 05h 2 - E0h No
multi plane READ STATUS REGISTER 78h 3 - - - - - Yes
multi plane PAGE PGM
/ multi plane CACHE PGM (end) 80h 5 Yes 11h~81h2) 5 Yes 10h No
multi plane COPY-BACK PGM 85h 5 option 11h~81h2) 5 option 10h No
multi plane CACHE PGM (start) 5) 80h 5 Yes 11h~81h2) 5 Yes 15h No
Rev 0.6 / Dec. 2009 13
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Notes:
1. Random Data Input/Output must be performed in a selected page.
2. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
3. Multi Plane Random data-out must be used after Multi Plane read operations (Multi Plane Page Read, Multi Plane
Cache Read and Multi Plane Read for Copy Back).
4. Do not change Plane address order when using all Multi Plane operations.
5. All cache operation (cache program, cache read) is available only within a block.
6. Interleave operation between two chips are allowed. Multi Plane Read Status (78h) can be used to check each chip
status. It is prohibited to use Read Status command (70h) in interleaved operation.
Caution:
1. Any undefined command inputs are prohibited except for above command set.
2. Multi Plane page read, Multi Plane cache read, and Multi Plane read for copy-back must be used after Multi Plane
pro grammed page, Multi Plane cache program, and Multi Plane copy-back program.
1.8. Mode Selection
Notes:
1. X can be VIL or VIH. H = Logic level HIGH. L = Logic level LOW.
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. WE# and RE# during Read Busy must be keep on high to prevent unplanned command/address/data input or to
avert unintended data out. In this time, only Reset, Read Status, and Multi Plane Read Status can be inputted to
the device.
CLE ALE CE# WE# RE# WP# MODE
HL L H X
Read Mode
Command Input
L H L H X Address Input ( 5 Cycles )
HL L H H
Write Mode
Command Input
LH1) L H H Address Input ( 5 Cycles )
LL L H HData Input
LL1) L H X Sequential Read and Data Output
XX XH3) H3) X During Read (Busy)
XX1) XXXHDuring Program (Busy)
X X X X X H During Erase (Busy)
X X X X X L Write Protect
XX H X X
OV/Vcc2) Stand-By
Rev 0.6 / Dec. 2009 14
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Start
Block No = 0
Read FFh
check column 8192
of the first page
Last Block
End
Entry Bad Block
Fail
Fail
Pass
Yes
Block No. = Block No. + 1 Pass
No
Read FFh
check col. 8192
of the last page
1.9. Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh).
The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the spare area of either the 1st or
the last page does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted
as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original
information it is recommended to create a Bad Block table following the flowchart shown in Flow chart 1. The 1st block,
which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.
â– Flow chart 1. Bad block management flow chart
Notes:
1. Do not try to erase the detected bad blocks, because the bad block information will be lost.
2. Do not perform program and erase operation in invalid block, it is impossible to guarantee the input data
and to ensure that the function is normal.
Rev 0.6 / Dec. 2009 15
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Block A Block B
Data Data
Failure
FFh FFh
Buffer memory
Controller
1 Page
st 1 Page
st
Nth Page Nth Page
(2)
(3)
1.10. Bad Block Replacement
This device may have the invalid blocks when shipped from factory. An invalid block is one that contains one or more bad
bits. Over the lifetime of the device additional Bad Blocks may develop. In this case, the block has to be replaced by
copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them
will give errors in the Status Register.
The failure of a page program operation does not affect the data in other pages in the same block. Bad block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. Refer
to Table 2 and Figure 6 for the recommended procedure to follow if an error occurs during an operation.
Table 2. Block failure
â– Figure 6. Block replacement
Notes:
1. An error occurs on nth page of the Block A during Program or Erase operation.
2. Data in Block A is copied to same location in Block B which is valid block.
3. Nth page of block A which is in controller buffer memory is copied into nth page of Block B.
4. Bad block table should be updated to prevent from erasing or programming Block A.
Operation Recommended Procedure
Erase Block Replacement
Program Block Replacement
Read ECC
Rev 0.6 / Dec. 2009 16
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2. Electrical Characteristics
2.1. Valid Blocks
Notes:
1. The 1st block is guaranteed to be a valid block at the time of shipment.
2. This single device has a maximum of 50 invalid blocks.
3. Invalid blocks are one that contains one or more bad bits. The device may contain bad blocks upon shipment.
2.2. Absolute Maximum Rating
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute
Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or any other conditions above those indicated in the Operating sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may
affect device reliability.
Refer also to the Hynix SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Symbol Min Typ Max Unit
Valid Block
Number NVB 1998 2048 Blocks
Symbol Parameter
Value
Unit
Min
TA
Ambient Operating Temperature
(Commercial Temperature Range) 0 to 70 °C
Ambient Operating Temperature
(Extended Temperature Range) -25 to 85 °C
Ambient Operating Temperature
(Industrial Temperature Range) -40 to 85 °C
TBIAS Temperature Under Bias -50 to 125 °C
TSTG Storage Temperature -65 to 150 °C
VIO Input or Output Voltage -0.6 to 4.6 V
VCC Supply Voltage -0.6 to 4.6 V
Rev 0.6 / Dec. 2009 17
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.3. DC and Operating Characteristics
Parameter Symbol Test
Conditions
HY27UCG8T2A
Unit3.3V
Min Typ Max
Power on reset current ICC0 FFh command input
after power on --
50per
device ㎃
Operating
Current
Read ICC1
tRC= tRC(min),
CE#=VIL,
IOUT=0 ㎃
--50
㎃
Program ICC2 ---50
㎃
Erase ICC3 ---50
㎃
Stand-by Current (TTL) ICC4
CE#=VIH, WP#=0V/
VCC
-- 1
㎃
Stand-by Current (CMOS) ICC5
CE#=VCC-0.2,
WP#=0V/VCC -1050
㎂
Input Leakage Current ILI VIN=0 to VCC(MAX) --
±10 ㎂
Output Leakage Current ILO VOUT=0 to VCC(MAX) --
±10 ㎂
Input High Voltage VIH - Vccx0.8 - Vcc+0.3 V
Input Low Voltage VIL - -0.3 - 0.2x Vcc V
Output High Voltage VOH IOH=-200 ㎂2.4 - - V
Output Low Voltage VOL IOL=2.1 ㎃--0.4V
Output Low Current (R/B#) IOL(R/B#) VOL=0.4V 810 - ㎃
Rev 0.6 / Dec. 2009 18
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.4. AC Test Conditions
Notes:
1.These parameters are verified device characterization and are not 100% tested.
2.5. Pin Capacitance (TA=25°C, F=1.0㎒)
2.6. Program/ Read / Erase Characteristics
Notes:
1. Typical value is measured at VCC=3.3V, TA=25℃. Not 100% tested.
Parameter
Value
2.7V ≤ Vcc ≤ 3.6V
Input Pulse Levels 0 V to VCC
Input Rise and Fall Times 5 ㎱
Input and Output Timing Levels Vcc /2
Output Load (2.7V-3.6V) 1 TTL GATE and CL=50㎊
Symbol Parameter Test
Condition Min Max Unit
CIN Input Capacitance VIN = 0V -10
㎊
CI/O Input/Output Capacitance VIN = 0V -10
㎊
Parameter Symbol Min Typ Max Unit
Program (following 10h) tPROG - 1600 5000 ㎲
Cache Program (following 15h) tCBSYW - - 5000 ㎲
multi plane Program / multi plane Cache
Program / multi plane Copy-Back Program
(following 11h)
tDBSY -3 5 ㎲
Cache Read / multi plane Cache Read
(following 31h/3Fh) tCBSYR -3200㎲
Block Erase / multi plane Block Erase tBERS -2.510 ㎳
Number of partial Program Cycles in the
same page NOP - - 1 cycles
Rev 0.6 / Dec. 2009 19
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.7. AC Timing Characteristics
Parameter Symbol
3.3V
Unit
Min Max
CLE setup time tCLS 12 ㎱
CLE Hold time tCLH 5㎱
CE# setup time tCS 20 ㎱
CE# hold time tCH 5㎱
WE# pulse width tWP 12 ㎱
ALE setup time tALS 12 ㎱
ALE hold time tALH 5㎱
Data setup time tDS 12 ㎱
Data hold time tDH 5㎱
Write cycle time tWC 25 ㎱
WE# high hold time tWH 10 ㎱
Data transfer from cell to register tR200 ㎲
ALE to RE# delay tAR 10 ㎱
CLE to RE# delay tCLR 10 ㎱
Ready to RE# low tRR 25 ㎱
RE# pulse width tRP 12 ㎱
WE# high to busy tWB 100 ㎱
Read cycle time tRC 25 ㎱
RE# access time tREA 20 ㎱
RE# high to output high Z tRHZ 100 ㎱
CE# high to output high Z tCHZ 50 ㎱
RE# high to output hold tRHOH 15 ㎱
RE# low to output hold tRLOH 5㎱
RE# or CE# high to output hold tCOH 15 ㎱
RE# high hold time tREH 10 ㎱
CE# low to RE# low tCR 10 ㎱
WE# high to RE# low tWHR 80 ㎱
Rev 0.6 / Dec. 2009 20
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
Notes:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. Program / Erase Enable Operation: WP# high to WE# High.
Program / Erase Disable Operation: WP# Low to WE# High.
3. The transition of the corresponding control pins must occur only while WE# is held low.
4. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
RE# high to WE# low tRHW 100 ㎱
Output high Z to RE# low tIR 0㎱
Address to data loading time tADL 100 ㎱
Device resetting time
(Read/Program/Erase) tRST 20/30/500 ㎲
Write protection time tWW 100 ㎱
Rev 0.6 / Dec. 2009 21
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.8. Status Register Coding
Notes:
1. I/O0: This bit is only valid for Program and Erase operations. During Cache Program operations,
this bit is only valid when I/O5 is set to one.
2. I/O1: This bit is only valid for cache program operations. This bit is not valid until after the
second 15h command or the 10h command has been transferred in a Cache program sequence.
When Cache program is not supported, this bit is not used.
3. I/O5: If set to one, then there is no array operation in progress. If cleared to zero, then there is a
command being processed (I/O6 is cleared to zero) or an array operation in progress. When
overlapped interleaved operations or cache commands are not supported, this bit is not used.
4. I/O6: If set to one, then the device or interleaved address is ready for another command and
all other bits in the status value are valid. If cleared to zero, then the last command issued
is not yet complete and Status Register bits<5:0> are invalid value. When cache operations
are in use, then this bit indicates whether another command can be accepted, and I/O5
indicates whether the last operation is complete.
I/O Page
Program
Block
Erase Read Cache
Read
Cache
Program
Coding
70h/ 78h
0 Pass/ Fail Pass/ Fail N/A N/A Pass/ Fail N page
Pass : '0' Fail : '1'
1 N/A N/A N/A N/A Pass/ Fail N-1 page
Pass : '0' Fail : '1'
2 N/A N/A N/A N/A N/A '0'
3 N/A N/A N/A N/A N/A '0'
4 N/A N/A N/A N/A N/A '0'
5 N/A N/A N/A Ready / Busy Ready / Busy Ready / Busy
Busy : '0' Ready : '1'
6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy Data Cache Ready /
Busy : '0' Ready : '1'
7 Write Protect Write Protect Write Protect Write Protect Write Protect Protected : '0'
Not Protected : '1'
Rev 0.6 / Dec. 2009 22
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.9. Device Identifier Coding
2.10. Read ID Data Table
2.10.1. 3rd Byte of Device Identifier Description
Parameter Symbol
Device Identifier Byte Description
1st Manufacturer Code
2nd Device Identifier
3rd Internal chip number, cell Type, Number of Simultaneously
Programmed Pages, Interleaved Program, Write Cache.
4th Page size, Block size, Redundant area size
5th Plane Number, ECC Level
6th Technology (Design Rule), EDO, Interface
Part Number Voltage Bus
Width
Manufacture
Code
Device
Code 3rd 4th 5th 6th
H27UBG8T2A 3.3V X8 ADh D7h 94h 9Ah 74h 42h
3rd cycle Description I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
Internal Chip Number
1
2
4
Reserved
0
0
1
1
0
1
0
1
Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
0
0
1
1
0
1
0
1
Number of Simultaneously
Programmed Pages
1
2
4
8
0
0
1
1
0
1
0
1
Interleaved Program
between Multiple dice
Supported
Not Supported
0
1
Write Cache Not Supported
Supported
0
1
Rev 0.6 / Dec. 2009 23
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.10.2. 4th Byte of Device Identifier Description
2.10.3. 5th Byte of Device Identifier Description
4th cycle Description I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
Page Size
(Without Spare Area)
2KB
4KB
8KB
Reserved
0
0
1
1
0
1
0
1
Block Size
(Without Spare area)
128KB
256KB
512KB
768KB
1MB
2MB
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Redundant Area Size
128B
224B
448B
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5th cycle Description I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
Plane Number
1
2
4
8
0
0
1
1
0
1
0
1
ECC Level
1bit/512Bytes
2bit/512Bytes
4bit/512Bytes
8bit/512Bytes
16bit/512Bytes
24bit/2048Bytes
24bit/1024Bytes
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved 0 0 0
Rev 0.6 / Dec. 2009 24
Preliminary
H27UBG8T2A Series
32Gb (4096M x 8bit) NAND Flash
2.10.4. 6th Byte of Device Identifier Description
6th cycle Description I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
NAND Technology
48nm
41nm
32nm
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EDO Support Not Support
Support
0
1
NAND Interface SDR
DDR
0
1
Reserved 0 0 0