V =xV
N OUT
11
V
mVRMS
TPS735xx
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
www.ti.com
optimize noise, equivalent series resistance of the As with any linear regulator, PSRR and transient
output capacitor can be set to approximately 0.2Ω. response are degraded as (VIN – VOUT) approaches
This configuration maximizes phase margin in the dropout. This effect is shown in the Typical
control loop, reducing total output noise by up to Characteristics section.
10%. Startup and Noise Reduction Capacitor
Noise can be referred to the feedback point (FB pin)
such that with CNR = 0.01μF, total noise is given Fixed voltage versions of the TPS735xx use a
approximately by Equation 1:quick-start circuit to fast-charge the noise reduction
capacitor, CNR, if present (see the Functional Block
Diagrams). This architecture allows the combination
(1) of very low output noise and fast start-up times. The
The TPS73501 adjustable version does not have the NR pin is high impedance so a low leakage CNR
noise-reduction pin available, so ultra-low noise capacitor must be used; most ceramic capacitors are
operation is not possible. Noise can be minimized appropriate in this configuration.
according to the above recommendations. Note that for fastest startup, VIN should be applied
first, then the enable pin (EN) driven high. If EN is
Board Layout Recommendations to Improve tied to IN, startup is somewhat slower. Refer to the
PSRR and Noise Performance Typical Characteristics section. The quick-start switch
To improve ac performance such as PSRR, output is closed for approximately 135μs. To ensure that
noise, and transient response, it is recommended that CNR is fully charged during the quick-start time, a
the board be designed with separate ground planes 0.01μF or smaller capacitor should be used.
for VIN and VOUT, with each ground plane connected
only at the GND pin of the device. In addition, the Transient Response
ground connection for the bypass capacitor should As with any regulator, increasing the size of the
connect directly to the GND pin of the device. output capacitor reduces over/undershoot magnitude
but increases duration of the transient response. In
Internal Current Limit the adjustable version, adding CFB between OUT and
The TPS735xx internal current limit helps protect the FB improves stability and transient response. The
regulator during fault conditions. During current limit, transient response of the TPS735xx is enhanced by
the output sources a fixed amount of current that is an active pull-down that engages when the output
largely independent of output voltage. For reliable overshoots by approximately 5% or more when the
operation, the device should not be operated in device is enabled. When enabled, the pull-down
current limit for extended periods of time. device behaves like a 400Ωresistor to ground.
The PMOS pass element in the TPS735xx has a Undervoltage Lock-Out (UVLO)
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This The TPS735xx utilizes an undervoltage lock-out
current is not limited, so if extended reverse voltage circuit to keep the output shut off until internal
operation is anticipated, external limiting may be circuitry is operating properly. The UVLO circuit has a
appropriate. de-glitch feature so that it typically ignores
undershoot transients on the input if they are less
Shutdown than 50μs duration.
The enable pin (EN) is active high and is compatible Minimum Load
with standard and low voltage TTL-CMOS levels.
When shutdown capability is not required, EN can be The TPS735xx is stable and well-behaved with no
connected to IN. output load. To meet the specified accuracy, a
minimum load of 500μA is required. Below 500μA at
Dropout Voltage junction temperatures near +125°C, the output can
drift up enough to cause the output pull-down to turn
The TPS735xx uses a PMOS pass transistor to on. The output pull-down limits voltage drift to 5%
achieve low dropout. When (VIN – VOUT) is less than typically but ground current could increase by
the dropout voltage (VDO), the PMOS pass device is approximately 50μA. In typical applications, the
in its linear region of operation and the input-to-output junction cannot reach high temperatures at light loads
resistance is the RDS, ON of the PMOS pass element. because there is no appreciable dissipated power.
Because the PMOS device behaves like a resistor in The specified ground current would then be valid at
dropout, VDO approximately scales with output no load in most applications.
current.
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