Bringing the Best Together Lattice Solutions ispXPGATM Non-volatile + Reconfigurable ispXPLDTM CPLD + Memory Bringing the Best Together Today's leading-edge system designers have to satisfy multiple and often competing goals. Designers must balance speed, low power consumption, high functionality, board-space savings, cost, and fast time-to-market. ispPAC(R) ISP + Analog ispMACHTM Lowest Power + Speed FPSC FPGA + ASSP Power Manager ISP Analog + Logic Lattice Semiconductor brings together a variety of technologies and features to provide innovative solutions that address the real needs of designers. This approach has been adopted across the range of products that Lattice supplies. In silicon products this spans logic, interface, and analog. In design tools it covers design entry, intellectual property and development tools. Lattice's product portfolio includes the world's fastest programmable logic devices (2.3 ns pin-to-pin delay), the lowest power consumption (20 A static ICC), the world's only non-volatile, infinitely reconfigurable FPGAs (Field Programmable Gate Arrays), the fastest programmable SERDES (3.7 Gbps per channel), and programmable mixed signal devices. Lattice consistently brings the best together to deliver innovative, high-performance, Lattice Exceeding programmable solutions. Design Requirements Performance Leadership Lattice delivers the world's highest performance programmable logic devices. ispMACH 4000 - 2.5 ns / 400 MHz ispGAL(R)22V10 - 2.3 ns / 455 MHz fMAX (MHz) Lattice sysHSITM (system high-speed interface) serializer/deserializer (SERDES) technology leads the programmable logic industry in terms of maximum bit rate and low jitter. The following actual eye diagram illustrates the outstanding characteristics of Lattice's sysHSI SERDES technology. Lattice Speed p d h Leadership 400 300 Lattice 200 Xilinx Altera 100 256 512 Superior SERDES Solutions 768 1024 Number of Macrocells Highest Speed Logic Highest Performance I/Os Complex Functions Lowest Power Dissipation Smallest Footprint Mixed Signal Capability Lower Cost Faster Time-to-Market Technology Leadership Through the development of products utilizing advanced manufacturing processes, Lattice delivers higher speed and lower cost solutions to the marketplace. Current developments are focused on 0.13 m and 90 nm technology. 1.0X 256 Macrocell CPLD Evolution Dimension (m) 0.3 12 ns 0.2 0.4X 5 ns 0.25X 3 ns 0.1 ORT82G5 RX Eye Diagram over 26 inches (65 centimeters) of FR4 at 3.7 Gbps 1998 2000 2002 Year of Introduction 2 2004 Lattice Products Logic Devices Ultra Low Power Lattice delivers the world's lowest power programmable logic devices. ispMACH 4000Z - 20 A (max.) ORCA(R) FPSC - 225 mW per SERDES Channel @ 3.125 Gbps 120 Static ICC (A) 100 < 100 A 80 80% Power Reduction 60 40 20 Programmable Analog Today's system designs contain analog signals which must be monitored and processed. Lattice's innovative ispPAC family of programmable analog devices offers an excellent solution for signal conditioning, filtering and control loop applications. The ispPAC Power Manager combines programmable analog and digital providing an optimized power sequencing and monitoring solution. 5V Input Power Supply 20 A Lattice ispMACH 4032Z Competitive Device Brick LDO Advanced Packaging Lattice utilizes a variety of advanced packaging technologies that allow designers to increase functional density. Lattice offers TQFP, caBGA (0.8 mm), and fpBGA (1.0 mm) packaging - including thermally enhanced options. Current developments include packages ranging from the space-saving QFN to 1000+ ball BGA packages. 49-Ball caBGA 7 x 7 mm 2.5V 1.2V Other Board Circuitry Prog. CPLD Voltage Monitor Logic Driver ispPAC Power-1208 Faster Time to Market Programmable devices provide fast timeto-market. Lattice facilitates the design process by supporting users with easy-touse ispLEVERTM tools, IP cores, on-time delivery, a global network of field applications engineers, and over 20 years of experience in programmable products. ORCA Series 4 SRAM-based FPGAs 4 ispXPGA Non-volatile, reconfigurable FPGAs 5 ispXPLD 5000MX High-density CPLD plus memory 8 ispMACH 4000 Highest speed, lowest power CPLDs 9 ispPAC Power Manager Programmable analog + logic 10 SERDES Interface Devices ORT82G5 8 x 3.7 Gbps SERDES + FPGA 6 ORT42G5 4 x 3.7 Gbps SERDES + FPGA 6 ORSO82G5 8 x 2.7 Gbps SERDES + SONET + FPGA 6 ORSO42G5 4 x 2.7 Gbps SERDES + SONET + FPGA 6 ORT8850H/L 8 x 850 Mbps SERDES + SONET + FPGA 6 ispGDX2 Programmable SERDES + interconnect 7 Source Synchronous Interface Devices ORLI10G 10 Gbps line interface + FPGA 6 Programmable Analog ispPAC Programmable analog 10 ispPAC Power Manager Programmable analog + logic 10 Design Entry ispLEVER Digital design 11 PAC-Designer(R) Analog + mixed signal design 10 Intellectual Property IP Cores 11 Reference Designs 11 Development Tools 32-Pin QFN 5 x 5 mm Packages shown actual size. Timers High Voltage Driver 5V Page 900-Ball fine pitch BGA 31 x 31 mm Evaluation Boards 11 Programming Hardware 11 Programming Software 11 3 Bringing the Best Together FPGA Products Lattice Field Programmable Gate Arrays ORCA FPSC System Gates The ispXPGA (in system programmable eXpanded field Programmable Gate Array) family of devices allows the creation of high-performance logic designs that are both non-volatile and infinitely reconfigurable. Other FPGA solutions force a compromise, being either re-programmable, or reconfigurable, or non-volatile. Lattice's ispXPGA family offers all these capabilities with a mainstream architecture containing the features required for today's system-level design. ORCA 4 ispXPGA ORCA 3 ORCA 2 Time ORCA Series 4 FPGAs by Lattice Semiconductor are built on the familiar Optimized Reconfigurable Cell Array (ORCA) architecture. This FPGA device family offers many new features and architectural enhancements not available in any earlier FPGA generations. Bringing together highly flexible SRAMbased programmable logic, powerful system features, a rich hierarchy of routing and interconnect resources, and meeting multiple interface standards, the ORCA family of FPGAs accommodates the most complex and high-performance design challenges. ORCA Series 4 Block Diagram sysIO Buffers * * * * * sysMEMTM Blocks * Up to 148k Of Dedicated Memory * Configurable as Dual-port, FIFO, Single-port, ROM, CAM, or Multiplier * 256x36, 512x18, and 1kx9 Modes ORCA Series 4 Family High Performance FPGA - Up to 900k system gates - Up to 466 user I/Os - Up to 148k embedded memory - 250 MHz performance Flexible Programmable Logic Cells (PLCs) sysIOTM Capability for High Performance Interfacing Block and Distributed Memory sysCLOCKTM PLLs for Clock Management - 6 general purpose PLLs - 2 communication specific PLLs System-level Design Features - Embedded Microprocessor Interface (MPI) - Embedded system bus (ARM AHB bus) High Speed Memory Support: SSTL, HSTL Bus Support: PCI, GTL+ Differential Support: LVDS, LVPECL On-chip Differential Termination Standard Logic Support: LVTTL, LVCMOS 3.3, 2.5 and 1.8 Microprocessor Interface (MPI) and Associated System Bus * 32-/16-/8-bit External Interface * 32-bit Internal Interface With Automatic Width Conversion * Embedded System Multi-Master Bus * Configuration / Readback / Control / Status Modes Clock Pins (all 4 sides) Programmable Logic Cells (PLCs) * 8 LUT-4s Per PLC * 9 Flip-flops Per PLC - One Flip-flop Per LUT - Additional Flip-flop For Pipelining * Distributed Memory * Up to 250 MHz Operation sysCLOCK PLLs * * * * Programmable I/O Cells (PICs) Clock Multiplication and Division Phase Shifting 2.5 MHz to 420 MHz Supports DS-1/E-1 & STS3 /STM-1 * * * * Separate Input, Output, and OE Registers DDR Support Programmable Input Options Programmable Output Skew ORCA Series 4 Family of FPGAs Device OR4E02 OR4E04 OR4E06 4 System Gates LUT-4 Total Registers EBR RAM Blocks EBR RAM Bits Distributed RAM Bits PLLs User I/O 397k 5.0k 6.8k 8 74k 80k 8 405 643k 10.4k 13.4k 12 111k 166k 8 466 899k 16.2k 20.4k 16 148k 259k 8 466 ispXPGA Family ispXPTM Programming Technology Provides Non-volatility and Infinite Reconfigurability - Instant availability of logic at power-up - Single chip solution - Secure High-Performance FPGAs - Up to 1.25M system gates - Up to 496 I/Os - Up to 414k embedded memory High Performance Logic Blocks (PFUs) Block and Distributed Memory sysCLOCK PLLs for Clock Management sysIO Capability for High Performance Interfacing - Hot socketing support - Leave alone I/O - holds pin state during programming sysHSI for 850 Mbps Serial Communication ispXP Offers Unique Set of Advantages New ispXPGA and ispXPLD Families are Infinitely Reconfigurable and Nonvolatile sysMEM Blocks * Up to 414k of Dedicated Memory per ispXPGA * Configurable as Single- or Dual-Port, FIFO, or ROM * 512 x 9 Bits or 256 x 18 Bits * Cascadable Width and Depth ispXPGA Block Diagram Programmable Function Units (PFUs) * Up to 3,844 High Speed Logic Blocks * Four LUT-4 per PFU * Dual Flip-Flops per LUT-4 for Extensive Pipelining * Dedicated Logic for Adders Multipliers, Multiplexers, and Counters * Distributed Memory sysCLOCK PLL * 8 Phase Locked Loops * 10 MHz to 320 MHz * Clock Multiplication and Division * Phase Adjustment * Shift Clocks in 325 ps Steps sysHSI Blocks * * * * Cost Effective SERDES Up to 850 Mbps Performance Clock Data Recovery Up to 20 Channels per Device sysIO Buffers * High Speed Memory Support: SSTL and HSTL * Bus Support: PCI, GTL+, LVDS and LVPECL * Standard Logic Support: LVTTL, LVCMOS 3.3, 2.5 and 1.8 Programmable I/O Cells (PICs) * * * * Lattice offers an innovative new programming technology referred to as ispXP, for In-System Programmable eXpanded Programming. Previous programmable logic technologies have typically been either nonvolatile EEPROM based or reconfigurable SRAM based. Because both these technologies provide unique benefits, Lattice decided to combine them in ispXP. This provides users, for the first time, with the benefits of nonvolatility, including instant-on, single chip solutions, and high-security, with the infinite reconfigurability of SRAM technology. Single chip solution Instant-on - PLD logic available within microseconds of power-up (less than 200 S) ispXP devices include security bits to prevent unauthorized readback No external bitstream Separate Input, Output, and OE Registers Flexible Set, Reset, Clock Enable and Polarity Input Register Offers Delay Option for Zero tHOLD Programmable Output Slew Rate ispXPGA Family of FPGAs Family Member ispXPGA 125 ispXPGA 200 ispXPGA 500 ispXPGA 1200 System Gates LUT-4 Total Registers 139k 1.9k 4.4k 20 210k 2.7k 6.0k 24 476k 7.0k 15.1k 40 1.25M 15.3k 32.2k 90 Distributed RAM Bits SERDES Channels (850Mbps) PLLs User I/O 92k 30k 4 8 176 111k 43k 8 8 208 184k 112k 12 8 336 414k 246k 20 8 496 EBR RAM EBR RAM Blocks Bits 5 Bringing the Best Together Interface Product Lattice offers the world's fastest programmable interface products. Lattice Semiconductor pioneered the approach of putting ASIC macrocells and FPGA gates on the same silicon die. We call this a Field Programmable System Chip (FPSC). The embedded macrocells hold industry-standard Intellectual Property - bus interface, highspeed line interface, and high-speed transceiver cores. When these macrocells are combined with hundreds of thousands of programmable gates they can be used in a variety of advanced system designs. Aggregate Bandwidth Lattice Field Programmable System Chips and ispGDX2 Products ORT82G5 ORSO82G5 ORT42G5 ORSO42G5 ORLI10G ispGDX2 ORT8850L ORT8850H H Programmable Logic Gates In addition to the innovative FPSC products, Lattice delivers the high-speed line of ispGDX2 (insystem programmable Generic Digital Crosspoint) bus switching and interface products. These flexible devices offer low-cost SERDES solutions and high-performance bus switching. Lattice FPSC Families High Performance ORCA Series 4 based Field Programmable System Chips FPSC Functions - High-speed line interface - Programmable backplane transceiver - Serial backplane driver - SONET backplane transceiver sysCLOCK PLLs for Clock Management sysIO Capability for High Performance Interfacing - On-chip differential termination MPI and System Bus for Easy Connection to Microprocessor I/O ASIC Gates Provide cost effective, high-speed, pre-designed support logic ORCA Series 4 FPGA Gates Configurable I/O O FPSC Block Diagram Flexible sysIO Capability Single-ended (GTL+, HSTL, SSTL, etc.), Differential (LVDS, LVPECL), DDR I/O ASIC Gates ORT82G5/ORT42G5: 8b/10b encoding/decoding, multi-channel alignment logic, XAUI & Fibre Channel state machines SONET framing, SONET scrambling, payload processor ORT8850: SONET framing, SONET scrambling ORLI10G: High-speed MUX/deMUX FPSC Interface Devices FPSC Device 6 Data Rate per Channel SERDES Channels Encoding Support Standards Support FPSC Functionality FPGA Core ORT82G5 / ORT42G5 3.7 - 0.6 Gbps 8/4 8b/10b XAUI Fibre Channel, Gigabit Ethernet 8b/10b encoding XAUI & Fibre channel link state machines, multi-channel alignment 10,368 LUTS 643K Gates 372 / 204 I/O ORSO82G5 / ORSO42G5 2.7 - 0.6 Gbps 8/4 SONET SONET-based SERDES Links Pseudo-SONET framing, TOH insertion/extraction, multi-channel alignment, payload cell processor 10,368 LUTS 643K Gates 372 / 204 I/O ORT8850H 850 - 126 Mbps 8 SONET SONET-based SERDES Links Pseudo-SONET framing, TOH insertion/extraction, multi-channel alignment, pointer mover 16,192 LUTS 899K Gates 297 I/O ORT8850L 850 - 126 Mbps 8 SONET SONET-based SERDES Links Pseudo-SONET framing, TOH insertion/extraction, multi-channel alignment, pointer mover 4,992 LUTS 397K Gates 278 I/O ORLI10G 850 - 622 Mbps - OIF XSBI, OIF SFI-4 High speed MUX/deMUX 10,368 LUTS 643K Gates 316 I/O ts Superior SERDES Performance Lattice FPSC Devices Lattice sysHSI SERDES technology leads the programmable logic industry in terms of maximum bit rate and low jitter. The following eye diagram illustrates the outstanding characteristics of Lattice's sysHSI SERDES technology. ORT82G5 and ORT42G5 ORSO82G5 and ORSO42G5 The ORT82G5 provides eight 3.7 Gbps SERDES. Standard compliance and onchip link state machines make it ideal for implementing XAUI, 10 Gbps Ethernet and Fibre Channel links in chip-to-chip or backplane applications. The ORT42G5 offers four SERDES channels instead of eight. The ORSO82G5 includes eight 2.7 Gbps SERDES coupled with on-chip SONET framing. The ORSO82G5 provides an excellent SONET-based solution for chipto-chip or backplane applications. The ORSO42G5 offers four SERDES channels instead of eight. ORLI10G ORT8850 The ORLI10G provides a high-speed line interface with a flexible FPGA logic core. The ORLI10G can be used as the interface in a variety of emerging networks, including 10 Gbps SONET/SDH (OC192/STM-48), 10 Gbps optical transport networks (OTN) using digital wrapper and strong FEC, or 10 Gbps Ethernet. The ORT8850 includes eight 850 Mbps SERDES channels plus on-chip SONET framing. The ORT8850 provides an alternative to Ethernet technology for implementing chip-to-chip or backplane applications. ORT82G5 RX Eye Diagram over 40 inches (100 centimeters) of FR4 at 3.125 Gbps ispGDX2 Family of Digital Cross Point Switches ispGDX2 Features & Benefits High Performance Bus Switching - 13.6 Gbps (SERDES), 38 Gbps (without SERDES)* - Up to 16 (15x10) FIFOs for data buffering - I/O intensive: 64 to 256 I/Os sysCLOCK PLLs for Clock Management - Frequency synthesis and skew management - Clock shifting, multiply and divide capability - Jitter as low as 150 ps sysIO Capability for High Performance Interfacing - Hot socketing support - Leave alone I/O - holds pin state during programming Up to 16 Channels of 850 Mbps sysHSI SERDES - Serializer/de-serializer (SERDES) included - Built-in Clock Data Recovery (CDR) - 10b/12b and 8b/10b support Flexible Programming & Testing ispGDX2 Block Diagram sysIO Block SERDES GDX Block includes control logic and data multiplexers sysIO s O Block sIO SERDES FIFOs for buffering data streams (15x10 bits) FIFO FIFO GDX Block GDX Block PLL Global Routing Pool PLL Flexible routing optimized for bus switching sysIO Block sysHSI Block GDX Block GDX Block FIFO FIFO SERDES SERDES sysIO Block sysIO Block sysCLOCK PLLs for support: SSTL, HSTL, PCI, GTL+, LVCMOS 3.3, 2.5 and 1.8 sysHSI Block provides 2 duplex 850Mbps SERDES * Bandwidth assumes 50% of I/Os are inputs and 50% are outputs. ispGDX2 Families Fmax Bandwidth (SERDES) SERDES Bandwidth Data Rate Bus LVDS Channels (without SERDES) Per Channel (Pairs) (850Mbps) Family Member I/Os GDX Blocks ispGDX2-64 ispGDX2-128 ispGDX2-256 64 4 330 MHz 3.5 Gbps 11 Gbps 400-850 32 4 2 128 8 330 MHz 7.0 Gbps 21 Gbps 400-850 64 8 2 256 16 300 MHz 13.6 Gbps 38 Gbps 400-850 128 16 4 PLLs 7 Bringing the Best Together CPLD Products Through its optimized portfolio of CPLDs, Lattice provides products a generation ahead of other CPLD solutions. These architectures are optimized to fit a variety of CPLD design challenges. This contrasts to the "one size fits all" approach of other CPLD vendors. SuperFASTTM Performance Leadership - Up to 400 MHz Zero Power CPLD - As low as 20 A Standby Current SuperBIGTM Density Leadership - Up to 1024 macrocells SuperWIDETM Logic - 68-input logic blocks Multi-Function Block (MFB) Architecture combines memory, CAM and FIFO with logic Functionality Lattice ispXPLD and ispMACH CPLDs ispXPLD 5000MX ispMACH 5000 ispMACH 4000 Density Lattice pioneered the ispMACH 5000 architecture delivering SuperWIDE performance with 68 logic inputs and easy implementation of complex logic functions in a single level of logic. The new ispXPLD 5000MX family combines memory with Lattice's SuperWIDE architecture and SuperBIG density. The ispXPLD 5000MX family represents a new class of devices called eXpanded Programmable Logic Devices (XPLDs). These devices are built around a new building block, the Multi-Function Block (MFB). MFBs can be individually configured as SuperWIDE (136-input) logic, single- or dual-port memory, FIFO, or CAM depending on the application. This architecture delivers the ultimate PLD flexibility through ispXP. Lattice's ispMACH 4000 family is built on the industry's most advanced non-volatile CMOS process and delivers SuperFAST system performance for logic functions up to 36 inputs. The ispMACH 4000Z offers the industry's lowest power for handheld and other power-sensitive applications. Lattice's ispMACH 4000 family brings together high speed, low power and low cost to deliver the best solutions for a broad range of applications. Lattice's CPLD product portfolio offers commercial, industrial, automotive, and military grade devices. ispXPLD 5000MX Features and Benefits 8 ispXPLD 5000MX Block Diagram Flexible MFB Architecture - SuperWIDE logic, SuperBIG density sysIO Interfaces for ultra high - Arithmetic support speed I/Os. Supports SSTL, - Single- or Dual-Port RAM HSTL, PCI, GTL+, LVDS, - Asynchronous FIFO LVPECL, LVTTL, & LVCMOS. - Ternary CAM sysCLOCK PLLs for Clock Management sysIO Capability for High Performance Interfacing - Leave alone I/O - holds pin state during Global Routing Pool (GRP) programming provides flexible, - 5V tolerant inputs & I/Os deterministic routing In-system eXpanded Programming (ispXP) - Instant-on capability sysCLOCK PLLs - Single chip convenience - ISP via IEEE 1532 Interface - Infinitely reconfigurable via IEEE 1532 or sysCONFIGTM interface High Performance - 4.0 ns tPD pin-to-pin delays - 285 MHz fMAX Low Power Consumption - Static power as low as 20 mA Ease of Design - 3.3, 2.5 and 1.8V power supply operation Multi-Function Blocks (MFBs) are independently programmable as logic, single- or dual-port memory, FIFO, or CAM I/O Bank 0 sysIO sy sysIO I/O Bank 3 MFB M MFB MFB MFB ssysCLOCK PLL sysIO sysIO I/O Bank 1 Global Routing Pool sysIO sysCLOCK PLL MFB MFB MFB MFB ISP Port sysIO sysIO sysIO I/O Bank 2 ISP Port offers non-volatile, In-system programmability, and reconfigurability via sysCONFIG interface Output Routing Pool I/O Block 36 36 Global Routing Pool I/O Bank 0 16 16 36 36 120 Static ICC (A) 100 < 100 A 80 80% Power Reduction 60 40 20 20 A Lattice ispMACH 4032Z Competitive Device Generic Logic 16 Block I/O Block Generic 16 Logic Block I/O Bank power supply can be 1.8V, 2.5V or 3.3V. Input standard supported is independent of VCCO. I/O Bankk 1 Global Routing Pool (GRP) provides flexible, deterministic routing ispMACH 5000 Features and Benefits Lattice Offers Ultra-Low Power Consumption Generic Logic 16 Block Output Routing Pool 16 16 I/O Block Generic 16 Logic Block Output Routing Pool SuperFAST Performance - 2.5 ns tPD pin-to-pin delay - 400 MHz system performance Industry's Lowest Power Consumption - 1.8V core for low dynamic power - Low static current * 20 A max. (1.8V ispMACH 4000Z) * 1 - 3.5 mA (1.8V ispMACH 4000C) Ease of Design - In-system programmable * IEEE 1149.1, IEEE 1532 compliant - Flexible I/O support * 2 I/O banks with independent VCCO and GND * Leave alone I/O - holds pin state during programming * LVTTL, LVCMOS 1.8, 2.5, 3.3 * 5V tolerant inputs and I/Os * Hot socketing support Automotive Temperature Devices - Broadest density range: 32 to 256 macrocells - Available for 3.3V (4000V) and 1.8V (4000Z) power supply - 7.5 ns tPD pin-to-pin delay - 168 MHz system performance I/O Block ispMACH 4000 Block Diagram Output Routing Pool ispMACH 4000 Features and Benefits World's Fastest and Smallest PLD SuperWIDE Performance - 68 Inputs / 32 macrocells per logic block - 3.0 ns tPD pin-to-pin delay - 275 MHz system performance sysIO Capability for High Performance interfacing - Leave alone I/O - holds pin state during programming - 5V tolerant inputs & I/Os Ease of Design - In-system programmable * IEEE 1149.1, IEEE 1532 compliant - 2.5V power supply operation - Hot socketing support Lattice's ispGAL22V10A device takes board-space savings and speed to a new level. This high performance device brings together the best features in one tiny package. 2.3 ns / 455 MHz Speed 150 A Standby Current 5 x 5 mm QFN Package In-System Programmable XPLD and CPLD Device Families Power Supply Family Macrocells User I/O Options tPD (ns) fMAX (MHz) Logic Block Inputs Memory Kbits Standby Current 1.8V ispXPLD 5000MC ispMACH 4000C ispMACH 4000Z 256 - 1024 32 - 512 32 - 128 141 - 381 30 - 208 32 - 92 4.0 2.5 3.5 285 400 265 68 36 36 128-512 -- -- 20 mA 1.8 mA 20 A (Max.) 2.5V ispXPLD 5000MB ispMACH 5000B ispMACH 4000B 256 - 1024 128 - 512 32 - 512 141 - 381 92 - 256 30 - 208 4.0 3.0 2.5 285 275 400 68 68 36 128-512 -- -- 30 mA 83 mA 11.3 mA 3.3V ispXPLD 5000MV ispLSI 5000VE ispMACH 4000V 256 - 1024 128 - 512 32 - 512 141 - 381 72 - 256 30 - 208 4.0 5.0 2.5 285 180 400 68 68 36 128-512 -- -- 30 mA 100 mA 11.3 mA 32 - 256 32 - 128 5.0 182 36 -- 20 mA 5V ispMACH 4A5 9 Bringing the Best Together Analog Products Programmable Analog & Mixed Signal Devices Impossible was never so easy! Lattice delivers in-system programmable analog ICs (ispPAC) and the new Programmable Mixed Signal devices ... ispPAC Power Manager. Bringing the Best Together: Integrating in-system programmable analog and digital components on a single chip, the ispPAC Power Manager devices provide complete monitoring and sequencing control of power supplies on your circuit board. ispPAC Power Manager Block Diagram ispPAC Design Tools Lattice provides a complete set of tools for rapidly implementing analog and mixed signal designs. PAC-Designer Software Allows Intuitive Point & Click Design entry * Board power supply management * Adaptive analog front ends * Continuous-time filters from 5th order down * Flexible feedback control loops Simulation for Analog and Mixed Signal Designs Evaluation Boards for Rapid Prototyping Programmable Power Supply Monitor Simultaneously monitor up to 12 power supplies without discrete components Charge Pumped FET Drive with Digital Output Flexible Power supply sequencing through MOSFETS, Bricks, and LDOs System-level control for system reset and front panel shut-down CPLD Digital Signal Monitor Programmable Function Digital Output Supervisory signal generation controls CPU_RESET, Power_Good, Supply_Interrupt, etc. Basic timing generation, control sequence delay, and watchdog timer Internal Oscillatorr & Timers ispPAC Power Manager Devices Power Supply Sense Inputs Supervisory Outputs FET Drivers/ Digital Outputs Reprogrammable Timers CPLD Macrocells Power1208 12 4 4 4 16 Power604 6 4 -- 2 8 Device ispPAC Device Block Diagrams IA Vref1 OA IA IA Analog Routing Pool IA CP OA IA IA IA OA IA CP OA IA Reference MDAC IA IA DAC IA Auto-Cal OA IA PAC-Designer software's easy-to-use GUI E2CMOS Mem IA MDAC Reference E2CMOS Mem Auto-Cal ISP Control ISP Control Vref2 Summation Routing Pool OA IA Input/Output Routing Pool IA OA Filter Amplify Integrate Compare OA Filter Amplify Integrate Compare Analog Routing Pool JTAG/SPI Interface Logic & Configuration Memory ispPAC10 ispPAC20 Fully-Integrated, All-in-One, ISP, Fifth-Order Low Pass Filter Auto-Calibration IA OA 5th Order LPF E2CMOS Cfg A E2CMOS Cfg B Ref & Auto-Cal ISP Control 2.5V Reference ispPAC30 ispPAC80/81 ispPAC Device Families Device Power Manager and ispPAC Evaluation boards enable fast prototyping. 10 Filters Control Loop Sensor Interface Data Acquisition ispPAC10 -- -- ispPAC20 ispPAC30 -- ispPAC80/81 -- -- Bringing the Best Together ispLEVER The Simple Machine for Complex Design Lattice's ispLEVER is an advanced programmable logic design tool equipped to provide a complete system for FPGA, FPSC, CPLD, XPLD, ispGDX(R), and SPLD design. ispLEVER includes a fully integrated, push-button design environment, and advanced features for interactive design optimization and debug. ispLEVER Design Tools Features Integrated ModelSim(R) RTL Simulator Integrated Mentor Graphics(R) and Synplicity(R) Synthesis VHDL, Verilog, and ABEL Language Support Module Generator / IP Manager Comprehensive Constraints / Pin Editor Floorplanner for FPGA / FPSC Static Timing Analyzer Integrated Timing and Functional Simulator HTML Reporting Integrated ispVM(R) Programming Software Automated ispUPDATETM Utility PC and UNIX Versions Design Tools Intellectual Property Lattice offers an expanding range of IP cores (ispLeverCORETM IP modules) to support easy integration of commonly used complex functions for: Communications - UTOPIA - POS-PHY3 - Fast 10/100 Ethernet MAC - Gigabit Ethernet MAC - 10 Gigabit PCS Bus Interface - PCI Target Memory Control - DDR SDRAM Controller - Multi-channel DMA Controller Digital Signal Processing - Reed Solomon Encoder - Convolutional Encoder Additional cores are in progress. Check the Lattice website for details and schedules. Evaluation and Programming Hardware Project Navigator Evaluation boards are offered to allow users to evaluate, test, and perform design debug for a variety of Lattice devices and include: EV Board Download Cable Board Schematics Gerber Files Users Manual Constraints Editor Floorplanner ispLEVER Design Tools Package Part Number FPGA Starter Downloadable Base LS-HDL-BASE-PC-N Advanced LS-EXM-ADV-PC-F LS-HDL-ADV-PC-N LS-ADV-WS-F FPSC CPLD GDX/2 SPLD LeoSpec Synplify(R) ModelSim Synthesis Synthesis Simulation Lattice also offers a wide range of programming cables, desktop programmers, and adapters for advanced packages: ispDOWNLOAD(R) Cables - Parallel (1 x 8, 2 x 5, Flywire) - USB (Flywire) Model 300 Desktop Programmer and Adapters 11 Lattice Semiconductor Corporation 5555 Northeast Moore Court Hillsboro, Oregon 97124 U.S.A. Telephone: (503) 268-8000 * FAX: (503) 268-8556 Applications & Literature Hotline: 1-800-LATTICE www.latticesemi.com Copyright (c) 2003 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), E2CMOS, ISP, ispDOWNLOAD, ispGAL, ispGDX, ispLEVER, ispLeverCORE, ispMACH, ispPAC, ispVM, ispXP, ispXPGA, ispXPLD, ORCA, PAC-Designer, SuperBIG, SuperFAST, SuperWIDE, sysCLOCK, sysCONFIG, sysHSI, sysIO and sysMEM are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. March 2003 Order #: I0156