LMK048xx Evaluation Board User's Guide August 2011 SNAU076B Revised August 2014 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs Evaluation Board Operating Instructions 2 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Table of Contents TABLE OF CONTENTS ..............................................................................................................................................................3 GENERAL DESCRIPTION ..........................................................................................................................................................5 EVALUATION BOARD KIT CONTENTS ...................................................................................................................................................5 AVAILABLE LMK048XX EVALUATION BOARDS ......................................................................................................................................5 AVAILABLE LMK04800 FAMILY DEVICES ............................................................................................................................................5 QUICK START ..........................................................................................................................................................................6 DEFAULT CODELOADER MODES FOR EVALUATION BOARDS .....................................................................................................................7 EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04808B ............................................................................................8 1. START CODELOADER 4 APPLICATION ...............................................................................................................................................8 2. SELECT DEVICE............................................................................................................................................................................8 3. PROGRAM/LOAD DEVICE ..............................................................................................................................................................8 4. RESTORING A DEFAULT MODE .......................................................................................................................................................9 5. VISUAL CONFIRMATION OF FREQUENCY LOCK .................................................................................................................................10 6. ENABLE CLOCK OUTPUTS ............................................................................................................................................................10 PLL LOOP FILTERS AND LOOP PARAMETERS .........................................................................................................................12 PLL 1 LOOP FILTER .......................................................................................................................................................................12 122.88 MHz VCXO PLL .........................................................................................................................................................12 PLL2 LOOP FILTER ........................................................................................................................................................................13 Integrated VCO PLL .............................................................................................................................................................13 EVALUATION BOARD INPUTS AND OUTPUTS........................................................................................................................14 RECOMMENDED TEST EQUIPMENT ......................................................................................................................................22 PROGRAMMING 0-DELAY MODE IN CODELOADER ...............................................................................................................23 OVERVIEW...................................................................................................................................................................................23 DUAL LOOP 0-DELAY MODE EXAMPLES ............................................................................................................................................23 Programming Steps .............................................................................................................................................................23 Details .................................................................................................................................................................................23 SINGLE LOOP 0-DELAY MODE EXAMPLES ..........................................................................................................................................25 Programming Steps .............................................................................................................................................................25 Details .................................................................................................................................................................................25 APPENDIX A: CODELOADER USAGE.......................................................................................................................................27 PORT SETUP TAB ..........................................................................................................................................................................27 CLOCK OUTPUTS TAB.....................................................................................................................................................................28 PLL1 TAB ....................................................................................................................................................................................30 Setting the PLL1 VCO Frequency and PLL2 Reference Frequency ........................................................................................31 PLL2 TAB ....................................................................................................................................................................................32 BITS/PINS TAB .............................................................................................................................................................................33 REGISTERS TAB .............................................................................................................................................................................38 APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS..................................................................................................39 PLL1 ..........................................................................................................................................................................................39 122.88 MHz VCXO Phase Noise ...........................................................................................................................................39 Clock Output Measurement Technique ...............................................................................................................................40 Buffered OSCout Phase Noise ..............................................................................................................................................40 Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 3 CLOCK OUTPUTS (CLKOUT) ............................................................................................................................................................41 LMK04808B CLKout Phase Noise .........................................................................................................................................41 LMK04808B OSCout Phase Noise ........................................................................................................................................43 LMK04806B CLKout Phase Noise .........................................................................................................................................44 LMK04806B OSCout Phase Noise ........................................................................................................................................46 LMK04803B CLKout Phase Noise .........................................................................................................................................47 LMK04803B OSCout Phase Noise ........................................................................................................................................49 APPENDIX C: SCHEMATICS .................................................................................................................................................... 50 POWER SUPPLIES ..........................................................................................................................................................................50 LMK048XXB DEVICE WITH LOOP FILTER AND CRYSTAL CIRCUITS ...........................................................................................................51 REFERENCE INPUTS (CLKIN0 & CLKIN1), EXTERNAL VCXO (OSCIN) & VCO CIRCUITS, AND OSCOUT1 OUTPUT...........................................52 CLOCK OUTPUTS (OSCOUT0, CLKOUT0 TO CLKOUT3)........................................................................................................................53 CLOCK OUTPUTS (CLKOUT4 TO CLKOUT7)........................................................................................................................................54 CLOCK OUTPUTS (CLKOUT8 TO CLKOUT11)......................................................................................................................................55 UWIRE HEADER, LOGIC I/O PORTS AND STATUS LEDS ......................................................................................................................... 56 USB INTERFACE............................................................................................................................................................................57 APPENDIX D: BILL OF MATERIALS .........................................................................................................................................58 APPENDIX E: PCB LAYERS STACKUP .....................................................................................................................................68 APPENDIX F: PCB LAYOUT ..................................................................................................................................................... 69 LAYER #1 - TOP ...........................................................................................................................................................................69 LAYER #2 - RF GROUND PLANE (INVERTED) ......................................................................................................................................70 LAYER #3 - VCC PLANES ................................................................................................................................................................71 LAYER #4 - GROUND PLANE (INVERTED) ...........................................................................................................................................72 LAYER # 5 - VCC PLANES 2 .............................................................................................................................................................73 LAYER #6 - BOTTOM .....................................................................................................................................................................74 LAYERS #1 AND 6 - TOP AND BOTTOM (COMPOSITE) ..........................................................................................................................75 APPENDIX G: EVM SOFTWARE AND COMMUNICATION: INTERFACING UWIRE.....................................................................76 APPENDIX H: TROUBLESHOOTING INFORMATION ................................................................................................................78 1) 2) 3) CONFIRM COMMUNICATIONS ................................................................................................................................................78 CONFIRM PLL1 OPERATION/LOCKING .....................................................................................................................................78 CONFIRM PLL2 OPERATION/LOCKING .....................................................................................................................................79 4 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 General Description The LMK048xx Evaluation Board simplifies evaluation of the LMK048xxB Low-Noise Clock Jitter Cleaner with Dual Loop PLLs. Texas Instruments Incorporated's CodeLoader software can be used to program the internal registers of the LMK048xxB device through the USB2ANY-uWire interface. The CodeLoader software will run on a Windows 7 or Windows XP PC and can be downloaded from http://www.ti.com/tool/codeloader/. Evaluation Board Kit Contents The evaluation board kit includes: * (1) LMK048xx Evaluation Board from Table 1 * (1) LMK04800 Family Quick Start Guide o Evaluation board instructions can be downloaded from www.ti.com. * (1) LPT Cable or USB2ANY-uWire (HPA665-001) + adapter (Please see "EVM Software and Communication" for more information) Available LMK048xx Evaluation Boards The LMK048xx Evaluation Board supports any of the four devices offered in the LMK04800 Family. All evaluation boards use the same PCB layout and bill-of-materials, except for the corresponding LMK0480xxB device affixed to the board. A commercial-quality VCXO is also mounted to the board to provide a known reference point for evaluating device performance and functionality. Table 1: Available Evaluation Board Configurations Evaluation Board ID LMK04803BEVAL LMK04805BEVAL LMK04806BEVAL LMK04808BEVAL Device LMK04803B LMK04805B LMK04806B LMK04808B PLL1 VCXO 122.88 MHz Crystek VCXO Model CVHD-950-122.880 Available LMK04800 Family Devices Table 2: LMK048xxB Devices Device LMK04803B LMK04805B LMK04806B LMK04808B Reference Inputs 2 Revised - August 2014 Buffered/ Divided OSCin Outputs Programmable LVDS/LVPECL/ LVCMOS Outputs VCO Frequency 12 1840 to 2030 MHz 2148 to 2370 MHz 2370 to 2600 MHz 2750 to 3072 MHz 2 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 5 Quick Start Full evaluation board instructions are downloadable from the LMK048xxB device product folder at www.ti.com. 1. Connect a power supply voltage of 5 V to the Vcc SMA connector. The onboard LP3878-ADJ LDO regulator will output a low-noise 3.3 V supply to operate the device. 2. Connect a reference clock from a signal source to the CLKin1 SMA port. Use 122.88 MHz for default. The reference frequency depends on the device programming. 3. Please see Appendix G for quick start on interfacing the board 4. Program the device with a default mode using CodeLoader. Ctrl+L must be pressed at least once to load all registers. Alternatively click menu "Keyboard Controls" "Load Device". CodeLoader can be downloaded from http://www.ti.com/tool/codeloader. 5. Measurements may be made on an active output clock port via its SMA connector. Figure 1: Quick Start Diagram 6 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Default CodeLoader Modes for Evaluation Boards CodeLoader saves the state of the selected LMK048xxB device when exiting the software. To ensure a common starting point, the following modes listed in Table 3 may be restored by clicking "Mode" and selecting the appropriate device configuration, as shown in Figure 2 in the case of the LMK04808B device. Similar default modes are available for each LMK048xxB device in CodeLoader. Choose a mode with CLKin0 for differential clock signal or CLKin1 for a single ended signal. Figure 2: Selecting a Default Mode for the LMK04808 Device After restoring a default mode, press Ctrl+L to program the device. The default modes also disable certain outputs, so make sure to enable the output under test to make measurements. Table 3: Default CodeLoader Modes for LMK04808 Default CodeLoader Mode 122.88 MHz CLKin1, 122.88 MHz VCXO 122.88 MHz CLKin1, Dual Loop 0delay, 122.88 MHz VCXO 122.88 MHz CLKin1, 122.88 MHz VCXO 122.88 MHz CLKin1, 122.88 MHz VCXO 122.88 MHz CLKin1, Dual Loop 0delay, 122.88 MHz VCXO 122.88 MHz CLKin1, 122.88 MHz VCXO Device Mode CLKin Frequency OSCin Frequency Dual PLL, Internal VCO 122.88 MHz 122.88 MHz 122.88 MHz 122.88 MHz 122.88 MHz 20.48 MHz 122.88 MHz 122.88 MHz 122.88 MHz 122.88 MHz 122.88 MHz 20.48 MHz Dual PLL, Internal VCO, 0-Delay with Internal Feedback Dual PLL, Internal VCO, PLL2 Crystal Oscillator Enabled Dual PLL, Internal VCO Dual PLL, Internal VCO, 0-Delay with Internal Feedback Dual PLL, Internal VCO, PLL2 Crystal Oscillator Enabled The next section outlines step-by-step procedures for using the evaluation board with the LMK04808B. For boards with another part number, make sure to select the corresponding part number under the "Device" menu. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 7 Example: Using CodeLoader to Program the LMK04808B The purpose of this section is to walk the user through using CodeLoader 4 to make some measurements with the LMK04808B device as an example. For more information on CodeLoader refer to Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at http://www.ti.com/tool/codeloader. Before proceeding, be sure to follow the Quick Start section above to ensure proper connections. 1. Start CodeLoader 4 Application Click "Start" "Programs" "CodeLoader 4" "CodeLoader 4" The CodeLoader 4 program is installed by default to the CodeLoader 4 application group. 2. Select Device Click "Select Device" "Clock Conditioners" "LMK04808B" Once started CodeLoader 4 will load the last used device. To load a new device click "Select Device" from the menu bar, then select the subgroup and finally device to load. For this example, the LMK04808B is chosen. Selecting the device does cause the device to be programmed. Figure 3 - Selecting the LMK04808B device 8 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 3. Program/Load Device Assuming the Port Setup settings are correct, press the "Ctrl+L" shortcut or click "Keyboard Controls" Device" from the menu to program the device to the current state of the newly loaded LMK04800 file. "Load Once the device has been initially loaded, CodeLoader will automatically program changed registers so it is not Figure 4 - Loading the Device necessary to re-load the device upon subsequent changes in the device configuration. It is possible to disable this functionality by ensuring there is no checkmark by the "Options" "AutoReload with Changes." Because a default mode will be restored in the next step, this step isn't really needed but included to emphasize the importance of pressing "Ctrl+L" to load the device at least once after starting CodeLoader, restoring a mode, or restoring a saved setup using the File menu. See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at http://www.ti.com/tool/codeloader for more information on Port Setup. Appendix H: Troubleshooting Information contains information on troubleshooting communications. 4. Restoring a Default Mode Click "Mode" "LMK04808B, 122.88 MHz VCXO, 122.88 MHz CLKin1"; then press Ctrl+L. Figure 5: Setting the Default mode for LMK04808 For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point. This is important because when CodeLoader is closed, it remembers the last settings used for a particular device. Again, remember to press Ctrl+L as the first step after loading a default mode. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 9 5. Visual Confirmation of Frequency Lock After a default mode is restored and loaded, LED D5 should illuminate when PLL1 and PLL2 are locked to the reference clock applied to CLKin1. This assumes LD_MUX = PLL1/2 DLD and LD_TYPE = Active High, which are the default settings. 6. Enable Clock Outputs While the LMK048xxB offers programmable clock output buffer formats, the evaluation board is shipped with preconfigured output terminations to match the default buffer type for each output. Refer to the CLKout port description in the Evaluation Board Inputs and Outputs section. To measure phase noise at one of the clock outputs, for example, CLKout0: 1. Click on the Clock Outputs tab, 2. Uncheck "Powerdown" in the Digital Delay box to enable the channel, 3. Set the following settings as needed: a. Digital Delay value b. Clock Divider value c. Analog Delay select and Analog Delay value (if not "Bypassed") d. Clock Output type. Figure 6: Setting Digital Delay, Clock Divider, Analog Delay, and Output Format for CLKout0 4. Depending on the configured output type, the clock output SMAs can be interfaced to a test instrument with a single-ended 50-ohm input as follows. a. For LVDS: i. A balun (like ADT2-1T) is recommended for differential-to-single-ended conversion. b. For LVPECL: i. A balun can be used, or ii. One side of the LVPECL signal can be terminated with a 50-ohm load and the other side can be run single-ended to the instrument. c. For LVCMOS: i. There are two single-ended outputs, CLKoutX and CLKoutX*, and each output can be set to Normal, Inverted, or Off. There are nine (9) combinations of LVCMOS modes in the Clock Output list. ii. One side of the LVCMOS signal can be terminated with a 50-ohm load and the other side can be run single-ended to the instrument. iii. A balun may also be used. Ensure Figure 7: Setting LVCMOS modes CLKoutX and CLKoutX* states are 10 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 complementary to each other, i.e.: Norm/Inv or Inv/Norm. 5. The phase noise may be measured with a spectrum analyzer or signal source analyzer. See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock outputs. Texas Instruments Incorporated's Clock Design Tool can be used to calculate divider values to achieve desired clock output frequencies. See: http://www.ti.com/tool/clockdesigntool. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 11 PLL Loop Filters and Loop Parameters In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL's purpose is to substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for the phase noise of a "dirty" reference clock. The first PLL is typically configured with a narrow loop bandwidth in order to minimize the impact of the reference clock phase noise. The reference clock consequently serves only as a frequency reference rather than a phase reference. The loop filters on the LMK048xx evaluation board are setup using the approach above. The loop filter for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop filter of PLL2 has been configured for a wide loop bandwidth (> 100 kHz). The specific loop bandwidth values depend on the phase noise performance of the oscillator mounted on the board. The following tables contain the parameters for PLL1 and PLL2 for each oscillator option. Texas Instruments Incorporated's Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications. See: http://www.ti.com/tool/clockdesigntool/. PLL 1 Loop Filter Table 4: PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO 122.88 MHz VCXO PLL Phase Margin Loop Bandwidth 49 12 Hz K (Charge Pump) Phase Detector Freq VCO Gain 2.5 kHz/Volt 100 uA 1.024 MHz Reference Clock Frequency 122.88 MHz Output Frequency 122.88 MHz (To PLL 2) Loop Filter Components C1_A1 = 100 nF C2_A1 = 680 nF R2_A1 = 39 k Note: PLL Loop Bandwidth is a function of K, Kvco, N as well as loop components. Changing K and N will change the loop bandwidth. 12 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 PLL2 Loop Filter Table 5: PLL2 Loop Filter Parameters for LMK048xxB Integrated VCO PLL LMK04803B C1_A2 C2_A2 C3 (internal) C4 (internal) R2_A2 R3 (internal) R4 (internal) Charge Pump Current, K Phase Detector Frequency Frequency Kvco N Phase Margin Loop Bandwidth LMK04805B LMK04806B 0.047 3.9 0 0 0.62 0.2 0.2 LMK04808B nF nF nF nF k k k 3.2 mA 122.88 MHz 1966.08 17.9 16 75 2211.84 16.5 18 75 2457.6 18.8 20 75 2949.12 32.3 24 76 MHz MHz/V 355 320 321 424 kHz degrees Note: PLL Loop Bandwidth is a function of K, Kvco, N as well as loop components. Changing K and N will change the loop bandwidth. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 13 Evaluation Board Inputs and Outputs The following table contains descriptions of the inputs and outputs for the evaluation board. Unless otherwise noted, the connectors described can be assumed to be populated by default. Additionally, some applicable CodeLoader programming controls are noted for convenience. Refer to the LMK04800 Family Datasheet for complete register programming information. Table 6: Evaluation Board Inputs and Outputs Connector Name Signal Type, Input/Output Description Clock outputs with programmable output buffers. The output terminations by default on the evaluation board are shown below, and the output type selected by default in CodeLoader is indicated by an asterisk (*): Clock output pair Populated: CLKout0, CLKout0*, CLKout2, CLKout2*, CLKout4, CLKout4*, CLKout6, CLKout6*, CLKout8, CLKout8*, CLKout10, CLKout10* Not Populated: CLKout1, CLKout1*, CLKout3, CLKout3*, CLKout5, CLKout5*, CLKout7, CLKout7*, CLKout9, CLKout9*, CLKout11, CLKout11* Analog, Output CLKout0 CLKout1 CLKout2 CLKout3 CLKout4 CLKout5 CLKout6 CLKout7 CLKout8 CLKout9 CLKout10 CLKout11 Default Board Termination LVPECL* LVPECL LVPECL* LVPECL LVDS* / LVCMOS LVDS / LVCMOS LVDS* / LVCMOS LVDS / LVCMOS LVDS* / LVCMOS LVDS / LVCMOS LVPECL* LVPECL Each CLKout pair has a programmable LVDS, LVPECL, or LVCMOS buffer. The output buffer type can be selected in CodeLoader in the Clock Outputs tab via the CLKoutX_TYPE control. All clock outputs are AC-coupled to allow safe testing with RF test equipment. All LVPECL clock outputs are source-terminated using 240-ohm resistors. If an output pair is programmed to LVCMOS, each output can be independently configured (normal, inverted, or off/tri-state). 14 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Connector Name Signal Type, Input/Output Description Buffered outputs of OSCin port. The output terminations on the evaluation board are shown below, the output type selected by default in CodeLoader is indicated by an asterisk (*): Default Board OSC output pair Termination OSCout0 LVDS* / LVCMOS OSCout1 LVPECL* (fixed) Populated: OSCout0, OSCout0*, OSCout1, OSCout1* Analog, Output Only OSCout0 has a programmable LVDS, LVPECL, or LVCMOS output buffer. The OSCout0 buffer type can be selected in CodeLoader on the Clock Outputs tab via the OSCout0_TYPE control. OSCout1 has LVPECL buffer only but has programmable swing amplitude. Both OSCout pairs are AC-coupled to allow safe testing with RF test equipment. The OSCout1 output is source-terminated using 240ohm resistors. If OSCout0 is programmed as LVCMOS, each output can be independently configured (normal, inverted, inverted, and off/tri-state). Main power supply input for the evaluation board. A 3.9 V DC power source applied to this SMA will, by default, source the onboard LDO regulators that power the inner layer planes that supply the LMK048xxB and its auxiliary circuits (e.g. VCXO). Vcc Power, Input The LMK048xxB contains internal voltage regulators for the VCO, PLL and other internal blocks. The clock outputs do not have an internal regulator, so a clean power supply with sufficient output current capability is required for optimal performance. On-board LDO regulators and 0 resistor options provide flexibility to supply and route power to various devices. See schematics for more details. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 15 Connector Name Signal Type, Input/Output Populated: J1 Power, Input Populated: VccVCO/Aux Power, Input Populated: VccVCXO/Aux Power, Input 16 SNAU076B Description Alternative power supply input for the evaluation board using two unshielded wires (Vcc and GND). Apply power to either Vcc SMA or J1, but not both. Optional Vcc input to power the VCO circuit if separated voltage rails are needed. The VccVCO/Aux input can power these circuits directly or supply the onboard LDO regulators. 0 resistor options provide flexibility to route power. Optional Vcc input to power the VCXO circuit if separated voltage rails are needed. The VccVCXO/Aux input can power these circuits directly or supply the on-board LDO regulators. 0 resistor options provide flexibility to route power. LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Connector Name Signal Type, Input/Output Description Reference Clock Inputs for PLL1 (CLKin0, 1). CLKin1 can alternatively be used as an External Feedback Clock Input (FBCLKin) in 0-delay mode or an RF Input (Fin) in External VCO mode. Reference Clock Inputs for PLL1 (CLKin0, 1) FBCLKin/CLKin1* is configured by default for a single-ended reference clock input from a 50-ohm source. The non-driven input pin (FBCLKin/CLKin1) is connected to GND with a 0.1 uF. CLKin0/CLKin0* is configured by default for a differential reference clock input from a 50-ohm source. Populated: CLKin0, CLKin0*, FBCLKin*/CLKin1* Not Populated: FBCLKin/CLKin1 CLKin1* is the default reference clock input selected in CodeLoader. The clock input selection mode can be programmed on the Bits/Pins tab via the CLKin_Select_MODE control. Refer to the LMK04800 Family Datasheet section "Input Clock Switching" for more information. Analog, Input AC coupled Input Clock Swing Levels Input Mode Min Max Differential Bipolar or 0.5 3.1 CMOS Single Ended 0.25 2.4 Units Vpp Vpp External Feedback Input (FBCLKin) for 0-Delay CLKin1 is shared for use with FBCLKin as an external feedback clock input to PLL1 for 0-delay mode. See section, Programming 0-Delay Mode in CodeLoader below, for more details on using 0-delay mode with the evaluation board and the evaluation board software. RF Input (Fin) for External VCO CLKin1 is also shared for use with Fin as an RF input for external VCO mode using the onboard VCO footprint (U3) or add-on VCO board. To enable Dual PLL mode with External VCO, the following registers must be properly configured in CodeLoader: * MODE = (3) Dual PLL, Ext VCO (Fin), (5) Dual PLL, Ext VCO, 0-Delay, (11) PLL2, Ext VCO (Fin) Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 17 Connector Name Signal Type, Input/Output Description Feedback VCXO clock input to PLL1 and Reference clock input to PLL2. By default, these SMAs are not connected to the traces going to the OSCin/OSCin* pins of the LMK048xxB. Instead, the single-ended output of the onboard VCXO (U2) drives the OSCin* input of the device and the OSCin input of the device is connected to GND with 0.1 uF. Not populated: OSCin, OSCin* Analog, Input A VCXO add-on board may be optionally attached via these SMA connectors with minor modification to the components going to the OSCin/OSCin* pins of device. This is useful if the VCXO footprint does not accommodate the desired VCXO device. A single-ended or differential signal may be used to drive the OSCin/OSCin* pins and must be AC coupled. If operated in single-ended mode, the unused input must be connected to GND with 0.1 uF. Test point: VTUNE1_TP Not populated: Vtune1 Test point: VTUNE2_TP Refer to the LMK04800 Family Datasheet section "Electrical Characteristics" for PLL2 Reference Input (OSCin) specifications. Tuning voltage output from the loop filter for PLL1. Analog, Output Analog, Output If a VCXO add-on board is used, this tuning voltage can be connected to the voltage control pin of the external VCXO when this SMA connector is installed and connected through R72 by the user. Tuning voltage output from the loop filter for PLL2. 10-pin header for uWire programming interface and programmable logic I/O pins for the LMK048xxB. Populated: uWire Test points: DATAuWire_TP CLKuWIRE_TP LEuWIRE_TP 18 SNAU076B CMOS, Input/Output The uWire interface includes CLKuWire, DATAuWire, and LEuWire signals. The programmable logic I/O signals accessible through this header include: SYNC, Status_Holdover, Status_LD, Status_CLKin0, and Status_CLKin1. These logic I/O signals also have dedicated SMAs and test points. LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Connector Name Signal Type, Input/Output Description Programmable status output pin. By default, set to output the digital lock detect status signal for PLL1 and PLL2 combined. In the default CodeLoader modes, LED D5 will illuminate green when PLL lock is detected by the LMK048xxB (output is high) and turn off when lock is lost (output is low). Test point: LD_TP Not populated: Status_LD CMOS, Output The status output signal for the Status_LD pin can be selected on the Bits/Pins tab via the LD_MUX control. Refer to the LMK04800 Family Datasheet section "Status Pins" and "Digital Lock Detect" for more information. Note: Before a high-frequency internal signal (e.g. PLL divider output signal) is selected by LD_MUX, it is suggested to first remove the 270 ohm resistor to prevent the LED from loading the output. Programmable status output pin. By default, set to the output holdover mode status signal. In the default CodeLoader mode, LED D8 will illuminate red when holdover mode is active (output is high) and turn off when holdover mode is not active (output is low). Test point: Holdover_TP Not populated: Status_Hold CMOS, Output The status output signal for the Status_Holdover pin can be selected on the Bits/Pins tab via the HOLDOVER_MUX control. Refer to the LMK04800 Family Datasheet section "Status Pins" and "Holdover Mode" for more information. Note: Before a high-frequency internal signal (e.g. PLL divider output signal) is selected by HOLDOVER_MUX, it is suggested to first remove the 270 ohm resistor to prevent the LED from loading the output. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 19 Connector Name Signal Type, Input/Output Description Programmable status I/O pins. By default, set as input pins for controlling input clock switching of CLKin0 and CLKin1. These inputs will not be functional because CLKin_Select_MODE is set to 0 (CLKin0 Manual) by default in the Bits/Pins tab in CodeLoader. To enable input clock switching, CLKin_Select_MODE must be 3 or 6 and Status_CLKinX_TYPE must be 0 to 3 (pin enabled as an input). Test point: CLKin0_SEL_TP CLKin1_SEL_TP Not populated: Status_CLKin0, Status_CLKin1 Input Clock Switching - Pin Select Mode When CLKin_SELECT_MODE is 3, the Status_CLKinX pins select which clock input is active as follows: Status_CLKin1 Status_CLKin0 Active Clock 0 0 CLKin0 0 1 CLKin1 1 0 Reserved 1 1 Holdover CMOS, Input/Output Input Clock Switching - Auto with Pin Select When CLKin_SELECT_MODE is 6, the active clock is selected using the Status_CLKinX pins upon an input clock switch event as follows: Active Status_CLKin1 Status_CLKin0 Clock X 0 CLKin0 1 0 CLKin1 0 0 Reserved Refer to the LMK04800 Family Datasheet section "Input Clock Switching" for more information. Status Outputs When Status_CLKinX_TYPE is 3 to 6 (pin enabled as an output), the status output signal for the corresponding Status_CLKinX pin can be programmed on the Bits/Pins tab via the Status_CLKinX_MUX control. Refer to the LMK04800 Family Datasheet section "Status Pins" for more information. 20 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Connector Name Signal Type, Input/Output Description Programmable status I/O pin. By default, set as an input pin for synchronize the clock outputs with a fixed and known phase relationship between each clock output selected for SYNC. A SYNC event also causes the digital delay values to take effect. Test point: SYNC_TP Not populated: SYNC CMOS, Input/Output In the default CodeLoader mode, SYNC will asserted when the SYNC pin is low and the outputs to be synchronized will be held in a logic low state. When SYNC is unasserted, the clock outputs to be synchronized are activated and will be initially phase aligned with each other except for outputs programmed with different digital delay values. A SYNC event can also be programmed by toggling the SYNC_POL_INV bit in the Bits/Pins tab in CodeLoader. Refer to the LMK04800 Family Datasheet section "Clock Output Synchronization" for more information. Status Output When SYNC_MUX is 3 to 6 (pin enabled as output), a status signal for the SYNC pin can be selected on the Bits/Pins tab via the SYNC_MUX control. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 21 Recommended Test Equipment Power Supply The Power Supply should be a low noise power supply, particularly when the devices on the board are being directly powered (onboard LDO regulators bypassed). Phase Noise / Spectrum Analyzer To measure phase noise and RMS jitter, an Agilent E5052 Signal Source Analyzer is recommended. An Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the architecture of the E5052 is superior for phase noise measurements. At frequencies less than 100 MHz the local oscillator noise of the E4445A is too high and measurements will reflect the E4445A's internal local oscillator performance, not the device under test. Oscilloscope To measure the output clocks for AC performance, such as rise time or fall time, propagation delay, or skew, it is suggested to use a real-time oscilloscope with at least 1 GHz analog input bandwidth (2.5+ GHz recommended) with 50 ohm inputs and 10+ Gsps sample rate. To evaluate clock synchronization or phase alignment between multiple clock outputs, it's recommended to use phase-matched, 50-ohm cables to minimize external sources of skew or other errors/distortion that may be introduced if using oscilloscope probes. 22 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Programming 0-Delay Mode in CodeLoader Overview When enabling the 0-Delay mode the feedback path of the VCO is altered to include a clock output. See the datasheet for more details on 0-Delay functionality. The current version of the CodeLoader software does not include this extra divider in the frequency calculations when in holdover mode. To successfully lock the LMK04800 device in a 0-Delay mode the user must program the device "manually" account for this divider. Programming "manually" means that the VCO frequency and therefore the clock output frequencies displayed by the CodeLoader software may be incorrect. For the LMK04800 device to lock properly the divider values must be programmed correctly. The frequencies displayed in the application are only for the benefit of the user and for proper automatic programming of the OSCin_FREQ register which will not be affected by 0-Delay. When using the device in Dual Loop mode vs. Single Loop mode different procedures are used to cause the device to lock when using the CodeLoader software. The following two sections describe the process for when the LMK04800 device is programmed for a Dual Loop mode and Single Loop mode respectively. Each section contains a brief introduction, the programming steps to execute to make the device lock, and finally a detailed section discussing the workaround and some example cases. Dual Loop 0-Delay Mode Examples In Dual Loop 0-Delay Modes, MODE = 2 or MODE = 5, the feedback from the VCXO of PLL1 to the PLL1 N divider is broken and a clock output will drive the PLL1 N divider. This permits phase alignment between the clock output and the clock input (0-Delay). As such, the PLL1_N and PLL1_R divide values may need to be adjusted to permit the LMK04800 to lock. Programming Steps 1. 2. 3. 4. Program a Dual Loop 0-Delay mode. Enable the feedback mux. EN_FEEDBACK_MUX = 1. Select clock output for feedback with the feedback mux. FEEDBACK_MUX = User value. Program the VCXO (VCO) frequency of PLL1 tab to the clock output frequency selected by the feedback mux. If for any reason the CLKout frequency is less than the phase detector frequency, the PLL1 R divider must be increased so that the phase detector is at the same or lower value than the CLKout frequency. Details When using the CodeLoader software in Dual Loop 0-Delay mode, programming the VCXO (VCO) frequency of the PLL1 tab to the frequency of the fed back output clock will re-program the PLL1 N divider to allow the LMK04800 will be able to lock. The PLL1 loop has been altered and actual VCXO no longer directly feeds into PLL1 N divider. The VCXO is only used by the reference input of PLL2 now. The PLL2 reference frequency will remain at the VCXO frequency. When the PLL1 VCXO frequency is different from the PLL2 reference frequency, a warning will be displayed on the clock outputs tab informing the user that PLL1 VCO and PLL2 reference frequency are mismatched and the one or more of the PLLs are out of lock. While there still could be an error in the Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 23 divider values which may cause a non-locked PLL, this warning by itself may no longer be assumed true. It is up to the user to ensure the PLL dividers are programmed correctly. To illustrate the proper programming of the LMK04800 device in dual loop 0-delay mode the following case examples are provided. Note that in one of the cases, the feedback frequency from the clock output matches the VCXO frequency and CodeLoader will display the proper frequency values. Dual Loop 0-Delay (MODE=2 or 5) Case 1: For example the default configuration, 122.88 MHz CLKin, 122.88 MHz VCXO, of the LMK04808 has the following register programming. Case2: Default 0-Delay Mode (CLKout8 = 122.88 MHz) Case 3: Default 0-Delay Mode (Updated CLKout8 = 245.76 MHz) Case 4: Default 0-Delay Mode (Updated CLKout8 = 61.44 MHz) 122.88 122.88 122.88 122.88 122.88 122.88 61.44 245.76 120 120 60 240 2949.12 MHz 2949.12 MHz 2949.12 MHz 2949.12 MHz 2949.12 MHz 2949.12 MHz 2949.12 MHz 2949.12 MHz 12 2 Bypassed 12 12 2 Bypassed 24 12 2 Bypassed 12 12 2 Bypassed 48 245.76 MHz 122.88 MHz 245.76 MHz 61.44 MHz 245.76 MHz 122.88 MHz 245.76 MHz 61.44 MHz Case 1: Default Mode No 0-Delay Actual PLL1 VCXO Frequency Reported PLL1 VCXO Frequency PLL1 N Actual PLL2 VCO Frequency Reported PLL2 VCO Frequency PLL2_N PLL2_P (Pre-N) PLL2 VCO Divider CLKout8 Divide Actual CLKout8 Output Frequency Reported CLKotu8 Output Frequency 24 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Single Loop 0-Delay Mode Examples In Single Loop 0-Delay Mode, MODE = 8, the feedback from the VCO of PLL2 to the PLL2_P/PLL2 N divider is broken and a fed back clock output will drive the PLL2 N divider directly. This permits phase alignment between the clock output and the OSCin input (0-Delay). As such, the PLL2_N, PLL2_R, and PLL2_N_CAL divide values may need to be adjusted to permit the LMK04800 to lock. Programming Steps 1. 2. 3. 4. Program the Single Loop 0-Delay mode. Enable the feedback mux. EN_FEEDBACK_MUX = 1. Select clock output for feedback with the feedback mux. FEEDBACK_MUX = User value. Program the VCO frequency of PLL2 tab to: The actual VCO frequency * PLL2_P (which is PLL2 PreN) / CLKout Divider. * Entered CodeLoader 4 VCO Frequency = Actual VCO Frequency * PLL2_P / CLKout Divider. 5. Updated the PLL2_N_CAL register on the Bits/Pins tab to the N value when in non-0-Delay mode. 6. Press Ctrl-L to cause all registers to be programmed. * The reason is to cause the programming of register R30 to start the VCO calibration routine now that the proper PLL2_N_CAL value is programmed. * PLL2_N_CAL value is automatically updated when a new VCO frequency is entered and the PLL2_N value is calculated. In this case the VCO frequency entered is wrong and the PLL2_N_CAL value will be incorrect. If for any reason the CLKout frequency is less than the phase detector frequency, the PLL2 R divider must be increased so that the phase detector is at the same or lower value than the CLKout frequency. Details The 0-Delay mode for Single Loop mode is more complicated to program than for Dual Loop mode in part because of the PLL2_N_CAL register. When performing the VCO calibration the device uses PLL2_N_CAL for in non-0-Delay mode. Once the VCO is calibrated the device enters 0-Delay mode. For more information on the PLL programming equations, refer to PLL PROGRAMMING in the applications section of the datasheet. In Table 7 case 1 illustrates the register programming when note using 0-Delay. Case 2 shows 0-Delay with a clock out divider of 2. Since PLL2_P = 2, this substitution of which circuit is performing the divide by two results in no impact o the software. All the values display correctly. Case 3 shows 0-Delay mode with a CLKout divider not equal to the PLL2_P value. So the proper frequency to program in the VCO to lock the VCO to 2949.12 MHz will be 491.52 MHz. This is calculated by Actual VCO Frequency * PLL2_P / CLKoutX_Y_DIV. Case 4 shows 0-Delay mode with CLKout divider not equal to the PLL2_P value; however the CLKout frequency will be less than the current phase detector frequency. This requires PLL2_R to be increased from a value of 1 to 2 to reduce the PLL2 phase detector frequency from 122.88 MHz to 61.44 MHz. Now the adjusted VCO frequency can be programmed to allow PLL2 to lock. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 25 In any case where the actual VCO frequency and the display VCO frequency are not equal the user is required to manually update the PLL2_N_CAL register with the PLL2_N value to be used as if the device were operating in the non-0-Delay mode. Once this update has been performed, Ctrl-L will reload the part and cause the VCO calibration to occur with the proper PLL2_N_CAL value. Table 7 - Single PLL 0-Delay Operation Examples Case 2: Default 0-Delay Mode (CLKout8 = 1474.56 MHz) Case 3: Default 0-Delay Mode (Updated CLKout8 = 245.76 MHz) Case 4: Default 0-Delay Mode (Updated CLKout8 = 61.44 MHz) 2949.12 MHz 2949.12 MHz 2949.12 MHz 2949.12 MHz 2949.12 MHz 2949.12 MHz 491.52 MHz 122.88 MHz 1 12 12 2 Bypassed 12 1 12 12 2 Bypassed 2 1 2 12 2 Bypassed 12 2 1 24 2 Bypassed 48 245.76 1474.56 MHz 245.76 MHz 61.44 MHz 245.76 1474.56 MHz 40.96 MHz 2.56 MHz Case 1: Default Mode No 0-Delay Actual PLL2 VCO Frequency Reported PLL2 VCO Frequency PLL2_R PLL2_N PLL2_N_CAL PLL2_P (Pre-N) PLL2 VCO Divider CLKout8 Divide Actual CLKout8 Output Frequency Reported CLKout8 Output Frequency 26 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Appendix A: CodeLoader Usage Code Loader is used to program the evaluation board with LPT or USB2ANY-uWire interface available from www.ti.com. Port Setup Tab Figure 8: Port Setup tab On the Port Setup tab, the user may select the type of communication port (LPT or USB) that will be used to program the device on the evaluation board. The Pin Configuration field is hardware dependent and normally does not need to be changed by the user. Figure 8 shows the default settings. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 27 Clock Outputs Tab Figure 9: Clock Outputs tab The Clock Outputs tab allows the user to control the output channel blocks, including: * Clock Group Source from either VCO or OSCin (via OSC Mux1 and OSC Mux2) * Channel Powerdown (affects digital and analog delay, clock divider, and buffer blocks) * Digital Delay value and Half Step * Clock Divide value * Analog Delay value and Delay bypass/enable (per output) * Clock Output format (per output) This tab also allows the user to select the VCO Divider value (2 to 8). Note that the total PLL2 N divider value is the product of the VCO Divider value and the PLL N Prescaler and N Counter 28 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 values (shown in the PLL2 tab), and is given by: PLL2 N Total = VCO Divider * PLL2 N Prescaler * PLL2 N Counter Clicking on the cyan-colored PLL2 block that contains R, PDF and N values will bring the PLL2 tab into focus where these values may be modified, if needed. Clicking on the values in the box containing the Internal Loop Filter component (R3, C3, R4, C4) allow one to step through the possible values. Left click to increase the component value, and right click to decrease the value. These values can also be changed in the Bits/Pins tab. The Reference Oscillator value field may be changed in either the Clock Outputs tab or the PLL2 tab. The PLL2 Reference frequency should match the frequency of the onboard VCXO or Crystal (i.e. VCO frequency in the PLL1 tab); if not, a warning message will appear to indicate that the PLL(s) may be out of lock, as highlighted by the red box in Figure 10. Figure 10: Warning message indicating mismatch between PLL1 VCO frequency (30.72MHz) and PLL2 reference frequency (122.88 MHz) Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 29 PLL1 Tab Figure 11: PLL1 tab The PLL1 tab allows the user to change the following parameters in Table 8. Table 8: Registers Controls and Descriptions in PLL1 tab Control Name Reference Oscillator Frequency (MHz) Phase Detector Frequency (MHz) 30 SNAU076B Register Name n/a n/a Description CLKin frequency of the selected reference clock. PLL1 Phase Detector Frequency (PDF). This value is calculated as: PLL1 PDF = CLKin Frequency / (PLL1_R * CLKinX_PreR_DIV), where CLKinX_PreR_DIV is the predivider value of the selected input clock. LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 VCO Frequency (MHz) n/a R Counter N Counter Phase Detector Polarity PLL1_R PLL1_N PLL1_CP_POL Charge Pump Gain PLL1_CP_GAIN Charge Pump State PLL1_CP_TRI The VCO Frequency should be the OSCin frequency, except when operating in Dual PLL with 0-delay feedback. This value is calculated as: VCO Freq (OSCin freq) = PLL1 PDF * PLL1_N. In Dual PLL mode with 0-delay feedback, the VCO frequency should be set to the feedback clock input frequency. See the section Setting the PLL1 VCO Frequency and PLL2 Reference Frequency for details. PLL1 R Counter value (1 to 16383). PLL1 N Counter value (1 to 16383). PLL1 Phase Detector Polarity. Click on the polarity sign to toggle polarity "+" or "-". PLL1 Charge Pump Gain. Left-click/right-click to increase/decrease charge pump gain (100, 200, 400, 1600 uA). PLL1 Charge Pump State. Click to toggle between Active and Tri-State. Setting the PLL1 VCO Frequency and PLL2 Reference Frequency When operating in Dual PLL mode without 0-delay feedback, the VCO frequency value on the PLL1 tab must match the Reference Oscillator (OSCin) frequency value on the PLL2 tab; otherwise, the one or both PLLs may be out of lock. Updating the Reference Oscillator frequency on the PLL2 tab will automatically update the value of OSCin_FREQ on the Bits/Pins tab. However, when operating in Dual PLL mode with 0-delay feedback, it may be valid for the VCO frequency value on the PLL1 tab to be different from the Reference Oscillator (OSCin) frequency value on the PLL2 tab. This is because in 0-delay mode, the PLL1 feedback clock is taken from an output clock instead of the OSCin clock. For example, if the CLKin frequency (to PLL1_R) is 30.72 MHz, the 0-delay feedback clock frequency (to PLL1_N) is 30.72 MHz, and the VCXO frequency is 122.88 MHz, then the VCO frequency value on the PLL1 tab should be 30.72 MHz (0-delay feedback frequency) and the Reference Oscillator frequency value on the PLL2 tab should be 122.88 MHz (VCXO frequency). Because of the mismatched frequencies, a warning message will indicate this condition on the Clock Outputs tab but may be disregarded in a case like this. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 31 PLL2 Tab Figure 12: PLL2 tab The PLL2 tab allows the user to change the following parameters in Table 9. Table 9: Registers Controls and Descriptions in PLL2 tab Control Name Reference Oscillator Frequency (MHz) Phase Detector Frequency (MHz) Register Name OSCin_FREQ VCO Frequency (MHz) n/a Doubler EN_PLL2_REF_2X R Counter N Counter PLLN Prescaler PLL2_R PLL2_N PLL2_P 32 SNAU076B n/s Description OSCin frequency from the External VCXO or Crystal. PLL2 Phase Detector Frequency (PDF). This value is calculated as: PLL2 PDF = OSCin Frequency *(2EN_PLL2_REF_2X) / PLL2_R. Internal VCO Frequency should be within the allowable range of the LMK048xxB device. This value is calculated as: VCO Frequency = PLL2 PDF * (PLL2_N * PLL2_P * VCO divider value). PLL2 Doubler. 0 = Bypass Doubler 1 = Enable Doubler PLL2 R Counter value (1 to 4095). PLL2 N Counter value (1 to 262143). PLL2 N Prescaler value (2 to 8). LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Phase Detector Polarity PLL2_CP_POL Charge Pump Gain PLL2_CP_GAIN Charge Pump State PLL2_CP_TRI PLL2 Phase Detector Polarity. Click on the polarity sign to toggle polarity "+" or "-". PLL2 Charge Pump Gain. Left-click/right-click to increase/decrease charge pump gain (100, 400, 1600, 3200 uA). PLL2 Charge Pump State. Click to toggle between Active and Tri-State. Changes made on this tab will be reflected in the Clock Outputs tab. The VCO Frequency should conform to the specified internal VCO frequency range for the LMK048xxB device (per Table 2). Bits/Pins Tab Figure 13: Bits/Pins tab The Bits/Pins tab allows the user to program bits directly, many of which are not available on other tabs. Brief descriptions for the controls on this tab are provided in Table 10 to supplement the datasheet. Refer to the LMK04800 Family Datasheet for more information. TIP: Right-clicking any register name in the Bits/Pins tab will display a Help prompt with the register address, data bit location/length, and a brief register description. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 33 Table 10: Register Controls and Descriptions on Bits/Pins tab Group Register Name RESET POWERDOWN MODE Mode Control PD_OSCin FEEDBACK_MUX OSCin_FREQ VCO_MUX uWire_LOCK CLKin_Select_MODE EN_CLKin1 CLKin EN_CLKin0 CLKinX_BUF_TYPE EN_LOS LOS_TIMEOUT IO Control Crystal 34 EN_PLL2_XTAL XTAL_LVL LD_MUX LD_TYPE HOLDOVER_MUX SNAU076B Description Resets the device to default register values. RESET must be cleared for normal operation to prevent an unintended reset every time R0 is programmed. Places the device in powerdown mode. Selects the operating mode (topology) for the LMK048xx device. Powers down the OSCin buffer. For use in Clock Distribution mode if OSCin path is not used. Selects the feedback source for 0-delay mode. Must be set to the OSCin frequency range for PLL2. Used for proper operation of the internal VCO calibration routine. Entering a reference oscillator frequency on PLL2 tab will automatically update OSCin_FREQ to the proper frequency range. Selects between VCO and VCO divider to drive the clock distribution path. The VCO divider is only valid if MODE is selecting the Internal VCO. When checked, no other uWire programming will have effect. Must be unchecked to enable uWire programming of registers R0 to R30. Selects operational mode for how the device selects the reference clock for PLL1. Enables CLKin1 as a usable reference input during auto switching mode. Enables CLKin0 as a usable reference input during auto switching mode. Selects the CLKinX input buffer to Bipolar (internal 0 mV offset) or MOS (internal 55 mV offset). Enable the Loss-Of-Signal (LOS) detect circuitry. Sets the timeout value for the LOS detect circuitry to assert a loss of signal state on a clock input. Enables Crystal Oscillator Sets peak amplitude on the tunable crystal. Values listed are for a 20.48 MHz crystal. Sets the selected signal on the Status_LD pin. Sets I/O pin type on the Status_LD pin. Sets the selected signal on the Status_HOLDOVER pin. LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 DAC/Holdover IO Control - Sync HOLDOVER_TYPE Status_CLKin0 _MUX Status_CLKin0_TYPE Status_CLKin1_MUX Status_CLKin1_TYPE CLKin_Sel_INV Sets I/O pin type on the Status_Holdover pin. Sets the selected signal on the Status_CLKin0 pin. Sets I/O pin type on the Status_CLKin0 pin. Sets the selected signal on the Status_CLKin1 pin. Sets I/O pin type on the Status_CLKin1 pin. Inverts the Status_CLKin0/1 pin polarity when set to an input type. Significant when CLKin_SELECT_MODE is 3 or 6. SYNC_MUX Sets the selected signal on the SYNC pin. SYNC_TYPE Sets I/O pin type on the SYNC pin. SYNC_POL_INV Sets polarity on SYNC input to active low when checked. Toggling this bit will initiate a SYNC event. SYNC_PLL1_DLD Engage SYNC mode until PLL1 DLD is true SYNC_PLL2_DLD Engage SYNC mode until PLL2 DLD is true NO_SYNC_CLKoutX_Y Synchronization will not affect selected clock outputs, where X = even-numbered output and Y = odd-numbered output. SYNC_QUAL Sets the SYNC to qualify mode for dynamic digital delay. EN_SYNC Must be set when using SYNC, but may be cleared after the SYNC event. When using dynamic digital delay (SYNC_QUAL = 1), EN_SYNC must always be set. Changing this value from 0 to 1 can cause a SYNC event, so clocks which should not be SYNCed when setting this bit should have the NO_SYNC_CLKoutX_Y bit set. NOTE: This bit is not a valid method of generating a SYNC event. Use one of the other SYNC generation methods to ensure a proper SYNC occurs. SYNC_EN_AUTO Enable auto SYNC when R0 to R5 is written. HOLDOVER_MODE Sets holdover mode to be disabled or enabled. FORCE_HOLDOVER Engages holdover when checked regardless of HOLDOVER_MODE value. Turns the DAC on. EN_TRACK Enables DAC tracking. DAC tracks the PLL1 Vtune to provide for an accurate HOLDOVER mode. DAC_CLK_DIV should also be set so that DAC update rate is <= 100 kHz. EN_VTUNE_RAIL_DET Allows rail-to-rail operation of VCXO with default of 0. Allows use of DAC_LOW_TRIP, DAC_HIGH_TRIP. Must be used with EN_MAC_DAC = 1. CLKin_SELECT_MODE must be 4 or 6 (auto mode) to use. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 35 HOLD_DLD_CNT DAC_CLK_DIV EN_MAN_DAC MAN_DAC DAC_LOW_TRIP DAC_HIGH_TRIP PLL1_WND_SIZE PLL1 PLL1_DLD_CNT CLKinX_PreR_DIV 36 SNAU076B In HOLDOVER mode, wait for this many clocks of PLL1 PDF within the tolerances of PLL1_WND _SIZE before exiting holdover mode. DAC update clock is the PLL1 phase detector divided by this divisor. For proper operation, DAC update clock rate should be <= 100 kHz. DAC update rate = PLL1 phase detector frequency / DAC_CLK_DIV Enables manual DAC mode and set DAC voltage when in holdover. Sets the value for the DAC when EN_MAN_DAC is 1 and holdover is engaged. Readback from this register is the current DAC value whether in manual DAC mode or DAC tracking mode Value from GND in ~50mV steps at which a clock switch event is generated. If Holdover mode is enabled, it will be engaged upon the clock switch event. NOTE: EN_VTUNE_RAIL_DET must be enabled for this to be valid. Value from VCC (3.3V) in ~50mV steps at which clock switch event is generated. If Holdover mode is enabled, it will be engaged upon the clock switch event. NOTE: EN_VTUNE_RAIL_DET must be enabled for this to be valid. If the phase error between the PLL1 reference and feedback clocks is less than specified time, then the PLL1 lock counter increments. NOTE: Final lock detect valid signal is determined when the PLL1 lock counter meets or exceeds the PLL1_DLD_CNT value. The reference and feedback of PLL1 must be within the window of phase error as specified by PLL1_WND_SIZE for this many cycles before PLL1 digital lock detect is asserted. The PreR dividers divide the CLKinX reference before the PLL1_R divider. Unique divides on individual CLKinX signals allows switchover from one clock input to another clock input without needing to reprogram the PLL1_R divider to keep the device in lock. LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 PLL1_N_DLY PLL1_R_DLY PLL2_WND_SIZE PLL2_DLD_CNT PLL2 EN_PLL2_REF_2X PLL2_N_CAL PLL2_R3_LF PLL2_R4_LF PLL2_C3_LF PLL2_C4_LF PLL2_FAST_PDF Program Pins SYNC Status_CLKin0 Status_CLKin1 Revised - August 2014 N delay causes clock outputs to lead clock input when in a 0-delay mode. Increasing the N delay value increases the output phase lead relative to the input. R delay causes clock outputs to lag clock input when in a 0-delay mode. Increasing the R delay value increases the output phase lag relative to the input. If the phase error between the PLL2 reference and feedback clock is less than specified time, then the PLL2 lock counter increments. The reference and feedback of PLL2 must be within the window of phase error as specified by PLL2_WND_SIZE for this many cycles before PLL2 digital lock detect is asserted. Enables the doubler block to doubles the reference frequency into the PLL2 R counter. This can allow for frequency of 2/3, 2/5, etc. of OSCin to be used at the phase detector of PLL2. The PLL2_N_CAL register contains the N value used for the VCO calibration routine. Except during 0-delay modes, the PLL2_N and PLL2_N_CAL registers will be exactly the same. Set the corresponding integrated PLL2 loop filter values: R3, R4, C3, and C4. It is also possible to set these values by clicking on the loop filter values on the Clock Outputs tab. Enable this bit when using a PLL2 phase detector frequency > 100 MHz. Sets these pins on the uWire header to logic high (checked) or logic low (unchecked). LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 37 Registers Tab Figure 14: Registers Tab The Registers tab shows the value of each register. This is convenient for programming the device to the desired settings, then exporting to a text file the register values in hexadecimal for use in your own application. By clicking in the "bit field" it is possible to manually change the value of registers by typing `1' and `0.' 38 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Appendix B: Typical Phase Noise Performance Plots PLL1 The LMK048xxB's dual PLL architecture achieves ultra low jitter and phase noise by allowing the external VCXO or Crystal's phase noise to dominate the final output phase noise at low offset frequencies and the internal VCO's phase noise to dominate the final output phase noise at high offset frequencies. This results in the best overall noise and jitter performance. Table 11 lists the test conditions used for output clock phase noise measurements with the Crystek 122.88 MHz VCXO. Table 11: LMK048xxB Test Conditions Parameter PLL1 Reference clock input PLL1 Reference Clock frequency PLL1 Phase detector frequency PLL1 Charge Pump Gain VCXO frequency PLL2 phase detector frequency PLL2 Charge Pump Gain PLL2 REF2X mode Value CLKin0 single-ended input, CLKin0* AC-coupled to GND 122.88 MHz 122.88 MHz 100 uA 122.88 MHz 122.88 MHz 3200 uA Disabled 122.88 MHz VCXO Phase Noise The phase noise of the reference is masked by the phase noise of this VCXO by using a narrow loop bandwidth for PLL1 while retaining the frequency accuracy of the reference clock input. This VCXO sets the reference noise to PLL2. Figure 15 shows the open loop typical phase noise performance of the CVHD-950-122.88 Crystek VCXO. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 39 Phase Noise (dBc/Hz) VCXO Phase Noise -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 CVHD-950-122.88 10 100 1000 10000 100000 1000000 10000000 1E+08 Offset (Hz) Figure 15: Crystek CVHD-950-122.88 MHz VCXO Phase Noise at 122.88 MHz Table 12: VCXO Phase Noise at 122.88 MHz (dBc/Hz) Phase Offset Noise 10 Hz -76.6 100 Hz -108.9 1 kHz -137.4 10 kHz -153.3 100 kHz -162.0 1 MHz -165.7 10 MHz -168.1 40 MHz -168.1 Table 13: VCXO RMS Jitter to high offset of 20 MHz at 122.88 MHz (rms fs) Low Jitter Offset 10 Hz 515.4 100 Hz 60.5 1 kHz 36.2 10 kHz 35.0 100 kHz 34.5 1 MHz 32.9 10 MHz 22.7 Clock Output Measurement Technique The same technique was used to measure phase noise for all three output types available on the programmable OSCout and CLKout buffers. This was achieved by terminating one side of the LVPECL, LVDS, or LVCMOS output with a 50-ohm load, and measuring the other side singleended using an Agilent E5052B Source Signal Analyzer. Buffered OSCout Phase Noise Both OSCout0 and OSCout1 frequencies are 122.88 MHz since the OSCout Divider is bypassed. OSCout0 is programmed to LVCMOS mode and OSCout1 is fixed as LVPECL. 40 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Clock Outputs (CLKout) The LMK04800 Family features programmable LVDS, LVPECL, and LVCMOS buffer modes for the CLKoutX and OSCout0 output pairs. The OSCout1 output pair has a LVPECL buffer. Included below are various phase noise measurements for each output format. LMK04808B CLKout Phase Noise Phase Noise (dBc/Hz) 1474.56 MHz LVDS 1474.56 MHz LVPECL16 491.52 MHz LVDS 491.52 MHz LVPECL16 245.76 MHz LVDS 245.76 MHz LVCMOS 245.76 MHz LVPECL16 122.88 MHz LVDS 122.88 MHz LVCMOS 122.88 MHz LVPECL16 Frequency Offset (Hz) Figure 16: LMK04808B CLKout Phase Noise Table 14: LMK04808B Phase Noise (dBc/Hz) Phase Noise and RMS Jitter (fs) 1474.56 MHz 1474.56 MHz 491.52 MHz 491.52 MHz Offset LVDS LVPECL LVDS LVPECL -88.2 -87.8 -97.7 -99.7 100 Hz -109.8 -108.9 -118.9 -119.3 1 kHz -118.0 -117.4 -127.3 -127.4 10 kHz -119.8 -119.7 -129.1 -129.4 100 kHz -130.9 -130.8 -140.1 -140.3 800 kHz -132.7 -132.6 -141.7 -142.1 1 MHz -148.2 -149.2 -152.7 -154.9 10 MHz -148.9 -150.1 -153.2 -155.3 20 MHz RMS Jitter (fs) 99.3 99.4 109.1 103.3 10 kHz to 20 MHz RMS Jitter (fs) 111.4 113.5 121.3 116.1 100 Hz to 20 MHz Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 41 For the LMK04808B, the internal VCO frequency is 2949.12 MHz. The divide-by-12 CLKout frequency is 245.76 MHz, and the divide-by-24 CLKout frequency is 122.88 MHz. Table 15: LMK04808B Phase Noise and RMS Jitter for Different CLKout Output Formats and Frequencies 245.76 245.76 245.76 122.88 122.88 122.88 Offset LVDS LVCMOS LVPECL LVDS LVCMOS LVPECL 100 Hz -103.7 -104.4 -106.1 -108.4 -110.4 -108.5 1 kHz -123.7 -125.9 -125.7 -128.7 -129.7 -130.9 10 kHz -133.8 -133.5 -134.0 -139.3 -139.8 -140.0 100 kHz -135.5 -135.4 -135.8 -141.7 -141.4 -141.8 800 kHz -146.4 -146.3 -146.7 -151.7 -152.1 -152.4 1 MHz -147.9 -148.0 -148.3 -152.9 -153.4 -153.8 10 MHz -156.5 -157.5 -158.3 -158.7 -160.5 -161.0 20 MHz -156.9 -157.8 -158.6 -158.8 -160.7 -161.3 RMS Jitter (fs) 111.8 109.6 103.9 133.4 122.1 116.1 10 kHz to 20 MHz RMS Jitter (fs) 124.3 122.1 115.4 144.4 132.3 127.9 100 Hz to 20 MHz 42 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 LMK04808B OSCout Phase Noise Title 122.88 MHz LVCMOS OSCin through CLKout 122.88 MHz OSCout0 LVPECL16 122.88 MHz OSCout1 LVPECL16 Title Figure 17: LMK04808B OSCout Phase Noise Table 16: LMK04808B OSCout Phase Noise and RMS Jitter (fs) OSCout0 OSCout1 OSCin thru Offset LVPECL LVPECL CLKout -110.2 -111.1 -109.4 100 Hz -137.2 -136.1 -138.6 1 kHz -148.0 -148.0 -146.7 10 kHz -157.8 -156.0 -155.3 100 kHz -159.1 -159.4 -156.4 800 kHz -157.0 -157.5 -156.3 1 MHz -158.8 -159.2 -156.7 10 MHz -159.2 -159.5 -156.7 20 MHz RMS Jitter (fs) 94.1 91.0 123.7 10 kHz to 20 MHz RMS Jitter (fs) 103.2 99.6 131.3 100 Hz to 20 MHz Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 43 LMK04806B CLKout Phase Noise Phase Noise (dBc/Hz) 1228.8 MHz LVDS 1228.8 MHz LVPECL16 491.52 MHz LVDS 491.52 MHz LVPECL16 245.76 MHz LVDS 245.76 MHz LVCMOS 245.76 MHz LVPECL16 122.88 MHz LVDS 122.88 MHz LVCMOS 122.88 MHz LVPECL16 Frequency Offset (Hz) Figure 18: LMK04806B CLKout Phase Noise Table 17: LMK04806B Phase Noise (dBc/Hz) Phase Noise and RMS Jitter (fs) 1228.80 MHz 1228.80 MHz 491.52 MHz 491.52 MHz Offset LVDS LVPECL LVDS LVPECL -91.2 -90.5 -97.5 -98.2 100 Hz -111.2 -110.8 -118.7 -119.4 1 kHz -121.0 -121.1 -128.5 -128.6 10 kHz -121.3 -121.2 -129.5 -129.5 100 kHz -133.8 -133.7 -141.9 -141.9 800 kHz -135.8 -135.7 -143.4 -143.8 1 MHz -150.2 -150.4 -153.1 -155.7 10 MHz -150.8 -151.0 -153.8 -155.7 20 MHz RMS Jitter (fs) 92.9 93.4 97.5 94.5 10 kHz to 20 MHz RMS Jitter (fs) 104.0 105.3 109.0 105.4 100 Hz to 20 MHz For the LMK04806B, the internal VCO frequency is 2457.60 MHz. The divide-by-10 CLKout frequency is 245.76 MHz, and the divide-by-20 CLKout frequency is 122.88 MHz. 44 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Table 18: LMK04806B Phase Noise and RMS Jitter for Different CLKout Output Formats and Frequencies 245.76 245.76 245.76 122.88 122.88 122.88 Offset LVDS LVCMOS LVPECL LVDS LVCMOS LVPECL 100 Hz -105.8 -104.5 -106.5 -108.6 -113.0 -111.4 1 kHz -124.7 -124.9 -125.4 -130.2 -132.1 -131.0 10 kHz -134.8 -134.4 -134.9 -140.7 -140.7 -141.0 100 kHz -135.5 -135.4 -135.8 -141.7 -141.7 -141.9 800 kHz -147.8 -147.7 -148.0 -152.6 -153.5 -154.1 1 MHz -149.6 -149.4 -149.7 -153.3 -155.2 -155.5 10 MHz -156.1 -158.1 -158.4 -158.4 -161.5 -161.1 20 MHz -156.3 -158.2 -158.9 -159.5 -161.6 -161.3 RMS Jitter (fs) 106.9 101.5 96.4 134.2 109.7 108.2 10 kHz to 20 MHz RMS Jitter (fs) 116.8 112.4 106.4 143.2 118.9 117.9 100 Hz to 20 MHz Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 45 LMK04806B OSCout Phase Noise Title 122.88 MHz LVCMOS OSCin through CLKout 122.88 MHz OSCout0 LVPECL16 122.88 MHz OSCout1 LVPECL16 Title Figure 19: LMK04806B OSCout Phase Noise Table 19: LMK04806B OSCout Phase Noise and RMS Jitter (fs) OSCout0 OSCout1 OSCin thru Offset LVPECL LVPECL CLKout -110.3 -112.1 -110.0 100 Hz -136.9 -137.9 -138.9 1 kHz -151.1 -150.1 -150.0 10 kHz -154.3 -156.8 -154.6 100 kHz -158.9 -158.9 -156.6 800 kHz -159.2 -159.1 -156.6 1 MHz -159.4 -160.0 -156.8 10 MHz -157.6 -159.9 -156.9 20 MHz RMS Jitter (fs) 138.4 89.7 120.0 10 kHz to 20 MHz RMS Jitter (fs) 143.7 97.3 126.2 100 Hz to 20 MHz 46 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 LMK04803B CLKout Phase Noise Phase Noise (dBc/Hz) 983.04 MHz LVDS 983.04 MHz LVPECL16 491.52 MHz LVDS 491.52 MHz LVPECL16 245.76 MHz LVDS 245.76 MHz LVCMOS 245.76 MHz LVPECL16 122.88 MHz LVDS 122.88 MHz LVCMOS 122.88 MHz LVPECL16 Frequency Offset (Hz) Figure 20: LMK04803B CLKout Phase Noise Table 20: LMK04803B Phase Noise (dBc/Hz) Phase Noise and RMS Jitter (fs) 983.04 MHz 983.04 MHz 491.52 MHz 491.52 MHz Offset LVDS LVPECL LVDS LVPECL -93.0 -95.0 -99.7 -99.5 100 Hz -111.3 -113.1 -117.1 -118.3 1 kHz -121.8 -121.1 -126.9 -127.4 10 kHz -122.3 -121.9 -127.8 -128.3 100 kHz -134.9 -134.5 -140.3 -140.8 800 kHz -136.8 -136.3 -142.0 -142.7 1 MHz -150.3 -150.6 -152.0 -154.2 10 MHz -150.4 -151.1 -152.6 -154.6 20 MHz RMS Jitter (fs) 103.8 107.4 116.0 108.1 10 kHz to 20 MHz RMS Jitter (fs) 116.1 116.2 127.4 116.8 100 Hz to 20 MHz For the LMK04803B, the internal VCO frequency is 1966.08 MHz. The divide-by-8 CLKout frequency is 245.76 MHz, and the divide-by-16 CLKout frequency is 122.88 MHz. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 47 Table 21: LMK04803B Phase Noise and RMS Jitter for Different CLKout Output Formats and Frequencies 245.76 245.76 245.76 122.88 122.88 122.88 Offset LVDS LVCMOS LVPECL LVDS LVCMOS LVPECL 100 Hz -104.8 -104.2 -108.4 -112.1 -111.5 -112.7 1 kHz -124.8 -123.5 -125.0 -130.5 -130.2 -130.6 10 kHz -133.7 -134.0 -133.6 -140.1 -139.8 -140.1 100 kHz -134.4 -134.4 -134.6 -140.6 -140.4 -140.7 800 kHz -146.7 -146.7 -147.1 -152.5 -152.4 -152.7 1 MHz -148.5 -148.5 -148.7 -153.4 -154.0 -154.0 10 MHz -156.2 -157.2 -158.0 -158.4 -160.1 -160.5 20 MHz -156.6 -157.5 -158.2 -158.7 -160.4 -161.1 RMS Jitter (fs) 115.1 113.1 107.9 137.5 126.1 120.5 10 kHz to 20 MHz RMS Jitter (fs) 126.4 124.2 116.7 147.5 136.4 128.9 100 Hz to 20 MHz 48 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 LMK04803B OSCout Phase Noise Phase Noise (dBc/Hz) 122.88 MHz LVCMOS OSCin through CLKout 122.88 MHz OSCout0 LVPECL16 122.88 MHz OSCout1 LVPECL16 Frequency Offset (Hz) Figure 21: LMK04803B OSCout Phase Noise Table 22: LMK04803B OSCout Phase Noise and RMS Jitter (fs) OSCout0 OSCout1 OSCin thru Offset LVPECL LVPECL CLKout -114.0 -113.1 -113.3 100 Hz -136.6 -137.2 -138.4 1 kHz -147.6 -146.6 -148.5 10 kHz -156.3 -156.2 -154.0 100 kHz -159.4 -159.2 -156.6 800 kHz -159.0 -159.3 -156.7 1 MHz -157.2 -158.7 -156.9 10 MHz -158.1 -159.4 -157.0 20 MHz RMS Jitter (fs) 107.1 92.4 119.1 10 kHz to 20 MHz RMS Jitter (fs) 111.6 98.1 123.3 100 Hz to 20 MHz Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 49 Appendix C: Schematics Power Supplies 50 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 LMK048xxB Device with Loop Filter and Crystal Circuits 1 2 3 4 5 6 Crystal-mode Loop Filter 5 6 SYNC R376 DNP 51 CLKout6_P 49 CLKout6_N CLKout6* 51 CLKout7_P 52 53 CLKout8_P 54 CLKout8_N 55 CLKout9_N 56 CLKout9_P 57 58 CLKout10_P 59 CLKout10_N 60 CLKout11_N 61 CLKout11_P 62 Status_CLKin0 63 Status_CLKin1 50 CLKout7_N CLKout7* CLKout7 Vcc11 CLKout8 CLKout8* CLKout9* CLKout9 Vcc12 CLKout10 CLKout10* 47 LEuWire SYNC* 44 uWire_LE 43 NC CPout2 42 NC Vcc8 41 9 NC OSCout0* LDObyp1 Vcc7 12 LDObyp2 OSCin* 37 OSCin_N CLKout2_P 13 CLKout2 OSCin 36 OSCin_P CLKout2_N 14 CLKout2* Status_Holdover R59 OSCin_1_N R306 DNP 0 38 Y300 Vcc6_PDCP1 34 DNP 2pF R62 DNP DNPC33 0.1F B 4.7k D1 SMV1249-074LF Vtune_XTAL R307 3 10k DNP Vcc7_OSC 35 2200pF R308 DNP 0 B3 4 C32 R71 DNP 0 R73 Status_LD R72 DNP 0 2 SCTDNP NC P 1 SD BALUN - ADT2-1T+ R63 DNP 0 R66 DNP 0 R68 DNP 51 R70 OSCin_1_P OSCinP 0 OSCin Tuneable Crystal CPout1_1 Vtune_VCXO R74 R75 DNP 0 0 C2_A1 DNPC2pA1 2.7F 0.68F 0 C C1_A1 0.1F Status_Hold R76 DNP 0 R77 DNP 0 C39 DNP Vcc_VCXO_LDO DNP C40 Vcc_VCXO_OpAmp R78 R309 DNP DNP DNP 0 DNP C41 DNP 0.1F PLL1 Loop Filters R2_A1 39k 5 DNP 3 VCXO Loop Filter Vtune1 SMA 5 6 PD S R67 CPout1 33 Status_LD R64 DNP 51 R65 DNP 100 C304 1000pF C34 4.7k R69 2200pF DNP 0 C36 2pF DNP 0.1F C38 0.1F VTUNE1_TP OSCinN 0 R61 51 C28 C29 uWire_LE 39 OSCout0_P OSCout1* Status_LD OSCout1_N 32 OSCout1 OSCout1_P 31 Vcc5 30 CLKin0* 29 CLKin0_N 28 CLKin0 CPout1 CLKin0_P Status_Hold 27 FBCLKin*/CLKin1* 26 CLKin1_N FBCLKin/CLKin1 CLKin1_P 25 24 Vcc4 GND 23 CLKout5 22 CLKout5_P CLKout4* CLKout5* 21 CLKout5_N 17 Vcc2_CLKout_CG1 20 CLKout3 CLKout4_N CLKout3* CLKout3_P 16 CLKout4 CLKout3_N 15 Vcc6 uWire_CLK Y301 DNP Vcc1 OSCout0 R60 DNP 0 uWire_DATA Vcc8_PDCP2 40 OSCout0_N 11 DAP PAD C27 Vcc9_PLL2 10 0 C2_A2 3900pF 0.1F 45 uWire_CLK Vcc9 A R2_A2 620 46 uWire_DATA 7 LMK048xxB DNPC2pA2 100pF C1_A2 47pF Vcc10_CLKout_CG3 8 Vcc2 C 48 Vcc10 VCO_Vtune 0 VCXO-mode Loop Filter U1 LMK04800 CLKout6 DNPCb2pVCO DNPCb2_VCO DNP DNPCb1_VCO DNP DNP Rb2_VCO DNPDNP 0 CLKuWire 19 C37 0.1F CLKout1 NC CLKout4_P C35 10F R305 DNP 0 DATAuWire Vcc3 Vcc1_VCO CLKout1* 18 SYNC Vcc11_CLKout_CG4 R2_B2 470 R51 DNP 0 VTUNE2_TP R53 DNP 0 R55 2 CLKout1_P 4 B R304 R52 DNP 0 1 CLKout1_N 3 CLKout11* CLKout0* CLKout11 CLKout0 CLKout0_N 2 Status_CLKin0 Vcc13 CLKout0_P 1 Vcc12_CLKout_CG5 Status_CLKin1 64 Vcc13_CLKout_CG0 PLL2 Loop Filters C2pB2 0.12uF Status_LD Status_CLKin0 A C1_B2 DNPC2_B2 DNP 100pF Vtune2 Swith MA Monitoring via Status LD Status_CLKin1 Vtune_XTAL 4 Vcc_VCXO_OpAmp Vcc3_CLKout_CG2 Vcc4_Digital Vcc5_CLKin Cb1_B1 DNPCb2_B1 0.33F DNP Status_Hold Cb2pB1 10F R310 DNP 10k 3 R311 DNPC305 DNP 10k 0.1F V+ V- 2 Crystal Loop Filter Vtune1 Monitoring 1 U4 LMP7731MF Rb2_B1 3.9k D D Designators greater than and equal to 200 are placed on bottom of PCB 1 2 Revised - August 2014 National Semiconductor and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. National and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. National and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. 3 4 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Mod. Date: 8/12/2011 Designed for: Evaluation Customer Project: LMK048xx Evaluation Board Sheet Title: Main Sheet / IC Sheet:3 of 9 Size: B Schematic: 870600534 Rev: 3.0 Assembly Variant: LVPECL240 - 2011-07-26 File: LMK048xx_PLL.SchDoc http://www.national.com (c) Copyright, National Semiconductor, 2009 Contact: http://www.national.com/support 5 6 SNAU076B 51 Reference Inputs (CLKin0 & CLKin1), External VCXO (OSCin) & VCO Circuits, and OSCout1 Output 52 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Clock Outputs (OSCout0, CLKout0 to CLKout3) 1 2 3 4 OSCout0 5 6 Default: LVDS, AC coupled VccCLKoutPlane R88 DNP 120 R89 DNP 82 R90 DNP 51 C44 A OSCout0_1_P OSCout0_P R91 0.1F DNP 62 R231 240 GND R93 DNP 62 C46 OSCout0_1_N OSCout0_N GND R94 DNP 120 Default: LVPECL, AC coupled R95 DNP 82 R97 DNP 120 CLKout1 VccCLKoutPlane R98 DNP 82 CLKout0_P R106 62 DNP 0.1F CLKout0_1_N GND R110 DNP 62 C52 GND CLKout0* SMA CLKout1_P R112 240 R114 DNP 51 CLKout3 Default: LVPECL, AC coupled R120 DNP 82 C53 0.1F CLKout2_1_N GND D R139 DNP 120 SMA 0.1F R140 DNP 82 CLKout2* SMA Revised - August 2014 CLKout3* DNP R127 0.1F DNP 62 R130 R131 DNP 62 68 C56 DNP 0.1F C58 CLKout3_1_P CLKout3_P R136 DNP 120 National Semiconductor and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. National and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. National and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. 4 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com CLKout3 SMA R138 51 VccCLKoutPlane GND 3 R137 DNP 82 SMA DNP 0.1F R134 240 R135 DNP 51 1. Designators greater than and equal to 300 are placed on bottom of PCB R124 51 CLKout3_1_N GND VccCLKoutPlane 2 R123 DNP 82 CLKout3_N R126 240 Notes: 1 R117 51 C54 R129 C57 CLKout2_N R133 240 CLKout1 CLKout1_1_P SMA DNP C CLKout2 68 C55 DNP 0.1F R132 62DNP GND 68 C50 DNP 0.1F Default: LVPECL, AC coupled R122 DNP 120 R121 DNP 51 CLKout2_1_P R128 62 DNP B R108 VccCLKoutPlane CLKout2_P R125 240 R115 DNP 120 0.1F R116 DNP 82 CLKout1* SMA DNP VccCLKoutPlane GND VccCLKoutPlane R119 DNP 120 R102 51 CLKout1_1_N R1050.1F DNP 62 R104 240 VccCLKoutPlane CLKout2 C 0.1F R118 DNP 82 R101 DNP 82 C48 CLKout1_N R107 C51 CLKout0_N R113 DNP 120 CLKout0 SMA 68 C49 DNP 0.1F R109 62 DNP R111 240 R100 DNP 120 R99 DNP 51 CLKout0_1_P GND Default: LVPECL, AC coupled VccCLKoutPlane C47 R103 240 OSCout0* SMA R96 DNP 51 VccCLKoutPlane B A 0.1F R232 240 CLKout0 R92 DNP 68 C45 DNP 0.1F OSCout0 SMA D Designed for: Evaluation Customer Mod. Date: 6/8/2011 Project: LMK048xx Evaluation Board Sheet Title: Clock Outputs 1/3 Sheet: 6 of 9 Size: B Schematic: 870600534 Rev: 3.0 Assembly Variant: LVPECL240 - 2011-07-26 http://www.national.com File: OutClks0.SchDoc Contact: http://www.national.com/support (c) Copyright, National Semiconductor, 2009 5 6 SNAU076B 53 Clock Outputs (CLKout4 to CLKout7) 1 2 3 CLKout4 A 4 CLKout5 Default: LVDS or LVCMOS, AC coupled VccCLKoutPlane R143 DNP 120 R144 DNP 82 C59 R150 62 DNP 0.1F CLKout4 SMA CLKout6 R157 DNP 51 CLKout6_P 33 R172 62DNP R176 62DNP R234 CLKout6_N 33 CLKout7 R158 51 B Default: LVDS or LVCMOS, AC coupled R167 DNP 120 R163 DNP 51 CLKout6 SMA 68 C67 DNP 0.1F 0.1F R184 DNP 82 R170 DNP 240 R171 62 DNP GND R175 62 DNP CLKout6* C69 SMA R168 DNP 82 C66 CLKout7_N R173 CLKout6_1_N R183 DNP 120 0.1F C70 R178 DNP 240 R179 DNP 51 R180 DNP 120 R164 51 CLKout7* CLKout7_1_N SMA DNP R174 68 C68 DNP 0.1F CLKout7_P VccCLKoutPlane GND D 0.1F CLKout6_2_N R177 DNP 240 CLKout5 SMA DNP VccCLKoutPlane R166 DNP 82 C65 CLKout6_1_P GND C 0.1F R162 DNP 82 VccCLKoutPlane GND CLKout6_2_P R169 DNP 240 R161 DNP 120 SMA R152 CLKout5_1_P R156 DNP 240 VccCLKoutPlane R233 CLKout5* DNP 68 C62 DNP 0.1F CLKout5_P Default: LVDS or LVCMOS, AC coupled R165 DNP 120 R142 51 C64 SMA VccCLKoutPlane GND 0.1F R154 62 DNP CLKout4* CLKout4_1_N B R149 62 DNP GND C63 0.1F R160 DNP 82 R146 DNP 82 C60 CLKout5_1_N R148 DNP 240 R151 CLKout4_N R159 DNP 120 A CLKout5_N 68 C61 DNP 0.1F R153 62 DNP R155 DNP 240 Default: LVDS or LVCMOS, AC coupled R145 DNP 120 R141 DNP 51 CLKout4_1_P GND 6 VccCLKoutPlane CLKout4_P R147 DNP 240 5 0.1F R181 DNP 82 C CLKout7 CLKout7_1_P SMA DNP R182 51 VccCLKoutPlane GND Notes: D 1. Designators greater than and equal to 300 are placed on bottom of PCB 1 2 54 SNAU076B National Semiconductor and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. National and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. National and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. 3 4 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Mod. Date: 6/8/2011 Designed for: Evaluation Customer Project: LMK048xx Evaluation Board Sheet Title: Clock Outputs 2/3 Sheet: 7 of 9 Size: B Schematic: 870600534 Rev: 3.0 Assembly Variant: LVPECL240 - 2011-07-26 File: OutClks1.SchDoc http://www.national.com Contact: http://www.national.com/support (c) Copyright, National Semiconductor, 2009 5 6 Revised - August 2014 Clock Outputs (CLKout8 to CLKout11) 1 CLKout8 A 4 3 2 CLKout9 Default: LVDS or LVCMOS, AC coupled R187 DNP 51 R186 DNP 82 R185 DNP 120 R188 DNP 120 C71 CLKout8_1_P CLKout8_P R193 62DNP 0.1F A R195 CLKout8_N CLKout8* SMA 0.1F R198 62 DNP C76 R200 DNP 240 R204 DNP 51 R201 DNP 120 R190 51 CLKout9* CLKout9_1_N SMA DNP R196 68 C74 DNP 0.1F CLKout9_P 0.1F R203 DNP 82 R202 DNP 120 R194 62 DNP GND CLKout8_1_N R189 DNP 82 C72 CLKout9_N R192 DNP 240 C75 R199 DNP 240 CLKout8 SMA 68 C73 DNP 0.1F R197 62DNP GND Default: LVDS or LVCMOS, AC coupled VccCLKoutPlane VccCLKoutPlane R191 DNP 240 6 5 0.1F R205 DNP 82 CLKout9 CLKout9_1_P SMA DNP R206 51 VccCLKoutPlane GND B GND VccCLKoutPlane CLKout10 B CLKout11 Default: LVPECL, AC coupled VccCLKoutPlane R207 DNP 120 R209 DNP 51 R208 DNP 82 CLKout10_1_P CLKout10_P GND C R214 0.1F DNP 62 R217 R219 DNP 62 68 C79 DNP 0.1F C81 R221 240 R224 DNP 82 R211 DNP 82 C78 CLKout11_N R216 62DNP GND 0.1F C82 SMA CLKout11_P R222 240 R225 DNP 51 VccCLKoutPlane R226 DNP 120 GND R212 51 CLKout11* CLKout11_1_N SMA DNP R218 68 C80 DNP 0.1F R220 62 DNP CLKout10* 0.1F R223 DNP 120 GND D SMA R215 240 CLKout10_1_N CLKout10_N R210 DNP 120 CLKout10 C77 R213 240 Default: LVPECL, AC coupled VccCLKoutPlane 0.1F R227 DNP 82 CLKout11 CLKout11_1_P SMA DNP R228 51 VccCLKoutPlane Notes: D 1. Designators greater than and equal to 300 are placed on bottom of PCB National Semiconductor and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. National and/or its licensors do not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. National and/or its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application. 1 C 2 Revised - August 2014 4 3 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Designed for: Evaluation Customer Mod. Date: 6/8/2011 Project: LMK048xx Evaluation Board Sheet: 8 of 9 Sheet Title: Clock Outputs 3/3 Size: B Schematic: 870600534 Rev: 3.0 Assembly Variant: LVPECL240 - 2011-07-26 http://www.national.com File: OutClks2.SchDoc Contact: http://www.national.com/support (c) Copyright, National Semiconductor, 2009 6 5 SNAU076B 55 uWire Header, Logic I/O Ports and Status LEDs 56 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 USB Interface Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 57 Appendix D: Bill of Materials Table 23: Bill of Materials for LMK048xx Evaluation Boards Item Designator Description 1 C1, C5, C13, C20, FB, 120 ohm, 500 mA, 0603, RES, 0 ohm, 5%, 0.1W, C22, C25, C300, 0603 R3, R11, R12, R19, R21, R22, R29, R30, R37, R46, R55, R73, R74, R82, R84, R229, R304, R327, R329, R331, R333, R337, R340, R341, R346, R347, R349, R353, R354, R358, R361, R364, R365, R368, R371, R373, R374, R375, R400, R402 58 SNAU076B Manufacturer Vishay-Dale, Vishey/Dale LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com PartNumber CRCW06030000Z0EA Revised - August 2014 Quantity 47 2 C1_A1, C6, C14, C19, C21, C24, C27, C37, C38, C44, C46, C47, C48, C51, C52, C53, C54, C57, C58, C59, C60, C63, C64, C65, C66, C70, C71, C72, C75, C76, C77, C78, C81, C82, C312, C319, C329, C361 CAP, CERM, 0.1uF, 25V, +/-5%, X7R, 0603 Kemet C0603C104J3RACTU 38 3 4 5 C1_A2 C1_B2 C2, C12, C41, C302, C330, C346 C2pB2 C2_A1 C2_A2 C4, C69, C314, C322, C326, C367, C400, C401, C402, C409, C412, C414 CAP, CERM, 47pF, 50V, +/-5%, C0G/NP0, 0603 CAP, CERM, 150pF, 50V, +/-5%, C0G/NP0, 0603 CAP, CERM, 0.1uF, 16V, +/-10%, X7R, 0603 Kemet Kemet Kemet C0603C470J5GACTU C0603C151J5GACTU C0603C104K4RACTU 1 1 6 CAP, CERM, 0.12uF, 50V, +/-10%, X7R, 0805 CAP, CERM, 0.68F, 10V, +/-10%, X5R, 0603 CAP, CERM, 3900pF, 50V, +/-10%, X7R, 0603 CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603, CAP, CERM, 0.1F, 25V, +/-10%, X7R, 0603 Kemet Kemet MuRata Kemet C0805C124K5RACTU C0603C684K8PAC GRM188R71H392KA01D C0603C104K3RACTU 1 1 1 12 C9 C10, C29, C32, C341 C11 CAP, CERM, 82pF, 50V, +/-10%, C0G/NP0, 0603 CAP, CERM, 2200pF, 50V, +/-10%, X7R, 0603 Kemet Kemet C0603C820K5GACTU C0603C222K5RACTU 1 4 CAP, CERM, 10F, 10V, +/-20%, X5R, 0805 Kemet C0805C106M8PACTU 1 6 7 8 9 10 11 12 Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 59 13 C23, C26, R103, R104, R111, R112, R125, R126, R133, R134, R213, R215, R221, R222, R231, R232, R338 RES, 240 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW0603240RJNEA 17 14 15 C28, C34 C35, C310, C317, C324, C352, Cb2pB1 CAP, CERM, 2pF, 50V, +/-12.5%, C0G/NP0, 0603 CAP, CERM, 10uF, 10V, +/-10%, X5R, 0805 Kemet Kemet C0603C209C5GACTU C0805C106K8PACTU 2 6 16 17 C304 C311, C313, C318, C321, C325, C331, C342 CAP, CERM, 1000pF, 50V, +/-5%, C0G/NP0, 0603 CAP, CERM, 1uF, 10V, +/-10%, X5R, 0603 Kemet Kemet C0603C102J5GACTU C0603C105K8PACTU 1 7 18 19 20 C315, C323 C340 C350, C351, C359, C360 C368 C403 C404 C405, C408 C406, C407 C410, C411 C413, C415 Cb1_B1 CAP, CERM, 0.01uF, 100V, +/-10%, X7R, 0603 CAP, CERM, 4.7uF, 10V, +/-10%, X5R, 0603 CAP, CERM, 0.47uF, 16V, +/-10%, X7R, 0603 Kemet Kemet Kemet C0603C103K1RACTU C0603C475K8PACTU C0603C474K4RACTU 2 1 4 CAP, CERM, 100pF, 50V, +/-5%, C0G/NP0, 0603 CAP, CERM, 10uF, 6.3V, +/-10%, X5R, 0805 CAP, TANT, 1uF, 20V, +/-10%, 8.4 ohm, 3216-18 SMD CAP, CERM, 0.22uF, 16V, +/-10%, X7R, 0603 CAP, CERM, 18pF, 50V, +/-5%, C0G/NP0, 0603 CAP, CERM, 1uF, 16V, +/-10%, X5R, 0603 CAP, CERM, 0.01uF, 50V, +/-5%, X7R, 0603 CAP, CERM, 0.33uF, 16V, +/-10%, X7R, 0603 Kemet Kemet Vishay-Sprague Kemet Kemet Kemet Kemet Kemet C0603C101J5GACTU C0805C106K9PAC 293D105X9020A2TE3 C0603C224K4RACTU C0603C180J5GACTU C0603C105K4PACTU C0603C103J5RACTU C0603C334K4RACTU 1 1 1 2 2 2 2 1 21 22 23 24 25 26 27 28 60 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 29 CLKin0, CLKin0*, CLKout0, CLKout0*, CLKout2, CLKout2*, CLKout4, CLKout4*, CLKout6, CLKout6*, CLKout8, CLKout8*, CLKout10, CLKout10*, FBCLKin*/CLKin1*, OSCout0, OSCout0*, OSCout1, OSCout1* Connector, SMT, End launch SMA 50 Ohm Emerson Network Power 142-0701-851 19 30 31 32 CR400, CR401 D1 D2, D3, D4 ESD suppressor Common Cathode Tuning Varactor LED 2.8X3.2MM 565NM RED CLR SMD PGB1010603MR SMV1249-074LF SML-LX2832IC 2 1 3 33 D5 LED 2.8X3.2MM 565NM GRN CLR SMD SML-LX2832GC 1 34 35 J1 R2, R13, R36, R47, R59, R70, R332 CONN TERM BLK PCB 5.08MM 2POS OR RES, 0 ohm, 5%, 0.125W, 0805 Littelfuse Inc Skyworks Lumex Opto/Components Inc. Lumex Opto/Components Inc. Weidmuller Vishay-Dale 1594540000 CRCW08050000Z0EA 1 7 36 37 38 39 40 R2_A1 R2_A2 R2_B2 R4, R9 R18, R336, R342, R343 R24 RES, 39k ohm, 5%, 0.1W, 0603 RES, 620 ohm, 5%, 0.1W, 0603 RES, 470 ohm, 5%, 0.1W, 0603 RES, 100 ohm, 5%, 0.1W, 0603 FB, 1000 ohm, 600 mA, 0603, Ferrite Vishay-Dale Vishay-Dale Vishay-Dale Vishay-Dale Murata CRCW060339K0JNEA CRCW0603620RJNEA CRCW0603470RJNEA CRCW0603100RJNEA BLM18HE102SN1D 1 1 1 2 4 RES, 18 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW060318R0JNEA 1 41 Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 61 42 R26, R27, R83, R85 R43, R107, R108, R129, R130, R151, R152, R173, R174, R195, R196, R217, R218 RES, 270 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW0603270RJNEA 4 RES, 68 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW060368R0JNEA 13 44 R61, R102, R117, R124, R138, R142, R158, R164, R182, R190, R206, R212, R228 RES, 51 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW060351R0JNEA 13 45 46 R62, R67 R80, R81, R312, R315, R317, R318, R321, R324 RES, 4.7k ohm, 5%, 0.1W, 0603 RES, 15k ohm, 5%, 0.1W, 0603 Vishay-Dale Vishay-Dale CRCW06034K70JNEA CRCW060315K0JNEA 2 8 47 48 49 R233, R234 R307 R313, R316, R319, R320, R322, R325 RES, 33 ohm, 5%, 0.1W, 0603 RES, 10k ohm, 5%, 0.1W, 0603 RES, 27k ohm, 5%, 0.1W, 0603 Vishay-Dale Vishay-Dale Vishay-Dale CRCW060333R0JNEA CRCW060310K0JNEA CRCW060327K0JNEA 2 1 6 50 51 R344 R345, R348, R355, R359, R362, R366, R372 RES, 392 ohm, 1%, 0.1W, 0603 FB, 120 ohm, 500 mA, 0603 Vishay-Dale Murata CRCW0603392RFKEA BLM18AG121SN1D 1 7 52 53 54 55 56 57 58 R350, R369 R351 R356 R404, R405 R407, R411 Rb2_B1 S1, S2, S3, S4, S5, S6 U1 RES, 51k ohm, 5%, 0.1W, 0603 RES, 2.00k ohm, 1%, 0.1W, 0603 RES, 866 ohm, 1%, 0.1W, 0603 RES, 22 ohm, 5%, 0.125W, 0805 RES, 47k ohm, 5%, 0.1W, 0603 RES, 3.9k ohm, 5%, 0.1W, 0603 0.875" Standoff Vishay-Dale Vishay-Dale Vishay-Dale Vishay-Dale Vishay-Dale Vishay-Dale VOLTREX CRCW060351K0JNEA CRCW06032K00FKEA CRCW0603866RFKEA CRCW080522R0JNEA CRCW060347K0JNEA CRCW06033K90JNEA SPCS-14 2 1 1 2 2 1 6 LMK04800 Texas Instruments LMK048xxBISQ 1 43 59 62 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 60 61 62 U2 U4, U300 U302 63 U303, U305 64 65 uWire Vcc 66 VccVCO/Aux, VccVCXO/Aux 67 68 69 B1, B2, B3 C2pA1 C2pA2, C3_AB1, C15, C17, C42, C43, C306, C307, C308, C309 70 71 72 C2_B2 C3, C36, C335 C7, C8, C16, C18, C33, C45, C49, C50, C55, C56, C61, C62, C67, C68, C73, C74, C79, C80, C301, C303, C305 73 C39, C40, C333, Cb1_VCO, Cb2_B1, Cb2_VCO, Cb2pVCO 74 C316, C320, C327, C328, C332, C334, C336 122.88 MHz VCXO Precison Single Low Noise, Low 1/F corner Op Amp Micropower 800mA Low Noise 'Ceramic Stable' Adjustable Voltage Regulator for 1V to 5V Applications Ultra Low Noise, 150mA Linear Regulator for RF/Analog Circuits Requires No Bypass Capacitor Low Profile Vertical Header 2x5 0.100" Connector, TH, SMA Crystek Texas Instruments Texas Instruments CVHD-950-122.88 LMP7731MF LP3878SD-ADJ 1 2 1 Texas Instruments LP5900SD-3.3 2 FCI Emerson Network Power Emerson Network Power Connectivity 52601-G10-8LF 142-0701-201 1 1 142-0711-201 2 Unpopulated Components ADT2-1T Balun MiniCircuits CAP, CERM, 2.7uF, 10V, +/-10%, X5R, 0805 Kemet CAP, CERM, 100pF, 50V, +/-5%, C0G/NP0, 0603 Kemet ADT2-1T+ C0805C275K8PACTU C0603C101J5GACTU 0 0 0 CAP, CERM, 6800pF, 100V, +/-10%, X7R, 0603 CAP, CERM, 0.1uF, 25V, +/-5%, X7R, 0603 CAP, CERM, 0.1uF, 16V, +/-10%, X7R, 0603 C0603C682K1RACTU C0603C104J3RACTU C0603C104K4RACTU 0 0 0 DNP_CAP 0 C0603C104J4RACTU 0 Connector, SMA Jack, Vertical, Gold, SMD Kemet Kemet Kemet Technology, Dielectric, xxV, xx% CAP, CERM, 0.1uF, 16V, +/-5%, X7R, 0603 Revised - August 2014 Kemet LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 63 75 C337, C343, C347, C353, C356, C364 CAP, CERM, 1uF, 10V, +/-10%, X5R, 0603 Kemet C0603C105K8PACTU 0 76 C338, C344, C348, C354, C357, C365 CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603 Kemet C0603C104K3RACTU 0 77 C339, C345, C349, C355, C358, C366 CAP, CERM, 0.01uF, 100V, +/-10%, X7R, 0603 Kemet C0603C103K1RACTU 0 78 CLKin0_SEL, CLKin1_SEL, Status_Hold, Status_LD, SYNC Connector, SMA Jack, Vertical, Gold, SMD Emerson Network Power Connectivity 142-0711-201 0 79 CLKout1, CLKout1*, CLKout3, CLKout3*, CLKout5, CLKout5*, CLKout7, CLKout7*, CLKout9, CLKout9*, CLKout11, CLKout11*, FBCLKin/CLKin1, OSCin, OSCin*, Vtune1 Connector, SMT, End launch SMA 50 Ohm Emerson Network Power 142-0701-851 0 80 81 82 D300 GND_TP, Vcc_TP HWB, RESET Diode, Zener, 3.3V, 150mW, SOD-523F Comchip Technology 0 0 0 83 J400 CONN RCPT MINI USB2.0 5POS SMD APEM Components, LLC Hirose Electric Co. Ltd. CZRU52C3V3 DNP_TP ADTSM31NV UX60SA-MB-5ST 0 64 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 84 R1, R20, R23, R51, R52, R53, R54, R60, R63, R66, R69, R71, R72, R75, R76, R77, R78, R230, R300, R301, R305, R306, R308, R335, R339, R352, R363, R367, R370 RES, 0 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW06030000Z0EA 0 85 R5, R8, R14, R25, R33, R34, R41, R48, R64, R68, R90, R96, R99, R114, R121, R135, R141, R157, R163, R179, R187, R204, R209, R225, R376 RES, 51 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW060351R0JNEA 0 86 R6, R7, R15, R17, R31, R32, R39, R40, R49, R50, R79, R314 RES, 270 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW0603270RJNEA 0 Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 65 87 R10, R16, R88, R94, R97, R100, R113, R115, R119, R122, R136, R139, R143, R145, R159, R161, R165, R167, R180, R183, R185, R188, R201, R202, R207, R210, R223, R226 RES, 120 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW0603120RJNEA 0 88 89 R28, R42, R65 R35, R44, R89, R95, R98, R101, R116, R118, R120, R123, R137, R140, R144, R146, R160, R162, R166, R168, R181, R184, R186, R189, R203, R205, R208, R211, R224, R227 RES, 100 ohm, 5%, 0.1W, 0603 RES, 82 ohm, 5%, 0.1W, 0603 Vishay-Dale Vishay-Dale CRCW0603100RJNEA CRCW060382R0JNEA 0 0 66 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 90 R38, R45, R91, R93, R105, R106, R109, R110, R127, R128, R131, R132, R149, R150, R153, R154, R171, R172, R175, R176, R193, R194, R197, R198, R214, R216, R219, R220 RES, 62 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW060362R0JNEA 0 91 92 93 R86, R87 R92 R147, R148, R155, R156, R169, R170, R177, R178, R191, R192, R199, R200 RES, 27k ohm, 5%, 0.1W, 0603 RES, 68 ohm, 5%, 0.1W, 0603 RES, 240 ohm, 5%, 0.1W, 0603 Vishay-Dale Vishay-Dale Vishay-Dale CRCW060327K0JNEA CRCW060368R0JNEA CRCW0603240RJNEA 0 0 0 94 R302, R303, R310, R311, R401 R309, Rb2_VCO R323 R326, R328, R330 R334 R360 R403, R406, R408, R409, R410 U3 U301 U400, Y400 Y300, Y301 RES, 10k ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW060310K0JNEA 0 x%, x.xxxW RES, 2.2k ohm, 5%, 0.1W, 0603 FB, 1000 ohm, 600 mA, 0603 RES, 0 ohm, 5%, 0.125W, 0805 RES, 51k ohm, 5%, 0.1W, 0603 RES, 33 ohm, 5%, 0.1W, 0603 Vishay-Dale Murata Vishay-Dale Vishay-Dale Vishay-Dale DNP_RES CRCW06032K20JNEA BLM18HE102SN1D CRCW08050000Z0EA CRCW060351K0JNEA CRCW060333R0JNEA 0 0 0 0 0 0 VCO 3-Terminal Adjustable Regulator Texas Instruments CRO2949A-LF LM317AEMP 0 0 0 0 95 96 97 98 99 100 101 102 103 104 Revised - August 2014 DNP_XTAL LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 67 Appendix E: PCB Layers Stackup Top Layer [LMK048xxENG.GTL] RO4003 (Er = 3.3) 16 mil RF Ground plane [LMK048xxENG.G1] FR4 (Er = 4.8) 4 mil Power plane #1 [LMK048xxENG.G2] FR4 12.6 mil Ground plane [LMK048xxENG.GP1] FR4 8 mil Power plane #2 [LMK048xxENG.G3] FR4 12 mil Bottom Layer [LMK048xxENG.GBL] 68 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 62.2 mil thick 6-layer PCB Stackup includes: * Top Layer for high-priority high-frequency signals (2 oz.) * RO4003 Dielectric, 16 mils * RF Ground plane (1 oz.) * FR4, 4 mils * Power plane #1 (1 oz.) * FR4, 12.6 mils * Ground plane (1 oz.) * FR4, 8 mils * Power Plane #2 (1 oz.) * FR4, 12 mils * Bottom Layer copper clad for thermal relief (2 oz.) Appendix F: PCB Layout Layer #1 - Top Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 69 Layer #2 - RF Ground Plane (Inverted) 70 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Layer #3 - Vcc Planes Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 71 Layer #4 - Ground Plane (Inverted) 72 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Layer # 5 - Vcc Planes 2 Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 73 Layer #6 - Bottom 74 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 Layers #1 and 6 - Top and Bottom (Composite) Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 75 Appendix G: EVM Software and Communication: Interfacing uWire Codeloader is the software used to communicate with the EVM (Please download the latest version from TI.com - http://www.ti.com/tool/codeloader). This EVM can be controlled through the uWire interface on board. There are two options in communicating with the uWire interface from the computer. OPTION 1 Open Codeloader.exe Click "Select Device" Click "Port Setup" tab Click "LPT" (in Communication Mode) OPTION 2 76 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 The Adapter Board This table describes the pins configuration on the adapter board for each EVM board (See examples below table) Jumper Bank Code Loader Configuration EVM A B C D E F G H LMX2581 A4 B1 C2 E5 F1 G1 H1 BUFEN (pin 1), Trigger (pin 7) LMX2541 A4 C3 E4 F1 G1 H1 CE (pin 1), Trigger (pin 10) LMK0400x A0 C3 E5 F1 G1 H1 GOE (pin 7) LMK01000 A0 C1 E5 F1 G1 H1 GOE (pin 7) LMK030xx A0 C1 E5 F1 G1 H1 SYNC (pin 7) LMK02000 A0 C1 E5 F1 G1 H1 SYNC (pin 7) LMK0480x A0 B2 C3 E5 F0 G0 H1 Status_CLKin1 (pin 3) LMK04816/4906 A0 B2 C3 E5 F0 G0 H1 Status_CLKin1 (pin 3) LMK01801 A0 B4 C5 E2 F0 G0 H1 Test (pin 3), SYNC0 (pin 10) LMK0482x (prelease) A0 B5 C3 D2 E4 F0 G0 H1 CLKin1_SEL (pin 6), Reset (pin 10) LMX2531 A0 E5 F2 G1 H2 Trigger (pin 1) LMX2485/7 A0 C1 E5 F2 G1 H0 ENOSC (pin 7), CE (pin 10) LMK03200 A0 E5 F0 G0 H1 SYNC (pin 7) LMK03806 A0 C1 E5 F0 G0 H1 LMK04100 A0 C1 E5 F1 G1 H1 Example adapter configuration (LMK01801) Open Codeloader.exe Click "Select Device" Click "Port Setup" Tab Click "USB" (in Communication Mode) *Remember to also make modifications in "Pin Configuration" Section according to Table above. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 77 Appendix H: Troubleshooting Information If the evaluation board is not behaving as expected, the most likely issues are... 1) Board communication issue 2) Incorrect Programming of the device 3) Setup Error Refer to this checklist for a practical guide on identifying/exposing possible issues. 1) Confirm Communications 2) Confirm PLL1 operation/locking 1) Program LD_MUX = "PLL1_R/2" 2) Confirm that LD pin output is half the expected phase detector frequency of PLL1. i. If not, examine CLKin_SEL programming. ii. If not, examine CLKin0_BUFTYPE / CLKin1_BUFTYPE. iii. If not, examine PLL1 register R programming. iv. If not, examine physical CLKin input. 3) Program LD_MUX = "PLL1_N /2" 4) Confirm that LD pin output is half the expected phase detector frequency of PLL1. i. If not, examine PLL1 register N programming. ii. If not, examine physical OSCin input. Naturally, the output frequency of the above two items, PLL 1 R Divider/2 and PLL 1 N Divider /2, on LD pin should be the same frequency. 5) Program LD_MUX = "PLL1_DLD" 6) Confirm the LD pin output is high. i. If high, then PLL1 is locked, continue to PLL2 operation/locking. 7) If LD pin output is low, but the frequencies are the same, it is possible that excessive leakage on Vtune pin is causing the digital lock detect to not activate. By default PLL2 waits for the digital lock detect to go high before allowing PLL2 and the integrated VCO to lock. Different VCXO models have different input leakage specifications. High leakage, low PLL1 phase detector frequencies, and low PLL1 charge pump current settings can cause the PLL1 charge pump to operate longer than the digital lock detect timeout which allows the device to lock, but prevents the digital lock detect from activating. i. Redesign PLL1 loop filter with higher phase detector frequency ii. Redesign PLL1 loop filter with higher charge pump current iii. Isolate VCXO tuning input from PLL1 charge pump with an op amp. 78 SNAU076B LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com Revised - August 2014 3) Confirm PLL2 operation/locking 1) Program LD_MUX = "PLL2_R/2" 2) Confirm that LD pin output is half the expected phase detector frequency of PLL2. i. If not, examine PLL2_R programming. ii. If not, examine physical OSCin input. 3) Program LD_MUX = "PLL2_N/2" 4) Confirm that LD pin output is half the expected phase detector frequency of PLL2. i. If not, confirm OSCin_FREQ is programmed to OSCin frequency. ii. If not, examine PLL2_N programming. Naturally, the output frequency of the above two items should be the same frequency. 5) Program LD_MUX = "PLL2 DLD" 6) Confirm the LD pin output is high. 7) Program LD_MUX = "PLL1 & PLL2 DLD" 8) Confirm the LD pin output is high. Revised - August 2014 LMK04800 Family Copyright (c) 2014, Texas Instruments Incorporated www.ti.com SNAU076B 79 STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES 1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or documentation (collectively, an "EVM" or "EVMs") to the User ("User") in accordance with the terms and conditions set forth herein. Acceptance of the EVM is expressly subject to the following terms and conditions. 1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For clarification, any software or software tools provided with the EVM ("Software") shall not be subject to the terms and conditions set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software 1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned, or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production system. 2 Limited Warranty and Related Remedies/Disclaimers: 2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License Agreement. 2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as mandated by government requirements. TI does not test all parameters of each EVM. 2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM, or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day warranty period. 3 Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter. 3.1.2 For EVMs annotated as FCC - FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant: CAUTION This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER FCC Interference Statement for Class B EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: * * * * Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help. 3.2 Canada 3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 Concerning EVMs Including Radio Transmitters: This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concernant les EVMs avec appareils radio: Le present appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisee aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioelectrique subi, meme si le brouillage est susceptible d'en compromettre le fonctionnement. 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Concernant les EVMs avec antennes detachables Conformement a la reglementation d'Industrie Canada, le present emetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inferieur) approuve pour l'emetteur par Industrie Canada. Dans le but de reduire les risques de brouillage radioelectrique a l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnee equivalente (p.i.r.e.) ne depasse pas l'intensite necessaire a l'etablissement d'une communication satisfaisante. Le present emetteur radio a ete approuve par Industrie Canada pour fonctionner avec les types d'antenne enumeres dans le manuel d'usage et ayant un gain admissible maximal et l'impedance requise pour chaque type d'antenne. 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