LMK04808BEVAL/NOPB - Texas Instruments

LMK048xx Evaluation Board

User's Guide

August 2011

SNAU076B

Revised August 2014

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Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

Evaluation Boa rd O perating Instruc tions

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Table of Co nte n ts

TABLE OF CONTENTS ..............................................................................................................................................................3

GENERAL DESCRIPTION ..........................................................................................................................................................5

EVALUATION BOARD KIT CONTENTS ................................................................................................................................................... 5

AVAILABLE LMK048XX EVALUATION BOARDS ...................................................................................................................................... 5

AVAILABLE LMK04800 FAMILY DEVICES ............................................................................................................................................ 5

QUICK START ..........................................................................................................................................................................6

DEFAULT CODELOADER MODES FOR EVALUATION BOARDS ..................................................................................................................... 7

EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04808B ............................................................................................8

1. START CODELOADER 4 APPLICATION ............................................................................................................................................... 8

2. SELECT DEVICE ............................................................................................................................................................................ 8

3. PROGRAM/LOAD DEVICE .............................................................................................................................................................. 8

4. RESTORING A DEFAULT MODE ....................................................................................................................................................... 9

5. VISUAL CONFIRMATION OF FREQUENCY LOCK ................................................................................................................................. 10

6. ENABLE CLOCK OUTPUTS ............................................................................................................................................................ 10

PLL LOOP FILTERS AND LOOP PARAMETERS ......................................................................................................................... 12

PLL 1 LOOP FILTER ....................................................................................................................................................................... 12

122.88 MHz VCXO PLL ......................................................................................................................................................... 12

PLL2 LOOP FILTER ........................................................................................................................................................................ 13

Integrated VCO PLL ............................................................................................................................................................. 13

EVALUATION BOARD INPUTS AND OUTPUTS ........................................................................................................................ 14

RECOMMENDED TEST EQUIPMENT ...................................................................................................................................... 22

PROGRAMMING 0-DELAY MODE IN CODELOADER ............................................................................................................... 23

OVERVIEW ................................................................................................................................................................................... 23

DUAL LOOP 0-DELAY MODE EXAMPLES ............................................................................................................................................ 23

Programming Steps ............................................................................................................................................................. 23

Details ................................................................................................................................................................................. 23

SINGLE LOOP 0-DELAY MODE EXAMPLES .......................................................................................................................................... 25

Programming Steps ............................................................................................................................................................. 25

Details ................................................................................................................................................................................. 25

APPENDIX A: CODELOADER USAGE....................................................................................................................................... 27

PORT SETUP TAB .......................................................................................................................................................................... 27

CLOCK OUTPUTS TAB ..................................................................................................................................................................... 28

PLL1 TAB .................................................................................................................................................................................... 30

Setting the PLL1 VCO Frequency and PLL2 Reference Frequency ........................................................................................ 31

PLL2 TAB .................................................................................................................................................................................... 32

BITS/PINS TAB ............................................................................................................................................................................. 33

REGISTERS TAB ............................................................................................................................................................................. 38

APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS .................................................................................................. 39

PLL1 .......................................................................................................................................................................................... 39

122.88 MHz VCXO Phase Noise ........................................................................................................................................... 39

Clock Output Measurement Technique ............................................................................................................................... 40

Buffered OSCout Phase Noise .............................................................................................................................................. 40

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CLOCK OUTPUTS (CLKOUT) ............................................................................................................................................................ 41

LMK04808B CLKout Phase Noise ......................................................................................................................................... 41

LMK04808B OSCout Phase Noise ........................................................................................................................................ 43

LMK04806B CLKout Phase Noise ......................................................................................................................................... 44

LMK04806B OSCout Phase Noise ........................................................................................................................................ 46

LMK04803B CLKout Phase Noise ......................................................................................................................................... 47

LMK04803B OSCout Phase Noise ........................................................................................................................................ 49

APPENDIX C: SCHEMATICS .................................................................................................................................................... 50

POWER SUPPLIES .......................................................................................................................................................................... 50

LMK048XXB DEVICE WITH LOOP FILTER AND CRYSTAL CIRCUITS ........................................................................................................... 51

REFERENCE INPUTS (CLKIN0 & CLKIN1), EXTERNAL VCXO (OSCIN) & VCO CIRCUITS, AND OSCOUT1 OUTPUT ........................................... 52

CLOCK OUTPUTS (OSCOUT0, CLKOUT0 TO CLKOUT3) ........................................................................................................................ 53

CLOCK OUTPUTS (CLKOUT4 TO CLKOUT7)........................................................................................................................................ 54

CLOCK OUTPUTS (CLKOUT8 TO CLKOUT11)...................................................................................................................................... 55

UWIRE HEADER, LOGIC I/O PORTS AND STATUS LEDS ......................................................................................................................... 56

USB INTERFACE ............................................................................................................................................................................ 57

APPENDIX D: BILL OF MATERIALS ......................................................................................................................................... 58

APPENDIX E: PCB LAYERS STACKUP ..................................................................................................................................... 68

APPENDIX F: PCB LAYOUT ..................................................................................................................................................... 69

LAYER #1 – TOP ........................................................................................................................................................................... 69

LAYER #2 – RF GROUND PLANE (INVERTED) ...................................................................................................................................... 70

LAYER #3 – VCC PLANES ................................................................................................................................................................ 71

LAYER #4 – GROUND PLANE (INVERTED) ........................................................................................................................................... 72

LAYER # 5 – VCC PLANES 2 ............................................................................................................................................................. 73

LAYER #6 – BOTTOM ..................................................................................................................................................................... 74

LAYERS #1 AND 6 – TOP AND BOTTOM (COMPOSITE) .......................................................................................................................... 75

APPENDIX G: EVM SOFTWARE AND COMMUNICATION: INTERFACING UWIRE ..................................................................... 76

APPENDIX H: TROUBLESHOOTING INFORMATION ................................................................................................................ 78

1) CONFIRM COMMUNICATIONS ................................................................................................................................................ 78

2) CONFIRM PLL1 OPERATION/LOCKING ..................................................................................................................................... 78

3) CONFIRM PLL2 OPERATION/LOCKING ..................................................................................................................................... 79

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General Description

The LMK048xx Evaluation Board simplifies evaluation of the LMK048xxB Low-Noise Clock Jitter

Cleaner with Dual Loop PLLs. Texas Instruments Incorporated’s CodeLoader software can be used to

program the internal registers of the LMK048xxB device through the USB2ANY-uWire interface. The

CodeLoader software will run on a Windows 7 or Windows XP PC and can be downloaded from

http://www.ti.com/tool/codeloader/.

Evaluation Board Kit Contents

The evaluation board kit includes:

• (1) LMK048xx Evaluation Board from Table 1

• (1) LMK04800 Family Quick Start Guide

o Evaluation board instructions can be downloaded from www.ti.com.

• (1) LPT Cable or USB2ANY-uWire (HPA665-001) + adapter (Please see “EVM Software and

Communication” for more information)

Available LMK048xx Evaluation Boards

The LM K048x x Evaluation Board supports any of the four devices offered in the LMK04800 Family. All

evaluation boards use the same PCB layout and bill-of-materials, except for the corresponding

LMK0480xxB device affixed to the board. A commercial-quality VCXO is also mounted to the board to

provide a known reference point for evaluating device performance and functionality.

Table 1: Available Evaluation Board Configurations

Evaluation Board ID

Device

PLL1 VCXO

LMK04803BEVAL

LMK04803B

122.88 MHz Crystek VCXO

Model CVHD-950-122.880

LMK04805BEVAL

LMK04805B

LMK04806BEVAL

LMK04806B

LMK04808BEVAL

LMK04808B

Available LMK04800 Family Devices

Table 2: LMK048xxB Devices

Device Reference

Inputs

Buffered/

Divided

OSCin

Outputs

Programmable

LVDS/LVPECL/

LVCMOS

Outputs

VCO Frequency

LMK04803B

2 2 12

1840 to 2030 MHz

LMK04805B

2148 to 2370 MHz

LMK04806B

2370 to 2600 MHz

LMK04808B

2750 to 3072 MHz

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Quick Start

Full evaluation board instructions are downloadable from the LMK048xxB device product folder at

www.ti.com.

1. Connect a power supply voltage of 5 V to the Vcc SMA connector. The onboard LP3878-ADJ

LDO regulator will output a low-noise 3.3 V supply to operate the device.

2. Connect a reference clock from a signal source to the CLKin1 SMA port. Use 122.88 MHz for

default. The reference frequency depends on the device programming.

3. Please see Appendix G for quick start on interfacing the board

4. Program the device with a default mode using CodeLoader. Ctrl+L must be pressed at least once

to load all registers. Alternatively click menu “Keyboard Controls”  “Load Device”.

CodeLoader can be downloaded from http://www.ti.com/tool/codeloader.

5. Measurements may be made on an active output clock port via its SMA connector.

Figure

1: Quick Start Diagram

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Default CodeLoader Modes for Evaluation Boards

CodeLoader saves the state of the sele cted LMK04 8 xxB device when exiting the software. To ensure a

common starting point, the following modes listed in Table 3 may be restored by clicking “Mode” and

selecting the appropriate device configuration, as shown in Figure 2 in the case of the LMK04808B

device. Similar default modes are available for each LMK048xxB device in CodeLoader. Choose a mode

with CLKin0 for differential clock signal or CLKin1 for a single ended signal.

Figure 2: Selecting a Default Mode for the LM K04808 Device

After restoring a default mode, press Ctrl+L to program the device. The default modes also disable

certain outputs, so make sure to enable the output under test to make measurements.

Table 3: Default CodeLoader Modes for LMK04808

Default CodeLoader Mode Device Mode

CLKin

Frequency

OSCin

Frequency

122.88 MHz CLKin1, 122.88 MHz

VCXO

Dual PLL, Internal VCO 122.88 MHz 122.88 MHz

122.88 MHz CLKin1, Dual Loop 0-

delay, 122.88 MHz VCXO

Dual PLL, Internal VCO,

0-Delay with Internal

Feedback

122.88 MHz 122.88 MHz

122.88 MHz CLKin1, 122.88 MHz

VCXO

Dual PLL, Internal VCO,

PLL2 Crystal Oscillator

Enabled

122.88 MHz 20.48 MHz

122.88 MHz CLKin1, 122.88 MHz

VCXO

Dual PLL, Internal VCO 122.88 MHz 122.88 MHz

122.88 MHz CLKin1, Dual Loop 0-

delay, 122.88 MHz VCXO

Dual PLL, Internal VCO,

0-Delay with Internal

Feedback

122.88 MHz 122.88 MHz

122.88 MHz CLKin1, 122.88 MHz

VCXO

Dual PLL, Internal VCO,

PLL2 Crystal Oscillator

Enabled

122.88 MHz 20.48 MHz

The next section outlines step-by-step procedures for using the evaluation board with the LMK04808B.

For boards with another part number, make sure to select the corresponding part number under the

“Device” menu.

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Example: Using CodeLoader to Program the LMK04808B

The purpose of this section is to walk the user through using CodeLoader 4 to make some measurements

with the LMK04808B device as an example. For more information on CodeLoader refer to Appendix A:

CodeLoader Usage or the CodeLoader 4 instructions located at http://www.ti.com/tool/codeloader.

Before proceeding, be sure to follow the Quick Start section above to ensure proper connections.

1. Start CodeLoader 4 A pplication

Click “Start”  “Programs”  “CodeLoader 4”  “CodeLoader 4”

The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.

2. Select Device

Click “Select Device”  “Clock Conditioners”  “LMK04808B”

Once started CodeLoader 4 will load the last used

device. To load a new device click “Select Device”

from the menu bar, then select the subgroup and

finally device to load. For this example, the

LMK04808B is chosen. Selecting the device does

cause the device to be programmed.

Figure 3 – Selecting the LMK04808B device

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3. Program/Load Device

Assuming the Port Setup settings are correct, press the

“Ctrl+L” shortcut or click “Keyboard Controls”  “Load

Device” from the menu to program the device to the

current state of the newly loaded LMK04800 file.

Once the device has been initially loaded, CodeLoader will

automatically program changed registers so it is not

necessary to re-load the device upon subsequent changes in the device configuration. It is possible to

disable this functionality by ensuring there is no checkmark by the “Options”  “AutoReload with

Changes.”

Because a default mode will be restored in the next step, this step isn’t really needed but included to

emphasize the importance of pressing “Ctrl+L” to load the device at least once after starting CodeLoader,

restoring a mode, or restoring a saved setup using the File menu.

See Appendix A: CodeLoader Usage or the CodeLoader 4 instructions located at

http://www.ti.com/tool/codeloader for more information on Port Setup. Appendix H: Troubleshooting

Information contains information on troubleshooting communications.

4. Restoring a Default Mode

Click “Mode”  “LMK04808B, 122.88 MHz VCXO, 122.88 MHz CLKin1”; then press Ctrl+L.

Figure 5: Setting the Default mode for LMK04808

For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point.

This is important because when CodeLoader is closed, it remembers the last settings used for a particular

device. Again, remember to press Ctrl+L as the first step after loadin g a default mode.

Figure 4 – Loading the Device

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5. V isual Confirmation of Frequency Lock

After a default mode is restored and loaded, LED D5 should illuminate when PLL1 and PLL2 are locked

to the reference clock applied to CLKin1. This assumes LD_MUX = PLL1/2 DLD and LD_TYPE =

Active High, which are the default settings.

6. Enable Clock Outputs

While the LMK048xxB offers programmable clock output buffer formats, the evaluation board is shipped

with preconfigured output terminations to match the default buffer type for each output. Refer to the

CLKout port description in the Evaluation Board Inputs and Outputs section.

To measure phase noise at one of the clock outputs, for example, CLKout0:

1. Click on the Clock Outputs tab,

2. Uncheck “Powerdown” in the Digital Delay box to enable the channel,

3. Set the following settings as needed:

a. Digital Delay value

b. Clock Divider value

c. Analog Delay select and Analog Delay value (if not “Bypassed”)

d. Clock Output type.

4. Depending on the configured output type, the clock output SMAs can be interfaced to a test

instrument with a single-ended 50-ohm input as follows.

a. For LVDS:

i. A balun (like ADT2-1T) is recommended for differential-to-single-ended

conversion.

b. For LV P E CL:

i. A balun can be used, or

ii. One side of the LVPECL signal can be terminated with a 50-ohm load and the

other side can be run single-ended to the instrument.

c. For LVCMOS:

i. There are two single-ended outputs,

CLKoutX and CLKoutX*, and each output

can be set to Norm al , Inv ert ed, or Off. There

are nine (9) combinations of LVCMOS modes

in the Clock Output list.

ii. One side of the LVCMOS signal can be

terminated with a 50-ohm load and the other

side can be run single-ended to the

instrument.

iii. A balun may also be used. Ensure

CLKoutX and CLKoutX* states are

Figure 7: Setting LVCMOS modes

Figure 6: Setting Digital Delay, Clock Divider, Analog Delay, and Output Format for CLKout0

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complementary to each other, i.e.: Norm/Inv or Inv/Norm.

5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.

See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock outputs.

Texas Instrumen ts Inco rp o rated ’s Clock Design Tool can be used to calculate divider values to achieve

desired clock output frequencies. See: http://www.ti.com/tool/clockdesigntool.

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PLL Loop Filters and Loop Parameters

In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to

substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for the phase noise of a

“dirty” reference clock. The first PLL is typically configured with a narrow loop bandwidth in order to

minimize the impact of the reference clock phase noise. The reference clock consequently serves only as a

frequency reference rather than a phase reference.

The loop filters on the LMK048xx evaluation board are setup using the approach above. The loop filter

for PLL1 has been configured for a narrow loop bandwidth (< 100 Hz), while the loop filter of PLL2 has

been configured for a wide loop bandwidth (> 100 kHz). The specific loop bandwidth values depend on

the phase noise performance of the oscillator mounted on the board. The following tables contain the

parameters for PLL1 and PLL2 for each oscillator option.

Texas Instrumen ts Inco rp o rated ’s Clock Design Tool can be used to optimize PLL phase noise/jitter for

given specifications. See: http://www.ti.com/tool/clockdesigntool/.

PLL 1 Loop Filter

Table 4: PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO

122.88 MHz VCXO PLL

Phase Margin

49˚

Kφ (Ch arg e Pu mp)

100 uA

Loop Bandwidth 12 Hz Phase Detector Freq 1.024 MHz

VCO Gain

2.5 kHz/Volt

Referen ce Clo ck

Frequency 122.88 MHz Output Frequency 122.88 MHz (To PLL 2)

Loop Filter

Components C1_A1 = 100 nF C2_A1 = 680 nF R2_A1 = 39 kΩ

Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and

N will change the loop bandwidth.

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PLL2 Loop Filter

Table 5: PLL2 Loop Filter Parameters for LMK048xxB

Integrated VCO PLL

LMK04803B

LMK04805B

LMK04806B

LMK04808B

C1_A2

0.047

C2_A2

3.9

C3 (internal)

C4 (internal)

R2_A2

0.62

kΩ

R3 (internal)

0.2

kΩ

R4 (internal)

0.2

kΩ

Charge Pu mp

Current, Kφ

3.2 mA

Phase Detector

Frequency

122.88 MHz

Frequency

1966.08

2211.84

2457.6

2949.12

MHz

Kvco

17.9

16.5

18.8

32.3

MHz/V

Phase Margin

degrees

Loop

Bandwidth

355 320 321 424 kHz

Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and

N will change the loop bandwidth.

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Evaluation Board Inputs and Outputs

The following table contains descriptions of the inputs and outputs for the evaluation board. Unless

otherwise noted, the connectors described can be assumed to be populated by default. Additionally, some

applicable CodeLoader programming controls are noted for convenience. Refer to the LMK04800 Family

Datasheet for complete register programming information.

Table 6: Evaluation Board Inputs and Outputs

Connector Name

Signal Type,

Input/Output

Description

Populated:

CLKout0, CLKout0*,

CLKout2, CLKout2*,

CLKout4, CLKout4*,

CLKout6, CLKout6*,

CLKout8, CLKout8*,

CLKout10, CLKout10*

Not Populated:

CLKout1, CLKout1*,

CLKout3, CLKout3*,

CLKout5, CLKout5*,

CLKout7, CLKout7*,

CLKout9, CLKout9*,

CLKout11, CLKout11*

Analog,

Output

Clock outputs with programmable output buffers.

The output terminations by default on the evaluation

board are shown below, and the output type selected by

default in CodeLoader is indicated by an asterisk (*):

Clock output pair

Default Board

Termination

CLKout0

LVPECL*

CLKout1

LVPECL

CLKout2

LVPECL*

CLKout3

LVPECL

CLKout4

LVDS* / LVCMOS

CLKout5

LVDS / LVCMOS

CLKout6

LVDS* / LVCMOS

CLKout7

LVDS / LVCMOS

CLKout8

LVDS* / LVCMOS

CLKout9

LVDS / LVCMOS

CLKout10

LVPECL*

CLKout11

LVPECL

Each CLKout pair has a programmable LVDS,

LVPECL, or LVCMOS buffer. The output buffer type

can be selected in CodeLoader in the Clock Outputs

tab via the CLKoutX_TYPE control.

All clock outputs are AC-coupled to allow safe testing

with RF test equipment.

All LVPECL clock outputs are source-terminated using

240-ohm resistors.

If an output pair is programmed to LVCMOS, each

output can be independently configured (normal,

inverted, or off/tri-state).

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Connector Name

Signal Type,

Input/Output

Description

Populated:

OSCout0, OSCout0*,

OSCout1, OSCout1*

Analog,

Output

Buffered outputs of OSCin port.

The output terminations on the evaluation board are

shown below, the output type selected by default in

CodeLoader is indicated by an asterisk (*):

OSC output pair

Default Board

Termination

OSCout0

LVDS* / LVCMOS

OSCout1

LVPECL* (fixed)

Only OSCout0 has a programmable LVDS, LVPECL,

or LVCMOS output buffer. The OSCout0 buffer type

can be selected in CodeLoader on the Clock Outputs

tab via the OSCout0_TYPE control. OSCout1 has

LVPECL buffer only but has programmable swing

amplitude.

Both OSCout pairs are AC-coupled to allow safe

testing with RF test equipment.

The OSCout1 output is source-terminated using 240-

ohm resistors.

If OSCout0 is programmed as LVCMOS, each output

can be independently configured (normal, inverted,

inverted, and off/tri-state).

Vcc Power,

Input

Main power supply input for the evaluation board.

A 3.9 V DC power source applied to this SMA will, by

default, source the onboard LDO regulators that power

the inner layer planes that supply the LMK048xxB and

its auxiliary circuits (e.g. VCXO).

The LMK048xxB contains internal voltage regulators

for the VCO, PLL and other internal blocks. The clock

outputs do not have an internal regulator, so a clean

power supply with sufficient output current capability

is required for optimal performance.

On-board LDO regulators and 0 Ω resistor options

provide flexibility to supply and route power to various

devices. See schematics for more details.

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Connector Name

Signal Type,

Input/Output

Description

Populated:

J1 Power,

Input

Alternative power supply input for the evaluation board

using two unshielded wires (Vcc and GND).

Apply power to either Vcc SMA or J1, but not both.

Populated:

VccVCO/Aux Power,

Input

Optional Vcc input to power the VCO circuit if

separated voltage rails are needed. The VccVCO/Aux

input can power these circuits directly or supply the on-

board LDO regulators. 0 Ω resistor options provide

flexibility to route power.

Populated:

VccVCXO/Aux Power,

Input

Optional Vcc input to power the VCXO circuit if

separated voltage rails are needed. The

VccVCXO/Aux input can power these circuits directly

or supply the on-board LDO regulators. 0 Ω resistor

options provide flexibility to route power.

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Connector Name

Signal Type,

Input/Output

Description

Populated:

CLKin0, CLKin0*,

FBCLKin*/CLKin1*

Not Populated:

FBCLKin/CLKin1

Analog,

Input

Reference Clock Inputs for PLL1 (CLKin0, 1).

CLKin1 can alternatively be used as an Ex tern al

Feedback Clock Input (FBCLKin) in 0-delay mode or

an RF Input (Fin) in External VCO mode.

Reference Clock Inputs for PLL1 (CLKin0, 1)

FBCLKin/CLKin1* is configured by default for a

single-ended reference clock input from a 50-ohm

source. The non-driven input pin (FBCLKin/CLKin1)

is connected to GND with a 0.1 uF. CLKin0/CLKin0*

is configured by default for a differential reference

clock input from a 50-ohm source.

CLKin1* is the default refer en ce cl ock input selected in

CodeLoader. The clock input selection mode can be

programmed on the Bits/Pins tab via the

CLKin_Select_MODE control. Refer to the

LMK04800 Family Datasheet section “Input Clock

Switching” for more information.

AC coupled Input Clock Swing Levels

Input

Mode

Min

Max

Units

Differential

Bipolar or

CMOS

0.5

3.1

Vpp

Single Ended

0.25

2.4

Vpp

External Feedback Input (FBCLKin) for 0-Delay

CLKin1 is shared for use with FBCLKin as an external

feedback clock input to PLL1 for 0-delay mode. See

section, Programming 0-Delay Mode in CodeLoader

below, for more details on using 0-delay mode with the

evaluation board and the evaluation board software.

RF Input (Fin) for External VCO

CLKin1 is also shared for use with Fin as an RF input

for external VCO mode using the onboard VCO

footprint (U3) or add-on VCO board. To enable Dual

PLL mode with External VCO, the following registers

must be properly configured in CodeLoader:

• MODE = (3) Dual PLL, Ext VCO (Fin), (5)

Dual PLL, Ext VCO, 0-Delay, (11) PLL2, Ext

VCO (Fin)

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Connector Name

Signal Type,

Input/Output

Description

Not populated:

OSCin, OSCin* Analog,

Input

Feedback VCXO clock input to PLL1 and Reference

clock input to PLL2.

By default, these SMAs are not connected to the traces

going to the OSCin/OSCin* pins of the LMK048xxB.

Instead, the single-ended output of the onboard VCXO

(U2) drives the OSCin* input of the device and the

OSCin input of the device is connected to GND with

0.1 uF.

A VCXO add-on board may be optionally attached via

these SMA connectors with minor modification to the

components going to the OSCin/OSCin* pins of

device. This is useful if the VCXO footprint does not

accommodate the desired VCXO device.

A single-ended or differential signal may be used to

drive the OSCin/OSCin* pins and must be AC coupled

If operated in single-ended mode, the unused input

must be connected to GND with 0.1 uF.

Refer to the LMK04800 Family Datasheet section

“Electrical Characteristics” for PLL2 Reference Input

(OSCin) specifications.

Test point:

VTUNE1_TP

Not populated:

Vtune1

Analog,

Output

Tuning voltage output from the loop filter for PLL1.

If a VCXO add-on board is used, this tuning voltage

can be connected to the voltage control pin of the

external VCXO when this SMA connector is installed

and connected through R72 by the user.

Test point:

VTUNE2_TP

Analog,

Output

Tuning voltage output from the loop filter for PLL2.

Populated:

uWire

Test points:

DATAuWire_TP

CLKuWIRE_TP

LEuWIRE_TP

CMOS,

Input/Output

10-pin header for uWire programming interface and

programmable logic I/O pins for the LMK048xxB.

The uWire interface includes CLKuWire,

DATAuWire, and LEuWire signals.

The programmable logic I/O signals accessible through

this header include: SYNC, Status_Holdover,

Status_LD, Status_CLKin0, and Status_CLKin1.

These logic I/O signals also have dedicated SMAs and

test points.

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Connector Name

Signal Type,

Input/Output

Description

Test point:

LD_TP

Not populated:

Status_LD

CMOS,

Output

Programmable status output pin. By default, set to

output the digital lock detect status signal for PLL1 and

PLL2 combined.

In the default CodeLoader modes, LED D5 will

illuminate green when PLL lock is detected by the

LMK048xxB (output is high) and turn off when lock is

lost (output is low).

The status output signal for the Status_LD pin can be

selected on the Bits/Pins tab via the LD_MUX control.

Refer to the LMK04800 Family Datasheet section

“Status Pins” and “Digital Lock Detect” for more

information.

Note: Before a high-frequency internal signal (e.g. PLL

divider output signal) is selected b y LD_MUX, it is

suggested to first remove the 270 ohm resistor to

prevent the LED from loading the output.

Test point:

Holdover_TP

Not populated:

Status_Hold

CMOS,

Output

Programmable status output pin. By default, set to the

output holdover mode status signal.

In the default CodeLoader mode, LED D8 will

illuminate red when holdover mode is active (output is

high) and turn off when holdover mode is not active

(output is low).

The status output signal for the Status_Holdover pin

can be selected on the Bits/Pins tab via the

HOLDOVER_MUX control.

Refer to the LMK04800 Family Datasheet section

“Status Pins” and “Holdover Mode” for more

information.

Note: Before a high-frequency internal signal (e.g. PLL

divider output signal) is selected by

HOLDOVER_MUX, it is suggested to first remove the

270 ohm resistor to prevent the LED from loading the

output.

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Connector Name

Signal Type,

Input/Output

Description

Test point:

CLKin0_SEL_TP

CLKin1_SEL_TP

Not populated:

Status_CLKin0,

Status_CLKin1

CMOS,

Input/Output

Programmable status I/O pins. By default, set as input

pins for controlling input clock switching of CLKin0

and CLKin1.

These inputs will not be functional because

CLKin_Select_MODE is set to 0 (CLKin0 Manual) by

default in the Bits/Pins tab in CodeLoader. To enable

input clock switching, CLKin_Select_MODE must be

3 or 6 and Status_CLKinX_TYPE must be 0 to 3 (pin

enabled as an input).

Input Clock Switching – Pin Select Mode

When CLKin_SELECT_MODE is 3, the

Status_CLKinX pins select which clock input is active

as follows:

Status_CLKin1

Status_CLKin0

Active Clock

CLKin0

CLKin1

Reserved

Holdover

Input Clock Switching – Auto with Pin Select

When CLKin_SELECT_MODE is 6, the active clock is

selected using the Status_CLKinX pins upon an input

clock switch event as follows:

Status_CLKin1 Status_CLKin0

Active

Clock

CLKin0

CLKin1

Reserved

Refer to the LMK04800 Family Datasheet section

“Input Clock Switching” for more information.

Status Outputs

When Status_CLKinX_TYPE is 3 to 6 (pin enabled as

an output), the status output signal for the

corresponding Status_CLKinX pin can be programmed

on the Bits/Pins tab via the Status_CLKinX_MUX

control.

Refer to the LMK04800 Family Datasheet section

“Status Pins” for more information.

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Connector Name

Signal Type,

Input/Output

Description

Test point:

SYNC_TP

Not populated:

SYNC

CMOS,

Input/Output

Programmable status I/O pin. By default, set as an

input pin for synchronize the clock outputs with a fixed

and known phase relationship between each clock

output selected for SYNC. A SYNC event also causes

the digital delay values to take effect.

In the default CodeLoader mode, SYNC will asserted

when the SYNC pin is low and the outputs to be

synchronized will be held in a logic low state. When

SYNC is unasserted, the clock outputs to be

synchronized are activated and will be initially phase

aligned with each other except for outputs programmed

with different digital delay values.

A SYNC event can also be programmed by toggling

the SYNC_POL_INV bit in the Bits/Pins tab in

CodeLoader.

Refer to the LMK04800 Family Datasheet section

“Clock Output Synchronization” for more information.

Status Output

When SYNC_MUX is 3 to 6 (pin enabled as output), a

status signal for the SYNC pin can be selected on the

Bits/Pins tab via the SYNC_MUX control.

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Recommended Test Equipment

Power Supply

The Power Supply should be a low noise power supply, particularly when the devices on the board are

being directly powered (onboard LDO regulators bypassed).

Phase Noise / Spectrum Analyzer

To measure phase noise and RMS jitter, an Agilent E5052 Signal Source Analyzer is recommended. An

Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the

architecture of the E5052 is superior for phase noise measurements. At frequencies less than 100 MHz

the local oscillator noise of the E4445A is too high and measurements will reflect the E4445A’s internal

local oscillator performance, not the device under test.

Oscilloscope

To measure the output clocks for AC performance, such as rise time or fall time, propagation delay, or

skew, it is suggested to use a real-time oscilloscope with at least 1 GHz analog input bandwidth (2.5+

GHz recommended) with 50 ohm inputs and 10+ Gsps sample rate. To evaluate clock synchronization or

phase alignment between multiple clock outputs, it’s recommended to use phase-matched, 50-ohm cables

to minimize external sources of skew or other errors/distortion that may be introduced if using

oscilloscope probes.

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Programming 0-Delay Mode in CodeLoader

Overview

When enabling the 0-Delay mode the feedback path of the VCO is altered to include a clock output. See

the datasheet for more details on 0-Delay functionality.

The current version of the CodeLoader software does not include this extra divider in the frequency

calculations when in holdover mode. To successfully lock the LMK04800 device in a 0-Delay mode the

user must program the device “manually” account for this divider. Programming “manually” means th at

the VCO frequency and therefore the clock output frequencies displayed by the CodeLoader software may

be incorrect. For the LMK04800 device to lock properly the divider values must be programmed

correctly. The frequencies displayed in the application are only for the benefit of the user and for proper

automatic programming of the OSCin_FREQ register which will not be affected by 0-Delay.

When using the device in Dual Loop mode vs. Single Loop mode different procedures are used to cause

the device to lock when using the CodeLoader software. The following two sections describe the process

for when the LMK04800 device is programmed for a Dual Loop mode and Single Loop mode

respectively. Each section contains a brief introduction, the programming steps to execute to make the

device lock, and finally a detailed section discussing the workaround and some example cases.

Dual Loop 0-Delay Mode Examples

In Dual Loop 0-Delay Modes, MODE = 2 or MODE = 5, the feedback from the VCXO of PLL1 to the

PLL1 N divider is broken and a clock output will drive the PLL1 N divider. This permits phase

alignment between the clock output and the clock input (0-Delay). As such, the PLL1_N and PLL1_R

divide values may need to be adjusted to permit the LMK04800 to lock.

Programming Steps

1. Program a Dual Loop 0-Delay mode.

2. Enable the feedback mux. EN_FEEDBACK_MUX = 1.

3. Select clock output for feedback with the feedback mux. FEEDBACK_MUX = User value.

4. Program the VCXO (VCO) frequency of PLL1 tab to the clock output frequency selected by the

feedback mux.

If for any reason the CLKout frequency is less than the phase detector frequency, the PLL1 R divider

must be increased so that the phase detector is at the same or lower value than the CLKout frequency.

Details

When using the CodeLoader software in Dual Loop 0-Delay mode, programming the VCXO (VCO)

frequency of the PLL1 tab to the frequency of the fed back output clock will re-program the PLL1 N

divider to allow the LMK04800 will be able to lock. The PLL1 loop has been altered and actual VCXO

no longer directly feeds into PLL1 N divider. The VCXO is only used by the reference input of PLL2

now. The PLL2 reference frequency will remain at the VCXO frequency.

When the PLL1 VCXO frequency is different from the PLL2 reference frequency, a warning will be

displayed on the clock outputs tab informing the user that PLL1 VCO and PLL2 reference frequency are

mismatched and the one or more of the PLLs are out of lock. While there still could be an error in the

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divider values which may cause a non-locked PLL, this warning by itself may no longer be assumed true.

It is up to the user to ensure the PLL dividers are programmed correctly.

To illustrate the proper programming of the LMK04800 device in dual loop 0-delay mode the following

case examples are provided. Note that in one of the cases, the feedback frequency from the clock output

matches the VCXO frequency and CodeLoader will display the proper frequency values.

Dual Loo p 0-Delay (MODE=2 or 5) Case 1: For example the default configuration, 122.88 MHz CLKin,

122.88 MHz VCXO, of the LMK04808 has the following register programming.

Case 1:

Default Mode

No 0-Delay

Case2:

Default 0-Delay

Mode

(CLKout8 =

122.88 MHz)

Case 3:

Default 0-Delay

Mode (Updated

CLKout8 =

245.76 MHz)

Case 4:

Default 0-Delay

Mode (Updated

CLKout8 =

61.44 MHz)

Actual PLL1

VCXO Frequency

122.88 122.88 122.88 122.88

Reported PLL1

VCXO Frequency

122.88 122.88 61.44 245.76

PLL1 N

120

240

Actual PLL2

VCO Frequency

2949.12 MHz 2949.12 MHz 2949.12 MHz 2949.12 MHz

Reported PLL2

VCO Frequency

2949.12 MHz 2949.12 MHz 2949.12 MHz 2949.12 MHz

PLL2_N

PLL2_P (Pre-N)

PLL2 VCO Divider

Bypassed

CLKout8 Divide

Actual CLKout8

Output Frequency

245.76 MHz 122.88 MHz 245.76 MHz 61.44 MHz

Reported CLKotu8

Output Frequency

245.76 MHz 122.88 MHz 245.76 MHz 61.44 MHz

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Single Loop 0-Delay Mode Examp les

In Single Loop 0-Delay Mode, MODE = 8, the feedback from the VCO of PLL2 to the PLL2_P/PLL2 N

divider is broken and a fed back clock output will drive the PLL2 N divider directly. This permits phase

alignment between the clock output and the OSCin input (0-Delay). As such, the PLL2_N, PLL2_R, and

PLL2_N_CAL divide values may need to be adjusted to permit the LMK04800 to lock.

Programming Steps

1. Program the Single Loop 0-Delay mode.

2. Enable the feedback mux. EN_FEEDBACK_MUX = 1.

3. Select clock output for feedback with the feedback mux. FEEDBACK_MUX = User value.

4. Program the VCO frequency of PLL2 tab to: The actual VCO frequency * PLL2_P (which is

PLL2 PreN) / CLKout Divider.

• Entered CodeLoader 4 VCO Frequency = Actual VCO Frequency * PLL2_P / CLKout

Divider.

5. Updated the PLL2_N_CAL register on the Bits/Pins tab to the N value when in non-0-Dela y mode.

6. Press Ctrl-L to cause all registers to be programmed.

• The reason is to cause the programming of register R30 to start the VCO calibration

routine now that the proper PLL2_N_CAL value is programmed.

• PLL2_N_CAL value is automatically updated when a new VCO frequency is entered and

the PLL2_N value is calculated. In this case the VCO frequency entered is wrong and the

PLL2_N_CAL value will be incorrect.

If for any reason the CLKout frequency is less than the phase detector frequency, the PLL2 R divider

must be increased so that the phase detector is at the same or lower value than the CLKout frequency.

Details

The 0-Delay mode for Single Loop mode is more complicated to program than for Dual Loop mode in

part because of the PLL2_N_CAL register. When performing the VCO calibration the device uses

PLL2_N_CAL for in non-0-Delay mode. Once the VCO is calibrated the device enters 0-Delay mode.

For more information on the PLL programming equations, refer to PLL PROGRAMMING in the

applications section of the datasheet.

In Table 7 case 1 illustrates the register programming when note using 0-Delay.

Case 2 shows 0-Delay with a clock out divider of 2. Since PLL2_P = 2, this substitution of which circuit

is performing the divide by two results in no impact o the software. All the values display correctly.

Case 3 shows 0-Delay mode with a CLKout divider not equal to the PLL2_P value. So the proper

frequency to program in the VCO to lock the VCO to 2949.12 MHz will be 491.52 MHz. This is

calculated by Actual VCO Frequency * PLL2_P / CLKoutX_Y_DIV.

Case 4 shows 0-Delay mode with CLKout divider not equal to the PLL2_P value; however the CLKout

frequency will be less than the current phase detector frequency. This requires PLL2_R to be increased

from a value of 1 to 2 to reduce the PLL2 phase detector frequency from 122.88 MHz to 61.44 MHz.

Now the adjusted VCO frequency can be programmed to allow PLL2 to lock.

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In any case where the actual VCO frequency and the display VCO frequency are not equal the user is

required to manually update the PLL2_N_CAL register with the PLL2_N value to be used as if the device

were operating in the non-0-Delay mode. Once this update has been performed, Ctrl-L will reload the

part and cause the VCO calibration to occur with the proper PLL2_N_CAL value.

Table 7 - Sing l e PLL 0-Delay Ope r ation Examples

Case 1:

Default Mode

No 0-Delay

Case 2:

Default 0-Delay

Mode

(CLKout8 =

1474.56 MHz)

Case 3:

Default 0-Delay

Mode (Updated

CLKout8 =

245.76 MHz)

Case 4:

Default 0-Delay

Mode (Updated

CLKout8 =

61.44 MHz)

Actual PLL2

VCO Frequency

2949.12 MHz 2949.12 MHz 2949.12 MHz 2949.12 MHz

Reported PLL2

VCO Frequency

2949.12 MHz 2949.12 MHz 491.52 MHz 122.88 MHz

PLL2_R

PLL2_N

PLL2_N_CAL

PLL2_P (Pre-N)

PLL2 VCO Divider

Bypassed

CLKout8 Divide

Actual CLKout8

Output Frequency

245.76 1474.56 MHz 245.76 MHz 61.44 MHz

Reported CLKout8

Output Frequency

245.76 1474.56 MHz 40.96 MHz 2.56 MHz

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Appendix A: CodeLoader Usage

Code Loader is used to program the evaluation board with LPT or USB2ANY-uWire interface

available from www.ti.com.

Port Setup Tab

Figure 8: Port Setup tab

On the Port Setup tab, the user may select the type of communication port (LPT or USB) that

will be used to program the device on the evaluation board.

The Pin Configuration field is hardware dependent and normally does not need to be changed by

the user. Figure 8 shows the default settings.

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Clock Outputs Tab

Figure 9: Clo c k Outputs tab

The Clock Outputs tab allows the user to control the output channel blocks, including:

• Clock Group Source from either VCO or OSCin (via OSC Mux1 and OSC Mux2)

• Channel Powerdown (affects digital and analog delay, clock divider, and buffer blocks)

• Digital Delay value and Half Step

• Clock Divide value

• Analog Delay value and Delay bypass/enable (per output)

• Clock Output format (per output)

This tab also allows the user to select the VCO Divider value (2 to 8). Note that the total PLL2

N divider value is the product of the VCO Divider value and the PLL N Prescaler and N Counter

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values (shown in the PLL2 tab), and is given by:

PLL2 N Total = VCO Divider * PLL2 N Prescaler * PLL2 N Counter

Clicking on the cyan-colored PLL2 block that contains R, PDF and N values will bring the

PLL2 tab into focus where these values may be modified, if needed.

Clicking on the values in the box containing the Internal Loop Filter component (R3, C3, R4,

C4) allow one to step through the possible values. Left click to increase the component value,

and right click to decrease the value. These values can also be changed in the Bits/Pins tab.

The Reference Oscillator value field may be changed in either the Clock Outputs tab or the

PLL2 tab. The PLL2 Reference frequency should match the frequency of the onboard VCXO or

Crystal (i.e. VCO frequency in the PLL1 tab); if not, a warning message will appear to indicate

that the PLL(s) may be out of lock, as highlighted by the red box in Figure 10.

Figure 10: Warning message indicating mismatch between

PLL1 VC O frequency (30.72MHz) and PLL2 reference frequency (122.88 MHz)

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PLL1 Tab

Figure 11: PLL1 tab

The PLL1 tab allows the user to change the following parameters in Table 8.

Table 8: Registers Controls and Descrip tion s i n PLL1 tab

Control Name

Description

Reference Oscillator

Frequency (MHz)

n/a

CLKin frequency of the selected reference

clock.

Phase Detector Frequency

(MHz)

n/a

PLL1 Phase Detector Frequency (PDF).

This value is calculated as:

PLL1 PDF = CLKin Frequency / (PLL1_R *

CLKinX_PreR_DIV), where

CLKinX_PreR_DIV is the predivider value

of the selected input clock.

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VCO Frequency (MHz)

n/a

The VCO Frequency should be the OSCin

frequency, except when operating in Dual

PLL with 0-delay feedback. This value is

calculat ed as :

VCO Freq (OSCin freq) = PLL1 PDF *

PLL1_N.

In Dual PLL mode with 0-delay feedback,

the VCO frequency should be set to the

feedback clock input frequency. See the

section Setting the PLL1 VCO Frequency

and PLL2 Reference Frequency for details.

R Counter

PLL1_R

PLL1 R Counter value (1 to 16383).

N Counter

PLL1_N

PLL1 N Counter value (1 to 16383).

Phase Detector Polarity

PLL1_CP_POL

PLL1 Phase Detector Polarity.

Click on the polarity sign to toggle polarity

“+” or “–”.

Charge Pump Gain

PLL1_CP_GAIN

PLL1 Charge Pump Gain.

Left-click/right-click to increase/decrease

charge pump gain (100, 200, 400, 1600 uA).

Charge Pump State

PLL1_CP_TRI

PLL1 Charge Pump State.

Click to toggle between Active and Tri-State.

Setting the PLL1 VCO Frequency and PLL2 Reference Frequency

When operating in Dual PLL mode without 0-delay feedback, the VCO frequency value on the

PLL1 tab must match the Reference Oscillator (OSCin) frequency value on the PLL2 tab;

otherwise, the one or both PLLs may be out of lock. Updating the Reference Oscillator

frequency on the PLL2 tab will automatically update the value of OSCin_FREQ on the

Bits/Pins tab.

However, when operating in Dual PLL mode with 0-delay feedback, it may be valid for the VCO

frequency value on the PLL1 tab to be different from the Reference Oscillator (OSCin)

frequency value on the PLL2 tab. This is because in 0-delay mode, the PLL1 feedback clock is

taken from an output clock instead of the OSCin clock. For example, if the CLKin frequency (to

PLL1_R) is 30.72 MHz, the 0-delay feedback clock frequency (to PLL1_N) is 30.72 MHz, and

the VCXO frequency is 122.88 MHz, then the VCO frequency value on the PLL1 tab should be

30.72 MHz (0-delay feedback frequency) and the Reference Oscillator frequency value on the

PLL2 tab should be 122.88 MHz (VCXO frequency). Because of the mismatched frequencies, a

warning message will indicate this condition on the Clock Outputs tab but may be disregarded

in a case like this.

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PLL2 Tab

Figure 12: PLL2 tab

The PLL2 tab allows the user to change the following parameters in Table 9.

Table 9: Registers Controls and Descriptions in PLL2 tab

Control Name

Description

Reference Oscillator

Frequency (MHz)

OSCin_FREQ

OSCin frequency from the External VCXO

or Crystal.

Phase Detector Frequency

(MHz)

n/s

PLL2 Phase Detector Frequency (PDF).

This value is calculated as:

PLL2 PDF = OSCin Frequency

*(2

EN_PLL2_REF_2X

) / PLL2_R.

VCO Frequency (MHz)

n/a

Internal VCO Frequency should be within

the allowable range of the LMK048xxB

device.

This value is calcul ated a s:

VCO Frequency = PLL2 PDF * (PLL2_N *

PLL2_P * VCO divider value).

Doubler

EN_PLL2_REF_2X

PLL2 Doubler.

0 = Bypass Doubler

1 = Enable Doubler

R Counter

PLL2_R

PLL2 R Counter value (1 to 4095).

N Counter

PLL2_N

PLL2 N Counter value (1 to 262143).

PLLN Prescaler

PLL2_P

PLL2 N Prescaler value (2 to 8).

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Phase Detector Polarity

PLL2_CP_POL

PLL2 Phase Detector Polarity.

Click on the polarity sign to toggle polarity

“+” or “–”.

Charge Pump Gain

PLL2_CP_GAIN

PLL2 Charge Pump Gain.

Left-click/right-click to increase/decrease

charge pump gain (100, 400, 1600, 3200

uA).

Charge Pump State

PLL2_CP_TRI

PLL2 Charge Pump State.

Click to toggle between Active and Tri-State.

Changes made on this tab will be reflected in the Clock Outputs tab. The VCO Frequency

should conform to the specified internal VCO frequency range for the LMK048xxB device (per

Table 2).

Bits/Pins Tab

Figure 13: Bits/Pins tab

The Bits/Pins tab allows the user to program bits directly, many of which are not available on

other tabs. Brief descriptions for the controls on this tab are provided in Table 10 to supplement

the datasheet. Refer to the LMK04800 Family Datasheet for more information.

TIP: Right-clicking any register name in the Bits/Pins tab will display a Help prompt with the

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Table 10: Register Controls and Descript ions on Bits/Pins tab

Group

Description

Mode Control

RESET

Resets the device to default register values. RESET

must be cleared for normal operation to prevent an

unintended reset every time R0 is programmed.

POWERDOWN

Places the device in powerdown mode.

MODE

Selects the operating mode (topology) for the

LMK048xx device.

PD_OSCin

Powers down the OSCin buffer. For use in Clock

Distribution mode if OSCin path is not used.

FEEDBACK_MUX

Selects the feedback source for 0-delay mode.

OSCin_FREQ

Must be set to the OSCin frequency range for

PLL2. Used for proper operation of the internal

VCO calibration routine.

Entering a reference oscillator frequency on PLL2

tab will automatically update OSCin_FREQ to the

proper frequency range.

VCO_MUX

Selects between VCO and VCO divider to drive the

clock distribution path. The VCO divider is only

valid if MODE is selecting the Internal VCO.

uWire_LOCK

When checked, no other uWire programming will

have effect. Must be unchecked to enable uWire

programming of registers R0 to R30.

CLKin

CLKin_Select_MODE

Selects operational mode for how the device selects

the reference clock for PLL1.

EN_CLKin1

Enables CLKin1 as a usable reference input during

auto switching mode.

EN_CLKin0

Enables CLKin0 as a usable reference input during

auto switching mode.

CLKinX_BUF_TYPE

Selects the CLKinX input buffer to Bipolar

(internal 0 mV offset) or MOS (internal 55 mV

offset).

EN_LOS

Enable the Loss-Of-Signal (LOS) detect circuitry.

LOS_TIMEOUT

Sets the timeout value for the LOS det ect ci rcui t ry

to assert a loss of signal state on a clock input.

Crystal

EN_PLL2_XTAL

Enables Crystal Oscillator

XTAL_LVL

Sets peak amplitude on the tunable crystal. Values

listed are for a 20.48 MHz crystal.

Control

LD_MUX

Sets the selected signal on the Status_LD pin.

LD_TYPE

Sets I/O pin type on the Status_LD pin.

HOLDOVER_MUX

Sets the selected signal on the Status_HOLDOVER

pin.

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HOLDOVER_TYPE

Sets I/O pin type on the Status_Holdover pin.

Status_CLKin0 _MUX

Sets the selected signal on the Status_CLKin0 pin.

Status_CLKin0_TYPE

Sets I/O pin type on the Status_CLKin0 pin.

Status_CLKin1_MUX

Sets the selected signal on the Status_CLKin1 pin.

Status_CLKin1_TYPE

Sets I/O pin type on the Status_CLKin1 pin.

CLKin_Sel_INV

Inverts the Status_CLKin0/1 pin polarity when set

to an input type. Significant when

CLKin_SELECT_MODE is 3 or 6.

IO Control – Sync

SYNC_MUX

Sets the selected signal on the SYNC pin.

SYNC_TYPE

Sets I/O pin type on the SYNC pin.

SYNC_POL_INV

Sets polarity on SYNC input to active low when

checked. Toggling this bit will initiate a SYNC

event.

SYNC_PLL1_DLD

Engage SYNC mode until PLL1 DLD is true

SYNC_PLL2_DLD

Engage SYNC mode until PLL2 DLD is true

NO_SYNC_CLKoutX_Y

Synchronization will not affect selected clock

outputs, where X = even-numbered output and Y =

odd-numbered output.

SYNC_QUAL

Sets the SYNC to qualify mode for dynamic digital

delay.

EN_SYNC

Must be set when using SYNC, but may be cleared

after the SYNC event. When using dynamic digital

delay (SYNC_QUAL = 1), EN_SYNC must always

be set.

Changing this value from 0 to 1 can cause a SYNC

event, so clocks which should not be SYNCed

when setting this bit should have the

NO_SYNC_CLKoutX_Y bit set.

NOTE: This bit is not a valid method of generating

a SYNC event. Use one of the other SYNC

generation methods to ensure a proper SYNC

occurs.

SYNC_EN_AUTO

Enable auto SYNC when R0 to R5 is written.

DAC/Holdover

HOLDOVER_MODE

Sets holdover mode to be disabled or enabled.

FORCE_HOLDOVER

Engages holdover when checked regardless of

HOLDOVER_MODE value. Turns the DAC on.

EN_TRACK

Enables DAC tracking. DAC tracks the PLL1

Vtune to provide for an accurate HOLDOVER

mode. DAC_CLK_DIV should also be set so that

DAC update rate is <= 100 kHz.

EN_VTUNE_RAIL_DET

Allows rail-to-rail operation of VCXO with default

of 0. Allows use of DAC_LOW_TRIP,

DAC_HIGH_TRIP. Must be used with

EN_MAC_DAC = 1. CLKin_SELECT_MODE

must be 4 or 6 (auto mode) to use.

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HOLD_DLD_CNT

In HOLDOVER mode, wait for this many clocks of

PLL1 PDF within the tolerances of PLL1_WND

_SIZE before exiting holdover mode.

DAC_CLK_DIV

DAC update clock is the PLL1 phase detector

divided by this divisor. For proper operation, DAC

update clock rate should be <= 100 kHz.

DAC update rate = PLL1 phase detector frequency /

DAC_CLK_DIV

EN_MAN_DAC

Enables manual DAC mode and set DAC voltage

when in holdover.

MAN_DAC

Sets the value for the DAC when EN_MAN_DAC

is 1 and holdover is engaged. Readback from this

manual DAC mode or DAC tracking mode

DAC_LOW_TRIP

Value from GND in ~50mV steps at which a clock

switch event is generated. If Holdover mode is

enabled, it will be engaged upon the clock switch

event.

NOTE: EN_VTUNE_RAIL_DET must be enabled

for this to be valid.

DAC_HIGH_TRIP

Value from VCC (3.3V) in ~50mV steps at which

clock switch event is generated. If Holdover mode

is enabled, it will be engaged upon the clock switch

event.

NOTE: EN_VTUNE_RAIL_DET must be enabled

for this to be valid.

PLL1

PLL1_WND_SIZE

If the phase error between the PLL1 reference and

feedback clocks is less than specified time, then the

PLL1 lock counter increments.

NOTE: Final lock detect valid signal is determined

when the PLL1 lock counter meets or exceeds the

PLL1_DLD_CNT value.

PLL1_DLD_CNT

The reference and feedback of PLL1 must be within

the window of phase error as specified by

PLL1_WND_SIZE for this many cycles before

PLL1 digital lock detect is asserted.

CLKinX_PreR_DIV

The PreR dividers divide the CLKinX reference

before the PLL1_R divider.

Unique divides on individual CLKinX signals

allows switchover from one clock input to another

clock input without needing to reprogram the

PLL1_R divider to keep the device in lock.

Revised - August 2014 LMK04800 Family SNAU076B 37

www.ti.com

PLL1_N_DLY

N delay causes clock outputs to lead clock input

when in a 0-delay mode. Increasing the N delay

value increases the output phase lead relative to the

input.

PLL1_R_DLY

R delay causes clock outputs to lag clock input

when in a 0-delay mode. Increasing the R delay

value increases the output phase lag relative to the

input.

PLL2

PLL2_WND_SIZE

If the phase error between the PLL2 reference and

feedback clock is less than specified time, then the

PLL2 lock counter increments.

PLL2_DLD_CNT

The reference and feedback of PLL2 must be within

the window of phase error as specified by

PLL2_WND_SIZE for this many cycles before

PLL2 digital lock detect is asserted.

EN_PLL2_REF_2X

Enables the doubler block to doubles the reference

frequency into the PLL2 R counter. This can allow

for frequency of 2/3, 2/5, etc. of OSCin to be used

at the phase detector of PLL2.

PLL2_N_CAL

The PLL2_N_CAL register contains the N value

used for the VCO calibration routine. Except

during 0-delay modes, the PLL2_N and

PLL2_N_CAL registers will be exactly the same.

PLL2_R3_LF

Set the corresponding integrated PLL2 loop filter

values: R3, R4, C3, and C4.

It is also possible to set these values by clicking on

the loop filter values on the Clock Outputs tab.

PLL2_R4_LF

PLL2_C3_LF

PLL2_C4_LF

PLL2_FAST_PDF

Enable this bit when using a PLL2 phase detector

frequency > 100 MHz.

Program Pins

SYNC

Sets these pins on the uWire header to logic high

(checked) or logic low (unchecked).

Status_CLKin0

Status_CLKin1

38 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

Registers Tab

Figure 14: Registers Tab

The Registers tab shows the value of each register. This is convenient for programming the

device to the desired settings, then exporting to a text file the register values in hexadecimal for

use in your own application.

By clicking in the “bit field” it is possible to manually change the value of registers by typing ‘1’

and ‘0.’

Revised - August 2014 LMK04800 Family SNAU076B 39

www.ti.com

Appendix B: Typical Phase Noise Performance Plots

PLL1

The LMK048xxB’s dual PLL architecture achieves ultra low jitter and phase noise by allowing

the external VCXO or Crystal’s phase noise to dominate the final output phase noise at low

offset frequencies and the internal VCO’s phase noise to dominate the final output phase noise at

high offset frequencies. This results in the best overall noise and jitter performance.

Table 11 lists the test conditions used for output clock phase noise measurements with the

Crystek 122.88 MHz VCXO.

Table 11: LMK048xxB Test Co ndi tions

Parameter

Value

PLL1 Reference clock input

CLKin0 single-ended input, CLKin0* AC-coupled to GND

PLL1 Reference Clock frequency

122.88 MHz

PLL1 Phase detector frequency

122.88 MHz

PLL1 Charge Pump Gain

100 uA

VCXO frequency

122.88 MHz

PLL2 phase detector frequency

122.88 MHz

PLL2 Charge Pump Gain

3200 uA

PLL2 REF2X mode

Disabled

122.88 MHz VCXO Phase Noise

The phase noise of the reference is masked by the phase noise of this VCXO by using a narrow

loop bandwidth for PLL1 while retaining the frequency accuracy of the reference clock input.

This VCXO sets the reference noise to PLL2. Figure 15 shows the open loop typical phase noise

performance of the CVHD-950-122.88 Crystek VCXO.

40 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

Figure 15: Crystek CVHD-950-122.88 M Hz VCXO Phase Noise at 122.88 MHz

Table 12: VCXO Phase Noise

at 122.88 MHz (dBc/Hz)

Offset

Phase

Noise

10 Hz

-76.6

100 Hz

-108.9

1 kHz

-137.4

10 kHz

-153.3

100 kHz

-162.0

1 MHz

-165.7

10 MHz

-168.1

40 MHz

-168.1

Table 13: VCXO RMS Jitter

to high offset of 20 MHz

at 122.88 MHz (rm s fs)

Low

Offset

Jitter

10 Hz

515.4

100 Hz

60.5

1 kHz

36.2

10 kHz

35.0

100 kHz

34.5

1 MHz

32.9

10 MHz

22.7

Clock Output Measurement Technique

The same technique was used to measure phase noise for all three output types available on the

programmable OSCout and CLKout buffers. This was achieved by terminating one side of the

LVPECL, LVDS, or LVCMOS output with a 50-ohm load, and measuring the other side single-

ended using an Agilent E5052B Source Signal Analyzer.

Buffered OSCout Phase Noise

Both OSCout0 and OSCout1 frequencies are 122.88 MHz since the OSCout Divider is bypassed.

OSCout0 is programmed to LVCMOS mode and OSCout1 is fixed as LVPECL.

V CX O P hase Noise

-170

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

10 100 1000 10000 100000 1000000 10000000 1E+08

Offset (Hz)

Phase Noise ( dBc/Hz)

CVHD-950-122.88

Revised - August 2014 LMK04800 Family SNAU076B 41

www.ti.com

Clock Outputs (CLKout)

The LM K04800 Family features programmable LVDS, LVPECL, and LVCMOS buffer modes

for the CLKoutX and OSCout0 output pairs. The OSCout1 output pair has a LVPECL buffer.

Included below are various phase noise measurements for each output format.

LMK04808B CLKout Phase Noise

Figure 16: LMK04808B CLKout Phase Noise

Table 14: LM K04808B Phase Noise (dBc/Hz) Phase Noise and R MS Jitte r (fs)

Offset

1474.56 MHz

LVDS

1474.56 MHz

LVPECL

491.52 MHz

LVDS

491.52 MHz

LVPECL

100 Hz

-88.2

-87.8

-97.7

-99.7

1 kHz

-109.8

-108.9

-118.9

-119.3

10 kHz

-118.0

-117.4

-127.3

-127.4

100 kHz

-119.8

-119.7

-129.1

-129.4

800 kHz

-130.9

-130.8

-140.1

-140.3

1 MHz

-132.7

-132.6

-141.7

-142.1

10 MHz

-148.2

-149.2

-152.7

-154.9

20 MHz

-148.9

-150.1

-153.2

-155.3

RMS Jitter (fs)

10 kHz to 20 MHz

99.3 99.4 109.1 103.3

RMS Jitter (fs)

100 Hz to 20 MHz

111.4 113.5 121.3 116.1

Phase Noise (dBc/Hz)

Frequency Offset (Hz)

1474.56 MHz LVDS

1474.56 MHz LVPECL16

491.52 MHz LVDS

491.52 MHz LVPECL16

245.76 MHz LVDS

245.76 MHz LVCMOS

245.76 MHz LVPECL16

122.88 MHz LVDS

122.88 MHz LVCMOS

122.88 MHz LVPECL16

42 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

For the LMK04808B, the internal VCO frequency is 2949.12 MHz. The divide-by-12 CLKout

frequency is 245.76 MHz, and the divide-by-24 CLKout frequency is 122.88 MHz.

Table 15: LMK04808B Pha se Noise and RMS Jitter for Different CLKout Output For mats and Frequencies

Offset

245.76

LVDS

245.76

LVCMOS

245.76

LVPECL

122.88

LVDS

122.88

LVCMOS

122.88

LVPECL

100 Hz

-103.7

-104.4

-106.1

-108.4

-110.4

-108.5

1 kHz

-123.7

-125.9

-125.7

-128.7

-129.7

-130.9

10 kHz

-133.8

-133.5

-134.0

-139.3

-139.8

-140.0

100 kHz

-135.5

-135.4

-135.8

-141.7

-141.4

-141.8

800 kHz

-146.4

-146.3

-146.7

-151.7

-152.1

-152.4

1 MHz

-147.9

-148.0

-148.3

-152.9

-153.4

-153.8

10 MHz

-156.5

-157.5

-158.3

-158.7

-160.5

-161.0

20 MHz

-156.9

-157.8

-158.6

-158.8

-160.7

-161.3

RMS Jitter (fs)

10 kHz to 20 MHz

111.8 109.6 103.9 133.4 122.1 116.1

RMS Jitter (fs)

100 Hz to 20 MHz

124.3 122.1 115.4 144.4 132.3 127.9

Revised - August 2014 LMK04800 Family SNAU076B 43

www.ti.com

LMK04808B OSCout Phase Noise

Figure 17: LMK04808B OSCout Phase Noise

Table 16: LM K04808B OSCout Phase Noise and RMS Jitter (fs)

Offset

OSCout0

LVPECL

OSCout1

LVPECL

OSCin thru

CLKout

100 Hz

-110.2

-111.1

-109.4

1 kHz

-137.2

-136.1

-138.6

10 kHz

-148.0

-146.7

100 kHz

-157.8

-156.0

-155.3

800 kHz

-159.1

-159.4

-156.4

1 MHz

-157.0

-157.5

-156.3

10 MHz

-158.8

-159.2

-156.7

20 MHz

-159.2

-159.5

-156.7

RMS Jitter (fs)

10 kHz to 20 MHz

94.1 91.0 123.7

RMS Jitter (fs)

100 Hz to 20 MHz

103.2 99.6 131.3

Title

122.88 MHz LVCMOS

OSCin through CLKout

122.88 MHz OSCout0

LVPECL16

122.88 MHz OSCout1

LVPECL16

44 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

LMK04806B CLKout Phase Noise

Figure 18: LMK04806B CLKout Phase Noise

Table 17: LMK04806B Phase Noise (dBc/Hz) Phase Noise and R MS Jitte r (fs)

Offset

1228.80 MHz

LVDS

1228.80 MHz

LVPECL

491.52 MHz

LVDS

491.52 MHz

LVPECL

100 Hz

-91.2

-90.5

-97.5

-98.2

1 kHz

-111.2

-110.8

-118.7

-119.4

10 kHz

-121.0

-121.1

-128.5

-128.6

100 kHz

-121.3

-121.2

-129.5

800 kHz

-133.8

-133.7

-141.9

1 MHz

-135.8

-135.7

-143.4

-143.8

10 MHz

-150.2

-150.4

-153.1

-155.7

20 MHz

-150.8

-151.0

-153.8

-155.7

RMS Jitter (fs)

10 kHz to 20 MHz

92.9 93.4 97.5 94.5

RMS Jitter (fs)

100 Hz to 20 MHz

104.0 105.3 109.0 105.4

For the LMK04806B, the internal VCO frequency is 2457.60 MHz. The divide-by-10 CLKout

frequency is 245.76 MHz, and the divide-by-20 CLKout frequency is 122.88 MHz.

Phase Noise (dBc/Hz)

Frequency Offset (Hz)

1228.8 MHz LVDS

1228.8 MHz LVPECL16

491.52 MHz LVDS

491.52 MHz LVPECL16

245.76 MHz LVDS

245.76 MHz LVCMOS

245.76 MHz LVPECL16

122.88 MHz LVDS

122.88 MHz LVCMOS

122.88 MHz LVPECL16

Revised - August 2014 LMK04800 Family SNAU076B 45

www.ti.com

Table 18: LMK04806B Pha se Noise and RMS Jitter for Different CLKout Output For mats and Frequencies

Offset

245.76

LVDS

245.76

LVCMOS

245.76

LVPECL

122.88

LVDS

122.88

LVCMOS

122.88

LVPECL

100 Hz

-105.8

-104.5

-106.5

-108.6

-113.0

-111.4

1 kHz

-124.7

-124.9

-125.4

-130.2

-132.1

-131.0

10 kHz

-134.8

-134.4

-134.9

-140.7

-141.0

100 kHz

-135.5

-135.4

-135.8

-141.7

-141.9

800 kHz

-147.8

-147.7

-148.0

-152.6

-153.5

-154.1

1 MHz

-149.6

-149.4

-149.7

-153.3

-155.2

-155.5

10 MHz

-156.1

-158.1

-158.4

-161.5

-161.1

20 MHz

-156.3

-158.2

-158.9

-159.5

-161.6

-161.3

RMS Jitter (fs)

10 kHz to 20 MHz

106.9 101.5 96.4 134.2 109.7 108.2

RMS Jitter (fs)

100 Hz to 20 MHz

116.8 112.4 106.4 143.2 118.9 117.9

46 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

LMK04806B OSCout Phase Noise

Figure 19: LM K048 06B OSCout Phase Noise

Table 19: LM K04806B OSCout Phase N oise and RMS Jitter (fs)

Offset

OSCout0

LVPECL

OSCout1

LVPECL

OSCin thru

CLKout

100 Hz

-110.3

-112.1

-110.0

1 kHz

-136.9

-137.9

-138.9

10 kHz

-151.1

-150.1

-150.0

100 kHz

-154.3

-156.8

-154.6

800 kHz

-158.9

-156.6

1 MHz

-159.2

-159.1

-156.6

10 MHz

-159.4

-160.0

-156.8

20 MHz

-157.6

-159.9

-156.9

RMS Jitter (fs)

10 kHz to 20 MHz

138.4 89.7 120.0

RMS Jitter (fs)

100 Hz to 20 MHz

143.7 97.3 126.2

Title

122.88 MHz LVCMOS

OSCin through CLKout

122.88 MHz OSCout0

LVPECL16

122.88 MHz OSCout1

LVPECL16

Revised - August 2014 LMK04800 Family SNAU076B 47

www.ti.com

LMK04803B CLKout Phase Noise

Figure 20: LMK04803B CLKout Phase Noise

Table 20: LM K04803B Phase Noise (dBc/Hz) Phase Noise and R MS Jitte r (fs)

Offset

983.04 MHz

LVDS

983.04 MHz

LVPECL

491.52 MHz

LVDS

491.52 MHz

LVPECL

100 Hz

-93.0

-95.0

-99.7

-99.5

1 kHz

-111.3

-113.1

-117.1

-118.3

10 kHz

-121.8

-121.1

-126.9

-127.4

100 kHz

-122.3

-121.9

-127.8

-128.3

800 kHz

-134.9

-134.5

-140.3

-140.8

1 MHz

-136.8

-136.3

-142.0

-142.7

10 MHz

-150.3

-150.6

-152.0

-154.2

20 MHz

-150.4

-151.1

-152.6

-154.6

RMS Jitter (fs)

10 kHz to 20 MHz

103.8 107.4 116.0 108.1

RMS Jitter (fs)

100 Hz to 20 MHz

116.1 116.2 127.4 116.8

For the LMK04803B, the internal VCO frequency is 1966.08 MHz. The divide-by-8 CLKout

frequency is 245.76 MHz, and the divide-by-16 CLKout frequency is 122.88 MHz.

Phase Noise (dBc/Hz)

Frequency Offset (Hz)

983.04 MHz LVDS

983.04 MHz LVPECL16

491.52 MHz LVDS

491.52 MHz LVPECL16

245.76 MHz LVDS

245.76 MHz LVCMOS

245.76 MHz LVPECL16

122.88 MHz LVDS

122.88 MHz LVCMOS

122.88 MHz LVPECL16

48 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

Table 21: LMK04803B Pha se Noise and RMS Jitter for Different CLKout Output For mats and Frequencies

Offset

245.76

LVDS

245.76

LVCMOS

245.76

LVPECL

122.88

LVDS

122.88

LVCMOS

122.88

LVPECL

100 Hz

-104.8

-104.2

-108.4

-112.1

-111.5

-112.7

1 kHz

-124.8

-123.5

-125.0

-130.5

-130.2

-130.6

10 kHz

-133.7

-134.0

-133.6

-140.1

-139.8

-140.1

100 kHz

-134.4

-134.6

-140.6

-140.4

-140.7

800 kHz

-146.7

-147.1

-152.5

-152.4

-152.7

1 MHz

-148.5

-148.7

-153.4

-154.0

10 MHz

-156.2

-157.2

-158.0

-158.4

-160.1

-160.5

20 MHz

-156.6

-157.5

-158.2

-158.7

-160.4

-161.1

RMS Jitter (fs)

10 kHz to 20 MHz

115.1 113.1 107.9 137.5 126.1 120.5

RMS Jitter (fs)

100 Hz to 20 MHz

126.4 124.2 116.7 147.5 136.4 128.9

Revised - August 2014 LMK04800 Family SNAU076B 49

www.ti.com

LMK04803B OSCout Phase Noise

Figure 21: LM K048 03B OSCout Phase Noise

Table 22: LM K04803B OSCout Phase Noise and RMS Jitter (fs)

Offset

OSCout0

LVPECL

OSCout1

LVPECL

OSCin thru

CLKout

100 Hz

-114.0

-113.1

-113.3

1 kHz

-136.6

-137.2

-138.4

10 kHz

-147.6

-146.6

-148.5

100 kHz

-156.3

-156.2

-154.0

800 kHz

-159.4

-159.2

-156.6

1 MHz

-159.0

-159.3

-156.7

10 MHz

-157.2

-158.7

-156.9

20 MHz

-158.1

-159.4

-157.0

RMS Jitter (fs)

10 kHz to 20 MHz

107.1 92.4 119.1

RMS Jitter (fs)

100 Hz to 20 MHz

111.6 98.1 123.3

Phase Noise (dBc/Hz)

Frequency Offset (Hz)

122.88 MHz LVCMOS

OSCin through CLKout

122.88 MHz OSCout0

LVPECL16

122.88 MHz OSCout1

LVPECL16

50 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

Appendix C: Schematics

Power Supplies

Revised - August 2014 LMK04800 Family SNAU076B 51

www.ti.com

LMK048xxB Device with Loop Filter and Cry stal Circuits

D D

C C

3 9Main Sheet / IC

8/12/2011

LMK048xx_PLL.SchDoc

Sheet Title:

Size: Schematic:

Mod. Date:

File:

Rev:

Sheet: of

National Semiconductor and/or its licensors do not warrant the accuracy or completeness of

this specification or any information contained therein. National and/or its licensors do not

warrant that this design will meet the specifications, will be suitable for your application or fit

for any particular purpose, or will operate in an implementation. National and/or its licensors

do not warrant that the design is production worthy. You should completely validate and test

your design implementation to confirm the system functionality for your application.

http://www.national.com

Contact: http://www.national.com/support

LMK048xx E valuation BoardProject:

Designed for: Evaluation Customer

870600534 3.0

Assembly Variant: LVPEC L240 - 2011-07-26

CLKout0

CLKout0*

CLKout1

4CLKout1*

SYNC*

Vcc1

LDObyp1

LDObyp2

CLKout4

CLKout4*

CLKout5

22 CLKout5*

GND

Vcc4

FBCLKin/CLKin1

FBCLKin*/CLKin1*

Status_Holdover

CLKin0

CLKin0*

Vcc5

Vcc6 35

OSCin 36

OSCin* 37

Vcc7 38

OSCout0 39

OSCout0* 40

Vcc8 41

CPout2 42

Vcc9 43

LEuWire 44

CLKuWire 45

DATAuWire 46

CLKout7 51

Vcc11 52

CLKout8 53

CLKout8* 54

CLKout9* 55

CLKout9 56

Vcc12 57

CLKout10 58

CLKout10* 59

CLKout11* 60

CLKout11 61

Status_CLKin0 62

LMK048xxB

DAP PAD

CLKout2

CLKout2*

CLKout3*

CLKout3

Vcc2

Vcc3

OSCout1

OSCout1*

Status_LD 33

CPout1 34

Vcc10 47

CLKout6 48

CLKout6* 49

CLKout7* 50

Status_CLKin1 63

Vcc13 64

LMK04800

100pF

C2pA2

DNP

0.1µF

C36

DNP

0.1µF

C27

DNP

C2_B2

DNP

100pF

C1_B2

470

R2_B2

R55

0.12uF

C2pB2

R72

DNP

0.68µF

C2_A1

3.9k

Rb2_B1

10µF

Cb2pB1

0.33µF

Cb1_B1 DNP

Cb2_B1

DNP

Crystal Loop Filter

Y301

DNP

R69

DNP 2pF

C34

2200pF

C32

2pF

C28

2200pF

C29

PLL2 Loop F ilters

PLL1 Loop F ilters

O SC in Tuneable Crystal

4.7k

R62

1000pF

C304

10k

R307

VCXO Loop F ilter

Y300

DNP DNP

VTUNE2_TP

R306

DNP

R308

DNP

R73

Crystal-mode Lo op Filter

VCXO-mode Loop Filter

Designators greater than and equ al to 200 are placed on bottom of PCB

10µF

C35

0.1µF

C37

CLKout0_P

CLKout0_N

CLKout1_P

CLKout1_N

CLKout2_P

CLKout2_N

CLKout3_P

CLKout3_N

CLKout4_P

CLKout4_N

CLKout5_P

CLKout5_N

CLKin0_P

CLKin0_N

CLKin1_P

CLKin1_N

OSCout1_P

OSCout1_N

Status_Hold

Status_LD

Status_CLKin0

Status_CLKin1

CLKout11_N

CLKout11_P

CLKout10_N

CLKout10_P

CLKout9_N

CLKout9_P

CLKout8_N

CLKout8_P

CLKout7_N

CLKout7_P

CLKout6_N

CLKout6_P

SYNC

R60

DNP

uWire_DATA

uWire_CLK

uWire_LE

OSCout0_N

OSCout0_P

Vcc1_VCO

Vcc2_CLKout_CG1

Vcc3_CLKout_CG2 Vcc4_Digital Vcc5_CLKin

Vcc6_PDCP1

Vcc7_OSC

Vcc9_PLL2

Vcc12_CLKout_CG5

Vcc13_CLKout_CG0

Vcc8_PDCP2

OSCin_N

OSCin_P

Vtune1 Monitoring

4.7k

R67

R76

DNP

R51

DNP

R305

DNP

Vtune2 Sw ith MA M onitoring via Status LD

VTUNE1_TP

DNP

C40

DNP

C39

DNP

R309

DNP

10k

R310

DNP

10k

R311

DNP

Vcc_VCXO_OpAmp

R78

DNP

Vcc_VCXO_OpAmp

Vtune_VCXO

Vtune_XTAL

Status_Hold

SYNC

Status_LD

Status_CLKin0

Status_CLKin1

uWire_LE

uWire_DATA

uWire_CLK

0.1µF

C33

DNP

R74

V+

V- U4

LMP7731MF

Vtune_XTAL

Vcc_VCXO_LDO

0.1µF

C305

DNP

R71

DNP

R75

DNP

R53

DNP

Cb1_VCO

DNP DNP

Cb2pVCO

DNP

Rb2_VCO

DNP

Cb2_VCO

DNP VCO_Vtune

R304

0.1µF

C41

Vtune1

SMA DNP

0.1µF

C38

100

R65

DNP

R61

R68

DNP

0.1µF

C1_A1 2.7µF

C2pA1

DNP

39k

R2_A1

620

R2_A2

47pF

C1_A2 3900pF

C2_A2

NC 2

PD 3

SCT

BALUN - ADT2-1T+

DNP

R64

DNP

R59

R66

DNP

R63

DNP

OSCin_1_N

OSCin_1_P

SMV1249-074LF

R70

CPout1

CPout1_1

Vcc10_CLKout_CG3

Vcc11_CLKout_CG4

Status_LD

R52

DNP

Status_Hold

R77

DNP

OSCinN

OSCinP

R376

DNP

52 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

Reference Inputs (CLKin0 & CLKin1), External VCXO (OSCin) & VCO Circuits, and OSCout1 Output

Revised - August 2014 LMK04800 Family SNAU076B 53

www.ti.com

Clock Outputs (OSCout0, CLKout0 to CLKout3)

D D

C C

B B

A A

6 9Clock Outputs 1/3

6/8/2011

OutClks0.SchDoc

Sheet Title:

Size: Schematic:

Mod. Date:

File:

Rev:

Sheet: of

National Se m iconductor and/or its licensors do not wa rrant the accura cy or com ple tene ss of

this specification or any informa tion contained the rein. Na tional a nd/or its licensors do not

warran t that this design w ill m ee t the spe cifications, will be suitable for yo ur application or fit

for any pa rticular purpose, or will ope rate in an im ple m e ntation. Nationa l and/or its licens ors

do not warrant that the de sign is production worthy. Y ou s hould com pletely validate an d test

your de sign im ple m entation to confirm the s y stem functionality for your a pplication.

http://www.national.com

Contact: http://www.national.com/support

LMK 048xx Eva luation Boa rdProject:

Des igned for: Ev a luation C ustom er

870600534 3.0

Assembly Variant: LVPEC L240 - 2011-07-26

R106DNP

120

R97

DNP 82

R98

DNP

120

R113

DNP 82

R118

DNP

CLKout0_N

CLKout0_P

CLKout0

R127

DNP

120

R122

DNP 82

R123

DNP

120

R136

DNP 82

R137

DNP

0.1µF

C54

0.1µF

C58

CLKout3

R128DNP

120

R119

DNP 82

R120

DNP

R140

DNP

CLKout2_N

CLKout2_P

CLKout2

VccCLKoutPlane

R109

DNP

R132

DNP 62

R131

DNP

0.1µF

C57

120

R139

DNP

CLKout2_1_P

CLKout2_1_N

Notes:

1. Designators greater than and equal to 300 are placed on bottom of PCB

R105

DNP

120

R100

DNP 82

R101

DNP

120

R115

DNP 82

R116

DNP

0.1µF

C48

0.1µF

C52

CLKout1

VccCLKoutPlane

R110

DNP

R91

DNP

120

R88

DNP 82

R89

DNP

120

R94

DNP 82

R95

DNP

0.1µF

C44

0.1µF

C46

OSCout0_N

OSCout0_P

OSCout0

VccCLKoutPlane

R93

DNP

OSCout0_1_P

OSCout0_1_N

CLKout1_P

CLKout1_N

CLKout3_P

CLKout3_N

R107

0.1µF

C49

DNP

R129

0.1µF

C55

DNP

R108

0.1µF

C50

DNP

R130

0.1µF

C56

DNP

R92

DNP

0.1µF

C45

DNP

OSCout0

SMA

OSCout0*

SMA

CLKout0

SMA

CLKout0*

SMA

CLKout2

SMA

CLKout2*

SMA

CLKout3*

SMA

DNP

CLKout3

SMA

DNP

CLKout1*

SMA

DNP

CLKout1

SMA

DNP

Default: LVDS, AC coupled

Default: LVPECL, AC coupled Default: LVPECL, AC coupled

Default: LVPECL, AC coupledDefault: LVPECL, AC coupled

0.1µF

C47

0.1µF

C51

0.1µF

C53

CLKout0_1_P

CLKout0_1_N CLKout1_1_P

CLKout1_1_N

CLKout3_1_P

CLKout3_1_N

R99

DNP

R114

DNP

R121

DNP

R135

DNP

R124

R138

R102

R117

R90

DNP

R96

DNP

240

R103

GND

240

R111

GND

240

R125

GND

240

R133

GND

240

R134

GND

240

R126

GND

240

R112

GND

240

R104

GND

240

R231

GND

240

R232

GND

54 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

Clock Outputs (CLKout4 to CLKout7)

D D

C C

B B

A A

7 9Clock Outputs 2/3

6/8/2011

OutClks1.SchDoc

Sheet Title:

Size: Schematic:

Mod. Date:

File:

Rev:

Sheet: of

National Se m iconductor and/or its licensors do not wa rrant the accura cy or com ple tene ss of

this specification or any informa tion contained the rein. Na tional a nd/or its licensors do not

warran t that this design w ill m ee t the spe cifications, will be suitable for yo ur application or fit

for any pa rticular purpose, or will ope rate in an im ple m e ntation. Nationa l and/or its licens ors

do not warrant that the de sign is production worthy. Y ou s hould com pletely v a lida te an d test

your de sign im ple m entation to confirm the s y stem functionality for your a pplication.

http://www.national.com

Contact: http://www.national.com/support

LMK048x x Eva luation Boa rdProject:

Des igned for: Ev a luation C ustom er

870600534 3.0

Assembly Variant: LVPE CL240 - 2011-07-26

R150DNP

120

R143

DNP 82

R144

DNP

120

R159

DNP 82

R160

DNP

0.1µF

C59

0.1µF

C63

CLKout4_N

CLKout4_P

CLKout4

R171DNP

120

R167

DNP 82

R168

DNP

120

R180

DNP 82

R181

DNP

0.1µF

C66

0.1µF

C70

CLKout7

R172

DNP

120

R165

DNP 82

R166

DNP

R184

DNP

0.1µF

C65

CLKout6_N

CLKout6_P

CLKout6

VccCLKoutPlane

R153DNP

R176

DNP 62

R175DNP

0.1µF

C69

120

R183

DNP

R149DNP

120

R145

DNP 82

R146

DNP

120

R161

DNP 82

R162

DNP

0.1µF

C60

0.1µF

C64

CLKout5

VccCLKoutPlane

R154

DNP

Notes:

1. Designators greater than and equal to 300 are placed on bottom of PCB

CLKout5_N

CLKout5_P

CLKout7_N

CLKout7_P

R151

0.1µF

C61

DNP

R173

0.1µF

C67

DNP

R174

0.1µF

C68

DNP

R152

0.1µF

C62

DNP

CLKout4

SMA

CLKout4*

SMA

CLKout5*

SMA

DNP

CLKout5

SMA

DNP

CLKout7*

SMA

DNP

CLKout7

SMA

DNP

CLKout6

SMA

CLKout6*

SMA

Default: LVDS or LVCMOS , AC coupled Default: LVDS or LVCMOS , AC coupled

CLKout6_1_P

CLKout6_1_N

CLKout4_1_P

CLKout4_1_N

CLKout7_1_P

CLKout7_1_N

CLKout5_1_P

CLKout5_1_N

R141

DNP

R157

DNP

R163

DNP

R179

DNP

R164

R182

R142

R158

240

R169

DNP

GND

240

R177

DNP

GND

240

R155

DNP

GND

240

R147

DNP

GND

240

R148

DNP

GND

240

R156

DNP

GND

240

R170

DNP

GND

240

R178

DNP

GND

R233

R234

CLKout6_2_P

CLKout6_2_N

Revised - August 2014 LMK04800 Family SNAU076B 55

www.ti.com

Clock Outputs (CLKout8 to CLKout11)

D D

C C

B B

A A

8 9C lock Outputs 3/3

6/8/2011

OutClks2.SchDoc

Sheet Title:

Size: Schematic:

Mod. Date:

File:

Rev:

Sheet: of

National Se m iconductor and/or its licensors do not wa rrant the accura cy or com ple tene ss of

this specification or any informa tion contained the rein. Na tional a nd/or its licensors do not

warran t that this design w ill m ee t the spe cifications, will be suitable for yo ur application or fit

for any pa rticular purpose, or will ope rate in an im ple m e ntation. Nationa l and/or its licens ors

do not warrant that the de sign is production worthy. Y ou s hould com pletely validate an d test

your de sign im ple m entation to confirm the s y stem functionality for your a pplication.

http://www.national.com

Contact: http://www.national.com/support

LMK 048xx Eva luation Boa rd

Project:

Des igned for: Ev a luation C ustom er

870600534 3.0

Assembly Variant: LVPEC L240 - 2011-07-26

R214

DNP

120

R207

DNP 82

R208

DNP

120

R223

DNP 82

R224

DNP

0.1µF

C77

0.1µF

C81

R193

DNP

120

R185

DNP 82

R186

DNP

120

R202

DNP 82

R203

DNP

0.1µF

C71

0.1µF

C75

CLKout8_N

CLKout8_P

CLKout8

CLKout10

CLKout10_N

CLKout10_P

R216

DNP

120

R210

DNP 82

R211

DNP

120

R226

DNP 82

R227

DNP

0.1µF

C78

0.1µF

C82

CLKout11

R194DNP

120

R188

DNP 82

R189

DNP

R205

DNP

0.1µF

C72

CLKout9

VccCLKoutPlane

R197

DNP

R219

DNP

R198DNP

R220DNP

0.1µF

C76

120

R201

DNP

CLKout9_1_P

CLKout9_1_N

Notes:

1. Designators greater than and equal to 300 are placed on bottom of PCB

CLKout9_P

CLKout9_N

CLKout11_P

CLKout11_N

R195

0.1µF

C73

DNP

R217

0.1µF

C79

DNP

R218

0.1µF

C80

DNP

R196

0.1µF

C74

DNP

CLKout8

SMA

CLKout8*

SMA

CLKout9*

SMA

DNP

CLKout9

SMA

DNP

CLKout11*

SMA

DNP

CLKout11

SMA

DNP

CLKout10

SMA

CLKout10*

SMA

Default: LVDS or LVCMOS , AC coupled

Default: LVPECL, AC coupled

Default: LVDS or LVCMOS , AC coupled

Default: LVPECL, AC coupled

CLKout11_1_P

CLKout11_1_N

CLKout10_1_P

CLKout10_1_N

CLKout8_1_P

CLKout8_1_N

R190

R206

R212

R228

R209

DNP

R225

DNP

R187

DNP

R204

DNP

240

R191

DNP

GND

240

R199

DNP

GND

240

R213

GND

240

R221

GND

240

R222

GND

240

R215

GND

240

R200

DNP

GND

240

R192

DNP

GND

56 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

uWire Header, Logic I/O Ports and Status LEDs

Revised - August 2014 LMK04800 Family SNAU076B 57

www.ti.com

USB Interface

58 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

Appendix D: Bill of Materials

Table 23: Bill of Materials for LMK048xx Evaluation Boards

Item

Designator

Description

Manufacturer

PartNumber

Quantity

C1, C5, C13, C20,

C22, C25, C300,

R3, R11, R12,

R19, R21, R22,

R29, R30, R37,

R46, R55, R73,

R74, R82, R84,

R229, R304, R327,

R329, R331, R333,

R337, R340, R341,

R346, R347, R349,

R353, R354, R358,

R361, R364, R365,

R368, R371, R373,

R374, R375, R400,

R402

FB, 120 ohm, 500 mA, 0603, RES, 0 ohm, 5%, 0.1W,

0603

Vishay-Dale,

Vishey/Dale

CRCW06030000Z0EA

Revised - August 2014 LMK04800 Family SNAU076B 59

www.ti.com

C1_A1, C6, C14,

C19, C21, C24,

C27, C37, C38,

C44, C46, C47,

C48, C51, C52,

C53, C54, C57,

C58, C59, C60,

C63, C64, C65,

C66, C70, C71,

C72, C75, C76,

C77, C78, C81,

C82, C312, C319,

C329, C361

CAP, CERM, 0.1uF, 25V, +/-5%, X7R, 0603

Kemet

C0603C104J3RACTU

C1_A2

CAP, CERM, 47pF, 50V, +/-5%, C0G/NP0, 0603

Kemet

C0603C470J5GACTU

C1_B2

CAP, CERM, 150pF, 50V, +/-5%, C0G/N P0, 060 3

Kemet

C0603C151J5GACTU

C2, C12, C41,

C302, C330, C346

CAP, CERM, 0.1uF, 16V, +/-10%, X7R, 0603

Kemet

C0603C104K4RACTU

C2pB2

CAP, CERM, 0.12uF, 50V, +/-10%, X7R, 0805

Kemet

C0805C124K5RACTU

C2_A1

CAP, CERM, 0.68µF, 10V, +/-10%, X5R, 0603

Kemet

C0603C684K8PAC

C2_A2

CAP, CERM, 3900pF, 50V, +/-10%, X7R, 0603

MuRata

GRM188R71H392KA01D

C4, C69, C314,

C322, C326, C367,

C400, C401, C402,

C409, C412, C414

CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603, CAP,

CERM, 0.1µF, 25V, +/-10%, X7R, 0603

Kemet

C0603C104K3RACTU

CAP, CERM, 82pF, 50V, +/-10%, C0G/NP0, 0603

Kemet

C0603C820K5GACTU

C10, C29, C32,

C341

CAP, CERM, 2200pF, 50V, +/-10%, X7R, 0603

Kemet

C0603C222K5RACTU

C11

CAP, CERM, 10µF , 10 V, +/ -20%, X5R, 0805

Kemet

C0805C106M8PACTU

60 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

C23, C26, R103,

R104, R111, R112,

R125, R126, R133,

R134, R213, R215,

R221, R222, R231,

R232, R338

RES, 240 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW0603240RJNEA

C28, C34

CAP, CERM, 2pF, 50 V, +/-12.5%, C0G/NP0, 0603

Kemet

C0603C209C5GACTU

C35, C310, C317,

C324, C352,

Cb2pB1

CAP, CERM, 10uF, 10V, +/-10%, X5R, 0805

Kemet

C0805C106K8PACTU

C304

CAP, CERM, 1000pF, 50V, +/-5%, C0G/NP0, 0603

Kemet

C0603C102J5GACTU

C311, C313, C318,

C321, C325, C331,

C342

CAP, CERM, 1uF, 10 V, +/-10%, X5R, 0603

Kemet

C0603C105K8PACTU

C315, C323

CAP, CERM, 0.01uF, 100V, +/-10%, X7R, 0603

Kemet

C0603C103K1RACTU

C340

CAP, CERM, 4.7uF, 10V, +/-10%, X5R, 0603

Kemet

C0603C475K8PACTU

C350, C351, C359,

C360

CAP, CERM, 0.47uF, 16V, +/-10%, X7R, 0603

Kemet

C0603C474K4RACTU

C368

CAP, CERM, 100pF, 50V, +/-5%, C0G/N P0, 060 3

Kemet

C0603C101J5GACTU

C403

CAP, CE RM, 10uF , 6.3V, + /-10%, X5R, 0805

Kemet

C0805C106K9PAC

C404

CAP, TANT, 1uF, 20V, +/-10%, 8.4 ohm, 3216-18 SMD

Vishay-Sprague

293D105X9020A2TE3

C405, C408

CAP, CERM, 0.22uF, 16V, +/-10%, X7R, 0603

Kemet

C0603C224K4RACTU

C406, C407

CAP, CE RM, 18pF , 50V, +/ -5%, C0G/NP0, 0603

Kemet

C0603C180J5GACTU

C410, C411

CAP, CERM, 1uF, 16 V, +/-10%, X5R, 0603

Kemet

C0603C105K4PACTU

C413, C415

CAP, CERM, 0.01uF, 50V, +/-5%, X7R, 0603

Kemet

C0603C103J5RACTU

Cb1_B1

CAP, CERM, 0.33uF, 16V , +/-10%, X7R, 0603

Kemet

C0603C334K4RACTU

Revised - August 2014 LMK04800 Family SNAU076B 61

www.ti.com

CLKin0, CLKin0*,

CLKout0,

CLKout0*,

CLKout2,

CLKout2*,

CLKout4,

CLKout4*,

CLKout6,

CLKout6*,

CLKout8,

CLKout8*,

CLKout10,

CLKout10*,

FBCLKin*/CLKin1*,

OSCout0,

OSCout0*,

OSCout1,

OSCout1*

Connector, SMT, End launch SMA 50 Ohm

Emerson Network

Power

142-0701-851

CR400, CR401

ESD suppressor

Littelfuse Inc

PGB1010603MR

Common Cathode Tuning Varactor

Skyworks

SMV1249-074LF

D2, D3, D4

LED 2.8X3.2MM 565NM RED CLR SMD

Lumex

Opto/Components Inc.

SML-LX2832IC

LED 2.8X3.2MM 565NM GRN CLR SMD

Lumex

Opto/Components Inc.

SML-LX2832GC

CONN TERM BLK PCB 5.08MM 2POS OR

Weidmuller

1594540000

R2, R13, R36,

R47, R59, R70,

R332

RES, 0 ohm, 5%, 0.125W, 0805

Vishay-Dale

CRCW08050000Z0EA

R2_A1

RES, 39k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060339K0JNEA

R2_A2

RES, 620 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW0603620RJNEA

R2_B2

RES, 470 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW0603470RJNEA

R4, R9

RES, 100 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW0603100RJNEA

R18, R336, R342,

R343

FB, 1000 ohm, 600 mA, 0603, Ferrite

Murata

BLM18HE102SN1D

R24

RES, 18 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060318R0JNEA

62 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

R26, R27, R83,

R85

RES, 270 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW0603270RJNEA

R43, R107, R108,

R129, R130, R151,

R152, R173, R174,

R195, R196, R217,

R218

RES, 68 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060368R0JNEA

R61, R102, R117,

R124, R138, R142,

R158, R164, R182,

R190, R206, R212,

R228

RES, 51 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060351R0JNEA

R62, R67

RES, 4.7k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW06034K70JNEA

R80, R81, R312,

R315, R317, R318,

R321, R324

RES, 15k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060315K0JNEA

R233, R234

RES, 33 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060333R0JNEA

R307

RES, 10k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060310K0JNEA

R313, R316, R319,

R320, R322, R325

RES, 27k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060327K0JNEA

R344

RES, 392 ohm, 1%, 0.1W, 0603

Vishay-Dale

CRCW0603392RFKEA

R345, R348, R355,

R359, R362, R366,

R372

FB, 120 ohm, 500 mA, 0603

Murata

BLM18AG121SN1D

R350, R369

RES, 51k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060351K0JNEA

R351

RES, 2.00k ohm, 1%, 0.1W, 0603

Vishay-Dale

CRCW06032K00FKEA

R356

RES, 866 ohm, 1%, 0.1W, 0603

Vishay-Dale

CRCW0603866RFKEA

R404, R405

RES, 22 ohm, 5%, 0.125W, 0805

Vishay-Dale

CRCW080522R0JNEA

R407, R411

RES, 47k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060347K0JNEA

Rb2_B1

RES, 3.9k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW06033K90JNEA

S1, S2, S3, S4, S5,

0.875" Standof f

VOLTREX

SPCS-14

LMK04800

Texas Instruments

LMK048xxBISQ

Revised - August 2014 LMK04800 Family SNAU076B 63

www.ti.com

122.88 MHz VCXO

Crystek

CVHD-950-122.88

U4, U300

Precison S ingle Low Noise, Low 1/F corner Op Amp

Texas Instruments

LMP7731MF

U302

Micropower 800mA Low Noise 'Ceramic Stable'

Adjustable Voltage Regulator for 1V to 5V Applications

Texas Instruments

LP3878SD-ADJ

U303, U305

Ultra Low Noise, 150mA Linear Regulator for RF/Analog

Circuits Requires No Bypass Capacitor

Texas Instruments

LP5900SD-3.3

uWire

Low Profile Vert ical Header 2x5 0.100 "

FCI

52601-G10-8LF

Vcc

Connector, TH, SMA

Emerson Network

Power

142-0701-201

VccVCO/Aux,

VccVCXO/Aux

Connector, SMA Jack, Vertical, Gold, SMD

Emerson Network

Power Connec ti vit y

142-0711-201

Unpopulated Components

B1, B2, B3

ADT2-1T Balun

MiniCircuits

ADT2-1T+

C2pA1

CAP, CERM, 2.7uF, 10V, +/-10%, X5R, 0805

Kemet

C0805C275K8PACTU

C2pA2, C3_AB1,

C15, C17, C42,

C43, C306, C307,

C308, C309

CAP, CERM, 100pF, 50V, +/-5%, C0G/N P0, 060 3

Kemet

C0603C101J5GACTU

C2_B2

CAP, CERM, 680 0pF, 100 V, +/-10%, X7R, 0603

Kemet

C0603C682K1RACTU

C3, C36, C335

CAP, CERM, 0.1uF, 25V, +/-5%, X7R, 0603

Kemet

C0603C104J3RACTU

C7, C8, C16, C18,

C33, C45, C49,

C50, C55, C56,

C61, C62, C67,

C68, C73, C74,

C79, C80, C301,

C303, C305

CAP, CERM, 0.1uF, 16V, +/-10%, X7R, 0603

Kemet

C0603C104K4RACTU

C39, C40, C333,

Cb1_VCO,

Cb2_B1,

Cb2_VCO,

Cb2pVCO

Technology, Dielectric, xxV, xx%

DNP_CAP

C316, C320, C327,

C328, C332, C334,

C336

CAP, CERM, 0.1uF, 16V, +/-5%, X7R, 0603

Kemet

C0603C104J4RACTU

64 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

C337, C343, C347,

C353, C356, C364

CAP, CERM, 1uF, 10 V, +/-10%, X5R, 0603

Kemet

C0603C105K8PACTU

C338, C344, C348,

C354, C357, C365

CAP, CERM, 0.1uF, 25V, +/-10%, X7R, 0603

Kemet

C0603C104K3RACTU

C339, C345, C349,

C355, C358, C366

CAP, CERM, 0.01uF, 100V, +/-10%, X7R, 0603

Kemet

C0603C103K1RACTU

CLKin0_SEL,

CLKin1_SEL,

Status_Hold,

Status_LD, S YNC

Connector, SMA Jack, Vertical, Gold, SMD

Emerson Network

Power Connec ti vit y

142-0711-201

CLKout1,

CLKout1*,

CLKout3,

CLKout3*,

CLKout5,

CLKout5*,

CLKout7,

CLKout7*,

CLKout9,

CLKout9*,

CLKout11,

CLKout11*,

FBCLKin/CLKin1,

OSCin, OSCin*,

Vtune1

Connector, SMT, End launch SMA 50 Ohm

Emerson Network

Power

142-0701-851

D300

Diode, Zener, 3.3V, 150mW, SOD-523F

Comchip Technology

CZRU52C3V3

GND_TP, Vcc_TP

DNP_TP

HWB, RESET

APEM Com ponents ,

LLC

ADTSM31NV

J400

CONN RCPT MINI USB2.0 5POS SMD

Hirose Electr ic Co. Ltd.

UX60SA-MB-5ST

Revised - August 2014 LMK04800 Family SNAU076B 65

www.ti.com

R1, R20, R23,

R51, R52, R53,

R54, R60, R63,

R66, R69, R71,

R72, R75, R76,

R77, R78, R230,

R300, R301, R305,

R306, R308, R335,

R339, R352, R363,

R367, R370

RES, 0 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW06030000Z0EA

R5, R8, R14, R25,

R33, R34, R41,

R48, R64, R68,

R90, R96, R99,

R114, R121, R135,

R141, R157, R163,

R179, R187, R204,

R209, R225, R376

RES, 51 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060351R0JNEA

R6, R7, R15, R17,

R31, R32, R39,

R40, R49, R50,

R79, R314

RES, 270 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW0603270RJNEA

66 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

R10, R16, R88,

R94, R97, R100,

R113, R115, R119,

R122, R136, R139,

R143, R145, R159,

R161, R165, R167,

R180, R183, R185,

R188, R201, R202,

R207, R210, R223,

R226

RES, 120 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW0603120RJNEA

R28, R42, R65

RES, 100 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW0603100RJNEA

R35, R44, R89,

R95, R98, R101,

R116, R118, R120,

R123, R137, R140,

R144, R146, R160,

R162, R166, R168,

R181, R184, R186,

R189, R203, R205,

R208, R211, R224,

R227

RES, 82 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060382R0JNEA

Revised - August 2014 LMK04800 Family SNAU076B 67

www.ti.com

R38, R45, R91,

R93, R105, R106,

R109, R110, R127,

R128, R131, R132,

R149, R150, R153,

R154, R171, R172,

R175, R176, R193,

R194, R197, R198,

R214, R216, R219,

R220

RES, 62 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060362R0JNEA

R86, R87

RES, 27k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060327K0JNEA

R92

RES, 68 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060368R0JNEA

R147, R148, R155,

R156, R169, R170,

R177, R178, R191,

R192, R199, R200

RES, 240 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW0603240RJNEA

R302, R303, R310,

R311, R401

RES, 10k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060310K0JNEA

R309, Rb2_VCO

x%, x.xxxW

DNP_RES

R323

RES, 2.2k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW06032K20JNEA

R326, R328, R330

FB, 1000 ohm, 600 mA, 0603

Murata

BLM18HE102SN1D

R334

RES, 0 ohm, 5%, 0.125W, 0805

Vishay-Dale

CRCW08050000Z0EA

R360

RES, 51k ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060351K0JNEA

100

R403, R406, R408,

R409, R410

RES, 33 ohm, 5%, 0.1W, 0603

Vishay-Dale

CRCW060333R0JNEA

101

VCO

CRO2949A-LF

102

U301

3-Terminal Adjustable Regulator

Texas Instruments

LM317AEMP

103

U400, Y400

104

Y300, Y301

DNP_XTAL

68 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

Appendix E: PCB Layers Stackup

6-layer PCB Stackup includes:

• Top Layer for high-priority high-frequency signals (2 oz.)

• RO4003 Dielectric, 16 mils

• RF Ground plane (1 oz.)

• FR4, 4 mils

• Power plane #1 (1 oz.)

• FR4, 12.6 mils

• Ground plane (1 oz.)

• FR4, 8 mils

• Power Plane #2 (1 oz.)

• FR4, 12 mils

• Bottom Layer copper clad for thermal relief (2 oz.)

RO4003 (Er = 3.3)

16 mil

Top Layer [LMK048xxENG.GTL]

RF Ground plane [LMK048xxENG.G1]

FR4 (Er = 4.8)

4 mil

Power plane #1 [LMK048xxENG.G2]

FR4

12.6 mil

Ground plane [LMK048xxENG.GP1]

FR4

12 mil

Bottom Layer [LMK048xxENG.GBL]

62.2 mil thick

FR4

8 mil

Power plane #2 [LMK048xxENG.G3]

Revised - August 2014 LMK04800 Family SNAU076B 69

www.ti.com

Appendix F: PCB Layout

Lay er #1 – Top

70 SNAU076B LMK04800 Family Revised - August 2014

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Lay er #2 – RF Ground Plane (Inverted)

Revised - August 2014 LMK04800 Family SNAU076B 71

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Lay er #3 – Vcc Planes

72 SNAU076B LMK04800 Family Revised - August 2014

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Lay er #4 – Ground Plane (Inverted)

Revised - August 2014 LMK04800 Family SNAU076B 73

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Layer # 5 – Vcc Planes 2

74 SNAU076B LMK04800 Family Revised - August 2014

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Lay er #6 – Bottom

Revised - August 2014 LMK04800 Family SNAU076B 75

www.ti.com

Lay ers #1 and 6 – Top and Bottom (Composite)

76 SNAU076B LMK04800 Family Revised - August 2014

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Appendix G: EVM Software and Communication: Interfacing

uWire

Codeloader is the software used to communicate with the EVM (Please download the latest version from

TI.com - http://www.ti.com/tool/codeloader). This EVM can be controlled through the uWire interface on

board. There are two options in communicating with the uWire interface from the computer.

OPTION 1

Open Codeloader.exe  Click “Select Device”  Click “Port Setup” tab  Click “LPT” (in Communication

Mode)

OPTIO N 2

Revised - August 2014 LMK04800 Family SNAU076B 77

www.ti.com

The Adapter Board

This table describes the pins configuration on the adapter board for each EVM board (See examples below table)

EVM

Jumper Bank

Code Loader Configuration

LMX2581

BUFEN (pin 1), Trigger (pin 7)

LMX2541

CE (pin 1), Trigger (pin 10)

LMK0400x

GOE (pin 7)

LMK01000

GOE (pin 7)

LMK030xx

SYNC (pin 7)

LMK02000

SYNC (pin 7)

LMK0480x

Status_CLKin1 (pin 3)

LMK04816/4906

Status_CLKin1 (pin 3)

LMK01801

Test (pin 3), SYNC0 (pin 10)

LMK0482x (prelease)

CLKin1_SEL (pin 6), Reset ( pin 10)

LMX2531

Trigger (pin 1)

LMX2485/7

ENOSC (pin 7), CE (pin 10)

LMK03200

SYNC (pin 7)

LMK03806

LMK04100

Example adapter configuration (LMK01801)

Open Codeloader.exe  Click “Select Device”  Click “Port Setup” Tab  Click “ USB” (in Communic a tion

Mode)

*Remember to also make modifications in “Pin Configuration” Section according to Table above.

78 SNAU076B LMK04800 Family Revised - August 2014

www.ti.com

Appendix H: Troubleshooting Information

If the evaluation board is not behaving as expected, the most likely issues are…

1) Board communication issue

2) Incorrect Programming of the device

3) Setup Error

Refer to this checklist for a practical guide on identifying/exposing possible issues.

1) Confirm Communications

2) Confirm PLL1 operation/locking

1) Program LD_MUX = “PLL1_R/2”

2) Confirm that LD pin output is half the expected phase detector frequency of PLL1.

i. If not, examine CLKin_SEL programming.

ii. If not, examine CLKin0_BUFTYPE / CLKin1_BUFTYPE.

iii. If not, examine PLL1 register R programming.

iv. If not, examine physical CLKin input.

3) Program LD_MUX = “PLL1_N /2”

4) Confirm that LD pin output is half the expected phase detector frequency of PLL1.

i. If not, examine PLL1 register N programming.

ii. If not, examine physical OSCin input.

Naturally, the output frequency of the above two items, PLL 1 R Divider/2 and PLL 1 N Divider

/2, on LD pin should be the same frequency.

5) Program LD_MUX = “PLL1_DLD”

6) Confirm the LD pin output is high.

i. If high, then PLL1 is locked, continue to PLL2 operation/locking.

7) If LD pin output is low, but the frequencies are the same, it is possible that excessive

leakage on Vtune pin is causing the digital lock detect to not activate. By default

PLL2 waits for the digital lock detect to go high before allowing PLL2 and the

integrated VCO to lock. Different VCXO models have different input leakage

specifications. High leakage, low PLL1 phase detector frequencies, and low PLL1

charge pump current settings can cause the PLL1 charge pump to operate longer than

the digital lock detect timeout which allows the device to lock, but prevents the

digital lock detect from activating.

i. Redesign PLL1 loop filter with higher phase detector frequency

ii. Redesign PLL1 loop filter with higher charge pump current

iii. Isolate VCXO tuning input from PLL1 charge pump with an op amp.

Revised - August 2014 LMK04800 Family SNAU076B 79

www.ti.com

3) Confirm PLL2 operation/locking

1) Program LD_MUX = “PLL2_R/2”

2) Confirm that LD pin output is half the expected phase detector frequency of PLL2.

i. If not, examine PLL2_R programming.

ii. If not, examine physical OSCin input.

3) Program LD_MUX = “PLL2_N/2”

4) Confirm that LD pin output is half the expected phase detector frequency of PLL2.

i. If not, confirm OSCin_FREQ is programmed to OSCin frequency.

ii. If not, examine PLL2_N program ming.

Naturally, the output frequency of the above two items should be the same frequency.

5) Program LD_MUX = “PLL2 DLD”

6) Confirm the LD pin output is high.

7) Program LD_MUX = “PLL1 & PLL2 DLD”

8) Confirm the LD pin output is high.

STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES

1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or

documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.

Acceptance of the EVM is expressly subject to the following terms and conditions.

1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility

evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not

finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For

clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions

set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software

1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,

or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production

system.

2Limited Warranty and Related Remedies/Disclaimers:

2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software

License Agreement.

2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM

to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment

by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any

way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or

instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as

mandated by government requirements. TI does not test all parameters of each EVM.

2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,

or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the

warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to

repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall

be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day

warranty period.

3Regulatory Notices:

3.1 United States

3.1.1 Notice applicable to EVMs not FCC-Approved:

This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit

to determine whether to incorporate such items in a finished product and software developers to write software applications for

use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless

all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause

harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is

designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of

an FCC license holder or must secure an experimental authorization under part 5 of this chapter.

3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:

CAUTION

This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not

cause harmful interference, and (2) this device must accept any interference received, including interference that may cause

undesired operation.

Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to

operate the equipment.

FCC Interference Statement for Class A EVM devices

NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of

the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is

operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not

installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.

Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to

correct the interference at his own expense.

SPACER

FCC Interference Statement for Class B EVM devices

NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of

the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential

installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance

with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference

will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which

can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more

of the following measures:

•Reorient or relocate the receiving antenna.

•Increase the separation between the equipment and receiver.

•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

•Consult the dealer or an experienced radio/TV technician for help.

3.2 Canada

3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210

Concerning EVMs Including Radio Transmitters:

This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:

(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may

cause undesired operation of the device.

Concernant les EVMs avec appareils radio:

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation

est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit

accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concerning EVMs Including Detachable Antennas:

Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)

gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type

and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for

successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types

listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.

Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited

for use with this device.

Concernant les EVMs avec antennes détachables

Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et

d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage

radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope

rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le

présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le

manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne

non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de

l'émetteur

3.3 Japan

3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に

輸入される評価用キット、ボードについては、次のところをご覧ください。

http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page

3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified

by TI as conforming to Technical Regulations of Radio Law of Japan.

If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law of

Japan to follow the instructions below with respect to EVMs:

1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal

Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for

Enforcement of Radio Law of Japan,

2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to

EVMs, or

3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan

with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note

that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.

SPACER

【無線電波を送信する製品の開発キットをお使いになる際の注意事項】開発キットの中には技術基準適合証明を受けて

いないものがあります。技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの

措置を取っていただく必要がありますのでご注意ください。

1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用

いただく。

2. 実験局の免許を取得後ご使用いただく。

3. 技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。

上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。日本テキサス・イ

ンスツルメンツ株式会社

東京都新宿区西新宿６丁目２４番１号

西新宿三井ビル

3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page

電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ

い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page

SPACER

4EVM Use Restrictions and Warnings:

4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT

LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.

4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling

or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information

related to, for example, temperatures and voltages.

4.3 Safety-Related Warnings and Restrictions:

4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user

guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and

customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input

and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or

property damage. If there are questions concerning performance ratings and specifications, User should contact a TI

field representative prior to connecting interface electronics including input power and intended loads. Any loads applied

outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible

permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any

load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.

During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit

components may have elevated case temperatures. These components include but are not limited to linear regulators,

switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the

information in the associated documentation. When working with the EVM, please be aware that the EVM may become

very warm.

4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the

dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.

User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,

affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic

and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely

limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and

liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or

designees.

4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,

state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all

responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and

liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local

requirements.

5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate

as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as

accurate, complete, reliable, current, or error-free.

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6. Disclaimers:

6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE

DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER

WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED

WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY

THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.

6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND

CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY

OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD

PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY

INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF

THE EVM.

7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS

LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,

EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY

HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION

SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY

OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.

8. Limitations on Damages and Liability:

8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,

INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE

TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS

BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED

TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS

OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,

LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL

BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.

8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION

ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM

PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER

THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE

OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND

CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.

9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)

will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in

a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable

order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),

excluding any postage or packaging costs.

10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,

without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to

these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.

Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief

in any United States or foreign court.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

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Wireless Connectivity www.ti.com/wirelessconnectivity

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