Dual 256-Position I2C Compatible
Digital Potentiometer
AD5243/AD5248
Rev. 0
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
2-channel, 256-position
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Fast settling time: tS = 5 µs typ on power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins AD0 and AD1 (AD5248
only)
Computer software replaces µC in factory programming
applications
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 µA max
Wide operating temperature: −40°C to +125°C
Evaluation board available
APPLICATIONS
Systems calibrations
Electronics level settings
Mechanical Trimmers® replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
FUNCTIONAL BLOCK DIAGRAMS
A1
V
DD
G
ND
SDA
SCL
W1
WIPER
REGISTER 1
PC INTERFACE
AD5243
04109-0-001
B1 A2 W2
WIPER
REGISTER 2
B2
Figure 1. AD5243
VDD
G
ND
SDA
SCL
AD0
AD1
W1
RDAC
REGISTER 1
ADDRESS
DECODE
SERIAL INPUT
REGISTER
AD5248
B1 W2
RDAC
REGISTER 2
B2
/
8
04109-0-002
Figure 2. AD5248
GENERAL DESCRIPTION
The AD5243 and AD5248 provide a compact 3 mm × 4.9 mm
packaged solution for dual 256-position adjustment applica-
tions. These devices perform the same electronic adjustment
function as a 3-terminal mechanical potentiometer (AD5243)
or a 2-terminal variable resistor (AD5248). Available in four
different end-to-end resistance values (2.5 kΩ, 10 kΩ, 50 kΩ,
and 100 kΩ), these low temperature coefficient devices are ideal
for high accuracy and stability variable resistance adjustments.
The wiper settings are controllable through the I2C compatible
digital interface. The AD5248 has extra package address decode
pins AD0 and AD1, allowing multiple parts to share the same
I2C 2-wire bus on a PCB. The resistance between the wiper and
either endpoint of the fixed resistor varies linearly with respect
to the digital code transferred into the RDAC latch.1
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 6 µA allows for usage in portable battery-operated
applications.
For applications that program the AD5243/AD5258 at the
factory, Analog Devices offers device programming software
running on Windows® NT/2000/XP operating systems. This
software effectively replaces any external I2C controllers, which
in turn enhances users systems time-to-market. An AD5243/
AD5248 evaluation kit and software are available. The kit
includes a cable and instruction manual.
1The terms digital potentiometer, VR, and RDAC are used interchangeably.
AD5243/AD5248
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Electrical Characteristics—2.5 kΩ Version ................................... 3
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4
Timing Characteristics—All Versions ........................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 12
Theory of Operation ...................................................................... 13
Programming the Variable Resistor and Voltage .................... 13
Programming the Potentiometer Divider............................... 14
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range.......................................... 14
Power-Up Sequence ................................................................... 14
Layout and Power Supply Bypassing ....................................... 14
Constant Bias to Retain Resistance Setting............................. 15
Evaluation Board ........................................................................ 15
I2C Interface .................................................................................... 16
I2C Compatible 2-Wire Serial Bus ........................................... 16
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
Revision 0: Initial Version
AD5243/AD5248
Rev. 0 | Page 3 of 20
ELECTRICAL CHARACTERISTICS—2.5 kΩ VERSION
VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; 40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2R-DNL RWB, VA = no connect −2 ±0.1 +2 LSB
Resistor Integral Nonlinearity2R-INL RWB, VA = no connect −6 ±0.75 +6 LSB
Nominal Resistor Tolerance3RAB TA = 25°C −20 +55 %
Resistance Temperature Coefficient (∆RAB/RAB )/∆T VAB = VDD, wiper = no connect 35 ppm/°C
RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V 160 200
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity4DNL −1.5 ±0.1 +1.5 LSB
Integral Nonlinearity INL −2 ±0.6 +2 LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF −10 −2.5 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 2 10 LSB
RESISTOR TERMINALS
Voltage Range5VA, VB, VW GND VDD V
Capacitance6 A, B CA, CB
f = 1 MHz, measured to GND, Code = 0x80
45 pF
Capacitance6 W CW
f = 1 MHz, measured to GND, Code = 0x80
60 pF
Shutdown Supply Current7IA_SD VDD = 5.5 V 0.01 1 µA
Common-Mode Leakage ICM VA = VB = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH VDD = 5 V 2.4 V
Input Logic Low VIL VDD = 5 V 0.8 V
Input Logic High VIH VDD = 3 V 2.1 V
Input Logic Low VIL VDD = 3 V 0.6 V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance6CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
Supply Current IDD VIH = 5 V or VIL = 0 V 3.5 6 µA
Power Dissipation8PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 30 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10%, Code = midscale ±0.02 ±0.08 %/%
DYNAMIC CHARACTERISTICS 9
Bandwidth −3 dB BW_2.5 K Code = 0x80 4.8 MHz
Total Harmonic Distortion THDWVA = 1 V rms, VB = 0 V, f = 1 kHz 0.1 %
VW Settling Time tSVA = 5 V, VB = 0 V, ±1 LSB error band 1 µs
Resistor Noise Voltage Density eN_WB RWB = 1.25 kΩ, RS = 0 3.2 nV/Hz
See notes at end of section.
AD5243/AD5248
Rev. 0 | Page 4 of 20
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; 40°C < TA < 125°C; unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ1Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB
Resistor Integral Nonlinearity2R-INL RWB, VA = no connect −2.5 ±0.25 +2.5 LSB
Nominal Resistor Tolerance3RAB TA = 25°C −20 +20 %
Resistance Temperature Coefficient (∆RAB/RAB )/∆T VAB = VDD, wiper = no connect 35 ppm/°C
RWB (Wiper Resistance) RWB Code = 0x00, VDD =5 V 160 200
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity4DNL −1 ±0.1 +1 LSB
Integral Nonlinearity4INL −1 ±0.3 +1 LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF −2.5 −1 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 1 2.5 LSB
RESISTOR TERMINALS
Voltage Range5VA, VB, VW GND VDD V
Capacitance6 A, B CA, CB
f = 1 MHz, measured to GND, Code = 0x80
45 pF
Capacitance6 W CW
f = 1 MHz, measured to GND, Code = 0x80
60 pF
Shutdown Supply Current7IA_SD VDD = 5.5 V 0.01 1 µA
Common-Mode Leakage ICM VA = VB = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH VDD = 5 V 2.4 V
Input Logic Low VIL VDD = 5 V 0.8 V
Input Logic High VIH VDD = 3 V 2.1 V
Input Logic Low VIL VDD = 3 V 0.6 V
Input Current IIL VIN = 0 V or 5 V ±1 µA
Input Capacitance CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
Supply Current IDD VIH = 5 V or VIL = 0 V 3.5 6 µA
Power Dissipation PDISS VIH = 5 V or VIL = 0 V, VDD = 5 V 30 µW
Power Supply Sensitivity PSS VDD = 5 V ± 10%, Code = midscale ±0.02 ±0.0
8
%/%
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB BW
R
AB
= 10 kΩ/50 kΩ/100 kΩ, Code = 0x80
600/100/4
0
kHz
Total Harmonic Distortion THDW
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz, R
AB
= 10 kΩ
0.1 %
VW Settling Time (10 kΩ/50 kΩ/100
kΩ)
tSVA = 5 V, VB = 0 V, ±1 LSB error band 2 µs
Resistor Noise Voltage Density eN_WB RWB = 5 kΩ, RS = 0 9 nV/Hz
See notes at end of section.
AD5243/AD5248
Rev. 0 | Page 5 of 20
TIMING CHARACTERISTICS—ALL VERSIONS
VDD = 5V ± 10%, or 3V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ1 Max Unit
I2C INTERFACE TIMING CHARACTERISTICS10 (Specifications Apply to All Parts)
SCL Clock Frequency fSCL 0 400 kHz
tBUF Bus Free Time between STOP and START t1 1.3 µs
tHD;STA Hold Time (Repeated START) t2After this period, the first clock pulse is
generated.
0.6 µs
tLOW Low Period of SCL Clock t3 1.3 µs
tHIGH High Period of SCL Clock t4 0.6 µs
tSU;STA Setup Time for Repeated START Condition t5 0.6 µs
tHD;DAT Data Hold Time11 t6 0.9 µs
tSU;DAT Data Setup Time t7 100 ns
tF Fall Time of Both SDA and SCL Signals t8 300 ns
tR Rise Time of Both SDA and SCL Signals t9 300 ns
tSU;STO Setup Time for STOP Condition t10 0.6 µs
See notes at end of section.
NOTES
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9All dynamic characteristics use VDD = 5 V.
10See timing diagrams for locations of measured values.
11The maximum tHD:DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.
AD5243/AD5248
Rev. 0 | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Value
VDD to GND –0.3 V to +7 V
VA, VB, VW to GND VDD
Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx1
Pulsed ±20 mA
Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance2 θJA: MSOP-10 230°C/W
1Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2Package power dissipation = (TJMAX − TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5243/AD5248
Rev. 0 | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
10
9
8
7
1
2
3
4
B1
A1
W2
W1
B2
A2
SDAGND
6
5
SCLV
DD
TOP VIEW
AD5243
04109-0-027
Figure 3. AD5243 Pin Configuration
10
9
8
7
1
2
3
4
B1
AD0
W2
W1
B2
AD1
SDAGND
6
5
SCLV
DD
TOP VIEW
AD5248
04109-0-028
Figure 4. AD5248 Pin Configuration
Table 5. AD5243 Pin Function Descriptions
Pin
No. Mnemonic Description
1 B1 B1 Terminal.
2 A1 A1 Terminal.
3 W2 W2 Terminal.
4 GND Digital Ground.
5 VDD Positive Power Supply.
6 SCL Serial Clock Input. Positive edge
triggered.
7 SDA Serial Data Input/Output.
8 A2 A2 Terminal.
9 B2 B2 Terminal.
10 W1 W1 Terminal.
Table 6. AD5248 Pin Function Descriptions
Pin
No. Mnemonic Description
1 B1 B1 Terminal.
2 AD0 Programmable Address Bit 0 for Multiple
Package Decoding.
3 W2 W2 Terminal.
4 GND Digital Ground.
5 VDD Positive Power Supply.
6 SCL Serial Clock Input. Positive edge
triggered.
7 SDA Serial Data Input/Output.
8 AD1 Programmable Address Bit 1 for Multiple
Package Decoding.
9 B2 B2 Terminal.
10 W1 W1 Terminal.
AD5243/AD5248
Rev. 0 | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
–2.0
–1.5
–1.0
–0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-030
V
DD
= 5.5V
T
A
= 25°C
R
AB
= 10k
V
DD
= 2.7V
Figure 5. R-INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOSTAT MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-031
TA = 25°C
RAB = 10k
VDD = 2.7V
VDD = 5.5V
Figure 6. R-DNL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE INL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-032
RAB = 10k
VDD = 2.7V
TA = –40°C, +25°C, +85°C, +125°C
VDD = 5.5V
TA = –40°C, +25°C, +85°C, +125°C
Figure 7. INL vs. Code vs. Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-033
VDD = 2.7V; TA = –40°C, +25°C, +85°C, +125°C
RAB = 10k
Figure 8. DNL vs. Code vs. Temperature
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
POTENTIOMETER MODE INL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-034
TA = 25°C
RAB = 10k
VDD = 2.7V
VDD = 5.5V
Figure 9. INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-035
TA = 25°C
RAB = 10k
VDD = 2.7V
VDD = 5.5V
Figure 10. DNL vs. Code vs. Supply Voltages
AD5243/AD5248
Rev. 0 | Page 9 of 20
–2.0
–1.5
–1.0
–0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-036
RAB = 10k
VDD = 2.7V
TA = –40°C, +25°C, +85°C, +125°C
VDD = 5.5V
TA = –40°C, +25°C, +85°C, +125°C
Figure 11. R-INL vs. Code vs. Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOSTAT MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-037
VDD = 2.7V, 5.5V; TA = –40°C, +25°C, +85°C, +125°C
RAB = 10k
Figure 12. R-DNL vs. Code vs. Temperature
–2.0
–1.5
–1.0
–0.5
0
0.5
FSE, FULL-SCALE ERROR (LSB)
1.0
1.5
2.0
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04109-0-038
VDD = 5.5V, VA = 5.0V
RAB = 10k
VDD = 2.7V, VA = 2.7V
Figure 13. Full-Scale Error vs. Temperature
0
0.75
1.50
2.25
3.00
3.75
4.50
ZSE, ZERO-SCALE ERROR (LSB)
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04109-0-039
VDD = 5.5V, VA = 5.0V
RAB = 10k
VDD = 2.7V, VA = 2.7V
Figure 14. Zero-Scale Error vs. Temperature
I
DD
, SUPPLY CURRENT (
µ
A)
0.1
1
10
–40 –7 26 59 92 125
TEMPERATURE (°C)
04109-0-040
VDD = 5V
VDD = 3V
Figure 15. Supply Current vs. Temperature
–20
0
20
40
60
80
100
120
RHEOSTAT MODE TEMPCO (ppm/°C)
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-041
RAB = 10k
VDD = 2.7V
TA = –40°C TO +85°C, –40°C TO +125°C
VDD = 5.5V
TA = –40°C TO +85°C, –40°C TO +125°C
Figure 16. Rheostat Mode Tempco ∆RWB/∆T vs. Code
AD5243/AD5248
Rev. 0 | Page 10 of 20
–30
–20
–10
0
10
20
POTENTIOMETER MODE TEMPCO (ppm/°C)
30
40
50
1289632 640 160 192 224 256
CODE (DECIMAL)
04109-0-042
RAB = 10k
VDD = 2.7V
TA = –40°C TO +85°C, –40°C TO +125°C
VDD = 5.5V
TA = –40°C TO +85°C, –40°C TO +125°C
Figure 17. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
10k 1M100k 10M
04109-0-043
0x80
0x40
0x20
0x10
0x08
0x04
0x010x02
Figure 18. Gain vs. Frequency vs. Code, RAB = 2.5 k
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04109-0-044
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 19. Gain vs. Frequency vs. Code, RAB = 10 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04109-0-045
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 20. Gain vs. Frequency vs. Code, RAB = 50 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04109-0-046
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 21. Gain vs. Frequency vs. Code, RAB = 100 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
10k1k 100k 1M 10M
04109-0-047
100k
60kHz 50k
120kHz 10k
570kHz
2.5k
2.2MHz
Figure 22. –3 dB Bandwidth @ Code = 0x80
AD5243/AD5248
Rev. 0 | Page 11 of 20
I
DD
, SUPPLY CURRENT (mA)
0.01
1
0.1
10
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIGITAL INPUT VOLTAGE (V)
04109-0-052
T
A
= 25°C
V
DD
= 2.7V
V
DD
= 5.5V
Figure 23. IDD vs. Input Voltage
04109-0-048
SCL
V
W
Figure 24. Digital Feedthrough
04109-0-049
V
W1
V
W2
Figure 25. Digital Crosstalk
04109-0-051
V
W1
V
W2
Figure 26. Analog Crosstalk
04109-0-053
V
W
Figure 27. Midscale Glitch, Code 0x80 to 0x7F
04109-0-050
SCL
V
W
Figure 28. Large Signal Settling Time
AD5243/AD5248
Rev. 0 | Page 12 of 20
TEST CIRCUITS
Figure 29 through Figure 35 illustrate the test circuits that define the test conditions used in the product specification tables.
04109-0-003
V
MS
AW
B
DUT
V+
V+ = V
DD
1LSB = V+/2
N
Figure 29. Test Circuit for Potentiometer Divider Nonlinearity Error
(INL, DNL)
04109-0-004
NO CONNECT
I
W
V
MS
AW
B
DUT
Figure 30. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
04109-0-005
V
MS2
V
MS1
V
W
AW
B
DUT
I
W
= V
DD
/R
NOMINAL
R
W
= [V
MS1
– V
MS2
]/I
W
Figure 31. Test Circuit for Wiper Resistance
04109-0-006
V
MS
%
DUT
( )
AW
B
V+ V
DD
%
V
MS
V
DD
V
DD
V
A
V
MS
V+ = V
DD
± 10%
PSRR (dB) = 20 LOG
PSS (%/%) =
Figure 32. Test Circuit for Power Supply Sensitivity(PSS, PSSR)
04109-0-009
+15V
–15V
W
A
2.5V
BV
OUT
OFFSET
GND
DUT
AD8610
V
IN
Figure 33. Test Circuit for Gain vs. Frequency
04109-0-010
W
B
V
SS
TO V
DD
DUT
I
SW
CODE = 0x00
R
SW
=0.1V
I
SW
0.1V
Figure 34. Test Circuit for Incremental On Resistance
W
BV
CM
I
CM
A
NC
GND
NC
V
DD
DUT
NC = NO CONNECT
04109-0-011
Figure 35. Test Circuit for Common-Mode Leakage Current
AD5243/AD5248
Rev. 0 | Page 13 of 20
THEORY OF OPERATION
The AD5243/AD5248 are 256-position digitally controlled
variable resistor (VR) devices.
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between Terminals A and
B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal
resistance (RAB) of the VR has 256 contact points accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings.
A
W
B
A
W
B
A
W
B
04109-0-012
Figure 36. Rheostat Mode Configuration
Assuming that a 10 kΩ part is used, the wiper’s first connection
starts at the B terminal for data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between Terminals W and B. The
second connection is the first tap point, which corresponds to
139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for data
0x01. The third connection is the next tap point, representing
178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
04109-0-013
Figure 37. AD5243 Equivalent RDAC Circuit
The general equation determining the digitally programmed
output resistance between W and B is
W
AB
WB RR
D
DR ×+×= 2
256
)( (1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB = 10 kΩ and the A terminal is open
circuited, the following output resistance RWB is set for the
indicated RDAC latch codes.
Table 7. Codes and Corresponding RWB Resistance
D (Dec) RWB (Ω) Output State
255 9,961 Full scale (RAB − 1 LSB + RW)
128 5,060 Midscale
1 139 1 LSB
0 100 Zero scale (wiper contact resistance)
Note that, in the zero-scale condition, a finite wiper resistance
of 100 Ω is present. Care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA . When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
ABWA RR
D
DR ×+×
=2
256
256
)( (2)
For RAB = 10 kΩ and the B terminal open circuited, the
following output resistance RWA is set for the indicated RDAC
latch codes.
Table 8. Codes and Corresponding RWA Resistance
D (Dec) RWA (Ω) Output State
255 139 Full scale
128 5,060 Midscale
1 9,961 1 LSB
0 10,060 Zero scale
AD5243/AD5248
Rev. 0 | Page 14 of 20
Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. Because the resistance element is
processed in thin film technology, the change in RAB with
temperature has a very low 35 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
V
I
W
B
V
O
04109-0-014
Figure 38. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the volt-
age applied across terminal AB divided by the 256 positions of
the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to terminals A and B is
B
A
WV
D
V
D
DV
256
256
256
)(
+= (3)
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
B
AB
WA
A
AB
WB
WV
R
DR
V
R
DR
DV )(
)(
)( += (4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation overtemperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, shown in Figure 39 and
Figure 40. This applies to the digital input pins SDA, SCL, AD0,
and AD1 (AD5248 only).
LOGIC
340
GND
04109-0-015
Figure 39. ESD Protection of Digital Pins
A, B, W
GND
04109-0-016
Figure 40. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5243/AD5248 VDD and GND power supply defines the
boundary conditions for proper 3-terminal digital potentiome-
ter operation. Supply signals present on Terminals A, B, and W
that exceed VDD or GND are clamped by the internal forward
biased diodes (see Figure 41).
GND
A
W
B
V
DD
04109-0-017
Figure 41. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminals A, B, and W (see Figure 41), it is important to
power VDD/GND before applying any voltage to Terminals A, B,
and W; otherwise, the diode is forward biased such that VDD is
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA, VB, and VW. The relative
order of powering VA, VB, VW, and the digital inputs is not
important as long as they are powered after VDD/GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disk or chip ceramic capacitors
of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electro-
lytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 42). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
AD5243/AD5248
Rev. 0 | Page 15 of 20
VDD
GND
VDD C3
10µFC1
0.1µF
AD5243
+
04109-0-018
Figure 42. Power Supply Bypassing
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
For users who desire nonvolatility but cannot justify the addi-
tional cost for the EEMEM, the AD5243/AD5248 may be
considered as low cost alternatives by maintaining a constant
bias to retain the wiper setting. The AD5243/AD5248 are
designed specifically with low power in mind, which allows low
power consumption even in battery-operated systems. The
graph in Figure 43 demonstrates the power consumption from a
3.4 V 450 mAhr Li-Ion cell phone battery, which is connected to
the AD5243/AD5248. The measurement over time shows that
the device draws approximately 1.3 µA and consumes negligible
power. Over a course of 30 days, the battery is depleted by less
than 2%, the majority of which is due to the intrinsic leakage
current of the battery itself.
DAYS
BATTERY LIFE DEPLETED
0
90%
92%
94%
96%
51015
98%
100%
102%
104%
106%
108%
110%
20 25 30
04109-0-019
T
A
= 25
°C
Figure 43. Battery Operating Life Depletion
This demonstrates that constantly biasing the potentiometer is
not an impractical approach. Most portable devices do not
require the removal of batteries for the purpose of charging.
Although the resistance setting of the AD5243/AD5248 is lost
when the battery needs replacement, such events occur rather
infrequently such that this inconvenience is justified by the
lower cost and smaller size offered by the AD5243/AD5248. If
and when total power is lost, the user should be provided with a
means to adjust the setting accordingly.
EVALUATION BOARD
An evaluation board, along with all necessary software, is avail-
able to program the AD5243/AD5248 from any PC running
Windows 98/2000/XP. The graphical user interface, as shown in
Figure 44, is straightforward and easy to use. More detailed
information is available in the user manual, which comes with
the board.
Figure 44. AD5243 Evaluation Board Software
The AD5243/AD5248 start at midscale upon power-up. To
increment or decrement the resistance, the user may simply
move the scrollbars on the left. To write any specific value, the
user should use the bit pattern in the upper screen and press the
Run button. The format of writing data to the device is shown
in Table 9. To read the data out from the device, the user can
simply press the Read button. The format of the read bits is
shown in Table 10.
AD5243/AD5248
Rev. 0 | Page 16 of 20
I2C INTERFACE
I2C COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 46). The
following byte is the slave address byte, which consists of
the slave address followed by an R/W bit (this bit deter-
mines whether data is read from or written to the slave
device). The AD5243 has a fixed slave address byte, while
the AD5248 has two configurable address bits AD0 and
AD1 (see Table 9).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master reads
from the slave device. On the other hand, if the R/W bit is
low, the master writes to the slave device.
2. In the write mode, the second byte is the instruction byte.
The first bit (MSB) of the instruction byte is the RDAC
subaddress select bit. A Logic Low selects Channel 1 and a
Logic High selects Channel 2.
The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 Ω in rheostat
mode or 0 V in potentiometer mode. It is important to note
that the shutdown operation does not disturb the contents
of the register. When brought out of shutdown, the previ-
ous setting is applied to the RDAC. Also, during shutdown,
new settings can be programmed. When the part is
returned from shutdown, the corresponding VR setting is
applied to the RDAC.
The remainder of the bits in the instruction byte are don’t
care bits (see Table 9).
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 46
and Figure 47).
3. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the write mode, eight data
bits are followed by an acknowledge bit). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 48 and Figure 49).
Note that the channel of interest is the one that is previ-
ously selected in the write mode. In the case where users
need to read the RDAC values of both channels, they need
to program the first channel in the write mode and then
change to the read mode to read the first channel value.
After that, they need to change back to the write mode with
the second channel selected and read the second channel
value in the read mode again. It is not necessary for users
to issue the Frame 3 data byte in the write mode for subse-
quent readback operation. Users should refer to Figure 48
and Figure 49 for the programming format.
4. After all data bits have been read or written, a STOP condi-
tion is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the tenth clock pulse to establish a STOP
condition (see Figure 46 and Figure 47). In read mode, the
master issues a no acknowledge for the ninth clock pulse
(that is, the SDA line remains high). The master then
brings the SDA line low before the tenth clock pulse, which
goes high to establish a STOP condition (see Figure 48 and
Figure 49).
A repeated write function gives the user flexibility to
update the RDAC output a number of times after
addressing and instructing the part only once. For example,
after the RDAC has acknowledged its slave address and
instruction bytes in the write mode, the RDAC output
updates on each successive byte. If different instructions
are needed, the write/read mode has to start again with a
new slave address, instruction, and data byte. Similarly, a
repeated read function of the RDAC is also allowed.
AD5243/AD5248
Rev. 0 | Page 17 of 20
Table 9. Write Mode
AD5243
S 0 1 0 1 1 1 1 W A A0 SD X X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Instruction Byte Data Byte
AD5248
S 0 1 0 1 1 AD1 AD0 W A A0 SD X X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Instruction Byte Data Byte
Table 10. Read Mode
AD5243
S 0 1 0 1 1 1 1 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
AD5248
S 0 1 0 1 1 AD1 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
LEGEND
S = Start condition.
P = Stop condition.
A = Acknowledge.
X = Don’t care.
W = Write.
AD0, AD1 = Package pin
programmable address bits.
R = Read.
A0 = RDAC subaddress select bit.
SD = Shutdown connects wiper to B terminal and
open circuits A terminal. It does not change contents
of wiper register.
D7, D6, D5, D4, D3, D2, D1, D0 = Data bits.
04109-0-021
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
PS S
SCL
SDA
P
Figure 45. I2C Interface Detailed Timing Diagram
04109-0-022
SCL
START BY
MASTER
SDA 01
1
FRAME 1
SLAVE ADDRESS BYTE
01111
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5243
R/W A0 SD X X X X
19
D7 D6 D5 D4 D3
ACK BY
AD5243 FRAME 3
DATA BYTE
19
X
STOP BY
MASTER
9
D2 D1 D0
ACK BY
AD5243
X
Figure 46. Writing to the RDAC Register—AD5243
AD5243/AD5248
Rev. 0 | Page 18 of 20
04109-0-023
SCL
START BY
MASTER
SDA 01
1
FRAME 1
SLAVE ADDRESS BYTE
0 1 1 AD1 AD0
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5248
R/W A0 SD X X X X
19
D7 D6 D5 D4 D3
ACK BY
AD5248 FRAME 3
DATA BYTE
19
X
STOP BY
MASTER
9
D2 D1 D0
ACK BY
AD5248
X
Figure 47. Writing to the RDAC Register—AD5248
04109-0-024
SCL
START BY
MASTER STOP BY
MASTER
SDA 01
1
FRAME 1
SLAVE ADDRESS BYTE
01111
FRAME 2
RDAC REGISTER
ACK BY
AD5243
R/W D7 D6 D4 D3 D2 D1 D0
19
NO ACK
BY MASTER
9
D5
Figure 48. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5243
04109-0-025
SCL
START BY
MASTER
SDA 01
1
FRAME 1
SLAVE ADDRESS BYTE
0 1 1 AD1 AD0
FRAME 2
RDAC REGISTER
ACK BY
AD5248
R/W D7 D6 D4 D3 D2 D1 D0
199
D5
STOP BY
MASTER
NO ACK
BY MASTER
Figure 49. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5248
Multiple Devices on One Bus (Applies Only to AD5248)
Figure 50 shows four AD5248 devices on the same serial bus.
Each has a different slave address, because the states of their
AD0 and AD1 pins are different. This allows each device on the
bus to be written to or read from independently. The master
device output bus line drivers are open-drain pull-downs in a
fully I2C compatible interface.
SDA
SDA
AD1
AD0
MASTER
SCL
SCL
AD5248
SDA
AD1
AD0
SCL
AD5248
SDA
AD1
AD0
SCL
AD5248
SDA
5V
R
P
R
P
5V
5V
5V
AD1
AD0
SCL
AD5248
04109-0-026
Figure 50. Multiple AD5248 Devices on One I2C Bus
AD5243/AD5248
Rev. 0 | Page 19 of 20
OUTLINE DIMENSIONS
0.23
0.08
0.80
0.60
0.40
0.15
0.00 0.27
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10 6
5
1
0.50 BSC
3.00 BSC
3.00 BSC
4.90 BSC
PIN 1
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 51. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model RAB Temperature Package Description Package Option Branding
AD5243BRM2.5 2.5 kΩ −40°C to +125°C MSOP-10 RM-10 D0L
AD5243BRM2.5-RL7 2.5 kΩ −40°C to +125°C MSOP-10 RM-10 D0L
AD5243BRM10 10 kΩ −40°C to +125°C MSOP-10 RM-10 D0M
AD5243BRM10-RL7 10 kΩ −40°C to +125°C MSOP-10 RM-10 D0M
AD5243BRM50 50 kΩ −40°C to +125°C MSOP-10 RM-10 D0N
AD5243BRM50-RL7 50 kΩ −40°C to +125°C MSOP-10 RM-10 D0N
AD5243BRM100 100 kΩ −40°C to +125°C MSOP-10 RM-10 D0P
AD5243BRM100-RL7 100 kΩ −40°C to +125°C MSOP-10 RM-10 D0P
AD5243EVAL See Note 1 Evaluation Board
AD5248BRM2.5 2.5 kΩ −40°C to +125°C MSOP-10 RM-10 D1F
AD5248BRM2.5-RL7 2.5 kΩ −40°C to +125°C MSOP-10 RM-10 D1F
AD5248BRM10 10 kΩ −40°C to +125°C MSOP-10 RM-10 D1G
AD5248BRM10-RL7 10 kΩ −40°C to +125°C MSOP-10 RM-10 D1G
AD5248BRM50 50 kΩ −40°C to +125°C MSOP-10 RM-10 D1H
AD5248BRM50-RL7 50 kΩ −40°C to +125°C MSOP-10 RM-10 D1H
AD5248BRM100 100 kΩ −40°C to +125°C MSOP-10 RM-10 D1J
AD5248BRM100-RL7 100 kΩ −40°C to +125°C MSOP-10 RM-10 D1J
AD5248EVAL See Note 1 Evaluation Board
1The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
AD5243/AD5248
Rev. 0 | Page 20 of 20
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04109–0–1/04(0)