ARM7TDMI Cores - Atmel Corporation

INTEGRATION

SYSTEM LEVEL

ARM7TDMI

ICROCONTROLLER

ORE

YSTEM

Up to 63 MIPS at 90

MHz on 0.18-micron

CMOS technology

The industry-leading ARM7TDMI 16/32-bit

RISC core features:

High performance: code pipeline,

bit instruction/data bus

Very low power consumption: an

industry leader in MIPS/Watt

High code density: 16-bit Thumb®

code reduces program memory

requirement

Fast interrupt handling: banked

registers, FIQ and IRQ lines

Ease of debug: on-chip JTAG and in-

circuit emulator (ICE)

Comprehensive software development

tools: C and C++ compilers, debuggers

and emulators for parallel hardware/

software development.

Atmel’s wide range of ARM7TDMI bus-

compatible memory blocks and qualified

peripherals includes:

Memories customized to the precise

size and word width for the design

Enhanced real-time performance:

Advanced Interrupt Controller and

Peripheral Data Controller (DMA)

Wide range of peripherals: USART,

Timer/Counter, Real-time Clock, DES,

Triple DES, SPI, Watchdog Timer, plus

USB, CAN and Ethernet interfaces

Reduced pin count: Parallel I/O

controller

Custom analog: industry-leading

ADCs, DACs, CODECs, PLLs and

Oscillators.

These blocks are provided in Verilog for high-level system integration. They can be

combined with IP blocks developed by the customer.

Advanced

Interrupt Controller

Timer/Counter

Real-time Clock

Customer IP

Watchdog Timer

ARM7TDMI Bus

Interface

Bus Arbiter/

Master Signals Manager

Other MCU

Embedded Cores

ARM Memory Controller

Parallel I/O

Custom Analog:

ADC, DAC, CODEC

Peripheral

Data Controller

Serial

Peripheral

Interface

AMBA Bridge

(Atmel Enhancement)

Flash/ROM

Program

ARM7TDMI

Test I/O

External

MCUs

External

Interrupts

Timer/Counter

I/O

Real Time

Clock Interrupt

Customer

I/O

DSP

I/O

Watchdog

Overflow

MOSI/

MISO

Tx/Rx

External

Memories

Blocks

customized by Atmel

SRAM

Workspace

EEPROM

Data

ARM7TDMI

Core

Embedded

ICE Cache

RAM

ASB

APB

DPRAM

FIFO

DSP

Core

Analog I/O

Parallel I/O

USART

Atmel, the Atmel logo and any

combinations thereof are registered

trademarks of Atmel Corporation. ARM,

Thumb and the ARM logo are registered

trademarks of ARM Ltd. ARM7TDMI is a

trademark of ARM Ltd. HSDT200 is a

trademark of SIDSA. Other terms and

product names may be trademarks of

others.

All figures in this brochure are

for illustrative purposes only.

See Atmel data books for definitive

figures and for applicable limitations and

warranties.

0747D-07/00/12M

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E-mail

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Web Site

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SLI ARM7TDMI EMBEDDED MICROCONTROLLER CORE SYSTEM

Building a complete system around an embedded ARM7TDMI microcontroller core

couples the performance of a customized architecture with the flexibility of a

programmable device. Atmel’s experience of ARM-based standard products and

use of pre-qualified building blocks reduces design time and risk. Our design

emulator allows hardware and software development to proceed in parallel and the

hardware/software interface to be debugged before committing the device to

silicon.

Flash/ROM Program Memory

Atmel applies its leadership in

Flash memory technology to system

level integration. The benefits are the

ability to load software late in the

design cycle, and in-system software

upgrades if required.

With Flash, the time and expense

of a ROM mask cycle is eliminated,

although a masked ROM option is

available for mature products.

EEPROM Data Memory

EEPROM data memory combines the

benefits of nonvolatile memory with the

convenience of word-by-word or page-by-

page update.

SRAM Cache/Workspace

On-chip SRAM for cache memory and

workspace enables the MCU core to

operate at maximum speed. Also, the

ARM Memory Controller provides access

to off-chip memories with minimal delay.

DPRAM FIFO with On-chip DSP Core

Data transfer to/from an on-chip DSP

core is optimized by a DPRAM FIFO

acting as a postbox. The DSP core can be

clocked independently to the MCU core.

Bus Arbiter/Master Signals Manager

An open, multi-MCU architecture for

higher performance is possible thanks to

the Bus Arbiter/Master Signals Manager.

Peripheral Data Controller (DMA)

System performance is considerably

enhanced by using the PDC to transfer

data directly between serial peripherals

and memory, bypassing the MCU.

Advanced Interrupt Controller

The AIC improves the real-time

performance of the system by reducing

the time taken to reach an interrupt to a

single instruction cycle.

USART

The fully programmable two-channel

USART can be configured for any

application scenario.

Serial Peripheral Interface

The SPI provides serial

communication with a wide range of

external devices in master or slave mode.

Timer/Counter

The Timer/Counter provides such

enhanced functions as frequency or

interval measurement, event counting,

pulse generation, delay timing and pulse

width modulation.

Real-time Clock

The two-century RTC provides date,

time and alarm functions and features an

advanced power saving mode.

Watchdog Timer

The Watchdog Timer provides security

against system lockup if the MCU

becomes trapped in an endless loop.

DES/Triple DES Generator

For security applications the DES and

Triple DES blocks provide data encryption

to the recognized standards.

Parallel I/O Controller

The programmable PIO controller

reduces device pin count by multiplexing

peripheral I/Os with a set of general input/

output signals.

Custom Analog

Atmel can apply its leadership in

analog cell design to customize one of its

many qualified analog blocks to the

precise requirements of the application.

Alternatively we can develop a completely

new analog cell if required.

Customer IP

Many of our customers are experts in

their field of application, and have

developed proprietary IP blocks

embodying this expertise. Atmel has

already incorporated a number of such

blocks into market-leading products. We

can do the same for you.

The HSDT200 ARM-based ASIC Emulation Board

Right-first-time Silicon

Atmel’s experience, rich library of IP blocks and advanced design flow are

aimed at producing right-first-time silicon at minimal risk and in the shortest

possible design cycle time.