S34ML01G1
S34ML02G1
S34ML04G1
for Embedded
Distinctive Characteristics
■Density
❐1 Gb/ 2 Gb / 4 Gb
■Architecture
❐Input / Output Bus Width: 8-bits / 16-bits
❐Page size:
• x8 = 2112 (2048 + 64) bytes; 64 bytes is spare area
• x16 = 1056 (1024 + 32) words; 32 words is spare area
❐Block size: 64 Pages
• x8 = 128 KB + 4 KB
• x16 = 64k + 2k words
❐Plane size:
•1
Gb / 2 Gb: 1024 Blocks per Plane
x8 = 128 MB + 4 MB
x16 = 64M + 2M words
•4
Gb: 2048 Blocks per Plane
x8 = 256 MB+ 8 MB
x16 = 128M + 4M words
❐Device size:
•1
Gb: 1 Plane per Device or 128 MB
•2
Gb: 2 Planes per Device or 256 MB
•4
Gb: 2 Planes per Device or 512 MB
■NAND flash interface
❐Open NAND Flash Interface (ONFI) 1.0 compliant
❐Address, Data and Commands multiplexed
■Supply voltage
❐3.3-V device: Vcc = 2.7 V ~ 3.6 V
■Security
❐One Time Programmable (OTP) area
❐Hardware program/erase disabled during power transition
■Additional features
❐2 Gb and 4 Gb parts support Multiplane Program and Erase
commands
❐Supports Copy Back Program
❐2 Gb and 4 Gb parts support Multiplane Copy Back Program
❐Supports Read Cache
■Electronic signature
❐Manufacturer ID: 01h
■Operating temperature
❐Industrial: -40 °C to 85 °C
❐Automotive: -40 °C to 105 °C
Performance
■Page Read / Program
❐Random access: 25 µs (Max)
❐Sequential access: 25 ns (Min)
❐Program time / Multiplane Program time: 200 µs (Typ)
■Block Erase (S34ML01G1)
❐Block Erase time: 2.0 ms (Typ)
■Block Erase / Multiplane Erase (S34ML02G1, S34ML04G1)
❐Block Erase time: 3.5 ms (Typ)
■Reliability
❐100,000 Program / Erase cycles (Typ)
(with 1 bit ECC per 528 bytes (x8) or 264 words (x16))
❐10 Year Data retention (Typ)
❐For one plane structure (1-Gb density)
• Block zero is valid and will be valid for at least 1,000
program-erase cycles with ECC
❐For two plane structures (2-Gb and 4-Gb densities)
• Blocks zero and one are valid and will be valid for at least
1,000 program-erase cycles with ECC
■Package options
❐Lead Free and Low Halogen
❐48-Pin TSOP 12 20 1.2 mm
❐63-Ball BGA 9 11 1 mm
1Gb, 2 Gb, 4 Gb, 3 V, 1-bit ECC, SLC NAND
Flash Memory for Embedded
SkyHigh Memory Limited
Document Number: 002-00676 Rev. *W
Suite 4401-02, 44/F One Island East,
18 Westlands Road Hong Kong
www.skyhighmemory.com
Revised May 03, 2019
S34ML01G1
S34ML02G1
S34ML04G1
Contents
1. General Description..................................................... 4
1.1 Logic Diagram................................................................ 5
1.2 Connection Diagram ...................................................... 6
1.3 Pin Description............................................................... 7
1.4 Block Diagram................................................................ 8
1.5 Array Organization......................................................... 9
1.6 Addressing ................................................................... 10
1.7 Mode Selection ............................................................ 12
2. Bus Operation ............................................................ 13
2.1 Command Input ........................................................... 13
2.2 Address Input............................................................... 13
2.3 Data Input .................................................................... 13
2.4 Data Output.................................................................. 13
2.5 Write Protect ................................................................ 13
2.6 Standby........................................................................ 13
3. Command Set............................................................. 14
3.1 Page Read ................................................................... 15
3.2 Page Program.............................................................. 15
Multiplane Program3.3
— S34ML02G1 and S34ML04G1................................ 16
Page Reprogram3.4
— S34ML02G1 and S34ML04G1................................ 16
3.5 Block Erase.................................................................. 18
Multiplane Block Erase3.6
— S34ML02G1 and S34ML04G1................................ 18
3.7 Copy Back Program..................................................... 18
3.8 EDC Operation — S34ML02G1 and S34ML04G1....... 19
3.9 Read Status Register................................................... 21
3.10 Read Status Enhanced
— S34ML02G1 and S34ML04G1................................ 22
3.11 Read Status Register Field Definition .......................... 22
3.12 Reset............................................................................ 22
3.13 Read Cache ................................................................. 23
3.14 Cache Program............................................................ 24
3.15 Multiplane Cache Program
— S34ML02G1 and S34ML04G1................................ 25
3.16 Read ID........................................................................ 26
3.17 Read ID2...................................................................... 29
3.18 Read ONFI Signature .................................................. 29
3.19 Read Parameter Page ................................................. 29
3.20 One-Time Programmable (OTP) Entry ........................ 31
Signal Descriptions4. ................................................... 32
Data Protection and Power On / Off Sequence ........... 324.1
Ready/Busy..................................................4.2 ................ 32
Write Protect Operation .4.3 .............................................. 33
Electrical Characteristics5. .......................................... 34
5.1 Valid Blocks ................................................................. 34
5.2 Absolute Maximum Ratings ......................................... 34
5.3 Recommended Operating Conditions.......................... 34
5.4 AC Test Conditions...................................................... 34
5.5 AC Characteristics ....................................................... 35
5.6 DC Characteristics....................................................... 36
5.7 Pin Capacitance........................................................... 36
Thermal Resistance..........................................5.8 ............ 37
Program / Erase Characteri5.9 stics................................... 37
Timing Diagrams6. ......................................................... 38
6.1 Command Latch Cycle.................................................. 38
6.2 Address Latch Cycle..................................................... 38
6.3 Data Input Cycle Timing................................................ 39
Data Output Cycle Timing6.4
(CLE=L, WE#=H, ALE=L, WP#=H)............................... 39
Data Output Cycle Timing6.5
(EDO Type, CLE=L, WE#=H, ALE=L) .......................... 40
6.6 Page Read Operation ................................................... 40
6.7 Page Read Operation (Interrupted by CE#).................. 41
6.8 Page Read Operation Timing with CE# Don’t Care...... 41
6.9 Page Program Operation.............................................. 42
6.10 Page Program Operation Timing
with CE# Don’t Care ..................................................... 42
6.11 Page Program Operation with Random Data Input ...... 43
6.12 Random Data Output In a Page ................................... 43
6.13 Multiplane Page Program Operation
— S34ML02G1 and S34ML04G1................................. 44
6.14 Block Erase Operation.................................................. 45
6.15 Multiplane Block Erase
— S34ML02G1 and S34ML04G1................................. 45
6.16 Copy Back Read with Optional Data Readout.............. 46
6.17 Copy Back Program Operation
With Random Data Input............................................... 46
6.18 Multiplane Copy Back Program
— S34ML02G1 and S34ML04G1................................. 47
6.19 Read Status Register Timing ........................................ 48
6.20 Read Status Enhanced Timing ..................................... 48
6.21 Reset Operation Timing................................................ 48
6.22 Read Cache.................................................................. 49
6.23 Cache Program............................................................. 50
6.24 Multiplane Cache Program
— S34ML02G1 and S34ML04G1................................. 51
6.25 Read ID Operation Timing ............................................ 53
6.26 Read ID2 Operation Timing .......................................... 53
6.27 Read ONFI Signature Timing........................................ 54
6.28 Read Parameter Page Timing ...................................... 54
6.29 OTP Entry Timing ......................................................... 54
6.30 Power On and Data Protection Timing ......................... 55
6.31 WP# Handling............................................................... 55
Physical Interface7. ....................................................... 56
Physical Diagram............................................7.1 .............. 56
System Interface8. ......................................................... 58
Error Management9. ...................................................... 59
System Bad Block Replacement................................9.1 ... 59
Bad Block Management........9.2 ........................................ 60
Ordering Information10. .................................................. 61
Document History Page11. ............................................. 62
Document Number: 002-00676 Rev. *W
Page 2 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Sales, Solutions, and Legal Information .......................... 71
Worldwide Sales and Design Support ........................... 71
Products ........................................................................ 71
PSoC® Solutions ........................................................... 71
Cypress Developer Community ..................................... 71
Technical Support ......................................................... 71
Document Number: 002-00676 Rev. *W
Page 3 of 70
S34ML01G1
S34ML02G1
S34ML04G1
1. General Description
The Cypress S34ML01G1, S34ML02G1, and S34ML04G1 series is offered with a 3.3-V VCC power supply, and with ×8 or ×16 I/O
interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into
blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for ×8 is
(2048 + 64 spare) bytes; for ×16 (1024 + 32) words.
Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of
NAND flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the NAND flash memory device
by a microcontroller, since the CE# transitions do not stop the read operation.
The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load
the data in a cache register while the previous data is transferred to the I/O buffers to be read.
Like all other 2-kB page NAND flash devices, a program operation typically writes 2112 bytes (×8), or 1056 words (×16) in 200 µs
and an erase operation can typically be performed in 2 ms (S34ML01G1) on a 128-kB block (×8) or 64-kword block (×16). In
addition, thanks to multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a
time (again, one per plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by
50%.
In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as the ports for command
and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of the footprint.
Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins.
The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse repetition, where required,
and internal verification and margining of data. A WP# pin is available to provide hardware protection against program and erase
operations.
The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read
controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a
single pull-up resistor. In a system with multiple memories the
R/B# pins can be connected all together to provide a global status signal.
The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data
can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.
The Copy Back operation automatically executes embedded error detection operation: 1-bit error out of every 528 bytes (×8) or 256
words (×16) can be detected. With this feature it is no longer necessary to use an external mechanism to detect Copy Back
operation errors.
Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed.
In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by programing data
using the cache register.
The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page Reprogram re-programs
one page. Normally, this operation is performed after a failed Page Program operation. Similarly, the Multiplane Page Reprogram
re-programs two pages in parallel, one per plane. The first page must be in the first plane while the second page must be in the
second plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The Page
Reprogram and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted during
re-program operations.
Note: The S34ML01G1 device does not support EDC.
Document Number: 002-00676 Rev. *W
Page 4 of 70
S34ML01G1
S34ML02G1
S34ML04G1
The devices come with an OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be
stored permanently. This security feature is subject to an NDA (non-disclosure agreement) and is, therefore, not described in the
data sheet. For more details, contact your nearest Cypress sales office.
Logic Diagram1.1
Figure 1. Logic Diagram
Table 1. Product List
Device Density (bits) Number of Planes Number of Blocks
per Plane EDC Support
Main Spare
S34ML01G1 128M x 8
64M x 16
4M x 8
2M x 16 No10241
S34ML02G1 256M x 8
128M x 16
8M x 8
4M x 16 Yes10242
S34ML04G1 512M x 8
256M x 16
16M x 8
8M x 16 Yes20482
Table 2. Signal Names
Signal Description
I/O7 - I/O0 (×8) Data Input / Outputs
I/O8 - I/O15 (×16)
Command Latch EnableCLE
Address Latch EnableALE
Chip EnableCE#
Read EnableRE#
Write EnableWE#
Write ProtectWP#
Read/BusyR/B#
Power SupplyVCC
GroundVSS
Not ConnectedNC
VCC
VSS
WP#
CLE
ALE
RE#
WE#
CE# I/O0~I/O7
R/B#
Document Number: 002-00676 Rev. *W
Page 5 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Connection Diagram1.2
Figure 2. 48-Pin TSOP1 Contact ×8, ×16 Devices
Note
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Figure 3. 63-BGA Contact, ×8 Device (Balls Down, Top View)
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
[1]
[1]
[1]
[1]
F8F7F6F5F4F3
E8E7E6E5E4E3
D8D7D6D5D4D3
C8C7C6C5C4C3
RB#WE#CE#VSSALEWP#
NCNCNCCLERE#VCC (1)
NCNCNCNCNCNC
G8G7G6G5G4G3
NCVSS (1)NCNCNCNC
H8H7H6H5H4H3
Vcc
NCNCNCI/O0NC
B9
A9
NC
NC
A2
NC
NCNCNCNCVCC (1)NC
B10
A10
NC
NC
B1
A1
NC
NC
J8J7J6J5J4J3
I/O7I/O5VCC
NCI/O1NC
K8K7K6K5K4K3
VSS
I/O6I/O4I/O3I/O2VSS
L9
NC
L2
NC
L10
NC
L1
NC
M9
NC
M2
NC
M10
NC
M1
NC
Document Number: 002-00676 Rev. *W
Page 6 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Figure 4. 63-BGA Contact, ×16 Device (Balls Down, Top View)
Pin Description1.3
Notes
2. A 0.1 µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during program and erase operations.
3. An internal voltage detector disables all functions whenever VCC is below 1.8V to protect the device from any involuntary program/erase during power transitions.
Table 3. Pin Description
Pin Name Description
I/O0 - I/O7 (×8) Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The I/O pins float
to High-Z when the device is deselected or the outputs are disabled.
I/O8 - I/O15 (×16)
CLE Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the rising
edge of Write Enable (WE#).
ALE Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising edge
of Write Enable (WE#).
CE# Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the memory.
WE# Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#.
RE# Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE# which also increments the internal column address counter by one.
WP# Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification (program /
erase).
R/B# Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC Supply Voltage. The VCC supplies the power for all the operations (Read, Program, Erase). An internal lock circuit
prevents the insertion of Commands when VCC is less than VLKO.
VSS Ground.
NC Not Connected.
F8F7F6F5F4F3
E8E7E6E5E4E3
D8D7D6D5D4D3
C8C7C6C5C4C3
RB#WE#CE#VSSALEWP#
NCNCNCCLERE#VCC
NCNCNCNCNCNC
G8G7G6G5G4G3
NCVSSNCNCNCNC
H8H7H6H5H4H3
Vcc
I/O14I/O12I/O10I/O0I/O8
B9
A9
NC
NC
A2
NC
NCI/O15I/O13NCVCCNC
B10
A10
NC
NC
B1
A1
NC
NC
J8J7J6J5J4J3
I/O7I/O5VCC
I/O11I/O1I/O9
K8K7K6K5K4K3
VSS
I/O6I/O4I/O3I/O2VSS
L9
NC
L2
NC
L10
NC
L1
NC
M9
NC
M2
NC
M10
NC
M1
NC
Document Number: 002-00676 Rev. *W
Page 7 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Block Diagram1.4
Figure 5. Functional Block Diagram
Address
Register/
Counter
Controller
Command
Interface
Logic
Command
Register
Data
Register
RE#
I/O Buffer
Y Decoder
PAGE Buffer
X
D
E
C
O
D
E
R
NAND Flash
Memory Array
WP#
CE#
WE#
CLE
ALE
I/O0~I/O7 (x8)
I/O0~I/O15 (x16)
1024 Mbit + 32 Mbit (1 Gb Device)
Program Erase
HV Generation
2048 Mbit + 64 Mbit (2 Gb Device)
4096 Mbit + 128 Mbit (4 Gb Device)
Document Number: 002-00676 Rev. *W
Page 8 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Array Organization1.5
Figure 6. Array Organization — ×8
Figure 7. Array Organization — ×16
Plane(s)
64 bytes2048 bytes
I/O
[7:0]
1 Page = (2k + 64) bytes
1 Block = (2k + 64) bytes x 64 pages
= (128k + 4k) bytes
1 Plane = (128k + 4k) bytes x 1024 Blocks
Page Buffer
1024
Blocks
per
Plane
1022
1023
1
0
2
Array Organization (x8)
For 1 Gb and 2 Gb devices there are 1024 Blocks per Plane
For 4 Gb device there are 2048 Blocks per Plane
Note:
2 Gb and 4 Gb devices have two Planes
Plane(s)
1024 words
I/O0~I/O15
1 Page = (1k + 32) words
1 Block = (1k + 32) words x 64 pages
= (64k + 2k) words
1 Plane = (64k + 2k) words x 1024 Blocks
Page Buffer
1024
Blocks
per
Plane
1022
1023
1
0
2
Array Organization (x16)
For 1 Gb and 2 Gb devices there are 1024 Blocks per Plane
For 4 Gb device there are 2048 Blocks per Plane
Note:
2 Gb and 4 Gb devices have two Planes
32 words
Document Number: 002-00676 Rev. *W
Page 9 of 70
S34ML01G1
S34ML02G1
S34ML04G1
1.6 Addressing
1.6.1 S34ML01G1
Notes
4. CAx = Column Address bit.
5. PAx = Page Address bit.
6. BAx = Block Address bit.
7. Block address concatenated with page address = actual page address, also known as the row address.
8. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the ×8 address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18 - A27: block address
For the ×16 address bits, the following rules apply:
A0 - A10: column address in the page
A11 - A16: page address in the block
A17 - A26: block address
1.6.2 S34ML02G1
Table 4. Address Cycle Map — 1 Gb Device
Bus Cycle I/O [15:8] [8] I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
×8
— A5 (CA4 (CA4)A3 (CA3)A2 (CA2)A1 (CA1)A0 (CA0)1st / Col. Add. 1 A7 (CA7)A6 (CA6)A5)
LowLowLow— A11 (CA11)A10 (CA10)A9 (CA9)A8 (CA8)2nd / Col. Add. 2 Low
— AA16 (PA4)A15 (PA3)A14 (PA2)A13 (PA1)A12 (PA0)3rd / Row Add. 1 A19 (BA1)A18 (BA0)17 (PA5)
— AA24 (BA6)A23 (BA5)A22 (BA4)A21 (BA3)A20 (BA2)4th / Row Add. 2 A27 (BA9)A26 (BA8)25 (BA7)
×16
A5A4 (CA4)A3 (CA3)A2 (CA2)A1 (CA1)A0 (CA0)Low1st / Col. Add. 1 A7 (CA7)A6 (CA6)(CA5)
LowLowLowLowLowA10 (CA10)A9 (CA9)A8 (CA8)Low2nd / Col. Add. 2
A15 (PA4A14 (PA3)A13 (PA2)A12 (PA1)A11 (PA0)Low3rd / Row Add. 1 A18 (BA1)A17 (BA0)A16 (PA5))
A23 (BA6A22 (BA5)A21 (BA4)A20 (BA3)A19 (BA2)Low4th / Row Add. 2 A26 (BA9)A25 (BA8)A24 (BA7))
Table 5. Address Cycle Map — 2 Gb Device
Bus Cycle I/O [15:8] [14] I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
×8
— A5 (CA4 (CA4)A3 (CA3)A2 (CA2)A1 (CA1)A0 (CA0)1st / Col. Add. 1 A7 (CA7)A6 (CA6)A5)
LowLowLow— A11 (CA11)A10 (CA10)A9 (CA9)A8 (CA8)2nd / Col. Add. 2 Low
— AA16 (PA4)A15 (PA3)A14 (PA2)A13 (PA1)A12 (PA0)3rd / Row Add. 1 A19 (BA0)A18 (PLA0)17 (PA5)
— AA24 (BA5)A23 (BA4)A22 (BA3)A21 (BA2)A20 (BA1)4th / Row Add. 2 A27 (BA8)A26 (BA7)25 (BA6)
LowLowLowLowLowLowLow— A28 (BA9)5th / Row Add. 3
×16
A5A4 (CA4)A3 (CA3)A2 (CA2)A1 (CA1)A0 (CA0)Low1st / Col. Add. 1 A7 (CA7)A6 (CA6)(CA5)
LowLowLowLowLowA10 (CA10)A9 (CA9)A8 (CA8)Low2nd / Col. Add. 2
A15 (PA4A14 (PA3)A13 (PA2)A12 (PA1)A11 (PA0)Low3rd / Row Add. 1 A18 (BA0)A17 (PLA0)A16 (PA5))
A23 (BA5A22 (BA4)A21 (BA3)A20 (BA2)A19 (BA1)Low4th / Row Add. 2 A26 (BA8)A25 (BA7)A24 (BA6))
LowLowLowLowLowLowLowA27 (BA9)Low5th / Row Add. 3
Document Number: 002-00676 Rev. *W
Page 10 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Notes
9. CAx = Column Address bit.
10. PAx = Page Address bit.
11. PLA0 = Plane Address bit zero.
12. BAx = Block Address bit.
13. Block address concatenated with page address and plane address = actual page address, also known as the row address.
14. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the ×8 address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A28: block address
For the ×16 address bits, the following rules apply:
A0 - A10: column address in the page
A11 - A16: page address in the block
A17: plane address (for multiplane operations) / block address (for normal operations)
A18 - A27: block address
1.6.3 S34ML04G1
Notes
15. CAx = Column Address bit.
16. PAx = Page Address bit.
17. PLA0 = Plane Address bit zero.
18. BAx = Block Address bit.
19. Block address concatenated with page address and plane address = actual page address, also known as the row address.
20. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the ×8 address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A29: block address
Table 6. Address Cycle Map — 4 Gb Device
Bus Cycle I/O [15:8] [20] I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
×8
— A5 (CA4 (CA4)A3 (CA3)A2 (CA2)A1 (CA1)A0 (CA0)1st / Col. Add. 1 A7 (CA7)A6 (CA6)A5)
LowLowLow— A11 (CA11)A10 (CA10)A9 (CA9)A8 (CA8)2nd / Col. Add. 2 Low
— AA16 (PA4)A15 (PA3)A14 (PA2)A13 (PA1)A12 (PA0)3rd / Row Add. 1 A19 (BA0)A18 (PLA0)17 (PA5)
— AA24 (BA5)A23 (BA4)A22 (BA3)A21 (BA2)A20 (BA1)4th / Row Add. 2 A27 (BA8)A26 (BA7)25 (BA6)
LowLowLowLowLowLow— A29 (BA10)A28 (BA9)5th / Row Add. 3
×16
A5A4 (CA4)A3 (CA3)A2 (CA2)A1 (CA1)A0 (CA0)Low1st / Col. Add. 1 A7 (CA7)A6 (CA6)(CA5)
LowLowLowLowLowA10 (CA10)A9 (CA9)A8 (CA8)Low2nd / Col. Add. 2
A15 (PA4A14 (PA3)A13 (PA2)A12 (PA1)A11 (PA0)Low3rd / Row Add. 1 A18 (BA0)A17 (PLA0)A16 (PA5))
A23 (BA5A22 (BA4)A21 (BA3)A20 (BA2)A19 (BA1)Low4th / Row Add. 2 A26 (BA8)A25 (BA7)A24 (BA6))
LowLowLowLowLowLowA28 (BA10)A27 (BA9)Low5th / Row Add. 3
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S34ML02G1
S34ML04G1
For the ×16 address bits, the following rules apply:
A0 - A10: column address in the page
A11 - A16: page address in the block
A17: plane address (for multiplane operations) / block address (for normal operations)
A18 - A28: block address
1.7 Mode Selection
Notes
21. X can be VIL or VIH. High= Logic level high. Low = Logic level low.
22. WP# should be biased to CMOS high or CMOS low for stand-by mode.
23. During Busy Time in Read, RE# must be held high to prevent unintended data out.
Table 7. Mode Selection
Mode CLE ALE CE# WE# RE# WP#
Read Mode XHighRisingLowLowHighCommand Input
XHighRisingLowHighLowAddress Input
Program or Erase Mode HighHighRisingLowLowHighCommand Input
HighHighRisingLowHighLowAddress Input
HighHighRisingLowLowLowData Input
XFallingHighLowLowLowData Output (on going)
XHighHighXXXData Output (suspended)
HighHighXXXBusy Time in Read [23] X
HighXXXXXBusy Time in Program
HighXXXXXBusy Time in Erase
LowXXXXXWrite Protect
0V / VXXHighXXStand By CC [22]
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S34ML04G1
2. Bus Operation
There are six standard bus operations that control the device: Command Input, Address Input, Data Input, Data Output, Write
Protect, and Standby. (See Table 7.)
Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory and do not affect bus
operations.
2.1 Command Input
The Command Input bus operation is used to give a command to the memory device. Commands are accepted with Chip Enable
low, Command Latch Enable high, Address Latch Enable low, and Read Enable high and latched on the rising edge of Write Enable.
Moreover, for commands that start a modify operation (program/erase) the Write Protect pin must be high. See Figure 12
on page 38 and Table 20 on page 35 for details of the timing requirements. Command codes are always applied on I/O7:0
regardless of the bus configuration (×8 or ×16).
2.2 Address Input
The Address Input bus operation allows the insertion of the memory address. For the S34ML02G1 and S34ML04G1 devices, five
write cycles are needed to input the addresses. For the S34ML01G1, four write cycles are needed to input the addresses. If
necessary, a 5th dummy address cycle can be issued to S34ML01G1, which will be ignored by the NAND device without causing
problems. Addresses are accepted with Chip Enable low, Address Latch Enable high, Command Latch Enable low, and Read
Enable high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/erase)
the Write Protect pin must be high. See Figure 13 on page 38 and Table 20 on page 35 for details of the timing requirements.
Addresses are always applied on I/O7:0 regardless of the bus configuration (×8 or ×16). Refer to Table 4 through Table 6
on page 11 for more detailed information.
2.3 Data Input
The Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is serial and timed by
the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read
Enable high, and Write Protect high and latched on the rising edge of Write Enable. See Figure 14 on page 39 and Table 20
on page 35 for details of the timing requirements.
2.4 Data Output
The Data Output bus operation allows data to be read from the memory array and to check the Status Register content, the EDC
register content, and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable low, Write
Enable high, Address Latch Enable low, and Command Latch Enable low. See Figure 15 on page 39 and Table 20 on page 35 for
details of the timings requirements.
2.5 Write Protect
The Hardware Write Protection is activated when the Write Protect pin is low. In this condition, modify operations do not start and the
content of the memory is not altered. The Write Protect pin is not latched by Write Enable to ensure the protection even during power
up.
2.6 Standby
In Standby, the device is deselected, outputs are disabled, and power consumption is reduced.
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S34ML04G1
3. Command Set
Table 8. Command Set
Command 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle
Acceptable
Command
during Busy
Supported on
S34ML01G1
Page Read YesNo30h00h
Page Program YesNo10h80h
YesNo85hRandom Data Input
YesNoE0h05hRandom Data Output
Multiplane Program NoNo10h81h11h80h
NoNo10h80h11h80hONFI Multiplane Program
Page Reprogram NoNo10h8Bh
Multiplane Page Reprogram NoNo10h8Bh11h8Bh
Block Erase YesNoD0h60h
Multiplane Block Erase NoNoD0h60h60h
NoNoD0h60hD1h60hONFI Multiplane Block Erase
Copy Back Read YesNo35h00h
Copy Back Program YesNo10h85h
Multiplane Copy Back Program NoNo10h81h11h85h
NoNo10h85h11h85hONFI Multiplane Copy Back Program
Special Read For Copy Back NoNo36h00h
Read EDC Status Register NoYes7Bh
Read Status Register YesYes70h
Read Status Enhanced NoYes78h
Reset YesYesFFh
Read Cache YesNo31h
Read Cache Enhanced NoNo31h00h
Read Cache End YesNo3Fh
Cache Program (End) YesNo10h80h
Cache Program (Start) / (Continue) YesNo15h80h
Multiplane Cache Program (Start/Continue) NoNo15h81h11h80h
ONFI Multiplane Cache Program
(Start/Continue) NoNo15h80h11h80h
Multiplane Cache Program (End) NoNo10h81h11h80h
NoNo10h80h11h80hONFI Multiplane Cache Program (End)
Read ID YesNo90h
Read ID2 YesNo30h30h-65h-00h
Read ONFI Signature YesNo90h
Read Parameter Page YesNoECh
One-time Programmable (OTP) Area Entry YesNo29h-17h-04h-19h
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3.1 Page Read
Page Read is initiated by writing 00h and 30h to the command register along with five address cycles (four or five cycles for
S34ML01G1). Two types of operations are available: random read and serial page read. Random read mode is enabled when the
page address is changed. All data within the selected page are transferred to the data registers. The system controller may detect
the completion of this data transfer (tR) by analyzing the output of the R/B pin. Once the data in a page is loaded into the data
registers, they may be read out in 25 ns cycle time by sequentially pulsing RE#. The repetitive high to low transitions of the RE#
signal makes the device output the data, starting from the selected column address up to the last column address.
The device may output random data in a page instead of the sequential data by writing Random Data Output command. The column
address of next data, which is going to be out, may be changed to the address that follows Random Data Output command. Random
Data Output can be performed as many times as needed.
After power up, the device is in read mode, so 00h command cycle is not necessary to start a read operation. Any operation other
than read or Random Data Output causes the device to exit read mode. See Figure 6.1 on page 40 and Figure 21 on page 43 as
references.
3.2 Page Program
A page program cycle consists of a serial data loading period in which up to 2112 bytes (×8) or 1056 words (×16) of data may be
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address inputs
(four cycles for S34ML01G1) and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports Random Data Input within a page. The column address of next data, which will be entered, may be changed to the
address that follows the Random Data Input command (85h). Random Data Input may be performed as many times as needed.
The Page Program confirm command (10h) initiates the programming process. The internal write state controller automatically
executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks.
Once the program process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register. The
system controller can detect the completion of a program cycle by monitoring the
R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) or Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O0) may be checked. The
internal write verify detects only errors for 1’s that are not successfully programmed to 0’s. The command register remains in Read
Status command mode until another valid command is written to the command register. Figure6.2 onpage42 and Figure 20
on page 43 detail the sequence.
The device is programmable by page, but it also allows multiple partial page programming of a word or consecutive bytes up to 2112
bytes (×8) or 1056 words (×16) in a single page program cycle.
The number of consecutive partial page programming operations (NOP) within the same page must not exceed the number
indicated in Table 23 on page 37. Pages may be programmed in any order within a block.
Users who use “EDC check” (for S34ML02G1 and S34ML04G1 only) in copy back must comply with some limitations related to data
handling during one page program sequence. Refer to Section 3.8 on page 19 for details.
If a Page Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete.
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3.3 Multiplane Program — S34ML02G1 and S34ML04G1
The S34ML02G1 and S34ML04G1 devices support Multiplane Program, making it possible to program two pages in parallel, one
page per plane.
A Multiplane Program cycle consists of a double serial data loading period in which up to 4224 bytes (×8) or 2112 words (×16) of
data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into
the appropriate cell. The serial data loading period begins with inputting the Serial Data Input command (80h), followed by the five
cycle address inputs and serial data for the 1st page. The address for this page must be in the 1st plane (PLA0 = 0). The device
supports Random Data Input exactly the same as in the case of page program operation. The Dummy Page Program Confirm
command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again,
the ‘81h’ command must be issued, followed by 2nd page address (5 cycles) and its serial data input. The address for this page
must be in the 2nd plane (PLA0 = 1). The Program Confirm command (10h) starts parallel programming of both pages.
Figure 22 on page 44 describes the sequences using the legacy protocol. In this case, the block address bits for the first plane are
all zero and the second address issued selects the block for both planes. Figure 23 on page 44 describes the sequences using the
ONFI protocol. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select
the plane.
The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or 78h). The Read Status
Register command is also available during Dummy Busy time (tDBSY). In case of failure in either page program, the fail bit of the
Status Register will be set. Refer to Section 3.9 on page 21 for further info.
The number of consecutive partial page programming operations (NOP) within the same page must not exceed the number
indicated in Table 23 on page 37. Pages may be programmed in any order within a block.
If a Multiplane Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete
for the applicable blocks.
3.4 Page Reprogram — S34ML02G1 and S34ML04G1
Page Program may result in a fail, which can be detected by Read Status Register. In this event, the host may call Page Reprogram.
This command allows the reprogramming of the same pattern of the last (failed) page into another memory location. The command
sequence initiates with reprogram setup (8Bh), followed by the five cycle address inputs of the target page. If the target pattern for
the destination page is not changed compared to the last page, the program confirm can be issued (10h) without any data input
cycle, as described in Figure 8.
Figure 8. Page Reprogram
SR[6]
I/Ox
Cycle Type
As defined for Page
rogramP A
A
C1
I/Ox
SR[6]
Cycle Type CMD ADDR ADDR ADDR
00h C2 R1 R3
Page N
Din Din Din Din CMD
D0 D1 . . . Dn 10h
CMD Dout
70h E1
FAIL ! Page M
CMD
10h
tADL
tWB
tPROG
tWB
tPROG
ADDR
R2
ADDR
CMD ADDR ADDR ADDR ADDR
ADDR
8Bh C1 C2 R1 R3
R2
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On the other hand, if the pattern bound for the target page is different from that of the previous page, data in cycles can be issued
before program confirm ‘10h’, as described in Figure 9.
Figure 9. Page Reprogram with Data Manipulation
The device supports Random Data Input within a page. The column address of next data, which will be entered, may be changed to
the address which follows the Random Data Input command (85h). Random Data Input may be operated multiple times regardless
of how many times it is done in a page.
The Program Confirm command (10h) initiates the re-programming process. The internal write state controller automatically
executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks.
Once the program process starts, the Read Status Register command may be issued to read the Status Register. The system
controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register.
Only the Read Status command and Reset command are valid when programming is in progress. When the Page Program is
complete, the Write Status Bit (I/O0) may be checked. The internal write verify detects only errors for 1’s that are not successfully
programmed to 0’s. The command register remains in Read Status command mode until another valid command is written to the
command register.
The Page Reprogram must be issued in the same plane as the Page Program that failed. In order to program the data to a different
plane, use the Page Program operation instead. The Multiplane Page Reprogram can re-program two pages in parallel, one per
plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The command
sequence is very similar to Figure 22 on page 44, except that it requires the Page Reprogram Command (8Bh) instead of 80h and
81h.
If a Page Reprogram operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete.
C1
IOx
SR[6]
SR[6]
Cycle Type
I/Ox
Cycle Type
As defined for Page
rogramP A
A
ADDRADDRADDRADDRCMD
R3R1C280h
Page N
Din Din Din Din CMD
D0 D1 . . . Dn 10h
ADDRADDRADDRADDRCMD
R3R1C2C18Bh
FAIL !
Page M
CMD
10h
tADL
tWB tPROG
tWB
tPROG
CMD Dout
70h E1
Din Din Din Din
D0 D1 . . . Dn
tADL
ADDR
R2
ADDR
R2
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S34ML02G1
S34ML04G1
3.5 Block Erase
The Block Erase operation is done on a block basis. Block address loading is accomplished in three cycles (two cycles for
S34ML01G1) initiated by an Erase Setup command (60h). Only the block address bits are valid while the page address bits are
ignored.
The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step
sequence of setup followed by the execution command ensures that memory contents are not accidentally erased due to external
noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and erase verify. Once
the erase process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register.
The system controller can detect the completion of an erase by monitoring the R/B# output, or the Status bit (I/O6) of the Status
Register. Only the Read Status commands (70h or 78h) and Reset command are valid while erasing is in progress. When the erase
operation is completed, the Write Status Bit (I/O0) may be checked. Figure 24 on page 45 details the sequence.
If a Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted
block is erased under continuous power conditions before that block can be trusted for further programming and reading operations.
3.6 Multiplane Block Erase — S34ML02G1 and S34ML04G1
Multiplane Block Erase allows the erase of two blocks in parallel, one block per memory plane.
The Block erase setup command (60h) must be repeated two times, followed by 1st and 2nd block address respectively (3 cycles
each). As for block erase, D0h command makes embedded operation start. In this case, multiplane erase does not need any
Dummy Busy Time between 1st and 2nd block insertion. See Table 23 on page 37 for performance information.
For the Multiplane Block Erase operation, the address of the first block must be within the first plane (PLA0 = 0) and the address of
the second block in the second plane (PLA0 = 1). See Figure 25 on page 45 for a description of the legacy protocol. In this case, the
block address bits for the first plane are all zero and the second address issued selects the block for both planes. Figure 26
on page 46 describes the sequences using the ONFI protocol. For both addresses issued in this protocol, the block address bits
must be the same except for the bit(s) that select the plane.
The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or 78h). The Read Status
Register command is also available during Dummy Busy time (tDBSY). In case of failure in either erase, the fail bit of the Status
Register will be set. Refer to Section 3.9 on page 21 for further information.
If a Multiplane Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted blocks are erased under continuous power conditions before those blocks can be trusted for further programming and
reading operations.
3.7 Copy Back Program
The copy back feature is intended to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is greatly improved.
The benefit is especially obvious when a portion of a block needs to be updated and the rest of the block also needs to be copied to
the newly assigned free block. The operation for performing a copy back is a sequential execution of page-read (without mandatory
serial access) and Copy Back Program with the address of destination page. A read operation with the ‘35h’ command and the
address of the source page moves the whole page of data into the internal data register. As soon as the device returns to the Ready
state, optional data read-out is allowed by toggling RE# (see Figure 27 on page 46), or the Copy Back Program command (85h) with
the address cycles of the destination page may be written. The Program Confirm command (10h) is required to actually begin
programming.
The source and the destination pages in the Copy Back Program sequence must belong to the same device plane (same PLA0 for
S34ML02G1 and S34ML04G1). Copy Back Read and Copy Back Program for a given plane must be between odd address pages or
between even address pages for the device to meet the program time (tPROG) specification. Copy Back Program may not meet this
specification when copying from an odd address page (source page) to an even address page (target page) or from an even
address page (source page) to an odd address page (target page).
The data input cycle for modifying a portion or multiple distinct portions of the source page is allowed as shown in Figure 28
on page 46. As noted in Section 1. on page 4 the device may include an automatic EDC (for S34ML02G1 and S34ML04G1) check
during the copy back operation, to detect single bit errors in EDC units contained within the source page. More details on EDC
operation and limitations related to data input handling during one Copy Back Program sequence are available in Section 3.8
on page 19.
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If a Copy Back Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete.
3.7.1 Multiplane Copy Back Program — S34ML02G1 and S34ML04G1
The device supports Multiplane Copy Back Program with exactly the same sequence and limitations as the Page Program.
Multiplane Copy Back Program must be preceded by two single page Copy Back Read command sequences (1st page must be
read from the 1st plane and 2nd page from the 2nd plane).
Multiplane Copy Back cannot cross plane boundaries — the contents of the source page of one device plane can be copied only to
a destination page of the same plane. EDC check is available also for Multiplane Copy Back Program only for S34ML02G1 and
S34ML04G1.
When “EDC check” is used in copy back, it must comply with some limitations related to data handling during one Multiplane Copy
Back Program sequence. Please refer to Section 3.8 on page 19 for details on EDC operation. The Multiplane Copy Back Program
sequence represented in Figure 29 on page 47 shows the legacy protocol. In this case, the block address bits for the first plane are
all zero and the second address issued selects the block for both planes. Figure 30 on page 47 describes the sequence using the
ONFI protocol. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select
the plane.
If a Multiplane Copy Back Program operation is interrupted by hardware reset, power failure or other means, the host must ensure
that the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are
complete for the applicable blocks.
3.7.2 Special Read for Copy Back — S34ML02G1 and S34ML04G1
The S34ML02G1 and S34ML04G1 devices support Special Read for Copy Back. If Copy Back Read (described in Section 3.7 and
Section 3.7.1 on page 19) is triggered with confirm command ‘36h’ instead ‘35h’, Copy Back Read from target page(s) will be
executed with an increased internal (VPASS) voltage.
This special feature is used in order to minimize the number of read errors due to over-program or read disturb — it shall be used
only if ECC read errors have occurred in the source page using Page Read or Copy Back Read sequences.
Excluding the Copy Back Read confirm command, all other features described in Section 3.7 and Section 3.7.1 for standard copy
back remain valid (including the figures referred to in those sections).
3.8 EDC Operation — S34ML02G1 and S34ML04G1
Error Detection Code check is a feature that can be used during the copy back operation (both single and multiplane) to detect
single bit errors occurring in the source page(s).
Note: The S34ML01G1 device does not support EDC.
EDC check allows detection of up to 1 single bit error every 528 bytes, where each 528 byte group is composed of 512
bytes of main array and 16 bytes of spare area (see Table 10 and Table 11 on page 21). The described 528-byte area is
called an “EDC unit.”
In the ×16 device, EDC allows detection of up to 1 single bit error every 264 words, where each 264 word group is
composed by 256 words of main array and 8 words of spare area see Table 10 and Table 11 on page 21). The described
264-word area is called “EDC unit.”
EDC results can be checked through a specific Read EDC register command, available only after issuing a Copy Back Program or a
Multiplane Copy Back Program. The EDC register can be queried during the copy back program busy time (tPROG).
For the “EDC check” feature to operate correctly, specific conditions on data input handling apply for program operations.
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For the case of Page Program, Multiplane Page Program, Page Reprogram, Multiplane Page Reprogram, Cache Program, and
Multiplane Cache Program operations:
In Section3.2 onpage15 it was explained that a number of consecutive partial program operations (NOP) is allowed within
the same page. In case this feature is used, the number of partial program operations occurring in the same EDC unit must
not exceed 1. In other words, page program operations must be performed on the whole page, or on whole EDC unit at a
time.
“Random Data Input” in a given EDC unit can be executed several times during one page program sequence, but data
cannot be written to any column address more than once before the program is initiated.
For the case of Copy Back Program or Multiplane Copy Back Program operations:
If Random Data Input is applied in a given EDC unit, the entire EDC unit must be written to the page buffer. In other words,
the EDC check is possible only if the whole EDC unit is modified during one Copy Back Program sequence.
“Random Data Input” in a given EDC unit can be executed several times during one Copy Back Program sequence, but
data insertion in each column address of the EDC unit must not exceed 1.
If you use copy back without EDC check, none of the limitations described above apply.
After a Copy Back Program operation, the host can use Read EDC Status Register to check the status of both the program
operation and the Copy Back Read. If the EDC was valid and an error was reported in the EDC (see Table 9 on page 20), the host
may perform Special Read For Copy Back on the source page and attempt the Copy Back Program again. If this also fails, the host
can execute a Page Read operation in order to correct a single bit error with external ECC software or hardware.
3.8.1 Read EDC Status Register — S34ML02G1 and S34ML04G1
This operation is available only after issuing a Copy Back Program and it allows the detection of errors during Copy Back Read. In
the case of multiplane copy back, it is not possible to know which of the two read operations caused the error.
After writing the Read EDC Status Register command (7Bh) to the command register, a read cycle outputs the content of the EDC
Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last.
The operation is the same as the Read Status Register command. Refer to Table 9 for specific EDC Register definitions:
Table 9. EDC Register Coding
ID Copy Back Program Coding
Pass: 0; Fail: 1Pass / Fail0
No error: 0; Error: 1EDC status1
Invalid: 0; Valid: 1EDC validity2
—NA3
—NA4
Busy: 0; Ready: 1Ready / Busy5
Busy: 0; Ready: 1Ready / Busy6
ProtectWrite Protect7 ed: 0; Not Protected: 1
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3.9 Read Status Register
The Status Register is used to retrieve the status value for the last operation issued. After writing 70h command to the command
register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs
last. This two-line control allows the system to poll the progress of each device in multiple memory connections even when R/B#
pins are common-wired. Refer to Section 13 on page 22 for specific Status Register definition, and to Figure 31 on page 48 for
timings.
If the Read Status Register command is issued during multiplane operations then Status Register polling will return the combined
status value related to the outcome of the operation in the two planes according to the following table.
In other words, the Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
The command register remains in Status Read mode until further commands are issued. Therefore, if the Status Register is read
during a random read cycle, the read command (00h) must be issued before starting read cycles.
Note: The Read Status Register command shall not be used for concurrent operations in multi-die stack configurations (single CE#).
“Read Status Enhanced” shall be used instead.
Table 10. Page Organization in EDC Units
Main Field (2048 Byte) Spare Field (64 Byte)
“A” area
(1st sector)
“B” area
(2nd sector)
“C” area
(3rd sector)
“D” area
(4th sector)
“E” area
(1st sector)
“F” area
(2nd sector)
“G” area
(3rd sector)
“H” area
(4th sector)
×8
512512 byte512 byte 16 byte16 byte16 byte16 byte512 bytebyte
×16
8 word8 words8 words8 words256 words256 words256 words256 words s
Table 11. Page Organization in EDC Units by Address
Sector Main Field (Column 0-2047) Spare Field (Column 2048-2111)
Area Name Column Address Area Name Column Address
×8
2048-2063E0-511A1st 528-byte Sector
2064-2079F512-1023B2nd 528-byte Sector
2080-2095G1024-1535C3rd 528-byte Sector
2096-2111H1536-2047D4th 528-byte Sector
×16
1024-1031E0-255A1st 256-word Sector
1032-1039F256-511B2nd 256-word Sector
1040-1047G512-767C3rd 256-word Sector
4th 256-word Sector 1048-1055H768-1023D
Table 12. Read Status Definition
Status Register Bit Composite Status Value
ORBit 0, Pass/Fail
ORBit 1, Cache Pass/Fail
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S34ML01G1
S34ML02G1
S34ML04G1
3.10 Read Status Enhanced — S34ML02G1 and S34ML04G1
Read Status Enhanced is used to retrieve the status value for a previous operation in the specified plane.
Figure 32 on page 48 defines the Read Status Enhanced behavior and timings. The plane and die address must be specified in the
command sequence in order to retrieve the status of the die and the plane of interest.
Refer to Table 13 for specific Status Register definitions. The command register remains in Status Read mode until further
commands are issued.
The Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
3.11 Read Status Register Field Definition
Table 13 below lists the meaning of each bit of the Read Status Register and Read Status Enhanced (S34ML02G1 and
S34ML04G1).
3.12 Reset
The Reset feature is executed by writing FFh to the command register. If the device is in the Busy state during random read,
program, or erase mode, the Reset operation will abort these operations. The contents of memory cells being altered are no longer
valid, as the data may be partially programmed or erased. The command register is cleared to wait for the next command, and the
Status Register is cleared to value E0h when WP# is high or value 60h when WP# is low. If the device is already in reset state a new
Reset command will not be accepted by the command register. The R/B# pin transitions to low for tRST after the Reset command is
written. Refer to Figure 33 on page 48 for further details. The Status Register can also be read to determine the status of a Reset
operation.
Table 13. Status Register Coding
ID Page Program /
Page Reprogram Block Erase Read Read Cache Cache Program /
Cache Reprogram Coding
Pass / FailNANAPass / FailPass / Fail0
N Page
Pass: 0
Fail: 1
Pass / FailNANANANA1
N - 1 Page
Pass: 0
Fail: 1
—NANANANANA2
—NANANANANA3
—NANANANANA4
ReadyReady / BusyReady / Busy5 Ready / BusyReady / Busy/ Busy Internal Data Operation Active: 0
Idle: 1
ReadyReady / BusyReady / Busy6 Ready / BusyReady / Busy/ Busy
Ready / Busy
Busy: 0
Ready: 1
Write ProtectNANAWrite ProtectWrite Protect7 Protected: 0
Not Protected: 1
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S34ML01G1
S34ML02G1
S34ML04G1
3.13 Read Cache
Read Cache can be used to increase the read operation speed, as defined in Section 3.1 on page 15, and it cannot cross a block
boundary. As soon as the user starts to read one page, the device automatically loads the next page into the cache register. Serial
data output may be executed while data in the memory is read into the cache register. Read Cache is initiated by the Page Read
sequence (00-30h) on a page M.
After random access to the first page is complete (R/B# returned to high, or Read Status Register I/O6 switches to high), two
command sequences can be used to continue read cache:
Read Cache (command ‘31h’ only): once the command is latched into the command register (see Figure 35 on page 49),
device goes busy for a short time (tCBSYR), during which data of the first page is transferred from the data register to the
cache register. At the end of this phase, the cache register data can be output by toggling RE# while the next page (page
address M+1) is read from the memory array into the data register.
Read Cache Enhanced (sequence ‘00h’ <page N address> ‘31’): once the command is latched into the command register
(see Figure 36 on page 50), device goes busy for a short time (tCBSYR), during which data of the first page is transferred
from the data register to the cache register. At the end of this phase, cache register data can be output by toggling RE#
while page N is read from the memory array into the data register.
Note: The S34ML01G1 device does not support Read Cache Enhanced.
Subsequent pages are read by issuing additional Read Cache or Read Cache Enhanced command sequences. If serial data output
time of one page exceeds random access time (tR), the random access time of the next page is hidden by data downloading of the
previous page.
On the other hand, if 31h is issued prior to completing the random access to the next page, the device will stay busy as long as
needed to complete random access to this page, transfer its contents into the cache register, and trigger the random access to the
following page.
To terminate the Read Cache operation, 3Fh command should be issued (see Figure 37 on page 50). This command transfers data
from the data register to the cache register without issuing next page read.
During the Read Cache operation, the device doesn't allow any other command except for 00h, 31h, 3Fh, Read SR, or Reset (FFh).
To carry out other operations, Read Cache must be terminated by the Read Cache End command (3Fh) or the device must be reset
by issuing FFh.
Read Status command (70h) may be issued to check the status of the different registers and the busy/ready status of the cached
read operations.
The Cache-Busy status bit I/O6 indicates when the cache register is ready to output new data.
The status bit I/O5 can be used to determine when the cell reading of the current data register contents is complete.
Note: The Read Cache and Read Cache End commands reset the column counter, thus, when RE# is toggled to output the data of
a given page, the first output data is related to the first byte of the page (column address 00h). Random Data Output command can
be used to switch column address.
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S34ML01G1
S34ML02G1
S34ML04G1
3.14 Cache Program
Cache Program can improve the program throughput by using the cache register. The Cache Program operation cannot cross a
block boundary. The cache register allows new data to be input while the previous data that was transferred to the data register is
programmed into the memory array.
After the serial data input command (80h) is loaded to the command register, followed by five cycles of address, a full or partial page
of data is latched into the cache register.
Once the cache write command (15h) is loaded to the command register, the data in the cache register is transferred into the data
register for cell programming. At this time the device remains in the Busy state for a short time (tCBSYW). After all data of the cache
register is transferred into the data register, the device returns to the Ready state and allows loading the next data into the cache
register through another Cache Program command sequence (80h-15h).
The Busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the cache register to the data
register. Cell programming the data of the data register and loading of the next data into the cache register is consequently
processed through a pipeline model.
In case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off until cell programming
of current data register contents is complete; till this moment the device will stay in a busy state (tCBSYW).
Read Status commands (70h or 78h) may be issued to check the status of the different registers, and the pass/fail status of the
cached program operations.
The Cache-Busy status bit I/O6 indicates when the cache register is ready to accept new data.
The status bit I/O5 can be used to determine when the cell programming of the current data register contents is complete.
The Cache Program error bit I/O1 can be used to identify if the previous page (page N-1) has been successfully
programmed or not in a Cache Program operation. The status bit is valid upon I/O6 status bit changing to 1.
The error bit I/O0 is used to identify if any error has been detected by the program/erase controller while programming page
N. The status bit is valid upon I/O5 status bit changing to 1.
I/O1 may be read together with I/O0.
If the system monitors the progress of the operation only with R/B#, the last page of the target program sequence must be
programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5
must be polled to find out if the last programming is finished before starting any other operation. See Table 13 on page 22 and
Figure 38 on page 50 for more details.
If a Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete
for the applicable blocks.
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S34ML01G1
S34ML02G1
S34ML04G1
3.15 Multiplane Cache Program — S34ML02G1 and S34ML04G1
The Multiplane Cache Program enables high program throughput by programming two pages in parallel, while exploiting the data
and cache registers of both planes to implement cache.
The command sequence can be summarized as follows:
Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st page. Address
for this page must be within 1st plane (PLA0 = 0). The data of 1st page other than those to be programmed do not need to
be loaded. The device supports Random Data Input exactly like Page Program operation.
The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short
time (tDBSY).
Once device returns to ready again, 81h command must be issued, followed by 2nd page address
(5 cycles) and its serial data input. Address for this page must be within 2nd plane (PLA0 = 1). The data of 2nd page other
than those to be programmed do not need to be loaded.
Cache Program confirm command (15h). Once the cache write command (15h) is loaded to the command register, the data
in the cache registers is transferred into the data registers for cell programming. At this time the device remains in the Busy
state for a short time (tCBSYW). After all data from the cache registers are transferred into the data registers, the device
returns to the Ready state, and allows loading the next data into the cache register through another Cache Program
command sequence.
The sequence 80h-...- 11h...-...81h...-...15h can be iterated, and each time the device will be busy for the tCBSYW time needed to
complete programming the current data register contents, and transferring the new data from the cache registers. The sequence to
end Multiplane Cache Program is 80h-...- 11h...-...81h...-...10h.
The Multiplane Cache Program is available only within two paired blocks in separate planes. Figure 39 on page 51 shows the legacy
protocol for the Multiplane Cache Program operation. In this case, the block address bits for the first plane are all zero and the
second address issued selects the block for both planes. Figure 40 on page 52 shows the ONFI protocol for the Multiplane Cache
Program operation. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that
select the plane.
The user can check operation status by R/B# pin or Read Status Register commands (70h or 78h). If the user opts for 70h, Read
Status Register will provide “global” information about the operation in the two planes.
I/O6 indicates when both cache registers are ready to accept new data.
I/O5 indicates when the cell programming of the current data registers is complete.
I/O1 identifies if the previous pages in both planes (pages N-1) have been successfully programmed or not. This status bit
is valid upon I/O6 status bit changing to 1.
I/O0 identifies if any error has been detected by the program/erase controller while programming the two pages N. This
status bit is valid upon I/O5 status bit changing to 1.
See Table 13 on page 22 for more details.
If the system monitors the progress of the operation only with R/B#, the last pages of the target program sequence must be
programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5
must be polled to find out if the last programming is finished before starting any other operation. Refer to Section 3.9 on page 21 for
further information.
If a Multiplane Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that
the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are
complete for the applicable blocks.
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S34ML01G1
S34ML02G1
S34ML04G1
3.16 Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h.
Note: If you want to execute Read Status command (0x70) after Read ID sequence, you should input dummy command (0x00)
before Read Status command (0x70).
For the S34ML02G1 and S34ML04G1 devices, five read cycles sequentially output the manufacturer code (01h), and the device
code and 3rd, 4th, and 5th cycle ID, respectively. For the S34ML01G1 device, four read cycles sequentially output the manufacturer
code (01h), device id (F1h), 3rd cycle (00h), and 4th cycle ID of 1Dh respectively. The command register remains in Read ID mode
until further commands are issued to it. Figure 41 on page 53 shows the operation sequence, while Table 14 to Table 3.3 explain the
byte meaning.
Table 14. Read ID for Supported Configurations
Density Org VCC 1st 2nd 3rd 4th 5th
1 Gb
×8
3.3V
—1Dh00hF1h01h
44h95h90hDAh01h2 Gb
54h95h90hDCh01h4 Gb
1 Gb
×16
—5Dh00hC1h01h
44hD5h90hCAh01h2 Gb
54hD5h90hCCh01h4 Gb
Table 15. Read ID Bytes
Device Identifier Byte Description
Manufacturer Code1st
Device Identifier2nd
Internal chip number, cell type, etc.3rd
Page Size, Block Size, Spare4th Size, Serial Access Time, Organization
5th (S34ML02G1, S34ML04G1) ECC, Multiplane information
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S34ML01G1
S34ML02G1
S34ML04G1
3rd ID Data
4th ID Data
Table 16. Read ID Byte 3 Description
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Internal Chip Number
1
2
4
8
0 0
0 1
1 0
1 1
Cell type
2-level cell
4-level cell
8-level cell
16-level cell
0 0
0 1
1 0
1 1
Number of simultaneously
programmed pages
1
2
4
8
0 0
0 1
1 0
11
Interleave program
Between multiple chips
Not supported
Supported
0
1
Cache Program Not supported
Supported
0
1
Table 3.1 Read ID Byte 4 Description — S34ML01G1
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Page Size
(without spare area)
1 kB
2 kB
4 kB
8 kB
0 0
0 1
1 0
1 1
Block Size
(without spare area)
64 kB
128 kB
256 kB
512 kB
0 0
0 1
1 0
1 1
Spare Area Size
(byte / 512 byte)
8
16
0
1
Serial Access Time
45 ns
25 ns
Reserved
Reserved
0
0
1
1
0
1
0
1
Organization 0×8
1×16
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S34ML01G1
S34ML02G1
S34ML04G1
5th ID Data
Table 3.2 Read ID Byte 4 Description — S34ML02G1 and S34ML04G1
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Page Size
(without spare area)
1 kB
2 kB
4 kB
8 kB
0 0
0 1
1 0
1 1
Block Size
(without spare area)
64 kB
128 kB
256 kB
512 kB
0 0
0 1
1 0
1 1
Spare Area Size
(byte / 512 byte)
8
16
0
1
Serial Access Time
50 ns / 30 ns
25 ns
Reserved
Reserved
0
1
0
1
0
0
1
1
Organization 0×8
1×16
Table 3.3 Read ID Byte 5 Description — S34ML02G1 and S34ML04G1
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Plane Number
1
2
4
8
0 0
0 1
1 0
1 1
Plane Size
(without spare area)
64 Mb
128 Mb
256 Mb
512 Mb
1 Gb
2 Gb
4 Gb
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
000Reserved
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S34ML01G1
S34ML02G1
S34ML04G1
3.17 Read ID2
The device contains an alternate identification mode, initiated by writing 30h-65h-00h to the command register, followed by address
inputs, followed by command 30h. The address for S34ML01G1 will be
00h-02h-02h-00h. The address for S34ML02G1 and S34ML04G1 will be 00h-02h-02h-00h-00h. The ID2 data can then be read from
the device by pulsing RE#. The command register remains in Read ID2 mode until further commands are issued to it. Figure 42
on page 53 shows the Read ID2 command sequence. Read ID2 values are all 0xFs, unless specific values are requested when
ordering from Cypress.
3.18 Read ONFI Signature
To retrieve the ONFI signature, the command 90h together with an address of 20h shall be entered (i.e. it is not valid to enter an
address of 00h and read 36 bytes to get the ONFI signature). The ONFI signature is the ASCII encoding of 'ONFI' where 'O' = 4Fh,
'N' = 4Eh, 'F' = 46h, and 'I' = 49h. Reading beyond four bytes yields indeterminate values. Figure 43 on page 54 shows the operation
sequence.
3.19 Read Parameter Page
The device supports the ONFI Read Parameter Page operation, initiated by writing ECh to the command register, followed by an
address input of 00h. The host may monitor the R/B# pin or wait for the maximum data transfer time (tR) before reading the
Parameter Page data. The command register remains in Parameter Page mode until further commands are issued to it. If the Status
Register is read to determine when the data is ready, the Read Command (00h) must be issued before starting read cycles.
Figure 44 on page 54 shows the operation sequence, while Table 3.4 explains the parameter fields.
For ×16 devices, the upper eight I/Os are not used and are 0xFF.
Note: For 41nm 2Gb/4Gb Cypress NAND, for a particular condition, the Read Parameter Page command does not give the correct
values. To overcome this issue, the host must issue a Reset command before the Read Parameter Page command. Issuance of
Reset before the Read Parameter Page command will provide the correct values and will not output 00h values. This does not apply
to 48nm 1Gb.
Table 3.4 Parameter Page Description
Byte O/M Description Values
Revision Information and Features Block
M0-3
Parameter page signature
Byte 0: 4Fh, “O”
Byte 1: 4Eh, “N”
Byte 2: 46h, “F”
Byte 3: 49h, “I”
4Fh, 4Eh, 46h, 49h
M4-5
Revision number
Reserved (0)2-15
1 = supports ONFI version 1.01
0 Reserved (0)
02h, 00h
M6-7
Features supported
5-15 Reserved (0)
4 1 = supports odd to even page Copyback
3 1 = supports interleaved operations
2 1 = supports non-sequential page programming
1 1 = supports multiple LUN operations
0 1 = supports 16-bit data bus width
S34ML01G100 (×8): 14h, 00h
S34ML02G100 (×8): 1Ch, 00h
S34ML04G100 (×8): 1Ch, 00h
S34ML01G104 (×16): 15h, 00h
S34ML02G104 (×16): 1Dh, 00h
S34ML04G104 (×16): 1Dh, 00h
M8-9
Optional commands supported
6-15 Reserved (0)
5 1 = supports Read Unique ID
4 1 = supports Copyback
3 1 = supports Read Status Enhanced
2 1 = supports Get Features and Set Features
1 1 = supports Read Cache commands
0 1 = supports Page Cache Program command
S34ML01G1: 13h, 00h
S34ML02G1: 1Bh, 00h
S34ML04G1: 1Bh, 00h
Reserved (0)10-31 00h
Manufacturer Information Block
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Page 29 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Device manufacturer (12 ASCII characters)M32-43 53h, 50h, 41h, 4Eh, 53h, 49h, 4Fh, 4Eh,
20h, 20h, 20h, 20h
Device model (20 ASCII characters)M44-63
S34ML01G1: 53h, 33h, 34h, 4Dh, 4Ch,
30h, 31h, 47h, 31h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h
S34ML02G1: 53h, 33h, 34h, 4Dh, 4Ch,
30h, 32h, 47h, 31h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h
S34ML04G1: 53h, 33h, 34h, 4Dh, 4Ch,
30h, 34h, 47h, 31h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h
JEDEC manufacturer IDM64 01h
Date codeO65-66 00h
Reserved (0)67-79 00h
Memory Organization Block
00h, 08h, 00h, 00hNumber of data bytes per pageM80-83
40h, 00hNumber of spare bytes per pageM84-85
00h, 02h, 00h, 00Number of data bytes per partial pageM86-89 h
10h, 00hNumber of spare bytes per partial pageM90-91
40h, 00h, 00h, 00hNumber of pages per blockM92-95
Number of blocks per logical unit (LUN)M96-99
S34ML01G1: 00h, 04h, 00h, 00h
S34ML02G1: 00h, 08h, 00h, 00h
S34ML04G1: 00h, 10h, 00h, 00h
01hNumber of logical units (LUNs)M100
M101
Number of address cycles
Column address cycles4-7
Row address cycles0-3
S34ML01G1: 22h
S34ML02G1: 23h
S34ML04G1: 23h
Number of bits per cellM102 01h
Bad blocksM103-104 maximum per LUN
S34ML01G1: 14h, 00h
S34ML02G1: 28h, 00h
S34ML04G1: 50h, 00h
Block enduranceM105-106 01h, 05h
01hGuaranteed valid blocks at beginning of targetM107
01h, 03hBlock endurance for guaranteed valid blocksM108-109
04hNumber of programs per pageM110
M111
Partial programming attributes
Reserved5-7
1 = partial page layout is partial page data followed by4
partial page spare
1-3 Reserved
0 1 = partial page programming has constraints
00h
01hNumber of bits ECC correctabilityM112
M113
Number of interleaved address bits
Reserved (0)4-7
Number of interleaved address bits0-3
S34ML01G1: 00h
S34ML02G1: 01h
S34ML04G1: 01h
O114
Interleaved operation attributes
4-7 Reserved (0)
3 Address restrictions for program cache
2 1 = program cache supported
1 1 = no block address restrictions
0 Overlapped / concurrent interleaving support
S34ML01G1: 00h
S34ML02G1: 04h
S34ML04G1: 04h
Reserved (0)115-127 00h
Electrical Parameters Block
Table 3.4 Parameter Page Description (Continued)
Byte O/M Description Values
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Page 30 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Note
24. O” Stands for Optional, “M” for Mandatory.
3.20 One-Time Programmable (OTP) Entry
The device contains a one-time programmable (OTP) area, which is accessed by writing 29h-17h-04h-19h to the command register.
The device is then ready to accept Page Read and Page Program commands (refer to Page Read and Page Program on page 15).
The OTP area is of a single erase block size (64 pages), and hence only row addresses between 00h and 3Fh are allowed. The host
must issue the Reset command (refer to Reset on page 22) to exit the OTP area and access the normal flash array. The Block Erase
command is not allowed in the OTP area. Refer to Figure 45 on page 54 for more detail on the OTP Entry command sequence.
Note: The OTP feature in the S34ML01G1 does not have non-volatile protection.
I/O pin capacitanceM128 0Ah
M129-130
Timing mode support
Reserved (0)6-15
1 = supports timing mode 55
1 = supports timing mode 44
1 = supports timing mode 33
1 = supports timing mode 22
1 = supports timing mode 11
1 = supports timing mode 0, shall be 10
1Fh, 00h
O131-132
Program cache timing mode support
Reserved (0)6-15
1 = supports timing mode 55
4 1 = supports timing mode 4
3 1 = supports timing mode 3
2 1 = supports timing mode 2
1 1 = supports timing mode 1
0 1 = supports timing mode 0
1Fh, 00h
tM133-134 PROG BCh, 02hMaximum page program time (µs)
tM135-136 BERS Maximum block erase time (µs)
S34ML01G1: B8h, 0Bh
S34ML02G1: 10h, 27h
S34ML04G1: 10h, 27h
tM137-138 R19h, 00hMaximum page read time (µs)
tM139-140 CCS 64h, 00hMinimum Change Column setup time (ns)
Reserved (0)141-163 00h
Vendor Block
00hVendor specific Revision numberM164-165
Vendor specific166-253 00h
Integrity CRCM254-255
S34ML01G100 (×8): FFh, 63h
S34ML02G100 (×8): 3Bh, C5h
S34ML04G100 (×8): 45h, 8Eh
S34ML01G104 (×16): 8Dh, 15h
S34ML02G104 (×16): 49h, B3h
S34ML04G104 (×16): 37h, F8h
Redundant Parameter Pages
Value of bytes 0-255M256-511 Repeat Value of bytes 0-255
Value of bytes 0-255M512-767 Repeat Value of bytes 0-255
FFhAdditional redundant parameter pagesO768+
Table 3.4 Parameter Page Description (Continued)
Byte O/M Description Values
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Page 31 of 70
S34ML01G1
S34ML02G1
S34ML04G1
4. Signal Descriptions
4.1 Data Protection and Power On / Off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever VCC is below about 1.8V.
The power-up and power-down sequence is shown in Figure 46 on page 55.
The Ready/Busy signal shall be valid within 100 µs after the power supplies have reached the minimum values (as specified on),
and shall return to one within 5 ms (max).
During this busy time, the device executes the initialization process (cam reading), and dissipates a current ICC0 (30 mA max), in
addition, it disregards all commands excluding Read Status Register (70h).
At the end of this busy time, the device defaults into “read setup”, thus if the user decides to issue a page read command, the 00h
command may be skipped.
The WP# pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time
of minimum 100 µs is required before the internal circuit gets ready for any command sequences as shown in Figure 46 on page 55.
The two-step command sequence for
program/erase provides additional software protection.
4.2 Ready/Busy
The Ready/Busy output provides a method of indicating the completion of a page program, erase, copyback, or read completion.
The R/B# pin is normally high and goes to low when the device is busy (after a reset, read, program, or erase operation). It returns to
high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B#
outputs to be Or-tied. Because the pull-up resistor value is related to tr (R/B#) and the current drain during busy (ibusy), and output
load capacitance is related to tf an appropriate value can be obtained with the reference chart shown in Figure 10.
For example, for a particular system with 20 pF of output load, tf from VCC to VOL at 10% to 90% will be 10 ns, whereas for a
particular load of 50 pF, Cypress measured it to be 20 ns as shown in Figure 10.
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S34ML04G1
Figure 10. Ready/Busy Pin Electrical Application
4.3 Write Protect Operation
Erase and program operations are aborted if WP# is driven low during busy time, and kept low for about 100 ns. Switching WP# low
during this time is equivalent to issuing a Reset command (FFh). The contents of memory cells being altered are no longer valid, as
the data will be partially programmed or erased. The R/B# pin will stay low for tRST (similarly to Figure 33 on page 48). At the end of
this time, the command register is ready to process the next command, and the Status Register bit I/O6 will be cleared to 1, while
I/O7 value will be related to the WP# value. Refer to Table 13 on page 22 for more information on device status.
Erase and program operations are enabled or disabled by setting WP# to high or low respectively, prior to issuing the setup
commands (80h or 60h). The level of WP# shall be set tWW ns prior to raising the WE# pin for the set up command, as explained in
Figure 47 and Figure 48 on page 55.
Figure 11. WP# Low Timing Requirements during Program/Erase Command Sequence
Rp vs. tr, tf and Rp vs. ibusy
Rp ibusy
Busy
Ready V
CC
V
OH
V
OL
V
OL
: 0.4V, V
OH
: 2.4V
Vcc
GND
Device
open drain output
R/B#
C
L
300n
200n
100n
= t
f (ns)
20 20 20 20
50
= t
r (ns)
3m
2m
1m
ibusy [A]
t
r
,t
f
[s]
4k3k2k1k
= ibusy (
mA
)
1.2
2.4
100
150
200
0.8
0.6
Rp (ohm)
@ Vcc = 3.3V, Ta = 25°C, C
L
=50 pF
Rp value guidence
Rp (min.) = =
Vcc (Max.) - V
OL
3.2V(Max.)
8mA + ∑I
L
I
OL +
I
L
∑
Rp(max) is determined by maximum permissible limit of tr.
where is the sum of the input currents of all devices tied to the R/B# pin.
L
I
t
f
t
r
Legend
WE#
I/O[7:0]
WP#
Valid
> 100 ns
Sequence
Aborted
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5. Electrical Characteristics
5.1 Valid Blocks
Absolute Maximum Ratings5.2
Notes
25. Except for the rating “Operating Temperature Range”, stresses above those listed in the table Absolute Maximum Ratings “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating
sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
26. Minimum Voltage may undershoot to -2V during transition and for less than 20 ns during transitions.
27. Maximum Voltage may overshoot to VCC+2.0V during transition and for less than 20 ns during transitions.
5.3 Recommended Operating Conditions
AC Test Conditions5.4
Table 17. Valid Blocks
Device Symbol Min Typ Max Unit
NS34ML01G1 VB — Blocks10241004
NS34ML02G1 VB — Blocks20482008
NS34ML04G1 VB — Blocks40964016
Table 5.1 Absolute Maximum Ratings
Parameter Symbol Value Unit
Ambient Operating Temperature (I Tndustrial Temperature Range) A°C-40 to +85
TTemperature under Bias BIAS °C-50 to +125
TStorage Temperature STG °C-65 to +150
VInput or Output Voltage IO [26] V-0.6 to +4.6
VSupply Voltage CC V-0.6 to +4.6
Table 18. Recommended Operating Conditions
Parameter Symbol Min Typ Max Units
V3.63.32.7VccVcc Supply Voltage
V000VssGround Supply Voltage
Table 19. AC Test Conditions
Parameter Value
Input Pulse Levels 0.0V to VCC
5 nsInput Rise And Fall Times
VInput And Output Timing Levels CC / 2
Output Load (2.7V - 3.6V 1 TTL Gate and CL = 50 pF)
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AC Characteristics5.5
Notes
28. The time to Ready depends on the value of the pull-up resistor tied to R/B# pin.
29. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5 µs.
30. CE# low to high or RE# low to high can be at different times and produce three cases. Depending on which signal comes high first, either tCOH or tRHOH will be met.
31. During data output, tCEA depends partly on tCR (CE# low to RE# low). If tCR exceeds the minimum value specified, then the maximum time for tCEA may also be exceeded
(tCEA = tCR + tREA).
Table 20. AC Characteristics
Parameter Symbol Min Max Unit
tALE to RE# delay AR ns—10
tALE hold time ALH ns—5
tALE setup time ALS ns—10
tAddress to data loading time ADL ns—70
tCE# low to RE# low CR ns—10
tCE# hold time CH ns—5
tCE# high to output High-Z CHZ ns—30
tCLE hold time CLH ns—5
tCLE to RE# delay CLR ns—10
tCLE setup time CLS ns—10
tCE# access time CEA [31] ns—25
tCE# high to output hold COH [30] ns—15
tCE# high to ALE or CLE don't care CSD ns—10
tCE# setup time CS ns—20
tData hold time DH ns—5
tData setup time DS ns—10
tData transfer from cell to register Rµs—25
tOutput High-Z to RE# low IR ns—0
tRead cycle time RC ns—25
tRE# access time REA ns—20
tRE# high hold time REH ns—10
tRE# high to output hold RHOH [30] ns—15
tRE# high to WE# low RHW ns—100
tRE# high to output High-Z RHZ ns—100
tRE# low to output hold RLOH ns—5
tRE# pulse width RP ns—12
tReady to RE# low RR ns—20
tDevice resetting time (Read/Program/Erase) RST µs— 5/10/500
tWE# high to busy WB ns—100
tWrite cycle time WC ns—25
tWE# high hold time WH ns—10
tWE# high to RE# low WHR ns—60
tWE# pulse width WP ns—12
tWrite protect time WW ns—100
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DC Characteristics5.6
Notes
32. All VCC pins, and VSS pins respectively, are shorted together.
33. Values listed in this table refer to the complete voltage range for VCC and to a single device in case of device stacking.
34. All current measurements are performed with a 0.1 µF capacitor connected between the VCC Supply Voltage pin and the VSS Ground pin.
35. Standby current measurement can be performed after the device has completed the initialization process at power up. Refer to Section 4.1 for more details.
5.7 Pin Capacitance
Note
36. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].
Table 5.2 DC Characteristics and Operating Conditions
Parameter Symbol Test Conditions Min Typ Max Units
Power-On Current
(S34ML02G1, S34ML04G1) ICC0
Power-Up Current
(Refer to Section 4.1)— mA3015
Operating Current
ISequential Read CC1
tRC = see Table 20
CE#=VIL, IOUT = 0 mA — mA3015
IProgram CC2
Normal (S34ML01G1) — mA3015
Normal (S34ML02G1) — mA3015
Normal (S34ML04G1) —— mA30
Cache (S34ML02G1) — mA4020
Cache (S34ML04G1) —— mA40
IErase CC3
— (S34ML01G1) — mA3015
— (S34ML02G1) —— mA30
— (S34ML04G1) — mA3015
IStandby Current, (TTL) CC4
CE# = VIH,
WP# = 0V/Vcc —— mA1
IStandby Current, (CMOS) CC5
CE# = VCC –0.2,
WP# = 0/VCC
— µA5010
IInput Leakage Current LI VIN —— µA±10= 0 to 3.6V
IOutput Leakage Current LO VOUT —— µA±10= 0 to 3.6V
VInput High Voltage IH —V
CC — Vx 0.8 CC V+ 0.3
VInput Low Voltage IL —— V-0.3 CC Vx 0.2
VOutput High Voltage OH IOH —— V2.4= –400 µA
VOutput Low Voltage OL IOL —— V0.4= 2.1 mA
IOutput Low Current (R/B#) OL(R/B#) VOL — mA108= 0.4V
VErase and Program Lockout Voltage LKO ——— V1.8
Table 21. Pin Capacitance (TA = 25°C, f=1.0 MHz)
Parameter Symbol Test Condition Min Max Unit
CInput IN VIN — pF10= 0V
CInput / Output IO VIL — pF10= 0V
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Thermal Resistance5.8
Note
37. Test conditions follow standard methods and procedures for measuring thermal impedance in accordance with EIA/JESD51.
5.9 Program / Erase Characteristics
Notes
38. Typical program time is defined as the time within which more than 50% of the whole pages are programmed (VCC = 3.3V, 25°C).
39. Copy Back Read and Copy Back Program for a given plane must be between odd address pages or between even address pages for the device to meet the program
time (tPROG) specification. Copy Back Program may not meet this specification when copying from an odd address page (source page) to an even address page (target
page) or from an even address page (source page) to an odd address page (target page).
Table 22. Thermal Resistance
Parameter Symbol TS048 VBM063 VBT067 Unit
Theta JA Thermal Resistance
(Junction to Ambient) °C/W393940
Table 23. Program / Erase Characteristics
Parameter Description Min Typ Max Unit
Program Time / Multiplane Program Time [39] tPROG µs— 700200
Dummy Busy Time for Multiplane Program (S34ML02G1, S34ML04G1) tDBSY µs— 10.5
Cache Program short busy time (S34ML02G1, S34ML04G1) tCBSYW — t5
PROG µs
Number of partial Program Cycles i NMain + Sparen the same page —— Cycle4OP
Block Erase Time / Multiplane Erase Time (S34ML02G1, S34ML04G1) tBERS ms— 103.5
Block Erase Time (S34ML01G1) tBERS ms— 32
tRead Cache busy time CBSYR — t3 Rµs
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6. Timing Diagrams
6.1 Command Latch Cycle
Command Input bus operation is used to give a command to the memory device. Commands are accepted with Chip Enable low,
Command Latch Enable High, Address Latch Enable low, and Read Enable High and latched on the rising edge of Write Enable.
Moreover for commands that starts a modify operation (write/ erase) the Write Protect pin must be high.
Figure 12. Command Latch Cycle
6.2 Address Latch Cycle
Address Input bus operation allows the insertion of the memory address. To insert the 27 (×8 Device) addresses needed to access
the 1 Gb, four write cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch
Enable low, and Read Enable High and latched on the rising edge of Write Enable. Moreover, for commands that start a modify
operation (write/ erase) the Write Protect pin must be high.
Figure 13. Address Latch Cycle
tCL
S
tCS
tWP
Command
CLE
CE#
WE#
ALE
I/Ox
tDH tDS
tALHtALS
tCLH
tCH
= Don’t Care
tCLS
tCS
tWC
tALStALStALStALStALS tALHtALHtALHtALH
tWC tWC tWC
tWP tWP
tWH
tWP tWP
tWH
tWH tWH
tDS
Col.
Add1
CLE
CE#
WE#
ALE
I/Ox
tDS tDStDStDS
tDHtDHtDHtDHtDH
Col.
Add2
Row.
Add2
Row.
Add1
Row.
Add3
tALH
= Don’t Care
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6.3 Data Input Cycle Timing
Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is serially, and timed by the
Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read
Enable High, and Write Protect High and latched on the rising edge of Write Enable.
Figure 14. Input Data Latch Cycle
Data Output Cycle Timing (C6.4 LE=L, WE#=H, ALE=L, WP#=H)
Figure 15. Data Output Cycle Timing
Notes
40. Transition is measured at ± 200 mV from steady state voltage with load.
41. This parameter is sampled and not 100% tested.
42. tRHOH starts to be valid when frequency is lower than 33 MHz.
tWC
tCLH
tCH
tWP
tWH
Din
tWH
tDH tDH tDH
tDS
tDS tDS
tWP tWP
CLE
ALE
CE#
I/Ox
WE#
tALS
Din 0 Din final
= Don’t Care
tRC
CE#
RE#
I/Ox
R/B#
tREA
tRR
tuoDtuoDtuoD
tREA
tRHZ
tREA
ZtCH
tCOH
tRHOH
tREH
tRHZ
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Data Output Cycle Timing (ED6.5 O Type, CLE=L, WE#=H, ALE=L)
Figure 16. Data Output Cycle Timing (EDO)
Notes
43. Transition is measured at ± 200 mV from steady state voltage with load.
44. This parameter is sampled and not 100% tested.
45. tRLOH is valid when frequency is higher than 33 MHz.
46. tRHOH starts to be valid when frequency is lower than 33 MHz.
6.6 Page Read Operation
Figure 6.1 Page Read Operation (Read One Page)
Note
47. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data can be read from the page buffer.
tRC
tREHtRP
tREA
tCR
tRLOH
tRR
tREA
tCHZ
tCOH
tRHZ
tRHOH
DoutDout
CE#
RE#
I/Ox
R/B#
= Don’t Care
CE#
WE#
I/Ox
CLE
RE#
R/B#
ALE
00h Col.
Add. 1
Col.
Add. 2
Row
Add. 1
Row
Add. 2 Row
Add. 3 30h Dout N Dout
N +1
Column Address Row Address
tCSD
tWB
tCLR
tR tRC
tRR
Busy
tAR
Dout
M
tRHZ
tWC
= Don’t Care
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Page Read Operation (Interrupted by CE#)6.7
Figure 17. Page Read Operation Interrupted by CE#
Page Read Operation Timing with CE# Don’t Care6.8
Figure 18. Page Read Operation Timing with CE# Don’t Care
CE#
WE#
I/Ox
CLE
RE#
R/B#
ALE
00h Col.
Add. 1
Col.
Add. 2
Row
Add. 1
Row
Add. 2
Row
Add. 3 30h Dout N Dout
N +1
Column Address Row Address
tCSD
tWB
tCLR
tR tRC
tRR
Busy
tAR
tCHZ
tCOH
Dout
N +2
= Don’t Care
00h
Col.
Add. 1 Col.
Add. 2 Row
Add. 1 Row
Add. 2
Dout
N
Dout
N + 1
: Don’t Care (VIH or VIL)
CE#
RE# tREA
tCR
CE# don’t care
CE#
CLE
ALE
WE#
RE#
I/Ox
30h
Dout
N + 2
Dout
N + 3
Dout
N + 4 Dout
N + 5
Dout
M
Dout
M + 1
Dout
M + 2
R/B# tR
tRR
tRC
I/Ox
Dout
Row
Add. 3
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S34ML01G1
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Page Program Operation6.9
Figure 6.2 Page Program Operation
Note
48. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
6.10 Page Program Operation Timing with CE# Don’t Care
Figure 19. Page Program Operation Timing with CE# Don’t Care
CLE
ALE
CE#
RE#
R/B#
I/Ox
WE#
tWC
Serial Data
Input Command Column Address
Row Address Read Status
Command
Program
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
1 up to m byte
Serial Input
Din
N Din
M
tWC
tWB tPROG
tWHR
tWC
tADL
80h Col.
Add1
Col.
Add2
Row.
Add1
Row.
Add2 h07h01 I/O0
Row.
Add3
= Don’t Care
80h Col.
Add. 1 Col.
Add. 2 Row
Add. 1 Row
Add. 2 Din
N
Din
N + 1
Din
M
Din
P
Din
P + 1
Din
R10h
: Don’t Care
CE#
WE# tWP
tCS tCH
CE# don’t care
CE#
CLE
ALE
WE#
RE#
I/Ox Row
Add. 3
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Page Program Operat6.11 ion with Random Data Input
Figure 20. Random Data Input
Notes
49. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
50. For EDC operation only one Random Data Input is allowed at each EDC Unit.
6.12 Random Data Output In a Page
Figure 21. Random Data Output
CLE
ALE
CE#
RE#
R/B#
I/Ox
WE#
80h Din
N
Din
MDin
JDin
K
85h 10h 70h
Serial Data
Input Command
Random Data
Input Command
Column Address Column Address Serial Input Program
Command
Read Status
Command
tPROG
IO0
tWB
Col.
Add1
Col.
Add2
Row
Add1
Row
Add2
Row
Add3
Col.
Add1
Col.
Add2
tADL
Row Address
tWC tWC
tADL
tWC
tWHR
= Don’t Care
CE#
WE#
I/Ox
CLE
RE#
R/B#
ALE
00h Col.
Add. 1
Col.
Add. 2
Row
Add. 1
Row
Add. 2
Row
Add. 3
30h Dout N
Dout
N +1 05h
Col.
Add. 1
Col.
Add. 2
Dout M Dout
M +1
E0h
Column Address Row Address Column Address
tCLR
tWHR
tREA
tWB
tAR tRHW
tR tRC
tRR
Busy
= Don’t Care
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S34ML01G1
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Multiplane Page Program Opera6.13 tion — S34ML02G1 and S34ML04G1
Figure 22. Multiplane Page Program
Notes
51. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
52. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.
Figure 23. Multiplane Page Program (ONFI 1.0 Protocol)
Notes
53. C1A-C2A Column address for page A. C1A is the least significant byte.
54. R1A-R3A Row address for page A. R1A is the least significant byte.
55. D0A-DnA Data to program for page A.
56. C1B-C2B Column address for page B. C1B is the least significant byte.
57. R1B-R3B Row address for page B. R1B is the least significant byte.
58. D0B-DnB Data to program for page B.
59. The block address bits must be the same except for the bit(s) that select the plane.
CLE
ALE
CE#
RE#
R/B#
I/Ox
WE#
R/B#
I/O0~7
Ex.) Address Restriction for Multiplane Page Program
81h 70h IO
Program Confirm
Command (True)
tDBSY
Col Add 1,2 and Row Add 1,2,3
(2112 byte data)
A0 ~ A11: Valid
A12 ~ A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19 ~ A28: Fixed ‘Low’
Serial Data
Input Command Column Address sPage Row Addres to 2112 byte1 up Serial InputData
Program
Command
(Dummy)
11h 10h
Din
NDin
MDin
NDin
M
Col.
Add1
80h Col.
Add2
Row
Add1
Row
Add2 Row
Add3
tWB tPROG
tWB tDBSY
Col.
Add1 Col.
Add2
Row
Add1
Row
Add2 Row
Add3
tWC
Read Staus
Command
tWHR
tPROG
80h Address & Data Input 11h
Col Add 1,2 and Row Add 1,2,3
(2112 byte data)
A0 ~ A11: Valid
A12 ~ A17: Valid
A18: Fixed ‘High’
A19 ~ A28: Valid
tADL
tADL
81h Address & Data Input 10h 70h
(Note 51)
CMD ADDR ADDR ADDRADDR
ADDR
CMD ADDR ADDR ADDRADDR
ADDR
DIN DIN DIN DIN
DIN DIN DIN DIN CMD
CMD
80h C1AC2AD0A
R3A
R2A
R1AD1A... DnA11h
80h C1BC2BD0B
R3B
R2B
R1BD1B... DnB10h
Cycle Type
DQx
SR[6]
Cycle Type
DQx
SR[6]
A
tADL
tADL
tADL
tIPBSY
tADL
tPROG
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Block Erase Operation6.14
Figure 24. Block Erase Operation (Erase One Block)
Multiplane Block Erase6.15 — S34ML02G1 and S34ML04G1
Figure 25. Multiplane Block Erase
Note
60. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.
tWC
CLE
CE#
WE#
ALE
RE#
I/Ox
R/B#
tWB tBERS
BUSY
Auto Block Erase
Setup Command I/O0=0 Successful Erase
I/O0=1 Error in Erase
Row Address
D0h
60h 70h I/O0
Erase Command Read Status
Command
Row Add1 Row Add2 Row Add3
tWHR
= Don’t Care
Row Address
Erase Confirm CommandBlock Erase Setup Command2Block Erase Setup Command1
Read Status Command
Busy
Row Address
Ex.) Address Restriction for Multiplane Block Erase Operation
ALE
CLE
CE#
RE#
R/B#
I/Ox
WE#
R/B#
I/O0~7
tWC
60h
60h
Row Add1,2,3Row Add1,2,3
A12 ~ A17 : Fixed ‘Low’
A18 : Fixed ‘Low’
A19 ~ A28 : Fixed ‘Low’
A12 ~ A17 : Fixed ‘Low’
A18 : Fixed ‘High’
A19 ~ A28 : Valid
Address Address h07h06 D0h
h0Dh06 70h I/O0
Row Add1 Row Add1
Row Add2 Row Add2 3ddA woR3ddA woR
tWC
tWB tBERS
tBERS
tWHR
I/O 1 = 0 Successful Erase
I/O 1 = 1 Error in plane
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Figure 26. Multiplane Block Erase (ONFI 1.0 Protocol)
Notes
61. R1A-R3A Row address for block on plane 0. R1A is the least significant byte.
62. R1B-R3B Row address for block on plane 1. R1B is the least significant byte.
63. The block address bits must be the same except for the bit(s) that select the plane.
6.16 Copy Back Read with Optional Data Readout
Figure 27. Copy Back Read with Optional Data Readout
Copy Back Program Operat6.17 ion With Random Data Input
Figure 28. Copy Back Program with Random Data Input
60h
CLE
WE#
ALE
RE#
IOx R1AR2AR3AD1h 60h R1BR2B
SR[6]
tIEBSY
R3BD0h
tBERS
I/O
R/B#
Busy
tR
(Read Busy time)
Busy
tPROG
(Program Busy time)
00h Source
Add Inputs 35h Data Outputs 85h Target
Add Inputs 10h 70h/
7Bh
SR0/
EDC Reg
Read Status Register/
EDC Register
I/O
R/B#
Busy
tR
(Read Busy time)
Busy
tPROG
(Program Busy time)
00h Source
Add Inputs 35h 85h 2 Cycle
Add Inputs 10h
Unlimited number of repetitions
70h SR0
Read Status Register
85h Target
Add Inputs Data Data
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S34ML02G1
S34ML04G1
Multiplane Copy Back Progr6.18 am — S34ML02G1 and S34ML04G1
Figure 29. Multiplane Copy Back Program
Notes
64. Copy Back Program operation is allowed only within the same memory plane.
65. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
66. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.
Figure 30. Multiplane Copy Back Program (ONFI 1.0 Protocol)
Note
67. C1A-C2A Column address for page A. C1A is the least significant byte.
68. R1A-R3A Row address for page A. R1A is the least significant byte.
69. C1B-C2B Column address for page B. C1B is the least significant byte.
70. R1B-R3B Row address for page B. R1B is the least significant byte.
71. The block address bits must be the same except for the bit(s) that select the plane.
I/Ox
R/B#
R/B#
I/Ox
tR tR
tDBSY tPROG
1
1
00h Add. (5 cycles) 35h
Col. Add. 1, 2 and Row Add. 1, 2, 3
Source Address on Plane 0
00h Add. (5 cycles) 35h
Col. Add. 1, 2 and Row Add. 1, 2, 3
Source Address on Plane 1
85h Add. (5 cycles) 11h
Col. Add. 1, 2 and Row Add. 1, 2, 3
Destination Address
A0 ~ A11 : Fixed ‘Low’
A12 ~ A17 : Fixed ‘Low’
A18 : Fixed ‘Low’
A19 ~ A28 : Fixed ‘Low’
81h Add. (5 cycles)
Col. Add. 1, 2 and Row Add. 1, 2, 3
Destination Address
A0 ~ A11 : Fixed ‘Low’
A12 ~ A17 : Valid
A18 : Fixed ‘High’
A19 ~ A28 : Valid
10h 70h
Plane 0
(1) (3)
Data Field Spare Field
Plane 1
(2) (3)
Data Field Spare Field
Source Page
Source Page
Target Page
Target Page (1) : Copy Back Read on Plane 0
(2) : Copy Back Read on Plane 1
(3) : Multiplane Copy Back Program
(Note 65)
85h
CLE
WE#
ALE
RE#
IOx C1AC2 AR1AR2AR3A11h 85h C1BC2B
SR[6]
A
tIPBSY
R1BR2
BR3B10h
tPROG
Document Number: 002-00676 Rev. *W
Page 47 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Read Status Register Timing6.19
Figure 31. Status / EDC Read Cycle
Read Status Enhanced Timing6.20
Figure 32. Read Status Enhanced Timing
Reset Operation Timing6.21
Figure 33. Reset Operation Timing
tCLS
tCLR
tCLH
tCS
tCH
tWP
tWHR
tCEA
tDS tREA
tCHZ
tCOH
tRHZ
tRHOH
70h or 7Bh Status Output
tDH tIR
CE#
WE#
I/Ox
CLE
RE#
= Don’t Care
CLE
ALE
WE#
I/O0-7
RE#
78h SRR1 R2 R3
tWHR
tAR
FF
tRST
WE#
ALE
CLE
RE#
I/O7:0
R/B#
Document Number: 002-00676 Rev. *W
Page 48 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Read Cache6.22
Figure 34. Read Cache Operation Timing
Figure 35. “Sequential” Read Cache Timing, Start (and Continuation) of Cache Operation
Page N
Page N
Page N + 1
Page N + 2
Page N + 1
Page N + 3
Page N + 2 Page N + 3
Data Cache
Page Buffer
Cell Array
Page N + 3Page N + 2Page N + 1Page N
1
1
2
3
34
5
56
7
789
CE#
CLE
ALE
WE#
RE#
I/Ox
R/B#
CE#
CLE
ALE
WE#
RE#
I/Ox
R/B#
A
A
123
7 8 96
00h Col.
Add 1
Col.
Add 2
Column Address 00h
Row
Add 1
Row
Add 2
Page Address N
30h 31h Dout
0
Dout
1Dout 31h Dout
0
Dout
1
Col. Add. 0
Page N + 2
3Fh Dout
0
Dout
1Dout
31h Dout
0
Dout Dout
1Dout
tWC
tWB
tR tCBSYR
tWB
tRR
tWB
Col. Add. 0 Page N Col. Add. 0
Page N + 1
tRC tRC
tRR
tCBSYR
SYRtCB
tWB
tRR
tRC
SYRtCB
tWB
tRR
tRC
Col. Add. 0
Page N + 3
= Don’t Care
Row
Add 3
4
5
5
CMD CMD Dout Dout Dout CMD Dout
0Dh03 31h ... Dn D031h
Cycle Type
I/Ox
SR[6]
tRR
As defined for
Read
tRR
tWB
tR
tWB
tCBSYR
tWB
tCBSYR
Document Number: 002-00676 Rev. *W
Page 49 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Figure 36. “Random” Read Cache Timing, Start (and Continuation) of Cache Operation
Figure 37. Read Cache Timing, End Of Cache Operation
Cache Program6.23
Figure 38. Cache Program
Cycle Type
I/Ox
SR[6]
Cycle Type
I/Ox
SR[6]
As defined
or Readf
A
CMD ADDR ADDR ADDRADDR
tWB
tR
A
ADDR CMD
00h C1 C2 R2R1 R3 31h
CMD
30h
Dout Dout Dout
D0 . . . Dn
Page N
Page R
CMD ADDR ADDR ADDR ADDR ADDR CMD
00h C1 C2 R1 R2 R3 31h
Dout
D0
tRR tWB
tCBSYR
tRR
tWB
tCBSYR
tRR
Cycle Type
I/Ox
SR[6]
As defined for
Read Cache
(Sequential or Random)
Dout Dout Dout CMD
tWB
tCBSYR
D0 . . . Dn 3Fh
CMD
31h
Dout Dout Dout
D0 . . . Dn
tRR tWB
tCBSYR
tRR
Column Address Row Address
tWB
Column Address Row Address
tCBSYW
1
1
CLE
ALE
CE#
RE#
R/B#
I/Ox
WE#
tCBSYW
Din
NDin
MDin
NDin
M
Column Address Row Address
10h
Din
NDin
M70h
tPROG
80h
Col.
Add1
Col.
Add2
Row.
Add1
Row.
Add2
Row.
Add3
15h 80h 15h
80h
Col.
Add1
Col.
Add2
Row.
Add1
Row.
Add2
Row.
Add3
tADL
Status
tWC
Col.
Add1
Col.
Add2
Row.
Add1
Row.
Add2
Row.
Add3
tWC
tWC
CLE
ALE
CE#
RE#
R/B#
I/Ox
WE#
Document Number: 002-00676 Rev. *W
Page 50 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Multiplane Cache Program6.24 — S34ML02G1 and S34ML04G1
Figure 39. Multiplane Cache Program
Notes
72. Read Status Register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.
73. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.
CLE
ALE
CE#
RE#
R/B#
I/Ox
WE#
Column Address Row Address
tWB
tWC
Column Address Row Address
tCBSYW
1
1
tDBSY
80h Col.
Add1 Col.
Add2
Row
Add1
Row
Add2 Row
Add3
81h Col.
Add1 Col.
Add2
Row
Add1
Row
Add2 Row
Add3
15h
Din
NDin
M
11h
Din
NDin
M
Column Address Row Address
tWC
Column Address Row Address
tPROG
tDBSY
11h
Din
NDin
M
80h 81h Col.
Add1 Col.
Add2
Row
Add1
Row
Add2 Row
Add3
10h
Din
NDin
M
tWB
tADL tADL
tWB
Status
70h
80h Address Input Data Input 11h 81h Address Input Data Input 15h
Command Input
tDBSY
Return to 1
Repeat a max of 63 times
80h Address Input Data Input 11h 81h Address Input Data Input 10h
Command Input
tDBSY tPROG
tCBSYW
RY/BY#
RY/BY#
1
1
CLE
ALE
CE#
RE#
R/B#
I/Ox
WE#
Col.
Add1 Col.
Add2
Row
Add1
Row
Add2 Row
Add3
A0~A11: Valid
A12~A17: Fixed ‘Low’
A19~A28: Fixed ‘Low’
A18: Fixed ‘Low’
A0~A11: Valid
A18: Fixed ‘High’
A19~A28: Valid
A12~A17: Valid
A0~A11: Valid
A18: Fixed ‘High’
A19~A28: Valid
A12~A17: Valid
A0~A11: Valid
A18: Fixed ‘Low’
A19~A28: Fixed ‘Low’
A12~A17: Fixed ‘Low’
Document Number: 002-00676 Rev. *W
Page 51 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Figure 40. Multiplane Cache Program (ONFI 1.0 Protocol)
Notes
74. The block address bits must be the same except for the bit(s) that select the plane.
75. Read Status register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.
CLE
ALE
CE#
RE#
R/B#
IOx
WE#
Column Address Row Address
tWB
tWC
Column Address Row Address
tCBSYW
1
1
CLE
ALE
CE#
RE#
R/B#
IOx
WE#
tDBSY
11h
Din
NDin
M
80h Col.
Add1 Col.
Add2
Row
Add1
Row
Add2 Row
Add3
80h Col.
Add1 Col.
Add2
Row
Add1
Row
Add2 Row
Add3
15h
Din
NDin
M
Column Address Row Address
tWC
Column Address Row Address
tPROG
tDBSY
11h
Din
NDin
M
80h Col.
Add1 Col.
Add2
Row
Add1
Row
Add2 Row
Add3
80h Col.
Add1 Col.
Add2
Row
Add1
Row
Add2 Row
Add3
10h
Din
NDin
M
tWB
tADL tADL
tWB
Status
70h
80h Address Input Data Input 11h 80h Address Input Data Input 15h
Command Input
t
DBSY
Return to 1
Repeat a max of 63 times
80h Address Input Data Input 11h 80h Address Input Data Input 10h
Command Input
t
DBSY
t
PROG
t
CBSYW
RY/BY#
RY/BY#
1
1
Document Number: 002-00676 Rev. *W
Page 52 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Read ID Operation Timing6.25
Figure 41. Read ID Operation Timing
Read ID2 Operation Timing6.26
Figure 42. Read ID2 Operation Timing
Notes
76. 4-cycle address is shown for the S34ML01G1. For S34ML02G1 and S34ML04G1, insert an additional address cycle of 00h.
77. If Status Register polling is used to determine completion of the Read ID2 operation, the Read Command (00h) must be issued before ID2 data can be read from the flash.
CE#
WE#
CLE
RE#
ALE
tWHR
tAR
tREA
I/Ox
01h F1h 00h 1Dh
1 Gb Device
I/Ox
01h DAh 90h 95h
2 Gb Device
44h
I/Ox
01h DCh 90h 95h
4 Gb Device
54h
Read ID
Command
Address 1
Cycle
Maker
Code
Device
Code
3rd Cycle 5th Cycle4th Cycle
90h
90h
09h
00h
00h
00h
90
CE#
WE#
CLE
RE#
ALE
tR
Read ID2
Commands
4 Cycle Address 2nd Cycle1st Cycle 3rd Cycle 5th Cycle4th Cycle
I/Ox
Read ID2
Confirm
Command
30h 65h 00h 00h 02h 02h 00h 30h ID2 DataID2 DataID2 DataID2 DataID2 Data
R/B#
Busy
(Note 76)
Document Number: 002-00676 Rev. *W
Page 53 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Read ONFI Signature Timing6.27
Figure 43. ONFI Signature Timing
Read Parameter Page Timing6.28
Figure 44. Read Parameter Page Timing
Note
78. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data can be read from the page buffer.
6.29 OTP Entry Timing
Figure 45. OTP Entry Timing
90h
CLE
WE#
ALE
RE#
IO0~7 4Fh20h
t
46h4Eh
WHR
49h
tREA
00h
CLE
WE#
ALE
RE#
IO0-7 P1
R/B#
......
tR
1
P01
P10
P00
ECh
CLE
ALE
WE#
I/O0-7
29h 17h 19h04h
Document Number: 002-00676 Rev. *W
Page 54 of 70
S34ML01G1
S34ML02G1
S34ML04G1
Power On and Data Protection Timing6.30
Figure 46. Power On and Data Protection Timing
Note
79. VTH = 1.8 Volts.
6.31 WP# Handling
Figure 47. Program Enabling / Disabling Through WP# Handling
Figure 48. Erase Enabling / Disabling Through WP# Handling
VCC
V
)Vcc(min
100 µs max
Invalid
0V
CE
V
IL
V
Operation
5 ms max
IH
V
IL
WP
Ready/Busy
don’t
care
don’t
care
don’t
care
Vcc(min)
VTH TH
t
80h 10h
WW
WE#
I/Ox
WP#
R/B#
t
80h 10h
WW
WE#
I/Ox
WP#
R/B#
t
60h D0h
WW
t
60h D0h
WW
WE#
I/Ox
WP#
R/B#
WE#
WP#
R/B#
I/Ox
Document Number: 002-00676 Rev. *W
Page 55 of 70
S34ML01G1
S34ML02G1
S34ML04G1
7. Physical Interface
7.1 Physical Diagram
7.1.1 48-Pin Thin Small Outline Package (TSOP1)
Figure 49. TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
5006 \ f16-038 \ 6.5.13
TS/TSR 48PACKAGE
MO-142 (D) DDJEDEC
MAXNOMMINSYMBOL
1.20------A
0.15---0.05A1
1.051.000.95A2
0.230.200.17b1
0.270.220.17b
0.16---0.10c1
0.21---0.10c
20.2020.0019.80D
18.5018.4018.30D1
12.1012.0011.90E
0.50 BASICe
0.700.600.50L
O8---0˚
0.20---0.08R
48N
NOTES:
DIMENSIONS ARE IN MILLIMETERS (mm).1.
(DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1994).
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS
ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD
PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07mm.
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM
THE SEATING PLANE.
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
Document Number: 002-00676 Rev. *W
Page 56 of 70
S34ML01G1
S34ML02G1
S34ML04G1
63-Pin Ball Grid Array (BGA)7.1.2
Figure 50. VBM063 — 63-Pin BGA, 11 mm x 9 mm Package
g5011\ 16-038.25 \ 6.5.13
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3, SPP-020.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE TOTAL NUMBER OF POPULATED SOLDER
BALL POSITIONS FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 “SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW “SD” OR “SE” = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, “SD” = eD/2 AND “SE” = eE/2.
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
VBM 063PACKAGE
M0-207(M)JEDEC
11.00 mm x 9.00 mm NOM
PACKAGE
NOTEMAXNOMMINSYMBOL
PROFILE1.00------A
BALL HEIGHT------0.25A1
BODY SIZE11.00 BSC.D
BODY SIZE9.00 BSC.E
MATRIX FOOTPRINT8.80 BSC.D1
MATRIX FOOTPRINT7.20 BSC.E1
MATRIX SIZE D DIRECTION12MD
MATRIX SIZE E DIRECTION10ME
BALL COUNT63n
 BALL DIAMETER0.500.450.40b
BALL PITCH0.80 BSC.eE
BALL PITCH0.80 BSC.eD
SOLDER BALL PLACEMENT0.40 BSC.SD
SOLDER BALL PLACEMENT0.40 BSC.SE
DEPOPULATED SOLDER BALLSA3-A8,B2-B8,C1,C2,C9,C10
D1,D2,D9,D10,E1,E2,E9,E10
F1,F2,F9,F10,G1,G2,G9,G10
H1,H2,H9,H10,J1,J2,J9,J10
K1,K2,K9,K10
L3-L8,M3-M8
Document Number: 002-00676 Rev. *W
Page 57 of 70
S34ML01G1
S34ML02G1
S34ML04G1
8. System Interface
To simplify system interface, CE# may be unasserted during data loading or sequential data reading as shown in Figure 51. By
operating in this way, it is possible to connect NAND flash to a microprocessor.
Figure 51. Program Operation with CE# Don't Care
Figure 52. Read Operation with CE# Don't Care
Figure 53. Page Programming Within a Block
CE# don’t care
h01 tupnI ataD (5 Cycle).ddA tratS h08 Data Input
CLE
CE#
WE#
ALE
I/Ox
CE# don’t care
h03h00
CLE
CE#
RE#
ALE
R/B#
WE#
I/Ox
)laitneuqes(tuptuO ataD(5 Cycle).ddA tratS
tR
Page 63
Page 31
Page 2
Page 1
Page 0
Page 63
Page 31
Page 2
Page 1
Page 0
(64)
(32)
(3)
(2)
(1)
(64)
(1)
(3)
(32)
(1)
Data Register Data Register
From the LSB page to MSB page
DATA IN : Data (1) Data (64)
Ex.) Random page program (Optional)
DATA IN : Data (1) Data (64)
Document Number: 002-00676 Rev. *W
Page 58 of 70
S34ML01G1
S34ML02G1
S34ML04G1
9. Error Management
9.1 System Bad Block Replacement
Over the lifetime of the device, additional Bad Blocks may develop. In this case, each bad block has to be replaced by copying any
valid data to a new block. These additional Bad Blocks can be identified whenever a program or erase operation reports “Fail” in the
Status Register.
The failure of a page program operation does not affect the data in other pages in the same block, thus the block can be replaced by
re-programming the current data and copying the rest of the replaced block to an available valid block. Refer to Table 24 and
Figure 54 for the recommended procedure to follow if an error occurs during an operation.
Figure 54. Bad Block Replacement
Notes
80. An error occurs on the Nth page of Block A during a program operation.
81. Data in Block A is copied to the same location in Block B, which is a valid block.
82. The Nth page of block A, which is in controller buffer memory, is copied into the Nth page of Block B.
83. Bad block table should be updated to prevent from erasing or programming Block A.
Table 24. Block Failure
Operation Recommended Procedure
Block ReplacementErase
Block ReplacementProgram
ECC (1 bit / 512+16 byte)Read
Data
buffer memory of the controller
N page
FFh
Data
FFh
Failure
th
N page
th
Block BBlock A
[80
[81
[82
Document Number: 002-00676 Rev. *W
Page 59 of 70
S34ML01G1
S34ML02G1
S34ML04G1
9.2 Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are
valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by
a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad Block Information is
written prior to shipping. Any block where the 1st byte in the spare area of the 1st or 2nd or last page does not contain FFh is a Bad
Block. That is, if the first page has an FF value and should have been a non-FF value, then the non-FF value in the second page or
the last page will indicate a bad block.The Bad Block Information must be read before any erase is attempted, as the Bad Block
Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information, it is
recommended to create a Bad Block table following the flowchart shown in Figure 55. The host is responsible to detect and track
bad blocks, both factory bad blocks and blocks that may go bad during operation. Once a block is found to be bad, data should not
be written to that block.The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Figure 55. Bad Block Management Flowchart
Note
84. Check for FFh at the 1st byte in the spare area of the 1st, 2nd, and last pages.
Yes
Yes
No
No
rtSta
ddress=Block A
ck 0Blo
Data
=FFh?
Last
Block?
End
Increment
Block Address
Update
Bad Block Table
[84]
Document Number: 002-00676 Rev. *W
Page 60 of 70
S34ML01G1
S34ML02G1
S34ML04G1
10. Ordering Information
The ordering part number is formed by a valid combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Notes
85. BGA package marking omits the leading “S34” and the Packing Type designator from the ordering part number.
86. A, V, B: 4G ×16 (04 in bus width) available, but for other ×16 versions contact factory.
000IFT00104GS34ML
Packing Type
0 = Tray
3 = 13” Tape and Reel
Model Number
00 = Standard Interface / ONFI (×8)
00 = Standard Interface (×16)
01 = ONFI (×16)
Temperature Range
I = Industrial (–40°C to + 85°C)
A = Industrial with AECQ-100 and GT Grade (-40˚C to +85˚C)
V = Industrial Plus (–40°C to + 105°C)
B = Industrial Plus with AECQ-100 and GT Grade (-40˚C to +105˚C)
Materials Set
F = Lead (Pb)-free
H = Lead (Pb)-free and Low Halogen
Package
B = BGA
T = TSOP
Bus Width
00 = ×8 NAND, single die
04 = ×16 NAND, single die
Technology
1 = Cypress NAND Revision 1 (4x nm)
Density
01G = 1 Gb
02G = 2 Gb
04G = 4 Gb
Device Family
S34ML - 3V
Cypress SLC NAND Flash Memory for Embedded
Valid Combinations
Device
Family Density Technology Bus
Width
Package
Type
Temperature
Range
Additional
Ordering Options
Packing
Type
Package
Description
S34ML
01G
TF, BH00, 041 I
A, V, B [86] TSOP, BGA0, 300, 01 [85]02G
04G
Document Number: 002-00676 Rev. *W
Page 61 of 70
S34ML01G1
S34ML02G1
S34ML04G1
11. Document History Page
Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
Document Number: 002-00676
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
– 04/16/2012XILA** Initial release
– 05/04/2012XILA*A Global:
Removed Spansion Confidential designation
Read Status Enhanced:
Updated text
Command Set:
Updated table: Command Set
Read ID:
Updated table: Read ID for Supported Configurations
Legacy Read ID:
Removed section heading: Legacy Read ID
Valid Blocks:
Updated table: Valid Blocks
– 05/23/2012XILA*B Global:
Changed Cache Read to Read Cache
General Description:
Updated text
Block Diagram:
Combined three block diagrams into one
Addressing:
Updated Address Cycle Map tables
Mode Selection:
Updated table: Busy Time in Read; updated note
Command Set:
Updated table
Added ‘Supported in S34ML01G1’ column
Copy Back Program:
Updated text
Multiplane Copy Back Program:
Updated text
Special Read for Copy Back:
Updated text
Read EDC Status Register: Updated text
Read ID:
Read ID Byte 4 Description — S34ML01G1 table: changed Number of I/O to
Spare Area Size (byte / 512 byte)
Absolute Maximum Ratings:
Updated Input or Output Voltage and Supply Voltage rows
Program / Erase Characteristics:
Updated table
– 05/24/2012XILA*C Performance:
Updated Performance section
Read ID:
Updated Read ID for Supported Configurations table
Modified tables: Read ID Byte 3 Description, Read ID Byte 4 Description –
S34ML01G1, Read ID Byte 4 Description – S34ML02G1 and S34ML04G1,
Read ID Byte 5 Description – S34ML02G1 and S34ML04G1
AC Test Conditions:
Updated table
Document Number: 002-00676 Rev. *W
Page 62 of 70
S34ML01G1
S34ML02G1
S34ML04G1
– 05/31/2012XILA*D Global:
Data Sheet designation updated from Advance Information to Preliminary
Distinctive Characteristics/Performance:
Updated Distinctive Characteristics and Performance section
Pin Description:
Updated Pin Description table
Addressing:
Updated Address Cycle Map — 1 Gb Device table
Updated Address Cycle Map — 2 Gb Device table
Updated Address Cycle Map — 4 Gb Device table
Command Set:
Updated Command Set table
– 07/13/2012XILA*E Performance:
Corrected Page Read/Program - Sequential access: from 25ns (Max) to 25 ns
(Min)
Connection Diagram:
Corrected figure: 48-Pin TSOP1 Contact x8 Device
Mode Selection:
Mode selection table: corrected Busy Time in Read, WE# from High to X;
corrected Notes
Command Set:
Command Set table: added ONFI, Extended Read Status, and Read ID2
commands
Note that all ONFI information is in the Advanced Information designation
Copy Back Program:
Updated section
Multiplane Copy Back Program — S34ML02G1 and S34ML04G1:
Updated section
Read ID2:
Added section
Read ONFI Signature:
Added Section
Note that all ONFI information is in the Advanced Information designation
Read Parameter Page:
Added section
Note that all ONFI information is in the Advanced Information designation
One-Time Programmable (OTP) Entry:
Added section
Note that all ONFI information is in the Advanced Information designation
Program/Erase Characteristics:
Added note to table
Timing Diagrams:
Rearranged section
Added timing diagrams: Multiplane Block Erase (ONFI 1.0 Protocol), Multiplane
Cache Program (ONFI 1.0 Protocol), Read ID2 Operation Timing, ONFI
Signature Timing, Read Parameter Page Timing, Read ID2 Operation Timing,
OTP Entry Timing
Updated timing diagrams: Page Read Operation (Read One Page), Page Read
Operation Intercepted by CE#, Page Read Operation Timing with CE# Don’t
Care, Page Program Operation, Page Program Operation Timing with CE#
Don’t Care, Random Data Input, Random Data Output, Multiplane Page
Program, Block Erase Operation (Erase One Block), Reset Operation Timing,
Read Cache Operation Timing, Cache Program, Multiplane Cache Program,
Read ID Operation Timing
Note that all ONFI information is in the Advanced Information designation
11. Document History Page (Continued)
Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
Document Number: 002-00676
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 002-00676 Rev. *W
Page 63 of 70
S34ML01G1
S34ML02G1
S34ML04G1
– 07/23/2012XILA*F Command Set:
Command Set table: changed Read ONFI Signature to ‘Yes’ for Supported on
S34ML01G1
Read Parameter Page:
Parameter Page Description table: changed Byte 254-255 Values
Valid Blocks:
Valid Blocks table: removed Note 1 and Note 3
DC Characteristics:
DC Characteristics and Operating Conditions table:
corrected Output low voltage Test Conditions
corrected Output low current (R/B#) Typ and Max values
– 08/02/2012XILA*G Global:
Note that all ONFI information is now in the Preliminary designation
Read Parameter Page:
Parameter Page Description table: updated values for bytes 6-7, 108-109, 254-
255
Physical Interface:
Added TSOP (2 CE 8 Gb) diagram
Added BGA diagram
Ordering Information:
Updated data
Appendix A:
Added Errata
– 08/29/2012XILA*H Global:
Removed 8 Gb data
Added x16 I/O bus width data
– 09/06/2012XILA*I Connection Diagram:
48-Pin TSOP1 Contact x8, x16 Devices figure: corrected pinouts
63-VFBGA Contact, x16 Device (Balls Down, Top View) figure: corrected
pinouts, removed note
Command Set:
Reorganized section
AC Characteristics:
Corrected TALS Min and TDS Min
11. Document History Page (Continued)
Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
Document Number: 002-00676
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 002-00676 Rev. *W
Page 64 of 70
S34ML01G1
S34ML02G1
S34ML04G1
– 10/01/2012XILA*J Addressing
Address Cycle Map -1 Gb Device: corrected data
Address Cycle Map -2 Gb Device: corrected data
Address Cycle Map -4 Gb Device: corrected data
Multiplane Program -S34ML02G1 and S34ML04G:
Added text
Block Erase
Added text
Multiplane Block Erase -S34ML02G1 and S34ML04G1:
Added text
Copy Back Program:
Added text
Multiplane Copy Back Program — S34ML02G1 and S34ML04G:
Added text
Multiplane Cache Program — S34ML02G1 and S34ML04G1:
Added text
Read Parameter Page:
Parameter Page Description table:
corrected Electrical Parameters Block values for bytes 129-130 and bytes 131-
132
corrected Vendor Block values for bytes 254-255
Multiplane Page Program Operation — S34ML02G1 and S34ML04G1:
Added note to Multiplane Page Program figure
Added note to Multiplane Page Program (ONFI 1.0 Protocol) figure
Multiplane Block Erase — S34ML02G1 and S34ML04G1:
Added note to Multiplane Block Erase figure
Updated note to Multiplane Block Erase (ONFI 1.0 Protocol) figure
Multiplane Copy Back Program — S34ML02G1 and S34ML04G1:
Added note to Multiplane Copy Back Program figure
Multiplane Copy Back Program (ONFI 1.0 Protocol) figure: corrected IOx values
Updated note
Multiplane Cache Program — S34ML02G1 and S34ML04G1:
Added note to Multiplane Cache Program figure
Multiplane Cache Program (ONFI 1.0 Protocol) figure:
removed address values from RY/BY#
changed IOx value from F1h to 70h
updated note
AC Characteristics:
AC Characteristics table: added CE# access time
– 11/02/2012XILA*K Global:
Data Sheet designation updated from Preliminary to Full Production
Absolute Maximum Ratings:
Added note
Ordering Information:
Valid Combinations table: added to Additional Ordering Options
11. Document History Page (Continued)
Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
Document Number: 002-00676
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 002-00676 Rev. *W
Page 65 of 70
S34ML01G1
S34ML02G1
S34ML04G1
– 12/19/2012XILA*L Command Set:
Added Page Reprogram command
Changed ReadID2 to be “Supported on S34ML01G1”
Page Reprogram:
Moved section
Added paragraph
Copy Back Program:
Added paragraph
Reset:
Updated paragraph
ReadID2:
Updated paragraph
Read Parameter Page:
Parameter Page Description table:
fixed Values of Bytes 6-7 and 254-255
fixed Description of Bytes 129-130 and 131-132
DC Characteristics:
DC Characteristics and Operating Conditions table:
Power-On Reset Current (S34ML01G1): removed row
Operating Current: removed ICC1: tRC = tRC (min); ICC2: removed Cache
(S34ML01G1)
Input Leakage Current: removed VIN = 0 to VCC (max)
Output Leakage Current: removed VOUT = 0 to VCC (max)
Output High Voltage: removed IOH = -100 µA, IOH = 100 µA, and IOH = 400
µA rows
Output Low Voltage: removed IOL = -100 µA row
Output Low Current (R/B#): removed VOL = 0.1V row
AC Characteristics:
AC Characteristics table: added note
Page Read Operation:
Page Read Operation (Read One Page) figure: added note
Read ID2 Operation Timing:
Read ID2 Operation Timing figure:
replaced tWHR with tR and added R/B# timing signal
added note
Bad Block Management:
Added text
Bad Block Management Flowchart: updated note
11. Document History Page (Continued)
Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
Document Number: 002-00676
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 002-00676 Rev. *W
Page 66 of 70
S34ML01G1
S34ML02G1
S34ML04G1
– 02/28/2013XILA*M Command Set:
Command Set table: removed ‘Nth Page’ entries
Page Program:
Added paragraph
Multiplane Program — S34ML02G1 and S34ML04G1:
Added paragraph
Page Reprogram — S34ML02G1 and S34ML04G1: Added paragraph
Block Erase:
Added paragraph
Multiplane Block Erase — S34ML02G1 and S34ML04G1:
Added paragraph
Copy Back Program:
Added paragraph
Multiplane Copy Back Program — S34ML02G1 and S34ML04G1:
Added paragraph
Cache Program — S34ML02G1 and S34ML04G: Added paragraph
Multiplane Cache Program — S34ML02G1 and S34ML04G1
Added paragraph
Read Parameter Page:
Added paragraph
Electrical Characteristics:
Valid Blocks table: updated table
AC Characteristics:
AC Characteristics table: corrected Min value for tCLS and Max value for tCEA
Read Status Cycle Timing:
status / EDC Read Cycle figure: removed Note
– 03/07/2013XILA*N Ready/Busy:
Updated section
Corrected Ready/Busy Pin Electrical Application figure
11. Document History Page (Continued)
Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
Document Number: 002-00676
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 002-00676 Rev. *W
Page 67 of 70
S34ML01G1
S34ML02G1
S34ML04G1
– 08/09/2013XILA*O Distinctive Characteristics:
Security -removed Serial number (unique ID)
Operating Temperature: removed Commercial and Extended temperatures
Performance:
Updated Reliability
General Description:
Updated section
Removed bullet: Serial number (unique identifier)
Addressing:
Appended Note in all Address Cycle Map tables
Added text to Bus Cycle column in all Address Cycle Map tables
Mode Selection:
Updated Mode Selection table
Command Set:
Command Set table:
updated Acceptable Command during Busy column
Changed status of Cache Program (End) and Cache Program (Start) /
(Continue) to ‘Supported on S34ML01G1’
Page Read:
Updated section
Page Program:
Changed sentence “In addition, pages must be sequentially programmed within
a block.” to “Pages may be programmed in any order within a block.”
Multiplane Program — S34ML02G1 and S34ML04G1:
Changed sentence “In addition, pages must be programmed sequentially within
a block.” to “Pages may be programmed in any order within a block.”
Page Reprogram — S34ML02G1 and S34ML04G1:
Corrected Page Reprogram figure
Corrected Page Reprogram with Data Manipulation figure
Copy Back Program:
Updated section
Read Status Enhanced — S34ML02G1 and S34ML04G1:
Updated section
Read Status Register Field Definition:
Updated Status Register Coding table
Cache Program:
Removed S34ML02G1 and S34ML04G1 from heading
Read ID:
Read ID Bytes: updated Description
Read Parameter Page:
Parameter Page Description table: corrected Values for Bytes 8-9 and 254-255
Absolute Maximum Ratings:
Updated Absolute Maximum Ratings table
Multiplane Page Program Operation — S34ML02G1 and S34ML04G1:
Updated Multiplane Page Program figure
Updated Multiplane Page Program (ONFI 1.0 Protocol)
Copy Back Read with Optional Data Readout:
Corrected Copy Back Read with Optional Data Readout figure
Copy Back Program Operation With Random Data Input:
Updated Copy Back Program Operation With Random Data Input figure
Read Status Register Timing:
Removed Read Status Enhanced Cycle figure
Read Status Enhanced Timing:
Removed Read Status Timing figure
11. Document History Page (Continued)
Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
Document Number: 002-00676
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 002-00676 Rev. *W
Page 68 of 70
S34ML01G1
S34ML02G1
S34ML04G1
– 08/09/2013XILA*O (Cont’d) Read Cache:
Updated Read Cache Operation Timing figure
Removed Cache Timing heading
Cache Program:
Updated Cache Program figure
Multiplane Cache Program — S34ML02G1 and S34ML04G1:
Updated Multiplane Cache Program figure
Updated Multiplane Cache Program (ONFI 1.0 Protocol) figure
Read Parameter Page Timing:
Added Note to Read Parameter Page Timing figure
One-Time Programmable (OTP) Entry:
Added Note stating that the OTP feature in the S34ML01G1 does not have non-
volatile protection
Electrical Characteristics:
Absolute Maximum Ratings table: removed Ambient Operating Temperature
(Commercial Temperature Range) and Ambient Operating Temperature
(Extended Temperature Range)
Physical Interface:
Updated figures:
TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
VBM063 — 63-Pin BGA, 11 mm x 9 mm Package
System Interface:
Updated Read Operation with CE# Don't Care figure
Ordering Information:
Updated Materials Set: H = Low Halogen to H = Lead (Pb)-free and Low
Halogen
Added Note to Valid Combinations table
– 02/10/2014XILA*P Distinctive Characteristics:
Operating Temperature: Added Automotive
Read ID:
Updated section
Ordering Information:
Temperature Range: Added A, V, B
Valid Combinations:
Temperature Range: Added A, V, B
11/02/2015XILA4963050*Q Updated to Cypress template.
04/25/2016XILA5160512*R Updated Command Set:
Updated Read Parameter Page:
Updated description.
Updated Electrical Characteristics:
Added Recommended Operating Conditions.
Updated DC Characteristics:
Replaced “VCC supply Voltage (erase and program lockout)” with “Erase and
Program Lockout voltage” in “Parameter” column corresponding to VLKO.
Updated Ordering Information:
Updated details under Temperature Range.
Updated to new template.
08/30/2016XILA5409174*S Updated Performance:
Updated details under “Reliability”.
05/16/2017GNKK5738855*T Updated the Cypress logo and copyright information.
11. Document History Page (Continued)
Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
Document Number: 002-00676
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 002-00676 Rev. *W
Page 69 of 70
S34ML01G1
S34ML02G1
S34ML04G1
12/21/2017MNAD5995650*U Updated Electrical Characteristics:
Added Thermal Resistance.
Updated Timing Diagrams:
Updated Multiplane Cache Program — S34ML02G1 and S34ML04G1:
Updated Figure 39 on page 51.
Updated to new template.
03/20/2018MNAD6104589*V No technical updates.
Completing Sunset Review.
11. Document History Page (Continued)
Document Title: S34ML01G1/S34ML02G1/S34ML04G1, 1 Gb/2 Gb/4 Gb, 3 V, SLC NAND Flash for Embedded
Document Number: 002-00676
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
*W MNAD 05/03/2019 Updated to SkyHigh format
Document Number: 002-00676 Rev. *W
Page 70 of 70