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FEATURES
§ Real time clock keeps track of hundredths of
seconds, seconds, minutes, hours, days, date
of the month, months, and years
§ Adjusts for months with fewer than 31 days
§ Automatic leap year correction valid up to
2100
§ No address space required to communicate
with RTC
§ Provides nonvolatile controller functions for
battery backup of SRAM
§ Supports redundant battery attachment for
high–reliability applications
§ Full ±10% VCC operating range
§ +3.3 volt or +5 volt operation
§ Industrial (–45°C to +85°C) operating
temperature ranges available
§ Drop in replacement for DS1215
ORDERING INFORMATION
DS1315XX-XX
33-3.3 volt operation
5-5 volt operation
blank-commercial temp range
N-industrial temp range
blank-16-pin DIP
S-16-pin SOIC
E-20-pin TSSOP
PIN ASSIGNMENT
DS1315
Phantom Time Chip
www.dalsemi.com
{
16-Pin DIP (300-mil)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC1
V
CC0
RST
OE
CEI
CEO
ROM/RAM
X1
X2
WE
GND
D
Q
GND
20-Pin TSSOP
X1
X2
WE
NC
GND
NC
D
Q
GND
9
1
2
3
4
5
6
7
8
10
20
19
18
17
16
15
14
13
12
11
VCC1
VCC0
NC
RST
OE
NC
CEI
CEO
ROM/RAM
16-Pin SOIC (300-mil)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC1
V
CC0
RST
OE
CEI
CEO
ROM/RAM
X1
X2
WE
GND
D
Q
GND
DS1315
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PIN DESCRIPTION
X1, X2 - 32.768 kHz Crystal Connection
WE - Write Enable
BAT1 - Battery 1 Input
GND - Ground
D- Data Input
Q- Data Output
ROM/
RAM
- ROM/RAM Mode Select
CEO - Chip Enable Output
CEI - Chip Enable Input
OE - Output Enable
RST - Reset
BAT2 - Battery 2 Input
VCC0 - Switched Supply Output
VCC1 - Power Supply Input
DESCRIPTION
The DS1315 Phantom Time Chip is a combination of a CMOS timekeeper and a nonvolatile memory
controller. In the absence of power, an external battery maintains the timekeeping operation and provides
power for a CMOS static RAM. The watch keeps track of hundredths of seconds, seconds, minutes,
hours, day, date, month, and year information. The last day of the month is automatically adjusted for
months with less than 31 days, including leap year correction. The watch operates in one of two formats:
a 12-hour mode with an AM/PM indicator or a 24-hour mode. The nonvolatile controller supplies all the
necessary support circuitry to convert a CMOS RAM to a nonvolatile memory. The DS1315 can be
interfaced with either RAM or ROM without leaving gaps in memory.
OPERATION
The block diagram of Figure 1 illustrates the main elements of the Time Chip. The following paragraphs
describe the signals and functions.
DS1315
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TIMING BLOCK DIAGRAM Figure 1
Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits
which must be matched by executing 64 consecutive write cycles containing the proper data on data in
(D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the
chip enable output pin (CEO ).
After recognition is established, the next 64 read or write cycles either extract or update data in the Time
Chip and CEO remains high during this time, disabling the connected memory.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable input (CEI ), output enable (OE ), and write enable (WE ). Initially, a read cycle using the
CEI and OE control of the Time Chip starts the pattern recognition sequence by moving pointer to the
first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CEI
and WE control of the Time Chip. These 64 write cycles are used only to gain access to the Time Chip.
When the first write cycle is executed, it is compared to bit 1 of the 64-bit comparison register. If a match
is found, the pointer increments to the next location of the comparison register and awaits the next write
cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If
a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the
comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as
described above until all the bits in the comparison register have been matched. (This bit pattern is shown
in Figure 2). With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the
timekeeping registers may proceed. The next 64 cycles will cause the Time Chip to either receive data on
D, or transmit data on Q, depending on the level of OE pin or the WE pin. Cycles to other locations
DS1315
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outside the memory block can be interleaved with CEI cycles without interrupting the pattern recognition
sequence or data transfer sequence to the Time Chip.
A standard 32.768 kHz quartz crystal can be directly connected to the DS1315 via pins 1 and 2 (X1, X2).
The crystal selected for use should have a specified load capacitance (CL) of 6 pF. For more information
on crystal selection and crystal layout considerations, please consult Application Note 58, Crystal
Considerations with Dallas Real Time Clocks.
TIME CHIP COMPARISON REGISTER DEFINITION Figure 2
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being
accidentally duplicated and causing inadvertent entry to the Phantom Time Chip are less than 1 in 1019.
DS1315
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NONVOLATILE CONTROLLER OPERATION
The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the
ROM/
RAM
select pin. When ROM/
RAM
is connected to ground, the controller is set in the RAM mode
and performs the circuit functions required to make CMOS RAM and the timekeeping function
nonvolatile. A switch is provided to direct power from the battery inputs or VCCI to VCCO with a
maximum voltage drop of 0.3 volts. The VCCO output pin is used to supply uninterrupted power to CMOS
SRAM. The DS1315 also performs redundant battery control for high reliability. On power-fail, the
battery with the highest voltage is automatically switched to VCCO. If only one battery is used in the
system, the unused battery input should be connected to ground.
The DS1315 safeguards the Time Chip and RAM data by power-fail detection and write protection.
Power-fail detection occurs when VCCI falls below VPF which is set by an internal bandgap reference. The
DS1315 constantly monitors the VCCI supply pin. When VCCI is less than VPF, power-fail circuitry forces
the chip enable output (CEO ) to VCCI or VBAT-0.2 volts for external RAM write protection. During
nominal supply conditions, CEO will track CEI with a propagation delay. Internally, the DS1315 aborts
any data transfer in progress without changing any of the Time Chip registers and prevents future access
until VCCI exceeds VPF. A typical RAM/Time Chip interface is illustrated in Figure 3.
When the ROM/
RAM
pin is connected to VCCO, the controller is set in the ROM mode. Since ROM is a
read-only device that retains data in the absence of power, battery backup and write protection is not
required. As a result, the chip enable logic will force CEO low when power fails. However, the Time
Chip does retain the same internal nonvolatility and write protection as described in the RAM mode. A
typical ROM/Time Chip interface is illustrated in Figure 4.
DS1315 TO RAM/TIME CHIP INTERFACE Figure 3
DS1315
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ROM/TIME CHIP INTERFACE Figure 4
TIME CHIP REGISTER INFORMATION
Time Chip information is contained in eight registers of 8 bits, each of which is sequentially accessed 1
bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the Time
Chip registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a
register could produce erroneous results. These read/write registers are defined in Figure 5.
Data contained in the Time Chip registers is in binary coded decimal format (BCD). Reading and writing
the registers is always accomplished by stepping though all eight registers, starting with bit 0 of register 0
and ending with bit 7 of register 7.
AM–PM/12/24 MODE
Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode,
bit 5 is the second 10-hour bit (20-23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the
reset pin input. When the reset bit is set to logic 1, the reset input pin is ignored. When the reset bit is set
to logic 0, a low input on the reset pin will cause the Time Chip to abort data transfer without changing
data in the timekeeping registers. Reset operates independently of all other in-puts. Bit 5 controls the
oscillator. When set to logic 0, the oscillator turns on and the real time clock/calendar begins to
increment.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain 1 or more bits that will always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
DS1315
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TIME CHIP REGISTER DEFINITION Figure 5
DS1315
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ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature, commercial range 0°C to 70°C
Operating Temperature, industrial range -45°C to +85°C
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Power Supply Voltage 5
Volt Operation VCC 4.5 5.0 5.5 V 1
Power Supply Voltage 3.3
Volt Operation VCC 3.0 3.3 3.6 V 1
Input Logic 1 VIH 2.2 VCC+0.3 V 1
Input Logic 0 VIL -0.3 +0.6 V 1
Battery Voltage VBAT1 or
VBAT2
VBAT1,
VBAT2
2.5 3.7 V
DC OPERATING ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0 ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Average VCC Power
Supply Current ICC1 5mA 6
VCC Power Supply Current,
(VCC0 = VCCI-0.3) ICC01 150 mA 7
TTL Standby Current
(CEI = VIH)ICC2 3mA 6
CMOS Standby Current
(CEI = VCCI-0.2) ICC3 1mA 6
Input Leakage Current
(any input) IIL -1 +1 µA 10
Output Leakage Current
(any input) IOL -1 +1 µA
Output Logic 1 Voltage
(IOUT = -1.0 mA) VOH 2.4 V 2
Output Logic 0 Voltage
(IOUT = 4.0 mA) VOL 0.4 V 2
Power-Fail Trip Point VPF 4.25 4.5 V
Battery Switch Voltage VSW VBAT1,
VBAT2
13
DS1315
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DC POWER DOWN ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC < 4.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CEO Output Voltage VCEO VCCI-0.2
or
VBAT1,2
-0.2
V 8
VBAT1 or VBAT2 Battery
Current IBAT 0.5 µA 6
Battery Backup Current
@ VCCO = VBAT-0.2V ICCO2 10 µA 9
AC ELECTRICAL OPERATING CHARACTERISTICS
ROM/
RAM
= GND (0°C to 70°C; VCC = 5.0 ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 65 ns
CEI Access Time tCO 55 ns
OE Access Time tOE 55 ns
CEI to Output Low Z tCOE 5 ns
OE to Output Low Z tOEE 5 ns
CEI to Output High Z tOD 25 ns
OE to Output High Z tODO 25 ns
Read Recovery tRR 10 ns
Write Cycle tWC 65 ns
Write Pulse Width tWP 55 ns
Write Recovery tWR 10 ns 4
Data Setup tDS 30 ns 5
Data Hold Time tDH 0 ns 5
CEI Pulse Width tCW 55 ns
OE Pulse Width tOW 55 ns
RST Pulse Width tRST 65 ns
DS1315
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AC ELECTRICAL OPERATING CHARACTERISTICS
ROM/
RAM
= VCCO (0°C to 70°C; VCC = 5.0 ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 65 ns
CEI Access Time tCO 55 ns
OE Access Time tOE 55 ns
CEI to Output Low Z tCOE 5 ns
OE to Output Low Z tOEE 5 ns
CEI to Output High Z tOD 25 ns
OE to Output High Z tODO 25 ns
Address Setup Time tAS 5 ns
Address Hold Time tAH 5 ns
Read Recovery tRR 10 ns
Write Cycle tWC 65 ns
CEI Pulse Width tCW 55 ns
OE Pulse Width tOW 55 ns
Write Recovery tWR 10 ns 4
Data Setup tDS 30 ns 5
Data Hold Time tDH 0 ns 5
RST Pulse Width tRST 65 ns
DC OPERATING ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 3.3 ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Average VCC Power
Supply Current ICC1 3mA 6
Average VCC Power
Supply Current,
(VCCO = VCCI-0.3)
ICC01 100 mA 7
TTL Standby Current
(CEI = VIH)ICC2 2mA 6
CMOS Standby Current
(CEI = VCCI-0.2) ICC3 1mA 6
Input Leakage Current
(any input) IIL -1 +1 µA
Output Leakage Current
(any input) ILO -1 +1 µA
Output Logic 1 Voltage
(IOUT = 0.4 mA) VOH 2.4 V 2
Output Logic 0 Voltage
(IOUT = 1.6 mA) VOL 0.4 V 2
Power-Fail Trip Point VPF 2.8 2.97 V
Battery Switch Voltage VSW VBAT1,
VBAT2,
or VPF
14
DS1315
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DC POWER DOWN ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC < 2.97V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CEO Output Voltage VCEO VCCI
or
VBAT1,2
-0.2
V 8
VBAT1 OR VBAT2
Battery Current IBAT 0.3 µA 6
Battery Backup Current
@ VCCO = VBAT-0.2 ICCO2 10 µA 9
AC ELECTRICAL OPERATING CHARACTERISTICS
ROM/
RAM
= GND (0°C to 70°C; VCC = 3.3 ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 120 ns
CEI Access Time tCO 100 ns
OE Access Time tOE 100 ns
CEI to Output Low Z tCOE 5 ns
OE to Output Low Z tOEE 5 ns
CEI to Output High Z tOD 40 ns
OE to Output High Z tODO 40 ns
Read Recovery tRR 20 ns
Write Cycle tWC 120 ns
Write Pulse Width tWP 100 ns
Write Recovery tWR 20 ns 4
Data Setup tDS 45 ns 5
Data Hold Time tDH 0 ns 5
CEI Pulse Width tCW 100 ns
OE Pulse Width tOW 100 ns
RST Pulse Width tRST 120 ns
DS1315
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AC ELECTRICAL OPERATING CHARACTERISTICS
ROM/
RAM
= VCCO (0°C to 70°C; VCC = 3.3 ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 120 ns
CEI Access Time tCO 100 ns
OE Access Time tOE 100 ns
CEI to Output Low Z tCOE 5 ns
OE to Output Low Z tOEE 5 ns
CEI to Output High Z tOD 40 ns
OE to Output High Z tODO 40 ns
Address Setup Time tAS 10 ns
Address Hold Time tAH 10 ns
Read Recovery tRR 20 ns
Write Cycle tWC 120 ns
CEI Pulse Width tCW 100 ns
OE Pulse Width tOW 100 ns
Write Recovery tWR 20 ns 4
Data Setup tDS 45 ns 5
Data Hold Time tDH 0 ns 5
RST Pulse Width tRST 120 ns
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 10 pF
Output Capacitance COUT 10 pF
DS1315
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TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/
RAM
= GND Figure 6
TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/
RAM
= GND Figure 7
DS1315
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TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/
RAM
= VCCO Figure 8
TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/
RAM
= VCCO Figure 9
DS1315
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TIMING DIAGRAM: RESET PULSE Figure 10
5V DEVICE POWER-UP POWER-DOWN CHARACTERISTICS,
ROM/
RAM
= VCCO OR GND (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Recovery Time at
Power-Up tREC 1.5 2.5 mS 11
VCC Slew Rate
Power-Down
VPF(max) to VPF(min) tF300 µs 11
VCC Slew Rate
Power-Down
VPF(min) to VSW
tFB 10 µs 11
VCC Slew Rate
Power-Up
VPF(min) to VPF(max) tR0 µs 11
CEI High to Power-Fail tPF 0 µs 11
CEI Propagation Delay tPD 5 ns 2, 3, 11
5V DEVICE POWER-UP CONDITION Figure 11
RST
t
RST
DS1315
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5V DEVICE POWER-DOWN CONDITION Figure 12
3.3V DEVICE POWER-UP POWER-DOWN CHARACTERISTICS,
ROM/
RAM
= VCCO OR GND (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Recovery Time at
Power-Up tREC 1.5 2.5 ms 12
VCC Slew Rate
Power-Down
VPF(max) to VPF(min) tF300 µs 12
VCC Slew Rate
Power-Up
VPF(min) to VPF(max) tR0 µs 12
CEI High to Power-Fail tPF 0 µs 12
CEI Propagation Delay tPD 10 ns 2, 3, 11
DS1315
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3.3V DEVICE POWER-UP CONDITION Figure 13
3.3V DEVICE POWER-DOWN CONDITION Figure 14
DS1315
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NOTES:
1. All voltages are referenced to ground.
2. Measured with load shown in Figure 15.
3. Input pulse rise and fall times equal 10 ns.
4. tWR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM
mode.
5. tDH and tDS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in
ROM mode.
6. Measured without RAM connected.
7. ICCO1 is the maximum average load current the DS1315 can supply to external memory.
8. Applies to CEO with the ROM/
RAM
pin grounded. When the ROM/
RAM
pin is connected to VCCO,
CEO will go to a low level as VCCI falls below VBAT.
9. ICCO2 is the maximum average load current that the DS1315 can supply to memory in the battery
backup mode.
10. Applies to all input pins except RST . RST is pulled internally to VCCI.
11. See Figures 11 and 12.
12. See Figures 13 and 14.
13. VSW is determined by the larger of VBAT1 and VBAT2.
14. VSW is determined by the smaller of VBAT1, VBAT2, and VPF.
OUTPUT LOAD Figure 15
DS1315
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DS1315 TIME CHIP 16-PIN DIP
PKG 16-PIN
DIM. MIN MAX
A IN.
MM 0.740 0.780
B IN.
MM 0.240 0.260
C IN.
MM 0.120 0.140
D IN.
MM 0.300 0.325
E IN.
MM 0.015 0.040
F IN.
MM 0.110 0.140
G IN.
MM 0.090 0.110
H IN.
MM 0.300 0.370
J IN.
MM 0.008 0.012
K IN.
MM 0.015 0.021
DS1315
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DS1315 TIME CHIP 16-PIN SOIC
PKG 16-PIN
DIM MIN MAX
A IN.
MM 0.402
10.21 0.412
10.46
B IN.
MM 0.290
7.37 0.300
7.65
C IN.
MM 0.089
2.26 0.095
2.41
E IN.
MM 0.004
0.102 0.012
0.30
F IN.
MM 0.094
2.38 0.105
2.68
G IN.
MM 0.050 BSC
1.27 BSC
H IN.
MM 0.398
10.11 0.416
10.57
J IN.
MM 0.009
0.229 0.013
0.33
K IN.
MM 0.013
0.33 0.019
0.48
L IN.
MM 0.016
0.40 0.040
1.02
PHI
DS1315
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DS1315 TIME CHIP 16-PIN TSSOP
DIM MIN MAX
A MM - 1.10
A1 MM 0.05 -
A2 MM 0.75 1.05
C MM 0.09 0.18
L MM 0.50 0.70
e1 MM 0.65 BSC
B MM 0.18 0.30
D MM 6.40 6.90
E MM 4.40 NOM
G MM 0.25 REF
H MM 6.25 6.55
phi