PCA9554DB,118 - NXP Semiconductors

1. General description

The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General

Purpose parallel Inpu t/O ut pu t (GPIO) expansion for I2C-bus/SMBus applications and

were developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders.

The improvements include higher drive cap ability, 5 V I/O tolerance, lower supply current,

individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O

expanders provide a simple solution when additional I/O is needed for ACPI power

switches, sensors, push buttons, LEDs, fans, etc.

The PCA9554/PCA9554A consist of an 8-bit Configuration register (Input or Output

selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity

Inversion register (active HIGH or active LOW operation). The system master can enable

the I/Os as either inpu ts or outputs by writing to the I/O con fig ur at ion bits. The data for

each input or output is kept in the corresponding Inp ut Port or Output Port register. The

polarity of the read register can be inverted with the Polarity Inversion register. All

registers can be read by the system master. Although pin-to-pin and I2C-bus address

compatible with the PCF8574 series, software changes are required due to the

enhancem en ts and are dis cus se d in A pplication Note AN469.

The PCA9554/PCA9554A open-drain interrupt output is activated when any input state

differs from its corresponding Input Port register state and is used to indicate to the

system master that an input state has changed. The power-on reset sets the registers to

their default values and initializes the device state machine.

Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address an d allo w up to eigh t

devices to share the same I2C-bus/SMBus. The PCA9554A is identical to the PCA9554

except that the fixed I2C-bus address is different allowing up to sixteen of these devices

(eight of each) on the same I2C-bus/SMBus.

2. Features and benefits

Operating power supply voltage range of 2.3 V to 5.5 V

5 V tolerant I/Os

Polarity Inversion register

Active LOW interrupt output

Low standby current

Noise filter on SCL/SDA inputs

No glitch on power-up

Internal power- on res et

8 I/O pins which default to 8 inputs

0 Hz to 400 kHz clock frequency

PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Rev. 8 — 26 July 2011 Product data sheet

Product data sheet Rev. 8 — 26 July 2011 2 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

AEC-Q100 compliance available

Packages offered: DIP16, SO16, SSOP16, SSOP20, TSSOP16,

HVQFN16 (2 versions: 4 40.85 mm and 3 30.85 mm), and bare die

3. Ordering information

[1] PCA9554PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP.

Table 1. Ordering information

Tamb =





Cto+85



Type number Topside mark Package

Name Description Version

PCA9554N PCA9554N DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

PCA9554AN PCA9554AN

PCA9554D PCA9554D SO16 plastic small outline package; 16 leads;

body width 7.5 mm SOT162-1

PCA9554AD PCA9554AD

PCA9554DB 9554DB SSOP16 plastic shrink small outline package; 16 leads;

body width 5.3 mm SOT338-1

PCA9554ADB 9554A

PCA9554TS PCA9554 SSOP20 plastic shrink small outline package; 20 leads;

body width 4.4 mm SOT266-1

PCA9554ATS PA9554A

PCA9554PW 9554DH TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

PCA9554PW/Q900[1] 9554DH

PCA9554APW 9554ADH

PCA9554BS 9554 HVQFN16 plastic thermal enhanced very thin quad flat package;

no leads; 16 terminals; body 4 40.85 mm SOT629-1

PCA9554ABS 554A

PCA9554BS3 P54 HVQFN16 plastic thermal enhanced very thin quad flat package;

no leads; 16 terminals; body 3 30.85 mm SOT758-1

PCA9554ABS3 54A

PCA9554U - bare die - -

Product data sheet Rev. 8 — 26 July 2011 3 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

4. Block diagram

All I/Os are set to inputs at reset.

Fig 1. Block diagram of PCA9554/PCA9554A

PCA9554/PCA9554A

POWER-ON

RESET

002aac492

I2C-BUS/SMBus

CONTROL

INPUT

FILTER

SCL

SDA

VDD

INPUT/

OUTPUT

PORTS

IO0

VSS

8-bit

write pulse

read pulse

IO2

IO4

IO6

IO1

IO3

IO5

IO7

FILTER

VDD

INT

Product data sheet Rev. 8 — 26 July 2011 4 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

5. Pinning information

5.1 Pinning

Fig 2. Pin configuration for DIP16 Fig 3. Pin configuration for SO16

Fig 4. Pin configuration for SSOP16 Fig 5. Pin configuration for TSSOP16

PCA9554N

PCA9554AN

A0 VDD

A1 SDA

A2 SCL

IO0 INT

IO1 IO7

IO2 IO6

IO3 IO5

VSS IO4

002aac485

VDD

SDA

SCL

INT

IO7

IO6

IO5

IO4

IO0

IO1

IO2

IO3

VSS

PCA9554D

PCA9554AD

002aac486

PCA9554DB

PCA9554ADB

002aac487

15 VDD

SDA

SCL

INT

IO7

IO6

IO5

IO4

IO0

IO1

IO2

IO3

VSS

SDA

SCL

INT

IO7

IO6

IO5

IO4

IO0

IO1

IO2

IO3

PCA9554PW

PCA9554PW/Q900

PCA9554APW

002aac488

Product data sheet Rev. 8 — 26 July 2011 5 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Fig 6. Pin confi gura tio n for SSOP2 0

Fig 7. Pin configura tio n for HVQFN16

(SOT629-1) Fig 8. Pin configuration for HVQFN16

(SOT758-1)

PCA9554TS

PCA9554ATS

INT IO7

SCL IO6

n.c. n.c.

SDA IO5

VDD IO4

A0 VSS

A1 IO3

n.c. n.c.

A2 IO2

IO0 IO1

002aac489

002aac490

PCA9554BS

PCA9554ABS

Transparent top view

IO2 IO6

IO1 IO7

IO0 INT

A2 SCL

IO3

IO4

IO5

SDA

4 9

3 10

2 11

1 12

terminal 1

index area

002aac491

PCA9554BS3

PCA9554ABS3

Transparent top view

IO2 IO6

IO1 IO7

IO0

A2 SCL

IO3

VSS

IO4

IO5

VDD

SDA

4 9

3 10

2 11

1 12

terminal 1

index area

INT

Product data sheet Rev. 8 — 26 July 2011 6 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

5.2 Pin description

[1] HVQFN16 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

PCB in the thermal pad region.

6. Functional description

Refer to Figure 1 “Block dia gram of PCA9554/PCA9554A”.

6.1 Registers

6.1.1 Command byte

The command byte is the first byte to follow the address byte during a write tra nsmission.

It is used as a pointer to determine which of the following registers will be written or read.

Ta ble 2. Pin description

Symbol Pin Description

DIP16, SO16,

SSOP16, TSSOP16 HVQFN16 SSOP20

A0 1 15 6 address input 0

A1 2 16 7 address input 1

A2 3 1 9 address input 2

IO0 4 2 10 input/output 0

IO1 5 3 11 input/output 1

IO2 6 4 12 input/output 2

IO3 7 5 14 input/output 3

VSS 86

[1] 15 supply ground

IO4 9 7 16 input/output 4

IO5 10 8 17 input/output 5

IO6 11 9 19 input/output 6

IO7 12 10 20 input/output 7

INT 13 11 1 interrupt output (open-drain)

SCL 14 12 2 serial clock line

SDA 15 13 4 serial data line

VDD 16 14 5 supply voltage

n.c. - - 3, 8, 13, 18 not connected

Ta ble 3. Command by te

Command Protocol Function

0 read byte Input Port register

1 read/write byte Output Port register

2 read/write byte Polarity Inversion register

3 read/write byte Configuration register

Product data sheet Rev. 8 — 26 July 2011 7 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

6.1.2 Register 0 - Input Port register

This register is a read-only port. It refle cts the incomin g logic levels of the pins, regardless

of whether the pin is defined as an input or an output by Register 3. Writes to this register

have no effect.

The default ‘X’ is determined by the externally applied logic level, normally ‘1’ when no

external signal externally applied because of the internal pull-up resistors.

6.1.3 Register 1 - Output Port register

This register reflect s the outgoi ng logic levels of the pins d efined as output s by Re gister 3.

Bit values in this register have no ef fect on pins defined as inp uts. Reads from this register

return the value that is in the flip-flop controlling the output selection, not the actual pin

value.

Ta ble 4. Regist er 0 - Inpu t Port register bit description

Bit Symbol Access Value Description

7 I7 read only X determined by externally appli ed logic level

6 I6 read only X

5 I5 read only X

4 I4 read only X

3 I3 read only X

2 I2 read only X

1 I1 read only X

0 I0 read only X

Ta ble 5. Register 1 - Output Por t register bit description

Legend: * default value.

Bit Symbol Access Value Description

7 O7 R 1* reflects outgoing logic levels of pins defined as

outputs by Register 3

6O6 R 1*

5O5 R 1*

4O4 R 1*

3O3 R 1*

2O2 R 1*

1O1 R 1*

0O0 R 1*

Product data sheet Rev. 8 — 26 July 2011 8 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

6.1.4 Register 2 - Polarity Inversion register

This register allows the user to invert the polarity of the Input Port register data. If a bit in

this register is set (written with ‘1’), the corresponding Input Port dat a is inverted . If a bit in

this register is cleared (written with a ‘0’) , the Input Port data polarity is retained.

6.1.5 Register 3 - Configuration register

This register configures the directions of the I/O pins. If a bit in this register is set, the

corresponding port pin is enabled as an input with high-impedance output driver . If a bit in

this register is cleared, the corresponding port pin is enabled as an output. At reset, th e

I/Os are configured as inputs with a weak pull-up to VDD.

6.2 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the

PCA9554/PCA9554A in a reset condition until VDD has reached VPOR. At that point, the

reset condition is released and the PCA9554/PCA9554A registers and state machine will

initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the

device.

For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the

operating voltage.

Ta ble 6. Regist er 2 - Pola rity Inversion register bit descrip tion

Legend: * default value.

Bit Symbol Access Value Description

7 N7 R/W 0* inverts polarity of Input Port register data

0 = Input Port register data retained (default value)

1 = Input Port register data inverted

6N6 R/W 0*

5N5 R/W 0*

4N4 R/W 0*

3N3 R/W 0*

2N2 R/W 0*

1N1 R/W 0*

0N0 R/W 0*

Table 7. Register 3 - Configura t ion register bit description

Legend: * default value.

Bit Symbol Access Value Description

7 C7 R/W 1* configures the directio ns of the I/O pins

0 = corresponding port pin enabled as an output

1 = corresponding port pin configured as input

(default value)

6C6 R/W 1*

5C5 R/W 1*

4C4 R/W 1*

3C3 R/W 1*

2C2 R/W 1*

1C1 R/W 1*

0C0 R/W 1*

Product data sheet Rev. 8 — 26 July 2011 9 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

6.3 Interrupt output

The open-drain interrupt output is activated when one of the port pins change state and

the pin is configured as an input. The interrup t is deactivated when the input retu rns to its

previous state or the Input Port register is read.

Note that changing an I/O from and output to an inp ut may cause a false interrupt to occur

if the state of the pin does not match the contents of the Input Port register.

6.4 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a

high-impedance input with a weak pull-up (100 k typ.) to VDD. The input voltage may be

raised above VDD to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the

state of th e Output Port register. Care should be exercised if an ex ternal volta ge is applied

to an I/O configured as an outp ut because of the low-impedance paths that exist between

the pin and either VDD or VSS.

Remark: At power-on reset, all registers return to default values.

Fig 9. Simplified schematic of IO0 to IO7

VDD

IO0 to IO7

output port

configuration

CK Q

data from

shift register

write configuration

pulse

output port

write pulse

polarity inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity inversion

002aac493

data from

shift register

VSS

to INT

100 kΩ

Product data sheet Rev. 8 — 26 July 2011 10 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

6.5 Device address

6.6 Bus transactions

Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown

in Figure 12 and Figure 13. Data is r ead from the PCA9554/PCA9554A registers using the

Read mode as shown in Figure 14 and Figure 15. These devices do not implement an

auto-increment function, so once a command byte has been sent, the register which was

addressed will continue to be accessed by reads until a new command byte has been

sent.

Fig 10. PCA9554 device address Fig 11. PCA9554A device address

002aac494

0 1 0 0 A2 A1 A0 R/W

fixed

slave address

hardware

selectable

002aac495

0 1 1 1 A2 A1 A0 R/W

fixed

slave address

programmable

Fig 12. Write to Outp ut Port re g is t er

1 0 0 A2 A1 A0 0 AS0

START condition R/W

acknowledge

from slave

002aac472

acknowledge

from slave

SCL

SDA A

write to port

data out

from port

v(Q)

987654321

command byte

acknowledge

from slave

data to port

DATA 1

slave address

00000010

STOP

condition

data 1 valid

Fig 13. Write to Configuration register or Polarity Inversion register

1 0 0 A2 A1 A0 0 AS0

START condition R/W

acknowledge

from slave

002aac473

acknowledge

from slave

SCL

SDA A

data to

987654321

command byte

acknowledge

from slave

data to register

DATA

slave address

0000011/00

STOP

condition

Product data sheet Rev. 8 — 26 July 2011 11 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Fig 14. Read from register

1 0 0 A2 A1 A0 0 AS0

START condition R/W

acknowledge

from slave

002aac474

acknowledge

from slave

SDA

A P

command byte

acknowledge

from master

data from register

DATA (first byte)

slave address

STOP

condition

(repeated)

START condition

(cont.)

(cont.) 1 0 0 A2 A1 A0 1 A0

R/W

acknowledge

from slave

slave address

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

no acknowledge

from master

data from register

DATA (last byte)

This figure assumes the command byte has previously been programmed with 00h.

Transfer of data can be stopped at any moment by a STOP condition.

Fig 15. Read Input Port register

1 0 0 A2 A1 A0 1 AS0

START condition R/W

acknowledge

from slave

002aac475

acknowledge

from master

SCL

SDA NA

read from

port

data into

port

th(D)

987654321

data from port

no acknowledge

from master

data from port

DATA 4

slave address

DATA 1

STOP

condition

DATA 2 DATA 3 DATA 4

tsu(D)

INT

tv(INT_N) trst(INT_N)

Product data sheet Rev. 8 — 26 July 2011 12 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

7. Application design-in information

8. Limiting values

Device address configured as 0100 100X for this example.

IO0, IO1, IO2 configured as outputs.

IO3, IO4, IO5 configured as inputs.

IO6 and IO7 are not used and must be configured as outputs.

Fig 16. Typical application

PCA9554

IO0

IO1

SCL

SDA

VDD

002aac496

SCL

SDA IO2

IO3

VDD

VSS

MASTER

CONTROLLER

VSS

VDD (5 V)

2 kΩ

SUBSYSTEM 1

(e.g., temp. sensor)

INT

SUBSYSTEM 2

(e.g., counter)

RESET

controlled switch

(e.g., CBT device)

enable

INTINT

10 kΩ10 kΩ

SUBSYSTEM 3

(e.g., alarm system)

ALARM

IO4

IO5

VDD

IO6

IO7

10 kΩ10 kΩ

Ta ble 8. Limiting valu es

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +6.0 V

IIinput current - 20 mA

VI/O voltage on an input/output pin VSS 0.5 5.5 V

IO(IOn) output current on pin IOn - 50 mA

IDD supply current - 85 mA

ISS ground supply current - 100 mA

Ptot total power dissipation - 200 mW

Tstg storage temperature 65 +150 C

Tamb ambient temperature operating 40 +85 C

Product data sheet Rev. 8 — 26 July 2011 13 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

9. Static characteristics

Table 9. Static characteristics

VDD = 2.3 V to 5.5 V; VSS =0V; T

amb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage 2.3 - 5.5 V

IDD supply current operating mode; VDD =5.5V;

no load; fSCL = 100 kHz - 104 175 A

Istb standby current Standby mode; VDD = 5.5 V; no load;

VI=V

SS; fSCL = 0 kHz; I/O = inputs - 550 700 A

Standby mode; VDD = 5.5 V; no load;

VI=V

DD; fSCL = 0 kHz; I/O = inputs -0.251 A

VPOR power-on reset voltage no load; VI=V

DD or VSS [1] - 1.5 1.65 V

Input SCL; input/outpu t S DA

VIL LOW-level input voltage 0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -5.5V

IOL LOW-level output current VOL =0.4V 3 6 - mA

ILleakage current VI=V

DD =V

SS 1- +1 A

Ciinput capacitance VI=V

SS - 6 10 pF

I/Os

VIL LOW-level input voltage 0.5 - +0.8 V

VIH HIGH-level input voltage 2.0 - 5.5 V

IOL LOW-level output current VOL =0.5V; V

DD =2.3V [2] 810- mA

VOL =0.7V; V

DD =2.3V [2] 10 13 - mA

VOL =0.5V; V

DD =3.0V [2] 814- mA

VOL =0.7V; V

DD =3.0V [2] 10 19 - mA

VOL =0.5V; V

DD =4.5V [2] 817- mA

VOL =0.7V; V

DD =4.5V [2] 10 24 - mA

VOH HIGH-level output voltage IOH =8mA; V

DD =2.3V [3] 1.8 - - V

IOH =10 mA; VDD =2.3V [3] 1.7 - - V

IOH =8mA; V

DD =3.0V [3] 2.6 - - V

IOH =10 mA; VDD =3.0V [3] 2.5 - - V

IOH =8mA; V

DD =4.75V [3] 4.1 - - V

IOH =10 mA; VDD =4.75V [3] 4.0 - - V

ILI input leakage current VDD =3.6V; V

I=V

DD 1- +1 A

ILleakage current VDD =5.5V; V

I=V

SS --100 A

Ciinput capacitance - 3.7 5 pF

Cooutput capacitance - 3.7 5 pF

Interrupt INT

IOL LOW-level output current VOL =0.4V 3 - - mA

Product data sheet Rev. 8 — 26 July 2011 14 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

[1] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.

[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.

[3] The total current sourced by all I/Os must be limited to 85 mA.

10. Dynamic characteristics

[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW.

[3] Cb= total capacitance of one bus line in pF.

Select inputs A0, A1, A2

VIL LOW-level input voltage 0.5 - 0.8 V

VIH HIGH-level input voltage 2.0 - 5.5 V

ILI input leakage current 1- 1 A

Table 9. Static characteristics …continued

VDD = 2.3 V to 5.5 V; VSS =0V; T

amb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Table 10. Dynamic characteristics

Symbol Parameter Conditions Standard-mode

I2C-bus Fast-mode I2C-bus Unit

Min Max Min Max

fSCL SCL clock frequency 0 100 0 400 kHz

tBUF bus free time between a STOP and

START condition 4.7 - 1.3 - s

tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s

tSU;STA set-up time for a repeated START

condition 4.7 - 0.6 - s

tSU;STO set-up time for STOP condition 4.0 - 0.6 - s

tHD;DAT data hold time 0 - 0 - s

tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 s

tVD;DAT data valid time [2] 300 - 50 - ns

tSU;DAT data set-up time 250 - 100 - ns

tLOW LOW period of the SCL clock 4.7 - 1.3 - s

tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s

trrise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns

tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 ns

tSP pulse width of spikes that must be

suppressed by the input filter - 50 - 50 ns

Port timing

tv(Q) data output valid time - 200 - 200 ns

tsu(D) data input set-up time 100 - 100 - ns

th(D) data input hold time 1 - 1 - s

Interrupt timing

tv(INT_N) valid time on pin INT -4 - 4s

trst(INT_N) reset time on pin INT -4 - 4s

Product data sheet Rev. 8 — 26 July 2011 15 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Fig 17. Definition of timing

tSP

tBUF

tHD;STA PP S

tLOW

tHD;DAT

tHIGH tSU;DAT tSU;STA

tHD;STA

tSU;STO

SDA

SCL

002aaa986

Product data sheet Rev. 8 — 26 July 2011 16 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

11. Package outline

Fig 18. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Product data sheet Rev. 8 — 26 July 2011 17 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Fig 19. Package outline SOT162-1 (SO16)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 10.5

10.1 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT162-1

detail X

0.25

075E03 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.41

0.40 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

vMA

(A )

0 5 10 mm

scale

SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1

99-12-27

03-02-19

Product data sheet Rev. 8 — 26 July 2011 18 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Fig 20. Package outline SOT338-1 (SSOP16)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25

7.9

7.6 1.03

0.63 0.9

0.7 1.00

0.55 8

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1 99-12-27

03-02-19

(1)

vMA

16 9

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

max.

Product data sheet Rev. 8 — 26 July 2011 19 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Fig 21. Package outline SOT266-1 (SSOP20)

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

01.4

1.2 0.32

0.20 0.20

0.13 6.6

6.4 4.5

4.3 0.65 1 0.2

6.6

6.2 0.65

0.45 0.48

0.18 10

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

0.75

0.45

SOT266-1 MO-152 99-12-27

03-02-19

detail X

vMA

(A )

0.25

110

20 11

pin 1 index

0 2.5 5 mm

scale

SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

max.

1.5

Product data sheet Rev. 8 — 26 July 2011 20 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Fig 22. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 8 — 26 July 2011 21 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Fig 23. Package outline SOT629-1 (HVQFN16)

terminal 1

index area

0.651

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.1

3.9

2.25

1.95

4.1

3.9 2.25

1.95

0.38

0.23

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT629-1 MO-220 - - -- - -

0.75

0.50

0.1

0.05

0 2.5 5 mm

scale

SOT629-1

HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;

16 terminals; body 4 x 4 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

16 13

01-08-08

02-10-22

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 8 — 26 July 2011 22 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Fig 24. Package outline SOT758-1 (HVQFN16)

terminal 1

index area

0.51

A1Eh

UNIT y

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.75

1.45

3.1

2.9 1.75

1.45

1.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT758-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT758-1

HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;

16 terminals; body 3 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

16 13

02-03-25

02-10-21

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 8 — 26 July 2011 23 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

12. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate pre ca u tio ns ar e taken as

described in JESD625-A or equivalent standards.

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circui t board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 8 — 26 July 2011 24 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

13.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 25) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 11 and 12

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 25.

Ta ble 11. SnPb eutectic process (from J-STD-0 20C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Ta ble 12. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 8 — 26 July 2011 25 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

14. Soldering of through-hole mount packages

14.1 Introduction to soldering through-hole mount packages

This text gives a very brief insight into wave, dip an d man ua l s older ing .

Wave soldering is the preferred method for mounting of through-hole mount IC packages

on a printed-circuit board.

14.2 Soldering by dipping or by solder wave

Driven by legislatio n an d en viron m en tal forces the worldwide use of lead-free solder

pastes is increasing. Typical dwell time of the leads in the wave ranges from

3 seconds to 4 seconds at 250 C or 265 C, depending on sold er mate rial a pplied, SnPb

or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the specified maximum storage temperature (Tstg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

14.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 C and 400 C, contact may be up to 5 seconds.

MSL: Moisture Sensitivity Level

Fig 25. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 8 — 26 July 2011 26 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

14.4 Package related soldering information

[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit

board.

[2] For PMFP packages hot bar soldering or manual soldering is suitable.

15. Abbreviations

Ta ble 13. Suitability of through-ho le mount IC packages for dipping and wave soldering

Package Soldering method

Dipping Wave

CPGA, HCPGA - suitable

DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1]

PMFP[2] - not suitable

Ta ble 14. Abbreviations

Acronym Description

ACPI Advanced Configuration and Power Interface

CDM Charged Device Model

CMOS Complementary Metal-Oxide Semiconductor

ESD ElectroStatic Discharge

FET Field-Effect Transistor

GPIO General Purpose Input/Output

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bus

I/O Input/Output

LED Light-Emitting Diode

MM Machine Model

PCB Printed-Circuit Board

POR P ower-On Reset

SMBus System Management Bus

Product data sheet Rev. 8 — 26 July 2011 27 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

16. Revision history

Table 15. Revision history

Document ID Release d ate Data sheet status Change notice Supersedes

PCA9554_9554A v.8 20110726 Product data sheet - PCA9554_9554A v.7

Modifications: •Section 2 “Features and benefits”:

–11th bullet item: deleted phrase “200 V MM per JESD22-A115”

–added new (13th) bullet item “AEC-Q100 compliance available”

•Table 1 “Ordering information”:

–corrected package version from “SOT38-1” to “SOT38-4” for type numbers PCA9554N and

PCA9554AN

–added type number PCA9554PW/Q900

•Figure 5 “Pin configuration for TSSOP16”: added type number PCA9554PW/Q900

•Table 9 “Static characteristics”:

–sub-section “I/Os”: corrected symbol “IIH” to “ILI” (input leakage current)

–sub-section “I/Os”, symbol ILI: corrected Min value from “-” to “1A”

–sub-section “I/Os”: corrected symbol/parameter from “IIL, input leakage current”

to “IL, leakage current”

–Table note [1] modified (added phrase “for at least 5 s”)

•Table 10 “Dynamic characteristics”: unit for tf is corrected from “ s” to “ns”

•Figure 18: corrected package version from “SOT38-1” to “SOT38-4”

•updated soldering information

PCA9554_9554A v.7 20061113 Product data sheet - PCA9554_9554A v.6

PCA9554_9554A v.6

(9397 750 13289) 20040930 Product data - PCA9554_9554A v.5

PCA9554_9554A v.5

(9397 750 10163) 20020726 Product data 853-2243 28672 of

26 July 2002 PCA9554_9554A v.4

PCA9554_9554A v.4

(9397 750 09817) 20020513 Product specification - PCA9554_9554A v.3

PCA9554_9554A v.3

(9397 750 08342) 20010507 Product specification - PCA9554_9554A v.2

PCA9554_9554A v.2

(9397 750 08209) 20010319 Product specification - PCA9554_9554A v.1

PCA9554_9554A v.1

(9397 750 08159) 20010319 Product specification - -

Product data sheet Rev. 8 — 26 July 2011 28 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

17.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors product s are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessa ry

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property right s.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data fro m the objective specification fo r product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document cont ains the product specification.

Product data sheet Rev. 8 — 26 July 2011 29 of 30

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applicati ons.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims result ing from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

17.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PCA9554; PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 26 July 2011

Document identifier: PCA9554_9554A

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Functional description . . . . . . . . . . . . . . . . . . . 6

6.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.1.1 Command byte. . . . . . . . . . . . . . . . . . . . . . . . . 6

6.1.2 Register 0 - Input Port register . . . . . . . . . . . . . 7

6.1.3 Register 1 - Output Port register. . . . . . . . . . . . 7

6.1.4 Register 2 - Polarity Inversion register . . . . . . . 8

6.1.5 Register 3 - Configuration register . . . . . . . . . . 8

6.2 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8

6.3 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.4 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.5 Device address. . . . . . . . . . . . . . . . . . . . . . . . 10

6.6 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 10

7 Application d esign-in informatio n . . . . . . . . . 12

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12

9 Static characteristics. . . . . . . . . . . . . . . . . . . . 13

10 Dynamic characteristics . . . . . . . . . . . . . . . . . 14

11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

12 Handling information. . . . . . . . . . . . . . . . . . . . 23

13 Soldering of SMD packages . . . . . . . . . . . . . . 23

13.1 Introduction to soldering. . . . . . . . . . . . . . . . . 23

13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 23

13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 23

13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 24

14 Soldering of through-hole mount packages . 25

14.1 Introduction to soldering through-hole mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

14.2 Soldering by dipping or by solder wave . . . . . 25

14.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 25

14.4 Package related soldering information . . . . . . 26

15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 26

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28

17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

18 Contact information. . . . . . . . . . . . . . . . . . . . . 29

19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30