ADS5517IRGZRG4 - Texas Instruments

FEATURES

APPLICATIONS

DESCRIPTION

ADS5517

SLWS203 – DECEMBER 2007www.ti.com

11-BIT, 200 MSPS ADC

•Clock Duty Cycle Stabilizer•Maximum Sample Rate: 200 MSPS •No External Reference Decoupling Required•11-Bit Resolution •Internal and External Reference Support•No Missing Codes •Programmable Output Clock Position to EaseData Capture•Total Power Dissipation 1.23 W

•3.3-V Analog and Digital Supply•Internal Sample and Hold

•48-QFN Package (7 mm ×7 mm)•67-dBFS SNR at 70-MHz IF•84-dBc SFDR at 70-MHz IF, 0-dB Gain•High Analog Bandwidth up to 800 MHz

•Wireless Communications Infrastructure•Double Data Rate (DDR) LVDS and Parallel

•Software Defined RadioCMOS Output Options

•Power Amplifier Linearization•Programmable Gain up to 6 dB for SNR/SFDR

•802.16d/eTrade-Off at High IF

•Test and Measurement Instrumentation•Reduced Power Modes at Lower Sample Rates

•High Definition Video•Supports Input Clock Amplitude Down to

•Medical Imaging400 mV

•Radar SystemsIn a compact 48-pin QFN, the device offers fullydifferential LVDS DDR (Double Data Rate) interfacewhile parallel CMOS outputs can also be selected.ADS5517 is a high performance 11-bit, 200-MSPS

Flexible output clock position programmability isA/D converter. It offers state-of-the art functionality

available to ease capture and trade-off setup for holdand performance using advanced techniques to

times. At lower sampling rates, the ADC can beminimize board space. With high analog bandwidth

operated at scaled down power with no loss inand low jitter input clock buffer, the ADC supports

performance. The ADS5517 includes an internalboth high SNR and high SFDR at high input

reference, while eliminating the traditional referencefrequencies. It features programmable gain options

pins and associated external decoupling. The devicethat can be used to improve SFDR performance at

also supports an external reference mode.lower full-scale analog input ranges.

The device is specified over the industrialtemperature range (-40 °C to 85 °C).

ADS5517 PRODUCT FAMILY

210 MSPS 190 MSPS 170 MSPS

14 bit ADS5547 ADS5546 ADS554512 bit ADS5527 - ADS5525ADS551711 bit

(200MSPS)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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SHA 11-Bit

ADC

CLOCKGEN

Reference

Digital

Encoder

and

Serializer

Control

Interface

INP

INM

CLKP

CLKM

VCM

CLKOUTP

CLKOUTM

LOW_D0_P

LOW_D0_M

D1_D2_P

D3_D4_P

D5_D6_P

D7_D8_P

D9_D10_P

D1_D2_M

D3_D4_M

D5_D6_M

D7_D8_M

D9_D10_M

OVR

IREF

SCLK

SEN

SDATA

RESET

DFS

MODE

LVDSMODE

AVDD

AGND

DRVDD

DRGND

ADS5517

SLWS203 – DECEMBER 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

(1)

SPECIFIED TRANSPORTPACKAGE- PACKAGE PACKAGE ORDERINGPRODUCT TEMPERATURE MEDIA,LEAD DESIGNATOR MARKING NUMBERRANGE QUANTITY

Tape and Reel,ADS5517IRGZT

250ADS5517 QFN-48

(2)

RGZ – 40 °C to 85 °C AZ5517

Tape and Reel,ADS5517IRGZR

2500

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θ

= 25.41 °C/W (0 LFM air flow),θ

= 16.5 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in (7.62 cm x 7.62cm) PCB.

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ABSOLUTE MAXIMUM RATINGS

(1)

RECOMMENDED OPERATING CONDITIONS

ADS5517

SLWS203 – DECEMBER 2007

over operating free-air temperature range (unless otherwise noted)

VALUE UNIT

Supply voltage range, AVDD – 0.3 to 3.9 VSupply voltage range, DRVDD – 0.3 to 3.9 VVoltage between AGND and DRGND -0.3 to 0.3 VVoltage between AVDD to DRVDD -0.3 to 3.3 VVoltage applied to VCM pin (in external reference mode) -0.3 to 1.8 VVoltage applied to analog input pins, INP and INM – 0.3 to minimum (3.6, AVDD + 0.3) VVoltage applied to input clock pins, CLKP and CLKM -0.3 to AVDD + 0.3 VT

Operating free-air temperature range – 40 to 85 °CT

Operating junction temperature range 125 °CT

stg

Storage temperature range – 65 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

SUPPLIES

Analog supply voltage, AVDD 3 3.3 3.6 VDigital supply voltage, DRVDD 3 3.3 3.6 V

ANALOG INPUTS

Differential input voltage range 2 V

Input common-mode voltage 1.5 ± 0.1 VVoltage applied on VCM in external reference mode 1.45 1.5 1.55 V

CLOCK INPUT

Input clock sample rate

(1)

MSPSDEFAULT SPEED mode 50 200

MSPSLOW SPEED mode 1 60Input clock amplitude differential (V

(CLKP)

- V

(CLKM)

)Sine wave, ac-coupled 0.4 1.5 V

LVPECL, ac-coupled 1.6 V

LVDS, ac-coupled 0.7 V

LVCMOS, single-ended, ac-coupled 3.3 VInput clock duty cycle (See Figure 25 ) 35% 50% 65%

DIGITAL OUTPUTS

Maximum external load capacitance from each output pin to DRGND (LVDS and CMOS modes)Without internal termination (default after reset) 5 pFWith 100 Ωinternal termination

(2)

10 pFR

Differential load resistance between the LVDS output pairs (LVDS mode) 100 Ω

Operating free-air temperature – 40 85 °C

(1) See the section on Low Sampling Frequency Operation for more information.(2) See the section on LVDS Buffer Internal termination for more information.

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ELECTRICAL CHARACTERISTICS

ADS5517

SLWS203 – DECEMBER 2007

Typical values are at 25 °C, min and max values are across the full temperature range T

MIN

= – 40 °C to T

MAX

= 85 °C,AVDD = DRVDD = 3.3 V, sampling rate = 200 MSPS, sine wave input clock, 1.5 V

differential clock amplitude, 50% clockduty cycle, – 1 dBFS differential analog input, internal reference mode, 0-db gain, DDR LVDS data output (unless otherwisenoted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 11 bits

ANALOG INPUT

Differential input voltage range 2 V

Differential input capacitance 7 pFAnalog input bandwidth 800 MHzAnalog input common mode current

342 µA(per input pin)

REFERENCE VOLTAGES

(REFB)

Internal reference bottom voltage Internal reference mode 0.5 VV

(REFT)

Internal reference top voltage Internal reference mode 2.5 V

ΔV

(REF)

Internal reference error V

(REFT)

- V

(REFB)

-60 ± 25 60 mVV

Common mode output voltage Internal reference mode 1.5 VVCM output current capability Internal reference mode ± 4 mA

DC ACCURACY

No Missing Codes SpecifiedDNL Differential non-linearity -0.6 ± 0.3 1.0 LSBINL Integral non-linearity -1.5 ± 0.6 1.5 LSBOffset error -10 5 10 mVOffset temperature coefficient 0.002 ppm/ °CGain error due to internal reference ( ΔV

(REF)

/ 2.0V)% -3 ± 1 3 %FSerror aloneGain error excluding internal reference -2 ± 1 2 %FSerror

(1)

Gain temperature coefficient 0.01 Δ%/ °CPSRR DC Power supply rejection ratio 0.6 mV/V

POWER SUPPLY

(AVDD)

Analog supply current 306 mALVDS mode, I

= 3.5 mA,

66 mAR

= 100 Ω, C

= 5 pFI

(DRVDD)

Digital supply current

CMOS mode, F

= 2.5 MHz,

47 mAC

= 5 pFI

Total supply current LVDS mode 372 mATotal power dissipation LVDS mode 1.23 1.4 WStandby power In STANDBY mode with clock stopped 100 150 mWClock stop power With input clock stopped 100 150 mW

(1) Gain error is specified from design and characterization; it is not tested in production.

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ELECTRICAL CHARACTERISTICS

ADS5517

SLWS203 – DECEMBER 2007

Typical values are at 25 °C, min and max values are across the full temperature range T

MIN

= – 40 °C to T

MAX

= 85 °C,AVDD = DRVDD = 3.3 V, sampling rate = 200 MSPS, sine wave input clock, 1.5 V

differential clock amplitude, 50% clockduty cycle, – 1 dBFS differential analog input, internal reference mode, 0-db gain, DDR LVDS data output (unless otherwisenoted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AC CHARACTERISTICS

= 20 MHz 67.1F

= 70 MHz 64.5 66.9F

= 100 MHz 66.8F

= 170 MHz 66.6SNR Signal to noise ratio dBFS0 dB gain, 2 V

(1)

66F

= 230 MHz

3 dB gain, 1.4 V

FS 65.40 dB gain, 2 V

FS 65F

= 400 MHz

3 dB gain, 1.4 V

FS 64.5F

= 20 MHz 86F

= 70 MHz 75 84F

= 100 MHz 78F

= 170 MHz 790 dB gain, 2 V

FS 75SFDR Spurious free dynamic range F

= 230 MHz dBc3 dB gain, 1.4 V

FS 780 dB gain, 2 V

FS 74F

= 300 MHz

3 dB gain, 1.4 V

FS 760 dB gain, 2 V

FS 68F

= 400 MHz

3 dB gain, 1.4 V

FS 70F

= 20 MHz 67F

= 70 MHz 64 66.8F

= 100 MHz 66.6F

= 170 MHz 66.4SINAD Signal to noise and distortion ratio dBFS0 dB gain, 2 V

FS 65F

= 230 MHz

3 dB gain, 1.4 V

FS 650 dB gain, 2 V

FS 62.8F

= 400 MHz

3 dB gain, 1.4 V

FS 62.9F

= 20 MHz 91F

= 70 MHz 75 88F

= 100 MHz 87F

= 170 MHz 870 dB gain, 2 V

FS 86HD2 Second harmonic F

= 230 MHz dBc3 dB gain, 1.4 V

FS 880 dB gain, 2 V

FS 78F

= 300 MHz

3 dB gain, 1.4 V

FS 800 dB gain, 2 V

FS 69F

= 400 MHz

3 dB gain, 1.4 V

FS 71

(1) FS = Full scale range

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ADS5517

SLWS203 – DECEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)Typical values are at 25 °C, min and max values are across the full temperature range T

MIN

= – 40 °C to T

MAX

= 85 °C,AVDD = DRVDD = 3.3 V, sampling rate = 200 MSPS, sine wave input clock, 1.5 V

differential clock amplitude, 50% clockduty cycle, – 1 dBFS differential analog input, internal reference mode, 0-db gain, DDR LVDS data output (unless otherwisenoted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= 20 MHz 86F

= 70 MHz 75 84F

= 100 MHz 78F

= 170 MHz 790 dB gain, 2 V

FS 75HD3 Third harmonic F

= 230 MHz dBc3 dB gain, 1.4 V

FS 780 dB gain, 2 V

FS 74F

= 300 MHz

3 dB gain, 1.4 V

FS 760 dB gain, 2 V

FS 68F

= 400 MHz

3 dB gain, 1.4 V

FS 70F

= 20 MHz 95F

= 70 MHz 92F

= 100 MHz 92Worst harmonic (other than HD2, HD3) F

= 170 MHz 90 dBcF

= 230 MHz 90F

= 300 MHz 88F

= 400 MHz 87F

= 20 MHz 83F

= 70 MHz 73 82F

= 100 MHz 76THD Total harmonic distortion F

= 170 MHz 77 dBcF

= 230 MHz 73F

= 300 MHz 72F

= 400 MHz 65ENOB Effective number of bits F

= 70 MHz 10.3 10.8 bitsF

IN1

= 50.03 MHz, F

IN2

= 46.03 MHz, 91-7 dBFS each toneIMD Two-tone intermodulation distortion dBFSF

IN1

= 190.1 MHz, F

IN2

= 185.02 MHz,

86-7 dBFS each tonePSRR AC power supply rejection ratio 30 MHz, 200 mV

signal on 3.3-V supply 35 dBcRecovery to 1% (of final value) for 6-dB overload ClockVoltage overload recovery time 1with sine-wave input at Nyquist frequency cycles

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DIGITAL CHARACTERISTICS

(1)

TIMING CHARACTERISTICS – LVDS AND CMOS MODES

(1)

ADS5517

SLWS203 – DECEMBER 2007

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logiclevel 0 or 1 AVDD = DRVDD = 3.3 V, I

= 3.5 mA, R

= 100 Ω

(2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUTS

High-level input voltage 2.4 VLow-level input voltage 0.8 VHigh-level input current 33 µALow-level input current – 33 µAInput capacitance 4 pF

DIGITAL OUTPUTS – CMOS MODE

High-level output voltage 3.3 VLow-level output voltage 0 VOutput capacitance Output capacitance inside the device, from each output to 2 pFground

DIGITAL OUTPUTS – LVDS MODE

High-level output voltage 1375 mVLow-level output voltage 1025 mVOutput differential voltage, |V

| 225 350 425 mVV

Output offset voltage, single-ended Common-mode voltage of OUTP and OUTM 1200 mVOutput capacitance inside the device, from either output toOutput capacitance 2 pFground

(1) All LVDS and CMOS specifications are characterized, but not tested at production.(2) I

refers to the LVDS buffer current setting, R

is the differential load resistance between the LVDS output pair.

Typical values are at 25 °C, min and max values are across the full temperature range T

MIN

= – 40 °C to T

MAX

= 85 °C, AVDD =DRVDD = 3.3 V, sampling frequency = 200 MSPS, sine wave input clock, 1.5 V

clock amplitude, C

= 5 pF

(2)

, I

= 3.5 mA,R

= 100 Ω

(3)

, no internal termination, unless otherwise noted.For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this datasheet.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Aperture delay 1.2 nst

Aperture jitter 150 fs rmsTime to valid data after coming out of

100STANDBY modeWake-up time µsTime to valid data after stopping and

100restarting the input clock

clockLatency 14

cycles

DDR LVDS MODE

(4)

Data setup time

(5)

Data valid

(6)

to zero-cross of CLKOUTP 1.0 1.5 nsZero-cross of CLKOUTP to data becomingt

Data hold time

(5)

0.35 0.8 nsinvalid

(6)

(1) Timing parameters are specified by design and characterization and not tested in production.(2) C

is the effective external single-ended load capacitance between each output pin and ground.(3) I

refers to the LVDS buffer current setting; R

is the differential load resistance between the LVDS output pair.(4) Measurements are done with a transmission line of 100 Ωcharacteristic impedance between the device and the load.(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assumethat the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appearas reduced timing margin.(6) Data valid refers to logic high of +50 mV and logic low of – 50 mV.

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ADS5517

SLWS203 – DECEMBER 2007

TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this datasheet.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input clock rising edge zero-cross to outputt

PDI

Clock propagation delay

(7)

3.7 4.4 5.1 nsclock rising edge zero-crossDuty cycle of differential clock,LVDS bit clock duty cycle (CLKOUTP-CLKOUTM) 45% 50% 55%80 ≤Fs ≤200 MSPSRise time measured from – 50 mV to 50t

, Data rise time, mV

50 100 200 pst

Data fall time Fall time measured from 50 mV to – 50 mV1≤Fs ≤200 MSPSRise time measured from – 50 mV to 50t

CLKRISE

, Output clock rise time, mV

50 100 200 pst

CLKFALL

Output clock fall time Fall time measured from 50 mV to – 50 mV1≤Fs ≤200 MSPSOutput clock jitter Cycle-to-cycle jitter 120 ps ppOutput enable (OE) to valid data Time to valid data after OE becomest

1µsdelay active

PARALLEL CMOS MODE

Data valid

(8)

to 50% of CLKOUT rising nst

Data setup time

(5)

1.8 2.6edge

50% of CLKOUT rising edge to datat

Data hold time

(5)

0.4 0.8 nsbecoming invalid

(8)

Input clock rising edge zero-cross to 50%t

PDI

Clock propagation delay

(7)

2.6 3.4 4.2 nsof CLKOUT rising edgeDuty cycle of output clock (CLKOUT)Output clock duty cycle 45%80 ≤Fs ≤200 MSPSRise time measured from 20% to 80% ofDRVDDt

, Data rise time,

Fall time measured from 80% to 20% of 0.8 1.5 2.0 nst

Data fall time

DRVDD

1≤Fs ≤200 MSPSRise time measured from 20% to 80% ofDRVDDt

CLKRISE

, Output clock rise time,

Fall time measured from 80% to 20% of 0.4 0.8 1.2 nst

CLKFALL

Output clock fall time

DRVDD

1≤Fs ≤200 MSPSOutput enable (OE) to valid data Time to valid data after OE becomest

50 nsdelay active

(7) To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay (t

) to get the desired setup and holdtimes. Use either of these equations to calculate t

:Desired setup time = t

- (t

PDI

- t

)Desired hold time = (t

PDI

+ t

)-t

D(8) Data valid refers to logic high of 2 V and logic low of 0.8 V

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O O O O O O O OO O

E E E E E E E EE E

Input

Clock

CLKOUTM

CLKOUTP

OutputData

DXP,DXM

DDR

LVDS

N–14 N–13 N–12 N–11 N–10 N–1 NN+1 N+2

N–14 N–13 N–12 N–11 N–10 N N+2

14ClockCycles

CLKOUT

OutputData

D0–D10

Parallel

CMOS

Input

Signal

Sample

N+1

N+2 N+3 N+4

tPDI

tsu

tPDI

CLKP

CLKM

N+14

N+15 N+16 N+17

tsu

E – EvenBitsD0,D2,D4,D6,D8,D10

O – OddBitsD1,D3,D5,D7,D9 N+1N–1

ADS5517

SLWS203 – DECEMBER 2007

Figure 1. Latency

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Input

Clock

Output

Clock

Output

DataPair

CLKM

CLKOUTP

Dn_Dn+1_P,

Dn_Dn+1_M

CLKP

tPDI

tsu th

thtsu

CLKOUTM

Dn(Note A) Dn+1(Note B)

Input

Clock

Output

Clock

Output

Data

CLKM

CLKP

tPDI

tsu

CLKOUT

Dn(Note A)

ADS5517

SLWS203 – DECEMBER 2007

A. Dn – Bits D1, D3, D5, D7, and D9B. Dn+1 – Bits D0, D2, D4, D6, D8, and D10

Figure 2. LVDS Mode Timing

A. Dn – Bits D0 – D10

Figure 3. CMOS Mode Timing

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DEVICE PROGRAMMING MODES

USING PARALLEL INTERFACE CONTROL ONLY

USING SERIAL INTERFACE PROGRAMMING ONLY

USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS

ADS5517

SLWS203 – DECEMBER 2007

ADS5517 offers flexibility with several programmable features that are easily configured.

The device can be configured independently using either parallel interface control or serial interfaceprogramming.

In addition, the device supports a third configuration mode, where both the parallel interface and the serial controlregisters are used. In this mode, the priority between the parallel and serial interfaces is determined by a prioritytable (Table 2 ). If this additional level of flexibility is not required, the user can select either the serial interfaceprogramming or the parallel interface control.

To control the device using parallel interface, keep RESET tied to high (DRVDD). Pins DFS, MODE, SEN,SCLK, and SDATA are used to directly control certain modes of the ADC. The device is configured byconnecting the parallel pins to the correct voltage levels (as described in Table 3 to Table 7 ). There is no need toapply reset.

In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions arecontrolled in this mode — standby, selection between LVDS/CMOS output format, internal/external reference,two's complement/straight binary output format, and position of the output clock edge.

Table 1 has a description of the modes controlled by the parallel pins.

Table 1. Parallel Pin Definition

PIN CONTROL MODES

DFS DATA FORMAT and the LVDS/CMOS output interfaceMODE Internal or external referenceSEN CLKOUT edge programmabilitySCLK LOW SPEED mode control for low sampling frequencies (< 50 MSPS)SDATA STANDBY mode – Global (ADC, internal references and output buffers are powered down)

To program using the serial interface, the internal registers must first be reset to their default values, and theRESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and areused to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESETpin, or by a high setting on the <RST> bit (D1 in register 0x6C). The serial interface section describes theregister programming and register reset in more detail.

Since the parallel pins DFS and MODE are not used in this mode, they must be tied to ground.

For increased flexibility, a combination of serial interface registers and parallel pin controls (DFS, MODE) canalso be used to configure the device.

The serial registers must first be reset to their default values and the RESET pin must be kept low. In this mode,SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.The registers are reset either by applying a pulse on RESET pin or by a high setting on the <RST> bit (D1 inregister 0x6C). The serial interface section describes the register programming and register reset in more detail.

The parallel interface control pins DFS and MODE are used and their function is determined by the appropriatevoltage levels as described in Table 6 and Table 7 . The voltage levels are derived by using a resistor string asillustrated in Figure 4 . Since some functions are controlled using both the parallel pins and serial registers, thepriority between the two is determined by a priority table (Table 2 ).

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(1/3) AVDD

ToParallelPin

AVDD

AVDDGND

(2/3) AVDD

ADS5517

SLWS203 – DECEMBER 2007

Table 2. Priority Between Parallel Pins and Serial Registers

PIN FUNCTIONS SUPPORTED PRIORITY

When using the serial interface, bit <REF> (register 0x6D, bit D4) controls this mode, ONLYMODE Internal/External reference

if the MODE pin is tied low.When using the serial interface, bit <DF> (register 0x63, bit D3) controls this mode, ONLY ifDATA FORMAT

the DFS pin is tied low.DFS

When using the serial interface, bit <ODI> (register 0x6C, bits D3-D4) controls LVDS/CMOSLVDS/CMOS

selection independent of the state of DFS pin

Figure 4. Simple Scheme to Configure Parallel Pins

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DESCRIPTION OF PARALLEL PINS

SERIAL INTERFACE

ADS5517

SLWS203 – DECEMBER 2007

Table 3. SCLK Control Pin

SCLK (Pin 29) DESCRIPTION

0 LOW SPEED mode Disabled - Use for sampling frequencies above 50 MSPS.DRVDD LOW SPEED mode Enabled - Use for sampling frequencies below 50 MSPS.

Table 4. SDATA Control Pin

SDATA (Pin 28) DESCRIPTION

0 Normal operation (Default)DRVDD STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.

Table 5. SEN Control Pin

SEN (Pin 27) DESCRIPTION

0CMOS mode: CLKOUT edge later by (3/12)Ts

(1)

;LVDS mode: CLKOUT edge aligned with data transition(1/3)DRVDD CMOS mode: CLKOUT edge later by (2/12)Ts ; LVDS mode: CLKOUT edge aligned with data transition(2/3)DRVDD CMOS mode: CLKOUT edge later by (1/12)Ts ; LVDS mode: CLKOUT edge earlier by (1/12)TsDRVDD Default CLKOUT position

(1) Ts = 1/Sampling Frequency

Table 6. DFS Control Pin

DFS (Pin 6) DESCRIPTION

0 2's complement data and DDR LVDS output (Default)(1/3)DRVDD 2's complement data and parallel CMOS output(2/3)DRVDD Offset binary data and parallel CMOS outputDRVDD Offset binary data and DDR LVDS output

Table 7. MODE Control Pin

MODE (Pin 23) DESCRIPTION

0 Internal reference(1/3)AVDD External reference(2/3)AVDD External referenceAVDD Internal reference

The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After devicepower-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET(of width greater than 10 ns).

Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edgeof SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edgewhen SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded inmultiples of 16-bit words within a single active SEN pulse.

The first 8 bits form the register address and the remaining 8 bits form the register data. The interface can workwith SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK dutycycle.

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t(SCLK) t(DSU)

t(DH)

t(SLOADS)

D7A7 D3A3 D5A5 D1A1 D6A6 D2A2 D4A4 D0A0

SDATA

SCLK

SEN

RESET

t(SLOADH)

SERIAL INTERFACE TIMING CHARACTERISTICS

ADS5517

SLWS203 – DECEMBER 2007

After power-up, the internal registers must be reset to their default values. This is done in one of two ways:1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) asshown in Figure 5 .

OR2. By applying software reset. Using the serial interface, set the <RST> bit (D1 in register 0x6C) to high. Thisinitializes the internal registers to their default values and then self-resets the <RST> bit to low. In this casethe RESET pin is kept low.

Figure 5. Serial Interface Timing Diagram

Typical values at 25 °C, min and max values across the full temperature range T

MIN

= – 40 °C to T

MAX

= 85 °C,AVDD = DRVDD = 3.3 V (unless otherwise noted)

MIN TYP MAX UNIT

SCLK

SCLK frequency > DC 20 MHzt

SLOADS

SEN to SCLK setup time 25 nst

SLOADH

SCLK to SEN hold time 25 nst

DSU

SDATA setup time 25 nst

SDATA hold time 25 ns

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RESET TIMING

PowerSupply

AVDD,DRVDD

RESET

SEN

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Typical values at 25 °C, min and max values across the full temperature range T

MIN

= – 40 °C to T

MAX

= 85 °C,AVDD = DRVDD = 3.3 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Power-on delay Delay from power-up of AVDD and DRVDD to RESET pulse active 5 mst

Reset pulse width Pulse width of active RESET signal 10 nst

Power-up time Delay from power-up of AVDD and DRVDD to output stable 6.5 ms

NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.For parallel interface operation, RESET has to be tied permanently HIGH.

Figure 6. Reset Timing Diagram

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SERIAL REGISTER MAP

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Table 8 gives a summary of all the modes that can be programmed through the serial interface.

Table 8. Summary of Functions Supported by Serial Interface

(1) (2)

ADDRESS REGISTER FUNCTIONSIN HEX

A7 – A0 D7 D6 D5 D4 D3 D2 D1 D0

<DATA POSN>OUTPUT DATA <CLKOUT POSN>62

POSITION OUTPUT CLOCK POSITION PROGRAMMABILITYPROGRAMMABILITY

ENABLE LOW DATA FORMAT -GLOBAL63 SAMPLING 2's COMP orPOWER

FREQUENCY STRAIGHTDOWN

OPERATION BINARY

<TEST PATTERN> – ALL 0S, ALL 1s,65

TOGGLE, RAMP, CUSTOM PATTERN68 <GAIN> GAIN PROGRAMMING <GAIN> - 1 dB to 6 dB69 <CUSTOM A> CUSTOM PATTERN (D7 TO D0)6A <CUSTOM B> CUSTOM PATTERN (D13 TO D8)6B <CLKIN GAIN> INPUT CLOCK BUFFER GAIN PROGRAMMABILITY

<RST><ODI> OUTPUT DATA INTERFACE6C SOFTWARE- DDR LVDS or PARALLEL CMOS

RESET

<REF>

INTERNAL or6D <SCALING> POWER SCALING

EXTERNAL

REFERENCE

<DATA TERM> <LVDS CURR><CLKOUT TERM>7E INTERNAL TERMINATION – DATA LVDS CURRENTINTERNAL TERMINATION – OUTPUT CLOCKOUTPUTS PROGRAMMABILITY

<CURR DOUBLE>7F LVDS CURRENT

DOUBLE

(1) The unused bits in each register (shown by blank cells in above table) must be programmed as ‘ 0 ’ .(2) Multiple functions in a register can be programmed in a single write operation.

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DESCRIPTION OF SERIAL REGISTERS

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Each register function is explained in detail below.

Table 9. Serial Register A

A7 – A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0

<DATA POSN>OUTPUT DATA <CLKOUT POSN>62

POSITION OUTPUT CLOCK POSITION PROGRAMMABILITYPROGRAMMABILITY

D4 — D0 <CLKOUT POSN> Output clock position programmability00001 Default CLKOUT position after reset. Setup/hold timings with this clockposition are specified in the timing characteristics table.XX011 CMOS – Falling edge later by (1/12) TsLVDS – Falling edge earlier by (1/12) TsXX101 CMOS – Falling edge later by (3/12) TsLVDS – Falling edge aligned with data transitionXX111 CMOS – Falling edge later by (2/12) TsLVDS – Falling edge aligned with data transition01XX1 CMOS – Rising edge later by (1/12) TsLVDS – Rising edge earlier by (1/12) Ts10XX1 CMOS – Rising edge later by (3/12) TsLVDS – Rising edge aligned with data transition11XX1 CMOS – Rising edge later by (2/12) TsLVDS – Rising edge aligned with data transition

D6 — D5 <DATA POSN> Output Switching Noise and Data PositionProgrammability (in CMOS mode ONLY) (Only in CMOS mode)00 Data Position 1 – Default output data position after reset. Setup/holdtimings with this data position are specified in the timing characteristicstable.01 Data Position 2 – Setup time increases by (2/36) Ts10 Data Position 3 – Setup time increases by (5/36) Ts11 Data Position 4 – Setup time decreases by (6/36) Ts

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Table 10. Serial Register B

A7 – A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0

<DF><LOW SPEED><STBY> DATAENABLE LOWGLOBAL FORMAT63 SAMPLINGPOWER 2's COMP orFREQUENCYDOWN STRAIGHTOPERATION

BINARY

D3 <DF> Output data format0 2's complement1 Straight binary

D4 <LOW SPEED> Low sampling frequency operation0 Default SPEED mode for 50 < Fs ≤200 MSPS1 Low SPEED mode 1 ≤Fs ≤50 MSPS

D7 <STBY> Global power down0 Normal operation1 Global power down (includes ADC, internal references and output buffers)

Table 11. Serial Register C

A7 – A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0

<TEST PATTERNS> — ALL 0S, ALL 1s,65

TOGGLE, RAMP, CUSTOM PATTERN

D7 — D5 <TEST PATTERN> Outputs selected test pattern on data lines000 Normal operation001 All 0s010 All 1s011 Toggle pattern – alternate 1s and 0s on each data output and acrossdata outputs100 Ramp pattern – Output data ramps from 0x0000 to 0x3FFF by onecode every clock cycle101 Custom pattern – Outputs the custom pattern in CUSTOM PATTERNregisters A and B111 Unused

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Table 12. Serial Register D

A7 – A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0

68 <GAIN> GAIN PROGRAMMING <GAIN> - 1 dB to 6 dB

D3 — D0 <GAIN> Gain programmability1000 0 dB gain, default after reset1001 1 dB1010 2 dB1011 3 dB1100 4 dB1101 5 dB1110 6 dB

Table 13. Serial Register E

A7 – A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0

69 <CUSTOM A> CUSTOM PATTERN (D4 TO D0)6A <CUSTOM B> CUSTOM PATTERN (D10 TO D5)

Reg 69 D7 — D3 Program bits D4 to D0 of custom patternReg 6A D5 — D0 Program bits D10 to D5 of custom pattern

Table 14. Serial Register F

A7 – A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0

6B <CLKIN GAIN> INPUT CLOCK BUFFER GAIN PROGRAMMABILITY

D5 - D0 <CLKIN GAIN> Input clock buffer gain programming110010 Gain 4, maximum gain101010 Gain 3100110 Gain 2100000 Gain1, default after reset100011 Gain 0 minimum gain

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Table 15. Serial Register G

A7 – A0 (hex) D7 D6 D5 D4 D3 D2 D1 D0

<ODI> OUTPUT DATA <RST>6C INTERFACE - DDR LVDS OR SOFTWAREPARALLEL CMOS RESET

D1 <RST> Software resets the ADC1 Resets all registers to default values

D4 — D3 <ODI> Output data interface00 DDR LVDS outputs, default after reset01 DDR LVDS outputs11 Parallel CMOS outputs

Table 16. Serial Register H

A7 – A0 D7 D6 D5 D4 D3 D2 D1 D0

<REF> INTERNAL or6D <SCALING> POWER SCALING

EXTERNAL REFERENCE

D4 <REF> Reference0 Internal reference1 External reference mode, force voltage on Vcm to set reference.

D7 — D5 <SCALING> Program power scaling at lower samplingfrequencies001 Use for Fs > 150 MSPS, default after reset011 Power Mode 1, use for 105 < Fs ≤150 MSPS101 Power Mode 2, use for 50 < Fs ≤105111 Power Mode 3, use for Fs ≤50 MSPS

Table 17. Serial Register I

A7 – A0 D7 D6 D5 D4 D3 D2 D1 D0

<LVDS CURR> LVDS<DATA TERM> INTERNAL TERMINATION – <CLKOUT TERM> INTERNAL7E CURRENTDATA OUTPUTS TERMINATION – OUTPUT CLOCK

PROGRAMMABILITY

D1 — D0 <LVDS CURR> LVDS buffer current programming00 3.5 mA, default01 2.5 mA10 4.5 mA11 1.75 mA

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D4 — D2 <CLKOUT TERM> LVDS internal termination for outputclock pin (CLKOUT)000 No internal termination001 325 Ω

010 200 Ω

011 125 Ω

100 170 Ω

101 120 Ω

110 100 Ω

111 75 Ω

D7 — D5 <DATA TERM> LVDS internal termination for output datapins000 No internal termination001 325 Ω

010 200 Ω

011 125 Ω

100 170 Ω

101 120 Ω

110 100 Ω

111 75 Ω

Table 18. Serial Register J

A7 – A0 D7 D6 D5 D4 D3 D2 D1 D0

<CURR DOUBLE> LVDS7F

CURRENT DOUBLE

D7 — D6 <CURR DOUBLE> LVDS buffer current double00 Value specified by <LVDS CURR>01 2x data, 2x clockout currents10 1x data, 2x clockout currents11 2x data, 4x clockout currents

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PIN CONFIGURATION (LVDS MODE)

DRGND

VCM

DRVDD

AGND

OVR

INP

CLKOUTM

INM

CLKOUTP

AGND

DFS

AVDD

AGND

AVDD

AGND

IREF

CLKP

AVDD

CLKM

MODE

AGND

AVDD

DRGND

D9_D10_P

DRVDD

D9_D10_M

D7_D8_P

D7_D8_M

D5_D6_P

D5_D6_M

RESET

D3_D4_P

SCLK

D3_D4_M

SDATA

D1_D2_P

SEN

D1_D2_M

AVDD

LOW_D0_P

AGND

LOW_D0_M

ThermalPad

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RGZ PACKAGE

(TOP VIEW)

Figure 7. LVDS Mode Pinout

PIN ASSIGNMENTS – LVDS Mode

PIN PIN NUMBERPIN NAME DESCRIPTION

TYPE NUMBER OF PINS

8, 18, 20,AVDD Analog power supply I 622, 24, 269, 12, 14,AGND Analog ground I 617, 19, 25CLKP, CLKM Differential clock input I 10, 11 2INP, INM Differential analog input I 15, 16 2Internal reference mode – Common-mode voltage output.VCM External reference mode – Reference input. The voltage forced on this pin sets I/O 13 1the internal references.IREF Current-set resistor, 56.2-k Ωresistor to ground. I 21 1Serial interface RESET input.When using the serial interface mode, the user MUST initialize internal registersthrough hardware RESET by applying a high-going pulse on this pin, or by usingRESET the software reset option. See the SERIAL INTERFACE section. I 30 1In parallel interface mode, the user has to tie the RESET pin permanently HIGH.(SDATA and SEN are used as parallel pin controls in this mode)The pin has an internal 100-k Ωpull-down resistor.

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PIN ASSIGNMENTS – LVDS Mode (continued)

PIN PIN NUMBERPIN NAME DESCRIPTION

TYPE NUMBER OF PINS

This pin functions as serial interface clock input when RESET is low.It functions as LOW SPEED control pin when RESET is tied high. Tie SCLK toSCLK I 29 1LOW for Fs > 50 MSPS and SCLK to HIGH for Fs ≤50 MSPS. See Table 3 .The pin has an internal 100-k Ωpull-down resistor.This pin functions as serial interface data input when RESET is low. It functions asSTANDBY control pin when RESET is tied high.SDATA I 28 1See Table 4 for detailed information.The pin has an internal 100 k Ωpull-down resistor.This pin functions as serial interface enable input when RESET is low. It functionsas CLKOUT edge programmability when RESET is tied high. See Table 5 forSEN I 27 1detailed information.

The pin has an internal 100-k Ωpull-up resistor to DRVDD.Output buffer enable input, active high. The pin has an internal 100-k Ωpull-upOE I 7 1resistor to DRVDD.Data Format Select input. This pin sets the DATA FORMAT (Twos complement orDFS Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed I 6 1information.

Mode select input. This pin selects the Internal or External reference mode. SeeMODE I 23 1Table 7 for detailed information.CLKOUTP Differential output clock, true O 5 1CLKOUTM Differential output clock, complement O 4 1LOW_D0_P Differential output data LOW and D0 multiplexed, true O 38 1LOW_D0_M Differential output data LOW and D0 multiplexed, complement O 37 1D1_D2_P Differential output data D1 and D2 multiplexed, true O 40 1D1_D2_M Differential output data D1 and D2 multiplexed, complement O 39 1D3_D4_P Differential output data D3 and D4 multiplexed, true O 42 1D3_D4_M Differential output data D3 and D4 multiplexed, complement O 41 1D5_D6_P Differential output data D5 and D6 multiplexed, true O 44 1D5_D6_M Differential output data D5 and D6 multiplexed, complement O 43 1D7_D8_P Differential output data D7 and D8 multiplexed, true O 46 1D7_D8_M Differential output data D7 and D8 multiplexed, complement O 45 1D9_D10_P Differential output data D9 and D10 multiplexed, true O 48 1D9_D10_M Differential output data D9 and D10 multiplexed, complement O 47 1OVR Out-of-range indicator, CMOS level signal O 3 1DRVDD Digital and output buffer supply I 2, 35 2DRGND Digital and output buffer ground I 1, 36 231, 32, 33,NC Do not connect 434Connect the pad to the ground plane. See Board Design Considerations inPAD 0 1application information section.

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PIN CONFIGURATION (CMOS MODE)

DRGND

VCM

DRVDD

AGND

OVR

INP

UNUSED

INM

CLKOUT

AGND

DFS

AVDD

AGND

AVDD

AGND

IREF

CLKP

AVDD

CLKM

MODE

AGND

AVDD

DRGND

D10

DRVDD

RESET

SCLK

SDATA

SEN

AVDD

AGND

ThermalPad

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RGZ PACKAGE

(TOP VIEW)

Figure 8. CMOS Mode Pinout

PIN ASSIGNMENTS – CMOS Mode

PIN PIN NUMBERPIN NAME DESCRIPTION

TYPE NUMBER OF PINS

8, 18, 20,AVDD Analog power supply I 622, 24, 269, 12, 14, 17,AGND Analog ground I 619, 25CLKP, CLKM Differential clock input I 10, 11 2INP, INM Differential analog input I 15, 16 2Internal reference mode – Common-mode voltage output.VCM External reference mode – Reference input. The voltage forced on this pin sets the I/O 13 1internal references.IREF Current-set resistor, 56.2-k Ωresistor to ground. I 21 1Serial interface RESET input.When using the serial interface mode, the user MUST initialize internal registersthrough hardware RESET by applying a high-going pulse on this pin, or by usingthe software reset option. See the SERIAL INTERFACE section.RESET I 30 1In parallel interface mode, the user has to tie RESET pin permanently HIGH.(SDATA and SEN are used as parallel pin controls in this mode).The pin has an internal 100-k Ωpull-down resistor.This pin functions as serial interface clock input when RESET is low.It functions as LOW SPEED control pin when RESET is tied high. Tie SCLK toSCLK I 29 1LOW for Fs > 50 MSPS and SCLK to HIGH for Fs ≤50 MSPS. See Table 3 .The pin has an internal 100-k Ωpull-down resistor.

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PIN ASSIGNMENTS – CMOS Mode (continued)

PIN PIN NUMBERPIN NAME DESCRIPTION

TYPE NUMBER OF PINS

This pin functions as serial interface data input when RESET is low. It functions asSTANDBY control pin when RESET is tied high.SDATA I 28 1See Table 4 for detailed information.The pin has an internal 100 k Ωpull-down resistor.This pin functions as serial interface enable input when RESET is low. It functionsas CLKOUT edge programmability when RESET is tied high. See Table 5 forSEN I 27 1detailed information.

Mode select input. This pin selects the internal or external reference mode. SeeMODE I 23 1Table 7 for detailed information.CLKOUT CMOS output clock O 5 1D0 CMOS output data D0 (LSB) O 38 1D1 CMOS output data D1 O 39 1D2 CMOS output data D2 O 40 1D3 CMOS output data D3 O 41 1D4 CMOS output data D4 O 42 1D4 CMOS output data D5 O 43 1D6 CMOS output data D6 O 44 1D7 CMOS output data D7 O 45 1D8 CMOS output data D8 O 46 1D9 CMOS output data D9 O 47 1D10 CMOS output data D10 (MSB) O 48 1OVR Out-of-range indicator, CMOS level signal O 3 1DRVDD Digital and output buffer supply I 2, 35 2DRGND Digital and output buffer ground I 1, 36 2UNUSED Unused pin in CMOS mode 4 131, 32, 33,NC Do not connect 534, 37Connect the pad to the ground plane. See Board Design Considerations inPAD 0 1application information section.

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TYPICAL CHARACTERISTICS

-140

f Frequency MHz- -

Amplitude dB-

-20

-40

-60

-80

-100

-120

0100

5010 403020 7060 80 90

SFDR=86.68dBc,

SNR=67.27dBFS,

SINAD=67.19dBFS

THD=83.31dBc

-140

f Frequency MHz- -

Amplitude dB-

-20

-40

-60

-80

-100

-120

SFDR=89.4dBc,

SNR=66.91dBFS,

SINAD=66.84dBFS

THD=84.11dBc

0100

5010 403020 7060 80 90

-140

f Frequency MHz- -

Amplitude dB-

-20

-40

-60

-80

-100

-120

SFDR=82.5dBc,

SNR=66.82dBFS,

SINAD=66.69dBFS

THD=81.18dBc

0100

5010 403020 7060 80 90

-140

f Frequency MHz- -

Amplitude dB-

-20

-40

-60

-80

-100

-120

SFDR=74.46dBc,

SNR=66.09dBFS,

SINAD=65.13dBFS

THD=71.17dBc

0100

5010 403020 7060 80 90

-140

f Frequency MHz- -

Amplitude dB-

-20

-40

-60

-80

-100

-120

0100

5010 403020 7060 80 90

SFDR=66.56dBc,

SNR=65.04dBFS,

SINAD=62.77dBFS

THD=65.61dBc

-140

f Frequency MHz- -

Amplitude dB-

-20

-40

-60

-80

-100

-120

f =185.3MHz,-7dBFS,

2-ToneIMD,87

IN1

IN2 =190.1MHz,-7dBFS,

SFDR=98dBFS,

dBFS

100

10 403020 807050 90

ADS5517

SLWS203 – DECEMBER 2007

All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sampling frequency = 200 MSPS, sine wave input clock, 1.5 V

differentialclock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS dataoutput (unless otherwise noted)

FFT for 20 MHz INPUT SIGNAL FFT for 70 MHz INPUT SIGNAL

Figure 9. Figure 10.

FFT for 130 MHz INPUT SIGNAL FFT for 270 MHz INPUT SIGNAL

Figure 11. Figure 12.

FFT for 430 MHz INPUT SIGNAL INTERMODULATION DISTORTION (IMD) vs FREQUENCY

Figure 13. Figure 14.

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f − InputFrequency − MHz

0 50 100 150 200 250 300 350 400

SNR − dBFS

61 450 500

f InputFrequency MHz

IN - -

SFDR dBc-

0 50025050 200150100 450400

350300

f − InputFrequency − MHz

SFDR − dBc

50 100 150 200 250 300 350 400 450 500

3dB

0dB

2dB

6dB

4dB

1dB 5dB

f − InputFrequency − MHz

SNR − dBFS

0 50 100 150 200 250 300 350 400

2dB 3dB

0dB

5dB

6dB

1dB

4dB

450

AV SupplyVoltage V

DD - -

SFDR dBc

SNR dBFS-

3.63.33.23.13 3.53.4

SFDR

SNR

F =50.1MHz

DRV =3.3V

DRV − SupplyV

DD oltage − V

3.0 3.1 3.2 3.3 3.4 3.5 3.6

SFDR − dBc

SNR − dBFS

SNR

SFDR

f =50.1MHz

DD =3.3V

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TYPICAL CHARACTERISTICS (continued)All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sampling frequency = 200 MSPS, sine wave input clock, 1.5 V

differentialclock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS dataoutput (unless otherwise noted)

SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY

Figure 15. Figure 16.

SFDR vs GAIN SNR vs GAIN

Figure 17. Figure 18.

PERFORMANCE vs AVDD PERFORMANCE vs DRVDD

Figure 19. Figure 20.

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SFDR − dBc

SNR − dBFS

SNR

SFDR

T − Free-AirT

Aemperature − C

−40 10 35 85

f =50.1MHz

50−15

F − SamplingFrequency − MSPS

40 60 80 100 120 140 160 180

SNR-dBFS

200

Default PowerMode1

PowerMode2

PowerMode3

Input Amplitude − dBFS

105

−40 −30 −20 −10 0

SFDR − dBc

SNR − dBFS

SFDR(dBc)

SNR(dBFS)

f =50.1MHz

Clock Amplitude-VPP

SFDR-dBc

SNR-dBFS

SNR

f =20.1MHz

SineWaveInputClock

SFDR

1.30.80.50.3 1.5 2.11.1 2.3 2.81.8 2.5

InputClockDutyCycle − %

35 40 45 50 55 60

SFDR −dBc

SNR − dBFS

SFDR

f =20.1MHz

SNR

OutputCode

Occurence −%

1024

1026

1029

100

1021

1023

1025

1028

110

1022

1027

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SLWS203 – DECEMBER 2007

TYPICAL CHARACTERISTICS (continued)All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sampling frequency = 200 MSPS, sine wave input clock, 1.5 V

differentialclock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS dataoutput (unless otherwise noted)

SNR vs SAMPLING FREQUENCYPERFORMANCE vs TEMPERATURE (Across Power Scaling Modes)

Figure 21. Figure 22.

PERFORMANCE vs INPUT AMPLITUDE PERFORMANCE vs CLOCK AMPLITUDE

Figure 23. Figure 24.

OUTPUT NOISE HISTOGRAM WITHPERFORMANCE vs INPUT CLOCK DUTY CYCLE INPUTS TIED TO COMMON-MODE

Figure 25. Figure 26.

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VoltageForcedontheCMPin − V

1.4 1.45 1.5 1.55 1.6

SFDR − dBc

SNR − dBFS

SFDR

SNR

f =20MHz

f-Frequencyof ACCommon-ModeVoltage-MHz

-70

-65

-60

-45

-40

-35

0 20 40 60 80 100

CMRR − dBc

-55

-50

f − Frequency − MSPS

100

0 20 40 60 80 120 180

DRVDDCurrent − mA

200

160

DDRLVDS

CMOS

5-pFLoadCap

CMOS

0-pFLoadCap

CMOS

10-pFLoadCap

100 140

F − SamplingFrequency − MSPS

0.64

0.70

0.76

0.82

0.88

0.94

1.00

1.06

1.12

1.18

1.24

0 20 40 60 80 100 120 140 160 180

P − PowerDissipation − W

LVDSMode

Default

PowerMode1

PowerMode2

PowerMode3

200

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SLWS203 – DECEMBER 2007

TYPICAL CHARACTERISTICS (continued)All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sampling frequency = 200 MSPS, sine wave input clock, 1.5 V

differentialclock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS dataoutput (unless otherwise noted)

PERFORMANCE IN EXTERNAL REFERENCE MODE COMMON-MODE REJECTION RATIO vs FREQUENCY

Figure 27. Figure 28.

POWER DISSIPATION vs DIGITAL CURRENT vsSAMPLING FREQUENCY SAMPLING FREQUENCY (Parallel CMOS)

Figure 29. Figure 30.

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f -InputFrequency-MHz

f -SamplingFrequency-MSPS

SNR-dBFS

61.5

62.5

63.5

64.5

65.5

66.5

10 50 100 150 200 250 300 350 400 450 500

100

120

140

160

180

200

60 61 62 63 64 65 66 67

f -InputFrequency-MHz

f -SamplingFrequency-MSPS

10 50 100 150 200 250 300 350 400 450 500

100

120

140

160

180

200

50 55 60 65 70 75 80 85 90

SFDR-dBc

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TYPICAL CHARACTERISTICS (continued)All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sampling frequency = 200 MSPS, sine wave input clock, 1.5 V

differentialclock amplitude, 50% clock duty cycle, – 1 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS dataoutput (unless otherwise noted)

Figure 31. SNR Contour in dBFS

Figure 32. SFDR Contour in dBc

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APPLICATION INFORMATION

THEORY OF OPERATION

ANALOG INPUT

Resr

200 W

Lpkg

6nH 10 W

Sampling

Capacitor

Csamp

2.4pF

INP

INM

Cbond

2pF

50 W

Cpar1

0.8pF

Cpar2

1pF

Ron

15 W

Ron

10 W

Ron

15 W

Cpar2

1pF

50 W

1.6pF

Lpkg

6nH

10 W

Cbond

2pF Resr

200 W

Csamp

2.4pF

Sampling

Capacitor

Sampling

Switch

Sampling

Switch

R-C-RFilter

Drive Circuit Requirements

ADS5517

SLWS203 – DECEMBER 2007

ADS5517 is a low power 11-bit 200 MSPS pipeline ADC in a CMOS process. ADS5517 is based on switchedcapacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge ofthe external input clock. Once the signal is captured by the input sample and hold, the input sample issequentially converted by a series of lower resolution stages, with the outputs combined in a digital correctionlogic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of 14clock cycles. The output is available as 11-bit data, in DDR LVDS or CMOS and coded in either straight offsetbinary or binary 2 ’ s complement format.

The analog input consists of a switched-capacitor based differential sample and hold architecture, shown inFigure 33 .

This differential topology results in good ac-performance even for high input frequencies at high sampling rates.The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V available on VCMpin 13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM +0.5 V and VCM – 0.5 V, resulting in a 2-V

differential input swing. The maximum swing is determined by theinternal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).

Figure 33. Input Stage

The input sampling circuit has a high 3-dB bandwidth that extends up to 800 MHz (measured from the input pinsto the voltage across the sampling capacitors)

The input sampling circuit of the ADS5517 has a high 3-dB analog bandwidth of 800 MHz making it possible tosample input signals up to very high frequencies. To get best performance, it is recommended to have anexternal R-C-R filter across the input pins (Figure 34 ). This helps to filter the glitches due to the switching of thesampling capacitors. The R-C-R filter has to be designed to provide adequate filtering (for good performance)and at the same time ensure sufficient bandwidth over the desired frequency range.

In addition, it is recommended to have a 15- Ωseries resistor on each input line to damp out ringing caused bythe package parasitic. At higher input frequencies (> 100 MHz), a lower series resistance around 5 Ωto 10 Ωshould be used. It is also necessary to present low impedance (< 50 Ω) for the common-mode switchingcurrents. For example, this could be achieved by using two resistors from each input terminated to thecommon-mode voltage (Vcm).

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Example Drive Circuits

WBC1-1TLB

1:1 1:1

0.1 Fm

INP

INM

VCM

25 W

100 W

25 W

3.3pF

0.1 Fm

(Note A)

WBC1-1TLB

100 W33 W

33 W

Z andTFADC

-6

-5

-1

Magnitude − dB

f − Frequency − MHz

0 1000

-4

100 200 500 700

-2

-3

400300 600 800 900

250

350

Magnitude −W

f − Frequency − MHz

0 1000

500

100

100 200 500 700

200

150

300

400300 600 800 900

400

450

ADS5517

SLWS203 – DECEMBER 2007

Using 10- Ωseries resistance and 25 Ω-3.3 pF-25 Ωas the R-C-R filter, high effective bandwidth (700 MHz) canbe achieved, (see Figure 35 , transfer function from the analog input pins to the voltage across the samplingcapacitors).

In addition to the above ADC requirements, the drive circuit may have to be designed to provide a low insertionloss over the desired frequency range and matched impedance to the source. For this, the ADC input impedancehas to be taken into account (Figure 36 ).

A suitable configuration using RF transformers and including the R-C-R filter is shown in Figure 34 . Note the15- Ωseries resistors and the low common-mode impedance (using 33- Ωresistors terminated to VCM).

A. Use lower series resistance ( ≈5Ωto 10 Ω) at high input frequencies (> 100 MHz)

Figure 34. Example Drive Circuit With RF Transformers

Figure 35. Analog Input Bandwidth, TFADC (Actual Figure 36. Input Impedance, Z

ISilicon Data)

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Using RF transformers

Using Differential Amplifier Drive Circuits

RFIL

CFIL

0.1 Fm

10 Fm

RS T

||R

+VS

INP

INM

ADS5517

THS4509

VCM

500 W

200 W

500 W

0.1 Fm

–VS

ADS5517

SLWS203 – DECEMBER 2007

For optimum performance, the analog inputs have to be driven differentially. This improves the common-modenoise immunity and even order harmonic rejection. The single-ended signal is fed to the primary winding of theRF transformer. The transformer is terminated on the secondary side. Putting the termination on the secondaryside helps to shield the kickbacks caused by the sampling circuit from the RF transformer ’ s leakage inductances.The termination is accomplished by two resistors connected in series, with the center point connected to the 1.5V common-mode (VCM pin 13).

At higher input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) resultsin degraded even-order harmonic performance. Connecting two identical RF transformers back to back helpsminimize this mismatch and good performance is obtained for high frequency input signals. An additionaltermination resistor pair (Figure 34 ) may be required between the two transformers to improve the balancebetween the P and M sides. The center point of this termination must be connected to ground. (Note that thedrive circuit has to be tuned to account for this additional termination, to get the desired S11 and impedancematch).

Figure 37 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input todifferential output that can be interface to the ADC analog input pins. In addition to the single-ended to differentialconversion, the amplifier also provides gain (10 dB in Figure 37 ). R

FIL

helps to isolate the amplifier outputs fromthe switching input of the ADC. Together with C

FIL

, it forms a low-pass filter that band-limits the noise (and signal)at the ADC input. As the amplifier output is ac-coupled, the common-mode voltage of the ADC input pins is setusing two 200 Ωresistors connected to VCM.

The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADCinput pins can be biased to 1.5 V. In this case, use +4 V and -1 V supplies for the THS4509 so that its outputcommon-mode voltage (1.5 V) is at mid-supply.

Figure 37. Drive Circuit Using the THS4509

See the EVM User Guide (SLWU028 ) for more information.

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Input Common-Mode

200MSPS

(342 Am ) xFs

(1)

Reference

VCM

REFM

REFP

INTREF

EXTREF

Internal

Reference

Internal Reference

ADS5517

SLWS203 – DECEMBER 2007

To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1- µF low-inductance capacitorconnected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADCsinks a common-mode current in the order of 342 µA (at 200 MSPS). Equation 1 describes the dependency ofthe common-mode current and the sampling frequency.

This equation helps to design the output capability and impedance of the CM driving circuit accordingly.

ADS5517 has built-in internal references REFP and REFM, requiring no external components. Design schemesare used to linearize the converter load seen by the references; this and the integration of the requisite referencecapacitors on-chip eliminates the need for external decoupling. The full-scale input range of the converter can becontrolled in the external reference mode as explained below. The internal or external reference modes can beselected by controlling the MODE pin 23 (see Table 7 for details) or by programming the serial interface registerbit <REF> (Table 16 ).

Figure 38. Reference Section

When the device is in internal reference mode, the REFP and REFM voltages are generated internally.Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analoginput pins.

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External Reference

Full−scale differential input pp +(Voltage forced on VCM) 1.33

(2)

Low Sampling Frequency Operation

Clock Input

CLKP

VCM

5kW5kW

CLKM

VCM

ADS5517

SLWS203 – DECEMBER 2007

When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on theVCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differentialinput voltage corresponding to full-scale is given by Equation 2 .

In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is nochange in performance compared to internal reference mode.

For best performance at high sampling frequencies, ADS5517 uses a clock generator circuit to derive internaltiming for the ADC. The clock generator operates from 200 MSPS down to 50 MSPS in the DEFAULT SPEEDmode. The ADC enters this mode after applying reset (with serial interface configuration) or by tying SCLK pin tolow (with parallel configuration).

For low sampling frequencies (below 50 MSPS), the ADC must be put in the LOW SPEED mode. This mode canbe entered by:•setting the register bit <LOW SPEED> through the serial interface, OR•tying the SCLK pin to high (see Table 3 ) using the parallel configuration.

ADS5517 clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), withlittle or no difference in performance between configurations. The common-mode voltage of the clock inputs isset to VCM using internal 5-k Ωresistors as shown in Figure 39 . This allows the use of transformer-coupled drivecircuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources (Figure 40 and Figure 41 )

Figure 39. Internal Clock Buffer

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CLKP

CLKM

DifferentialSine-Wave

orPECL orLVDS

ClockInput

0.1 Fm

CLKP

CLKM

CMOSClockInput

0.1 Fm

Clock Buffer Gain

ADS5517

SLWS203 – DECEMBER 2007

For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility tocommon-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with0.1- µF capacitors, as shown in Figure 40 .

Figure 40. Differential Clock Driving Circuit

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground witha 0.1- µF capacitor, as shown in Figure 41 .

Figure 41. Single-Ended Clock Driving Circuit

For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-modenoise. For high input frequency sampling, the use a clock source with low jitter is recommended. Bandpassfiltering of the clock source can help reduce the effect of jitter. There is no change in performance with anon-50% duty cycle clock input. Figure 25 shows the performance variation of the ADC versus clock duty cycle

When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude isincreased. Therefore, using a large amplitude clock is recommended. In addition, the clock buffer has aprogrammable gain option to amplify the input clock. The clock buffer gain can be set by programming theregister bits <CLKIN GAIN> (Table 14 ). The clock buffer gain decreases monotonically from Gain 4 to Gain 0settings.

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Programmable Gain

Power Down

ADS5517

SLWS203 – DECEMBER 2007

ADS5517 has programmable gain from 0 dB to 6 dB in steps of 1 dB. The corresponding full-scale input rangevaries from 2 V

down to 1 V

, with 0 dB being the default gain. At high IF, this is especially useful as theSFDR improvement is significant with marginal degradation in SNR.

The gain can be programmed using the serial interface (bits D3-D0 in register 0x68).

ADS5517 has three power-down modes – global STANDBY, output buffer disabled, and input clock stopped.

Global STANDBY

This mode can be initiated by controlling SDATA (pin 28) or by setting the register bit <STBY> (Table 10 )through the serial interface. In this mode, the A/D converter, reference block and the output buffers are powereddown and the total power dissipation reduces to about 100 mW. The output buffers are in high impedance state.The wake-up time from the global power down to data becoming valid normal mode is maximum 100 µs.

Output Buffer Disable

The output buffers can be disabled using OE pin 7 in both the LVDS and CMOS modes, reducing the total powerby about 100 mW. With the buffers disabled, the outputs are in high impedance state. The wake-up time fromthis mode to data becoming valid in normal mode is maximum 1 µs in LVDS mode and 50 ns in CMOS mode.

Input Clock Stop

The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation isabout 100 mW and the wake-up time from this mode to data becoming valid in normal mode is maximum 100 µs.

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Power Scaling Modes

Power Supply Sequence

Digital Output Information

Output Interface

ADS5517

SLWS203 – DECEMBER 2007

ADS5517 has a power scaling mode in which the device can be operated at reduced power levels at lowersampling frequencies with no difference in performance. (See Figure 29 )

(1)

There are four power scaling modesfor different sampling clock frequency ranges, using the serial interface register bits <SCALING> (Table 16 ).Only the AVDD power is scaled, leaving the DRVDD power unchanged.

Table 19. Power Scaling vs Sampling Speed

Sampling Frequency Analog PowerPower Scaling Mode Analog Power in Default ModeMSPS (Typical)

> 150 Default 1010 mW at 200 MSPS 1010 mW at 200 MSPS105 to 150 Power Mode 1 841 mW at 150 MSPS 917 mW at 150 MSPS50 to 105 Power Mode 2 670 mW at 105 MSPS 830 mW at 105 MSPS< 50 Power Mode 3 525 mW at 50 MSPS 760 mW at 50 MSPS

(1) The performance in the power scaling modes is from characterization and not tested in production.

During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies areseparated inside the device. Externally, AVDD and DRVDD can be driven from separate supplies or from asingle supply.

ADS5517 provides 11-bit data, an output clock synchronized with the data and an out-of-range indicator thatgoes high when the output reaches the full-scale limits. In addition, output enable control (OE pin 7) is providedto power down the output buffers and put the outputs in high-impedance state.

Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. The options areselected using the DFS (see Table 6 ) or the serial interface register bit <ODI> (Table 15 ).

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DDR LVDS Outputs

CLKOUTP

LOW_D0_P

D1_D2_P

D3_D4_P

D5_D6_P

D7_D8_P

D9_D10_P

OVR

Pins

OutputClock

DataBitsLow,D0

DataBitsD1,D2

DataBitsD3,D4

DataBitsD5,D6

DataBitsD7,D8

DataBitsD9,D10

Out-of-RangeIndicator

CLKOUTM

LOW_D0_M

D1_D2_M

D3_D4_M

D5_D6_M

D7_D8_M

D9_D10_M

ADS5517

SLWS203 – DECEMBER 2007

In this mode, the 11 data bits and the output clock are available as LVDS (Low Voltage Differential Signal) levels.Two successive data bits are multiplexed and output on each LVDS differential pair as shown in Figure 42 . So,there are 6 LVDS output pairs for the 11 data bits and 1 LVDS output pair for the output clock.

Figure 42. DDR LVDS Outputs

Even data bits D0, D2, D4, D6, D8, and D10 are output at the rising edge of CLKOUTP and the odd data bits D1,D3, D5, D7, and D9 are output at the falling edge of CLKOUTP. Both the rising and falling edges of CLKOUTPmust be used to capture all the 11 data bits (see Figure 43 ).

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CLKOUTP

LOW_D0_P,

LOW_D0_M

D1_D2_P,

D1_D2_M

D3_D4_P,

D3_D4_M

D5_D6_P,

D5_D6_M

D7_D8_P,

D7_D8_M

D9_D10_P,

D9_D10_M

LOW

SampleN+1SampleN

LOW

D10

CLKOUTM

LVDS Buffer Current Programmability

LVDS Buffer Internal Termination

ADS5517

SLWS203 – DECEMBER 2007

Figure 43. DDR LVDS Interface

The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, the results is a 350-mVsingle-ended voltage swing (700-mV

differential swing). The LVDS buffer currents can also be programmed to2.5 mA, 4.5 mA, and 1.75 mA using the register bits <LVDS CURR> (Table 17 ). In addition, there exists acurrent double mode, where this current is doubled for the data and output clock buffers (register bits <CURRDOUBLE>,Table 18 ).

An internal termination option is available (using the serial interface), by which the LVDS buffers are differentiallyterminated inside the device. The termination resistences available are – 325, 200, and 170 Ω(nominal with± 20% variation). Any combination of these three terminations can be programmed; the effective termination isthe parallel combination of the selected resistences. This results in eight effective terminations from open (notermination) to 75 Ω.

The internal termination helps to absorb any reflections coming from the receiver end, improving the signalintegrity. With 100- Ωinternal and 100- Ωexternal termination, the voltage swing at the receiver end is halved(compared to no internal termination). The voltage swing can be restored by using the LVDS current doublemode. Figure 44 shows the eye diagram of one of the LVDS data outputs with a 10-pF load capacitance (fromeach pin to ground) and 100- Ωinternal termination enabled. The termination can be programmed using registerbits <DATA TERM> and <CLKOUT TERM> (Table 17 ).

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Parallel CMOS

CMOS Mode Power Dissipation

Output Switching Noise and Data Position Programmability (in CMOS mode ONLY)

ADS5517

SLWS203 – DECEMBER 2007

Figure 44. Eye Diagram of LVDS Data Output With Internal Termination

In this mode, the 11 data outputs and the output clock are available as 3.3-V CMOS voltage levels. Each data bitand the output clock is available on a separate pin in parallel. By default, the data outputs are valid during therising edge of the output clock. The output clock is CLKOUT (pin 5).

With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on everyoutput pin (see Figure 30 ). The maximum DRVDD current occurs when each output bit toggles between 0 and 1every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current isdetermined by the average number of output bits switching, which is a function of the sampling frequency andthe nature of the analog input signal.Digital current due to CMOS output switching = C

x V

DRVDD

x (N x F

AVG

)

where C

= load capacitance, N x F

AVG

= average number of output bits switching

Figure 30 shows the current with various load capacitances across sampling frequencies at 2MHz analog inputfrequency.

Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant ofsampling and degrade the SNR. To minimize this, the device includes programmable options to move the outputdata transitions with respect to the output clock. This can be used to position the data transitions at the optimumplace away from the sampling instant and improve the SNR. Figure 30 shows the variation of SNR for differentCMOS output data positions at 200 MSPS.

Note that the optimum output data position varies with the sampling frequency. The data position can beprogrammed using the register bits <DATA POSN> (Table 9 ).

It is recommended to put series resistors (50 to 100 Ω) on each output line placed close to the converter pins.This helps to isolate the outputs from seeing large load capacitances and in turn reduces the amount of switchingnoise. For example, the data in Figure 30 was taken with 50- Ωresistors on each output line.

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Output Clock Position Programmability

Output Data Format

Out-of-Range Indicator (OVR)

POL − Positiveoverloadcode

0x7FFforstraightbinary

0x3FFfor2scomplement

NOL − Negativeoverloadcode

0x000forstraightbinary

0x400for2scomplement

Output Timing

ADS5517

SLWS203 – DECEMBER 2007

In both the LVDS and CMOS modes, the output clock can be moved around its default position. This can bedone using SEN pin 27 (as described in Table 5 ) or using the serial interface register bits <CLKOUT POSN>(Table 9 ). Using this allows to trade-off the setup and hold times leading to reliable data capture. There alsoexists an option to align the output clock edge with the data transition.

Note that programming the output clock position also affects the clock propagation delay times.

Two output data formats are supported – 2's complement and offset binary. They can be selected using the DFS(pin 6) or the serial interface register bit <DF> (Table 10 ).

When the input voltage exceeds the full-scale range of the ADC, OVR (pin 3) goes high, and the output code isclamped to the appropriate full-scale level for the duration of the overload. For a positive overdrive, the outputcode is 0x7FF in offset binary output format, and 0x3FF in 2's complement output format. For a negative inputoverdrive, the output code is 0x000 in offset binary output format and 0x400 in 2's complement output format.Figure 45 shows the behavior of OVR during the overload. Note that OVR and the output code react to theoverload after a latency of 14 clock cycles.

Figure 45. OVR During Input Overvoltage

For the best performance at high sampling frequencies, ADS5517 uses a clock generator circuit to derive internaltiming for ADC. This results in optimal setup and hold times of the output data and 50% output clock duty cyclefor sampling frequencies from 80 MSPS to 200 MSPS. See Table 20 for timing information above 80 MSPS.

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SamplingFrequency − MHz

100

60 80 140 160 200

OutputClockDutyCycle − %

CMOS

45%DutyCycle

DDRLVDS

50%DutyCycle

0 20 40 100 120

180

ADS5517

SLWS203 – DECEMBER 2007

Table 20. Timing Characteristics (80 MSPS to 200 MSPS)

(1)

DATA SETUP TIME, ns t

DATA HOLD TIME, ns t

PDI

CLOCK PROPAGATION DELAY, nsFs, MSPS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

DDR LVDS

190 1.2 1.7 0.4 0.9 4.0 4.7 5.4

170 1.3 1.8 0.5 1.0 3.9 4.6 5.3

150 1.6 2.1 0.6 1.1 4.3 5.0 5.7

130 2.0 2.5 0.8 1.3 4.5 5.2 5.9

80 3.6 4.1 1.6 2.1 4.7 5.7 6.7

PARALLEL CMOS

190 2.2 3.0 0.5 0.9 2.4 3.2 4.0

170 2.5 3.3 0.8 1.2 1.9 2.7 3.5

150 2.8 3.6 1.2 1.6 1.7 2.5 3.3

130 3.3 4.1 1.7 2.1 1.1 1.9 2.7

80 6.0 7.0 3.7 4.1 10.8 12 13.2

(1) Timing parameters are specified by design and characterization and not tested in production.

Below 80 MSPS, the setup and hold times do not scale with the sampling frequency. The output clock duty cyclealso progressively moves away from 50% as the sampling frequency is reduced from 80 MSPS.

See Table 21 for timings at sampling frequencies below 80 MSPS. Figure 46 shows the clock duty cycle acrosssampling frequencies in the DDR LVDS and CMOS modes.

Table 21. Timing Characteristics (1 MSPS to 80 MSPS)

(1)

DATA SETUP TIME, ns t

DATA HOLD TIME, ns t

PDI

CLOCK PROPAGATION DELAY, nsFs, MSPS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

DDR LVDS

1 to 80 3.6 1.6 5.7

PARALLEL CMOS

1 to 80 6 3.7 12

(1) Timing parameters are specified by design and characterization and not tested in production.

Figure 46. Output Clock Duty Cycle (Typical) vs Sampling Frequency

The latency of ADS5517 is 14 clock cycles from the sampling instant (input clock rising edge). In the LVDSmode, the latency remains constant across sampling frequencies. In the CMOS mode, the latency is 14 clockcycles above 80 MSPS and 13 clock cycles below 80 MSPS.

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Board Design Considerations

Grounding

Supply Decoupling

Series Resistors on Data Outputs

Exposed Thermal Pad

ADS5517

SLWS203 – DECEMBER 2007

A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections ofthe board are cleanly partitioned. See the EVM User Guide (SLWU028 ) for details on layout and grounding.

As the ADS5517 already includes internal decoupling, minimal external decoupling can be used without loss inperformance. Note that decoupling capacitors can help to filter external power supply noise, so the optimumnumber of capacitors would depend on the actual application. The decoupling capacitors should be placed closeto the converter supply pins.

It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switchingnoise from sensitive analog circuitry. If only a single 3.3V supply is available, it should be routed first to AVDD. Itcan then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being routed toDRVDD.

It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermalperformance. For detailed information, see application notes QFN Layout Guidelines (SLOA122 ) and QFN/SONPCB Attachment (SLUA271 ).

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DEFINITION OF SPECIFICATIONS

Analog Bandwidth

Aperture Delay

Aperture Uncertainty (Jitter)

Clock Pulse Width/Duty Cycle

Maximum Conversion Rate

Minimum Conversion Rate

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

Gain Error

Offset Error

Temperature Drift

ADS5517

SLWS203 – DECEMBER 2007

The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the lowfrequency value.

The delay in time between the rising edge of the input sampling clock and the actual time at which the samplingoccurs.

The sample-to-sample variation in aperture delay.

The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width)to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differentialsine-wave clock results in a 50% duty cycle.

The maximum sampling rate at which certified operation is given. All parametric testing is performed at thissampling rate unless otherwise noted.

The minimum sampling rate at which the ADC functions.

An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is thedeviation of any single step from this ideal value, measured in units of LSBs

The INL is the deviation of the ADC ’ s transfer function from a best fit line determined by a least squares curve fitof that transfer function, measured in units of LSBs.

The gain error is the deviation of the ADC ’ s actual input full-scale range from its ideal value. The gain error isgiven as a percentage of the ideal input full-scale range.

The offset error is the difference, given in number of LSBs, between the ADC ’ s actual average idle channeloutput code and the ideal average idle channel output code. This quantity is often mapped into mV.

The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degreeCelsius of the parameter from T

MIN

to T

MAX

. It is calculated by dividing the maximum deviation of the parameteracross the T

MIN

to T

MAX

range by the difference T

MAX

– T

MIN

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Signal-to-Noise Ratio

SNR +10Log10 Ps

(4)

Signal-to-Noise and Distortion (SINAD)

SINAD +10Log10 Ps

PN)PD

(5)

Effective Number of Bits (ENOB)

ENOB +SINAD *1.76

6.02

(6)

Total Harmonic Distortion (THD)

THD +10Log10 Ps

(7)

Spurious-Free Dynamic Range (SFDR)

Two-Tone Intermodulation Distortion

DC Power Supply Rejection Ratio (DC PSRR)

ADS5517

SLWS203 – DECEMBER 2007

SNR is the ratio of the power of the fundamental (P

) to the noise floor power (P

), excluding the power at dcand the first nine harmonics.

SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as thereference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter ’ sfull-scale range.

SINAD is the ratio of the power of the fundamental (P

) to the power of all the other spectral componentsincluding noise (P

) and distortion (P

), but excluding dc.

SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as thereference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter ’ sfull-scale range.

The ENOB is a measure of a converter ’ s performance as compared to the theoretical limit based on quantizationnoise.

THD is the ratio of the power of the fundamental (P

) to the power of the first nine harmonics (P

THD is typically given in units of dBc (dB to carrier).

The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic).SFDR is typically given in units of dBc (dB to carrier).

IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectralcomponent at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given in units of dBc (dB to carrier) when theabsolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of thefundamental is extrapolated to the converter ’ s full-scale range.

The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR istypically given in units of mV/V.

Product Folder Link(s): ADS5517

www.ti.com

AC Power Supply Rejection Ratio (AC PSRR)

(ExpressedindBc)

DVSUP

DVOUT

PSRR=20Log

(8)

Common Mode Rejection Ratio (CMRR)

(ExpressedindBc)

DVCM

DVOUT

CMRR=20Log

(9)

Voltage Overload Recovery

ADS5517

SLWS203 – DECEMBER 2007

AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If ΔV

SUP

is the change in thesupply voltage and ΔV

OUT

is the resultant change in the ADC output code (referred to the input), then

CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If ΔVcm is thechange in the input common-mode voltage and ΔV

OUT

is the resultant change in the ADC output code (referredto the input), then

The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A6-dBFS sine wave at Nyquist frequency is used as the test stimulus.

Product Folder Link(s): ADS5517

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

ADS5517IRGZ25 ACTIVE VQFN RGZ 48 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5517IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5517IRGZRG4 ACTIVE VQFN RGZ 48 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5517IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5517IRGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 2-Apr-2010

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS5517IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

ADS5517IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Feb-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS5517IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6

ADS5517IRGZT VQFN RGZ 48 250 336.6 336.6 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Feb-2012

Pack Materials-Page 2

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