1. Product profile
1.1 General description
S tan dard level N-channel MOSFET in D2P AK (SOT 404) package qualified to 175 °C. This
product is designed and qualified for use in a wide range of industrial, communications
and domestic equipment.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for standard level gate drive
sources
1.3 Applications
DC-to-DC convertors
Load switching
Motor contro l
Server power supplies
1.4 Quick reference data
[1] Continuous current is limited by package
PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
Rev. 2 — 29 February 2012 Product data sheet
D2PAK
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage Tj≥25 °C; Tj≤175°C --40V
IDdrain current Tmb =25°C; V
GS =10V; see Figure 1 [1] - - 120 A
Ptot total power dissipation Tmb =25°C; see Figure 2 - - 306 W
Tjjunction temperature -55 - 175 °C
Static characteristics
RDSon drain-source on-state
resistance VGS =10V; I
D=25A; T
j= 100 °C;
see Figure 12 ;see Figure 13 -1.682mΩ
VGS =10V; I
D=25A; T
j=25°C;
see Figure 13 - 1.16 1.3 mΩ
Dynamic character istics
QGD gate-drain charge VGS =10V; I
D=75A; V
DS =20V;
see Figure 14 ;see Figure 15 -32-nC
QG(tot) total gate charge - 136 - nC
Avalanche ruggedness
EDS(AL)S non-repetitive
drain-source
avalanche energy
VGS =10V; T
j(init) =25°C; I
D=120A;
Vsup ≤40 V; unclamped; RGS =50Ω;
tp=0.1ms
--1.4J
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 2 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
2. Pinning information
[1] It is not possible to make connection to pin 2.
3. Ordering information
4. Limiting values
[1] Continuous current is limited by package.
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1 G gate
SOT404 (D2PAK)
2 D drain[1]
3Ssource
mb D drain
mb
13
2
S
D
G
mbb076
Table 3. Ordering informatio n
Type number Package
Name Description Version
PSMN1R1-40BS D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads
(one lead croppe d) SOT404
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage Tj≥25 °C; Tj≤175 °C - 40 V
VDGR drain-gate voltage Tj≥25 °C; Tj≤175 °C; RGS =20kΩ-40V
VGS gate-source voltage -20 20 V
IDdrain current VGS =10V; T
mb =100°C [1] - 120 A
VGS =10V; T
mb =25°C; see Figure 1 [1] - 120 A
IDM peak drain current pulsed; tp≤10 µs; Tmb =25°C; see Figure 3 - 1320 A
Ptot total power dissipation Tmb =25°C; see Figure 2 - 306 W
Tstg storage temperature -55 175 °C
Tjjunction temperature -55 175 °C
Tsld(M) peak soldering temperature - 260 °C
Source-drain diode
ISsource current Tmb =25°C [1] - 120 A
ISM peak source current pulsed; tp≤10 µs; Tmb = 25 °C - 1320 A
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy VGS =10V; T
j(init) =25°C; I
D=120A; V
sup ≤40 V ;
unclamped; RGS =50Ω; tp=0.1ms -1.4J
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 3 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
Fig 1. Normalized continuous drain curre nt as a
function of mounting base temperature Fig 2. Normalized tota l po we r dis si pation as a
function of mounting ba s e temperature
Fig 3. Safe operating area; continuou s and peak drain currents as a function of drain-source voltage
003aaf329
0
50
100
150
200
250
300
350
0 50 100 150 200
Tmb (C)
ID
(A)
(1)
Tmb (°C)
0 20015050 100
03aa16
40
80
120
Pder
(%)
0
003aaf328
10-1
1
10
102
103
104
10-1 1 10 102
V DS (V)
ID
(A)
Limit RDSon = VDS / ID
DC
100
s
10 ms
tp =10 s
100 ms
1 ms
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 4 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-mb) thermal resistance from
junction to mounting base see Figure 4 - 0.22 0.49 K/W
Rth(j-a) thermal resistance from
junction to ambient minimum footprint; mounted on
a printed-circuit board -50-K/W
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
003aag770
10-3
10-2
10-1
1
10
-6
10-5 10-4 10-3 10-2 10-1 1
tp (s)
tp T
P
t
tp
T
δ =
δ = 0.5
0.2
0.1
0.05
0.02
single shot
Z
th(j-mb)
(K/W)
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 5 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage ID=250µA; V
GS =0V; T
j= -55 °C 36 - - V
ID=250µA; V
GS =0V; T
j=25°C 40--V
VGS(th) gate-source threshold
voltage ID=1mA; V
DS =V
GS; Tj=-55°C;
see Figure 10 --4.6V
ID=1mA; V
DS =V
GS; Tj= 175 °C;
see Figure 10 1--V
ID=1mA; V
DS =V
GS; Tj=25°C;
see Figure 11;see Figure 10 234V
IDSS drain leakage current VDS =40V; V
GS =0V; T
j= 25 °C - 0.02 10 µA
VDS =40V; V
GS =0V; T
j= 175 °C - - 500 µA
IGSS gate leakage current VGS =20V; V
DS =0V; T
j= 25 °C - 10 100 nA
VGS =-20V; V
DS =0V; T
j= 25 °C - 10 100 nA
RDSon drain-source on-state
resistance VGS =10V; I
D=25A; T
j= 100 °C;
see Figure 12 ;see Figure 13 -1.682mΩ
VGS =10V; I
D=25A; T
j= 175 °C;
see Figure 12 ;see Figure 13 -2.32.8mΩ
VGS =10V; I
D=25A; T
j=25°C;
see Figure 13 - 1.16 1.3 mΩ
RGinternal gate resistance
(AC) f=1MHz - 1.1 - Ω
Dynamic character istics
QG(tot) total gate charge ID=0A; V
DS =0V; V
GS = 10 V - 133 - nC
ID=75A; V
DS =20V; V
GS =10V;
see Figure 14 ;see Figure 15 - 136 - nC
QGS gate-source charge - 52 - nC
QGS(th) pre-threshold
gate-source charge -30-nC
QGS(th-pl) post-threshold
gate-source charge -22-nC
QGD gate-drain charge - 32 - nC
VGS(pl) gate-source plateau
voltage ID=75A; V
DS = 20 V;see Figure 14;
see Figure 15 -6.1-V
Ciss input capacitance VDS =20V; V
GS = 0 V; f = 1 MHz;
Tj= 25 °C;see Figure 16 - 9710 - pF
Coss output capacitance - 2042 - pF
Crss reverse transfer
capacitance - 994 - pF
td(on) turn-on delay time VDS =20V; R
L=0.8Ω; VGS =5V;
RG(ext) =4.7Ω
-45-ns
trrise time - 66 - ns
td(off) turn-off delay time - 111 - ns
tffall time - 53 - ns
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 6 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
Source-drain diode
VSD source-drain voltage IS=25A; V
GS =0V; T
j=25°C;
see Figure 17 -0.81.2V
trr reverse recovery time IS=25A; dI
S/dt = -100 A/µs; VGS =0V;
VDS =20V -64-ns
Qrrecovered charge - 117 - nC
Table 6. Characteristics …continued
Symbol Parameter Conditions Min Typ Max Unit
Fig 5. Forward transconductance as a function of
drain current; typical values Fig 6. Transfer characteris tics: drain current as a
function of gate-s ourc e vol tage; typical value s
Fig 7. Input and reverse transfer capacitances as a
function of gate-source voltage; typical values Fig 8. Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aaf316
0
50
100
150
200
0 15304560
ID (A)
gfs
(S)
003aaf317
0
15
30
45
60
75
0246
VGS
(V)
ID
(A)
Tj = 25 °C
Tj = 175 °C
003aaf320
2000
6000
10000
14000
18000
1 10 102
VGS
(V)
C
(pF) Ciss
Crss
003aag669
0
2
4
6
8
4 8 12 16 20
VGS
(V)
RDSon
(mΩ)
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 7 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
Fig 9. Output characteristics: drain current as a
function of drain-source voltage; typical values Fig 10. Gate-source threshold voltage as a func tion of
junction temperature
Fig 11. Sub-threshold drain current as a function of
gate-source voltage Fig 12. Normalized drain-source on state resistance
factor as a function of junction temperature
003aaf319
0
20
40
60
80
0 0.25 0.5 0.75 1
VDS
(V)
ID
(A)
5.2
6.0 VGS
(V) = 4.8
5.010
4.7
4.6
4.5
Tj (°C)
−60 180120060
003aad280
2
3
1
4
5
VGS(th)
(V)
0
max
typ
min
03aa35
VGS (V)
0642
10−4
10−5
10−2
10−3
10−1
ID
(A)
10−6
min typ max
003aaf322
0
0.5
1
1.5
2
2.5
-60 0 60 120 180
Tj (C)
a
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 8 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
Fig 13. Drain-source on-state resistance as a function
of drain current; typical values Fig 14. Gate charge waveform definitions
Fig 15. Gate-source vo ltage as a function of gate
charge; typical values Fig 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aag670
0
2
4
6
8
0 20406080
ID (A)
RDSon
(m
Ω
)
5.2
4.6
20
4.8
VGS
(V) = 5
10
003aaa508
VGS
VGS(th)
QGS1 QGS2
QGD
VDS
QG(tot)
ID
QGS
VGS(pl)
003aaf323
0
2
4
6
8
10
0 40 80 120 160
QG (nC)
VGS
(V)
VDS
= 8V
20V
32V
003aaf324
10
102
103
104
105
10-1 1 10 102
VDS
(V)
C
(pF)
Ciss
Crss
Coss
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 9 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
Fig 17. Source current as a func tion of source-drain voltage; typica l values
003aaf325
0
15
30
45
60
75
0 0.25 0.5 0.75 1
VSD
(V)
IS
(A)
Tj = 25 °CTj = 175 °C
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 10 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
7. Package outline
Fig 18. Package outline SOT404 (D2PAK)
UNIT A
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
A1D1
D
max. EeL
pHDQc
2.54 2.60
2.20
15.80
14.80
2.90
2.10
11 1.60
1.20 10.30
9.70
4.50
4.10 1.40
1.27 0.85
0.60 0.64
0.46
b
DIMENSIONS (mm are the original dimensions)
SOT404
0 2.5 5 mm
scale
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) SOT404
e e
E
b
D1
HD
D
Q
Lp
c
A1
A
13
2
mounting
base
05-02-11
06-03-16
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 11 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PSMN1R1-40BS v.2 20120229 Product data sheet - PSMN1R1-40BS v.1
Modifications: •Status changed fro m ob jective to product.
•Various changes to content.
PSMN1R1-40BS v.1 20110929 Objective data sheet - -
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 12 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. The latest product
status information is available on the Internet at URLhttp://www.nxp.com.
9.2 Definitions
Preview— The document is a preview version only. The document is still
subject to formal approval, which may result in modificati ons or additions.
NXP Semiconductors does not give any representati ons or warranties as to
the accuracy or completeness of informati on included herein and shall have
no liability for the consequences of use of such info rmation.
Draft— The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data s heet— A short data sheet is an extract from a full dat a sheet with
the same product type number(s) and title. A short data sheet is intended for
quick reference only and sh ould not be re lied upon to co ntain detailed and full
information. For detailed and full informat i on see the relevant full data sheet,
which is available on request via the local NXP Semiconductors sales office.
In case of any inconsistency or conflict with the short data sheet, the full d ata
sheet shall prevail.
Product specifica t io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
9.3 Disclaimers
Limited warr a nty and liability— Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with theTerms and conditions of commercial saleof NXP Semiconduct ors.
Right to make changes— NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersed es an d r eplaces all inf ormation supplied pri or
to the publication hereof.
Suitability for use— NXP Semiconductors product s are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Quick reference data— The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications— Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values— Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
PSMN1R1-40BS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 29 February 2012 13 of 14
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
Terms and conditions of commercial sale— NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published athttp://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license— No thi ng in this do cu ment may be int er preted o r
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control— This document as well as the item(s) described her ein may
be subject to export control regulat i ons. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products— Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in au tomotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and st andards, customer
(a) shall use the product without NXP Semicond uctors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product cl aims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations— A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
9.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
Adelante,Bitport,Bitsound,CoolFlux,CoReUse,DESFire,EZ-HV,FabKey,G
reenChip,HiPerSmart,HITAG,I²C-buslogo,ICODE,I-CODE,ITEC,Labelution
,MIFARE,MIFARE Plus,MIFARE Ultralight,MoReUse,QLPAK,Silicon
Tuner,SiliconMAX,SmartXA,STARplug,TOPFET,TrenchMOS,TriMediaand
UCODE— are trademarks of NXP B.V.
HD RadioandHD Radiologo — are trademarks of iBiquity Digital Corporation.
10. Contact information
For more information, please visit:http://www.nxp.com
For sales office addresses, please send an email to:salesaddresses@nxp.com
NXP Semiconductors PSMN1R1-40BS
N-channel 40 V 1.3 mΩ standard level MOSFET in D2PAK
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 February 2012
Document iden tifier: PSM N 1R1-40BS
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 General description . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
10 Contact information. . . . . . . . . . . . . . . . . . . . . .13
