Product Folder Order Now Technical Documents Support & Community Tools & Software LM25575-Q1 SNVSB28 - DECEMBER 2017 LM25575-Q1 42-V, 1.5-A Step-Down Switching Regulator 1 Features 3 Description * The LM25575-Q1 is an easy to use buck regulator which allows design engineers to design and optimize a robust power supply using a minimum set of components. Operating with an input voltage range of 6 V to 42 V, the LM25575-Q1 delivers 1.5-A of continuous output current with an integrated 330-m N-Channel MOSFET. The regulator utilizes an Emulated Current Mode architecture which provides inherent line regulation, tight load transient response, and ease of loop compensation without the usual limitation of low-duty cycles associated with current mode regulators. The operating frequency is adjustable from 50-kHz to 1-MHz to allow optimization of size and efficiency. To reduce EMI, a frequency synchronization pin allows multiple IC's from the LM(2)557x family to self-synchronize or to synchronize to an external clock. The LM25575-Q1 ensures robustness with cycle-by-cycle current limit, short-circuit protection, thermal shut-down, and remote shut-down. The device is available in a power enhanced HTSSOP-16 package featuring an exposed die attach pad for thermal dissipation. The LM25575-Q1 is supported by the full suite of WEBENCH(R) On-Line design tools. 1 * * * * * * * * * * * * Qualified for Automotive Applications - Device Temperature Grade 1: -40C to +125C Ambient Operating Temperature Integrated 42-V, 330-m N-Channel MOSFET Ultra-Wide Input Voltage Range From 6 V to 42 V Adjustable Output Voltage as Low as 1.225 V 1.5% Feedback Reference Accuracy Operating Frequency Adjustable Between 50 kHz and 1 MHz With Single Resistor Master or Slave Frequency Synchronization Adjustable Soft-Start Emulated Current Mode Control Architecture Wide Bandwidth Error Amplifier Built-In Protection HTSSOP-16 EP (Exposed Pad) Create a Custom Design Using the LM25575-Q1 With the WEBENCH(R) Power Designer 2 Applications * Industrial Device Information(1) PART NUMBER LM25575-Q1 PACKAGE HTSSOP (16) BODY SIZE (NOM) 5.00 mm x 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application Schematic VIN VIN BST SYNC SW VOUT LM25575-Q1 SD IS RT VCC SS RAMP OUT FB COMP GND Copyright (c) 2017, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 5 5 5 5 6 7 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. 7.3 Feature Description................................................... 9 7.4 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application ................................................. 21 9 Layout ................................................................... 22 9.1 Layout Guidelines ................................................... 22 9.2 Layout Example ...................................................... 23 10 Device and Documentation Support ................. 25 10.1 10.2 10.3 10.4 10.5 10.6 Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 Device Support...................................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 25 25 25 25 25 25 11 Mechanical, Packaging, and Orderable Information ........................................................... 26 4 Revision History 2 DATE REVISION NOTES December 2017 * Initial release. Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com 5 SNVSB28 - DECEMBER 2017 Pin Configuration and Functions PWP 16-Pin HTSSOP Top View 1 VCC BST SD PRE VIN SW 2 3 4 5 6 7 8 SYNC IS COMP PGND FB OUT RT SS RAMP AGND 16 15 14 13 12 11 10 9 Pin Functions NO. Name Description 1 VCC Output of the bias regulator VCC tracks VIN up to 9 V. Beyond 9 V, VCC is regulated to 7 Volts. A 0.1 uF to 1 uF ceramic decoupling capacitor is required. An external voltage (7.5 V - 14 V) can be applied to this pin to reduce internal power dissipation. 2 SD Shutdown or UVLO input If the SD pin voltage is below 0.7 V the regulator will be in a low power state. If the SD pin voltage is between 0.7 V and 1.225 V the regulator will be in standby mode. If the SD pin voltage is above 1.225 V the regulator will be operational. An external voltage divider can be used to set a line undervoltage shutdown threshold. If the SD pin is left open circuit, a 5 A pull-up current source configures the regulator fully operational. 3 VIN Input supply voltage Nominal operating range: 6 V to 42 V 4 SYNC Oscillator synchronization input or output The internal oscillator can be synchronized to an external clock with an external pull-down device. Multiple LM25575Q1 devices can be synchronized together by connection of their SYNC pins. 5 COMP Output of the internal error amplifier The loop compensation network should be connected between this pin and the FB pin. 6 FB Feedback signal from the regulated output This pin is connected to the inverting input of the internal error amplifier. The regulation threshold is 1.225 V. 7 RT Internal oscillator frequency set input The internal oscillator is set with a single resistor, connected between this pin and the AGND pin. 8 RAMP Ramp control signal An external capacitor connected between this pin and the AGND pin sets the ramp slope used for current mode control. Recommended capacitor range 50 pF to 2000 pF. 9 AGND Analog ground Internal reference for the regulator control functions 10 SS 11 OUT 12 PGND 13 IS 14 SW Soft-start An external capacitor and an internal 10 A current source set the time constant for the rise of the error amp reference. The SS pin is held low during standby, VCC UVLO and thermal shutdown. Output voltage connection Connect directly to the regulated output voltage. Power ground Low side reference for the PRE switch and the IS sense resistor. Current sense Current measurement connection for the re-circulating diode. An internal sense resistor and a sample/hold circuit sense the diode current near the conclusion of the off-time. This current measurement provides the DC level of the emulated current ramp. Switching node The source terminal of the internal buck switch. The SW pin should be connected to the external Schottky diode and to the buck inductor. Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 3 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com Pin Functions (continued) NO. 4 Name Description 15 PRE Pre-charge assist for the bootstrap capacitor This open drain output can be connected to SW pin to aid charging the bootstrap capacitor during very light load conditions or in applications where the output may be pre-charged before the LM25575-Q1 is enabled. An internal pre-charge MOSFET is turned on for 250 ns each cycle just prior to the on-time interval of the buck switch. 16 BST Boost input for bootstrap capacitor An external capacitor is required between the BST and the SW pins. A 0.022 F ceramic capacitor is recommended. The capacitor is charged from VCC via an internal diode during the off-time of the buck switch. NA EP Exposed Pad Exposed metal pad on the underside of the device. It is recommended to connect this pad to the PWB ground plane, in order to aid in heat dissipation. Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com SNVSB28 - DECEMBER 2017 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MAX UNIT VIN to GND MIN 45 V BST to GND 60 V PRE to GND 45 V -1.5 V BST to VCC 45 V SD, VCC to GND 14 V BST to SW 14 V VIN V SW to GND (Steady State) OUT to GND Limited SYNC, SS, FB, RAMP to GND Storage temperature, Tstg (1) (2) -65 7 V 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. 6.2 ESD Ratings V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) VALUE UNIT 2 kV AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions (1) VIN TJ Operation junction temperature (1) MIN MAX 6 42 UNIT V -40 125 C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. 6.4 Thermal Information LM25575-Q1 THERMAL METRIC (1) PWP (HTSSOP) UNIT 16 PINS RJA Junction-to-ambient thermal resistance 14 C/W RJC(top) Junction-to-case (top) thermal resistance 50 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 5 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com 6.5 Electrical Characteristics at TJ = 25C, and VIN = 24 V, RT = 32.4 k (unless otherwise noted). (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 6.85 7.15 7.45 V STARTUP REGULATOR VCCReg VCC Regulator Output TJ = -40C to +125C VCC LDO Mode turn-off VCC Current Limit VCC = 0 V VCC UVLO Threshold (VCC increasing) 9 V 25 mA VCC SUPPLY TJ = -40C to +125C 5.03 VCC Undervoltage Hysteresis 5.35 5.67 0.35 V V Bias Current (Iin) FB = 1.3 V TJ = -40C to +125C 3.7 4.5 mA Shutdown Current (Iin) SD = 0 V TJ = -40C to +125C 48 70 A (SD Increasing) TJ = -40C to +125C 0.7 0.9 V SHUTDOWN THRESHOLDS Shutdown Threshold 0.47 Shutdown Hysteresis Standby Threshold 0.1 (Standby Increasing) TJ = -40C to +125C 1.17 1.225 V 1.28 V Standby Hysteresis 0.1 V SD Pull-up Current Source 5 A CURRENT LIMIT Cycle by Cycle Current Limit RAMP = 0 V TJ = -40C to +125C 1.8 Cycle by Cycle Current Limit Delay RAMP = 2.5 V 2.1 2.5 85 A ns SOFT-START SS Current Source TJ = -40C to +125C Frequency 1 TJ = -40C to +125C Frequency 2 RT = 11 k 7 10 14 A 180 200 220 kHz 425 485 545 kHz OSCILLATOR TJ = -40C to +125C SYNC Source Impedance 11 k SYNC Sink Impedance 110 SYNC Threshold (falling) 1.3 SYNC Frequency RT = 11 k SYNC Pulse Width Minimum TJ = -40C to +125C TJ = -40C to +125C V 550 kHz 15 ns RAMP GENERATOR Ramp Current 1 VIN = 36 V, VOUT = 10 V TJ = -40C to +125C 272 310 368 A Ramp Current 2 VIN = 10 V, VOUT = 10 V TJ = -40C to +125C 36 50 64 A 416 500 575 ns PWM COMPARATOR Forced Off-time (1) 6 TJ = -40C to +125C Min On-time 80 ns COMP to PWM Comparator Offset 0.7 V Min and Max limits are 100% production tested at 25C. Limits over the operating temperature range are assured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Texas Instruments' Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com SNVSB28 - DECEMBER 2017 Electrical Characteristics (continued) at TJ = 25C, and VIN = 24 V, RT = 32.4 k (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX 1.207 1.225 1.243 UNIT ERROR AMPLIFIER Feedback Voltage Vfb = COMP TJ = -40C to +125C FB Bias Current V 17 DC Gain nA 70 COMP Sink / Source Current TJ = -40C to +125C dB 3 mA Unity Gain Bandwidth 3 MHz 83 m Thermal Shutdown Threshold 165 C Thermal Shutdown Hysteresis 25 C DIODE SENSE RESISTANCE DSENSE THERMAL SHUTDOWN Tsd 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Buck Switch Rds(on) MIN TJ = -40C to +125C TYP MAX UNIT 330 660 m BOOST UVLO 4 BOOST UVLO Hysteresis 0.56 V V Pre-charge Switch Rds(on) 70 Pre-charge Switch on-time 250 ns 6.7 Typical Characteristics 1.10 NORMALIZED SOFTSTART CURRENT OSCILLATOR FREQUENCY (kHz) 1000 100 10 1 10 100 1000 1.05 1.00 0.95 0.90 -50 -25 0 25 50 75 100 125 o RT (k:) TEMPERATURE ( C) Figure 1. Oscillator Frequency vs RT Figure 2. Soft Start Current vs Temperature Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 7 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com Typical Characteristics (continued) 8 10 8 6 VCC (V) VCC (V) 6 4 4 2 Ramp Down 2 Ramp Up 0 0 0 12 8 4 16 20 0 24 2 4 6 ICC (mA) VIN = 12 V Figure 4. VCC vs VIN 50 225 40 180 30 135 100 VIN = 7V 90 10 90 45 0 0 GAIN -45 EFFICIENCY (%) PHASE PHASE () GAIN (dB) 80 -10 10 RL = 7 k Figure 3. VCC vs ICC 20 8 VIN (V) VIN = 24V 70 60 50 40 30 20 -20 -90 -30 10k 100k 1M 10M -135 100M 10 0 0.25 FREQUENCY (Hz) 0.5 0.75 1 1.25 1.5 IOUT (A) AVCL = 101 Figure 5. Error Amplifier Gain and Phase 8 Figure 6. Demoboard Efficiency vs IOUT and VIN Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com SNVSB28 - DECEMBER 2017 7 Detailed Description 7.1 Overview The LM25575-Q1 switching regulator features all of the functions necessary to implement an efficient high voltage buck regulator using a minimum of external components. This easy to use regulator integrates a 42-V NChannel buck switch with an output current capability of 1.5 Amps. The regulator control method is based on current mode control utilizing an emulated current ramp. Peak current mode control provides inherent line voltage feed-forward, cycle-by-cycle current limiting, and ease of loop compensation. The use of an emulated control ramp reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable processing of very small duty cycles necessary in high input voltage applications. The operating frequency is user programmable from 50 kHz to 1 MHz. An oscillator synchronization pin allows multiple LM25575-Q1 regulators to self synchronize or be synchronized to an external clock. The output voltage can be set as low as 1.225 V. Fault protection features include, current limiting, thermal shutdown and remote shutdown capability. The device is available in the HTSSOP-16 package featuring an exposed pad to aid thermal dissipation. The functional block diagram and typical application of the LM25575-Q1 are shown in Functional Block Diagram. The LM25575-Q1 can be applied in numerous applications to efficiently step-down a high, unregulated input voltage. The device is well suited for telecom, industrial and automotive power bus voltage ranges. 7.2 Functional Block Diagram VIN 7 V 42 V C1 1.0 C2 1.0 LM25575-Q1 VIN 3 VCC 7 V REGULATOR 1 5 A 1.225 V R1 OPEN C8 0.47 + STANDBY 2 SD THERMAL SHUTDOWN UVLO BST 16 + SHUTDOWN UVLO DIS VIN SD 10 A SS 1.225 V LEVEL SHIFT SW D1 CMSH3-60 C_LIMIT + ERROR AMP R4 49.9 k 5 COMP CLK 1 V/A 2.1 V VIN + CLK Ir OSCILLATOR SYNC 4 5V + + C5 0.01 L1 47 H 14 PRE 15 FB 6 R Q PWM 0.7 V C7 0.022 DRIVER S Q RAMP 8 RT 7 TRACK SAMPLE and HOLD + 10 C4 0.01 C6 open CLK 0.7 V R2 OPEN C12 OPEN RAMP GENERATOR Ir = (10 A x (VIN VOUT)) + 50 A CLK C11 330 p R7 10 C10 120 C9 10 IS 13 PGND 12 AGND 9 OUT R6 1.65 k 11 SYNC R3 21 k R5 5.11 k C3 470 p Copyright (c) 2017, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 High Voltage Start-Up Regulator The LM25575-Q1 contains a dual-mode internal high voltage startup regulator that provides the VCC bias supply for the PWM controller and boot-strap MOSFET gate driver. The input pin (VIN) can be connected directly to the input voltage, as high as 42 Volts. For input voltages below 9 V, a low dropout switch connects VCC directly to VIN. In this supply range, VCC is approximately equal to VIN. For VIN voltage greater than 9 V, the low dropout switch is disabled and the VCC regulator is enabled to maintain VCC at approximately 7 V. The wide operating range of 6 V to 42 V is achieved through the use of this dual mode regulator. Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 9 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com Feature Description (continued) The output of the VCC regulator is current limited to 25 mA. Upon power up, the regulator sources current into the capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the VCC UVLO threshold of 5.35 V and the SD pin is greater than 1.225 V, the output switch is enabled and a soft-start sequence begins. The output switch remains enabled until VCC falls below 5 V or the SD pin falls below 1.125 V. An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary voltage is greater than 7.3 V, the internal regulator will essentially shut off, reducing the IC power dissipation. The VCC regulator series pass transistor includes a diode between VCC and VIN that should not be forward biased in normal operation. Therefore the auxiliary VCC voltage should never exceed the VIN voltage. In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute maximum voltage rating of 45 V. During line or load transients, voltage ringing on the VIN line that exceeds the Absolute Maximum Ratings can damage the IC. Both careful PC board layout and the use of quality bypass capacitors located close to the VIN and GND pins are essential. VIN 9V VCC 7V 5.25V Internal Enable Signal Figure 7. VIN and VCC Sequencing 7.4 Device Functional Modes 7.4.1 Shutdown and Stand-by Mode The LM25575-Q1 contains a dual level Shutdown (SD) circuit. When the SD pin voltage is below 0.7 V, the regulator is in a low current shutdown mode. When the SD pin voltage is greater than 0.7 V but less than 1.225 V, the regulator is in standby mode. In standby mode the VCC regulator is active but the output switch is disabled. When the SD pin voltage exceeds 1.225 V, the output switch is enabled and normal operation begins. An internal 5 A pull-up current source configures the regulator to be fully operational if the SD pin is left open. An external set-point voltage divider from VIN to GND can be used to set the operational input range of the regulator. The divider must be designed such that the voltage at the SD pin will be greater than 1.225 V when VIN is in the desired operating range. The internal 5 A pull-up current source must be included in calculations of the external set-point divider. Hysteresis of 0.1 V is included for both the shutdown and standby thresholds. The SD pin is internally clamped with a 1 k resistor and an 8 V zener clamp. The voltage at the SD pin should never exceed 14 V. If the voltage at the SD pin exceeds 8 V, the bias current will increase at a rate of 1 mA/V. The SD pin can also be used to implement various remote enable and disable functions. Pulling the SD pin below the 0.7 V threshold totally disables the controller. If the SD pin voltage is above 1.225 V the regulator will be operational. 10 Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com SNVSB28 - DECEMBER 2017 Device Functional Modes (continued) 7.4.2 Error Amplifier and PWM Comparator The internal high gain error amplifier generates an error signal proportional to the difference between the regulated output voltage and an internal precision reference (1.225 V). The output of the error amplifier is connected to the COMP pin allowing the user to provide loop compensation components, generally a type II network, as illustrated in Functional Block Diagram. This network creates a pole at DC, a zero and a noise reducing high frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP generator to the error amplifier output voltage at the COMP pin. 7.4.3 Ramp Generator The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the buck switch current. This switch current corresponds to the positive slope portion of the output inductor current. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Also, the current measurement may introduce significant propagation delays. The filtering, blanking time and propagation delay limit the minimum achievable pulsewidth. In applications where the input voltage may be relatively large in comparison to the output voltage, controlling small pulsewidths and duty cycles is necessary for regulation. The LM25575-Q1 utilizes a unique ramp generator, which does not actually measure the buck switch current but rather reconstructs the signal. Reconstructing or emulating the inductor current provides a ramp signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is comprised of two elements; a sample and hold DC level and an emulated current ramp. RAMP (10 x (VIN - VOUT) + 50 ) x tON CRAMP Sample and Hold DC Level 1V/A TON Figure 8. Composition of Current Sense Signal The sample and hold DC level illustrated in Figure 8 is derived from a measurement of the re-circulating Schottky diode anode current. The re-circulating diode anode should be connected to the IS pin. The diode current flows through an internal current sense resistor between the IS and PGND pins. The voltage level across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The diode current sensing and sample & hold provide the DC level of the reconstructed current signal. The positive slope inductor current ramp is emulated by an external capacitor connected from the RAMP pin to AGND and an internal voltage controlled current source. The ramp current source that emulates the inductor current is a function of the VIN and VOUT voltages per Equation 1: IRAMP = (10 x (VIN - VOUT)) + 50 A (1) Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 11 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com Device Functional Modes (continued) Proper selection of the RAMP capacitor depends upon the selected value of the output inductor. The value of CRAMP can be selected from: CRAMP = L x 10-5, where L is the value of the output inductor in Henrys. With this value, the scale factor of the emulated current ramp will be approximately equal to the scale factor of the DC level sample and hold (1.0 V / A). The CRAMP capacitor should be located very close to the device and connected directly to the pins of the IC (RAMP and AGND). For duty cycles greater than 50%, peak current mode control circuits are subject to sub-harmonic oscillation. Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 50 A of offset current provided from the emulated current source adds some fixed slope to the ramp signal. In some high output voltage, high duty cycle applications, additional slope may be required. In these applications, a pull-up resistor may be added between the VCC and RAMP pins to increase the ramp slope compensation. For VOUT > 7.5 V: Calculate optimal slope current, IOS = VOUT x 10 A/V. For example, at VOUT = 10 V, IOS = 100 A. Install a resistor from the RAMP pin to VCC: RRAMP = VCC / (IOS - 50 A) VCC RRAMP RAMP CRAMP Figure 9. RRAMP to VCC for VOUT > 7.5 V 7.4.4 Maximum Duty Cycle and Input Drop-out Voltage There is a forced off-time of 500 ns implemented each cycle to ensure sufficient time for the diode current to be sampled. This forced off-time limits the maximum duty cycle of the buck switch. The maximum duty cycle will vary with the operating frequency. DMAX = 1 - Fs x 500 ns (2) Where Fs is the oscillator frequency. Limiting the maximum duty cycle will raise the input dropout voltage. The input dropout voltage is the lowest input voltage required to maintain regulation of the output voltage. An approximation of the input dropout voltage is: VinMIN = Vout + VD 1 - Fs x 500 ns (3) Where VD is the voltage drop across the re-circulatory diode. Operating at high switching frequency raises the minimum input voltage necessary to maintain regulation. 7.4.5 Current Limit The LM25575-Q1 contains a unique current monitoring scheme for control and over-current protection. When set correctly, the emulated current sense signal provides a signal which is proportional to the buck switch current with a scale factor of 1.0 V / A. The emulated ramp signal is applied to the current limit comparator. If the emulated ramp signal exceeds 2.1 V (2.1 A) the present current cycle is terminated (cycle-by-cycle current limiting). In applications with small output inductance and high input voltage the switch current may overshoot due to the propagation delay of the current limit comparator. If an overshoot should occur, the diode current 12 Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com SNVSB28 - DECEMBER 2017 Device Functional Modes (continued) sampling circuit will detect the excess inductor current during the off-time of the buck switch. If the sample & hold DC level exceeds the 2.1 V current limit threshold, the buck switch will be disabled and skip pulses until the diode current sampling circuit detects the inductor current has decayed below the current limit threshold. This approach prevents current runaway conditions due to propagation delays or inductor saturation since the inductor current is forced to decay following any current overshoot. 7.4.6 Soft-Start The soft-start feature allows the regulator to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. The internal soft-start current source, set to 10 A, gradually increases the voltage of an external soft-start capacitor connected to the SS pin. The soft-start capacitor voltage is connected to the reference input of the error amplifier. Various sequencing and tracking schemes can be implemented using external circuits that limit or clamp the voltage level of the SS pin. In the event a fault is detected (over-temperature, VCC UVLO, SD) the soft-start capacitor will be discharged. When the fault condition is no longer present a new soft-start sequence will commence. 7.4.7 Boost Pin The LM25575-Q1 integrates an N-Channel buck switch and associated floating high voltage level shift / gate driver. This gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.022 F ceramic capacitor, connected with short traces between the BST pin and SW pin, is recommended. During the off-time of the buck switch, the SW pin voltage is approximately -0.5 V and the bootstrap capacitor is charged from VCC through the internal bootstrap diode. When operating with a high PWM duty cycle, the buck switch will be forced off each cycle for 500 ns to ensure that the bootstrap capacitor is recharged. Under very light load conditions or when the output voltage is pre-charged, the SW voltage will not remain low during the off-time of the buck switch. If the inductor current falls to zero and the SW pin rises, the bootstrap capacitor will not receive sufficient voltage to operate the buck switch gate driver. For these applications, the PRE pin can be connected to the SW pin to pre-charge the bootstrap capacitor. The internal pre-charge MOSFET and diode connected between the PRE pin and PGND turns on each cycle for 250 ns just prior to the onset of a new switching cycle. If the SW pin is at a normal negative voltage level (continuous conduction mode), then no current will flow through the pre-charge MOSFET/diode. 7.4.8 Thermal Protection Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. When activated, typically at 165C, the controller is forced into a low power reset state, disabling the output driver and the bias regulator. This feature is provided to prevent catastrophic failures from accidental device overheating. Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 13 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 External Components The procedure for calculating the external components is illustrated with the following design example. The Bill of Materials for this design is listed in Table 1. The circuit shown in Functional Block Diagram is configured for the following specifications: * VOUT = 5 V * VIN = 7 V to 42 V * Fs = 300 kHz * Minimum load current (for CCM) = 200 mA * Maximum load current = 1.5 A 8.1.2 R3 (RT) RT sets the oscillator switching frequency. Generally, higher frequency applications are smaller but have higher losses. Operation at 300 kHz was selected for this example as a reasonable compromise for both small size and high efficiency. The value of RT for 300 kHz switching frequency can be calculated Equation 4: [(1 / 300 x 103) - 580 x 10-9] RT = 135 x 10-12 (4) The nearest standard value of 21 k was chosen for RT. 14 Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com SNVSB28 - DECEMBER 2017 Application Information (continued) 8.1.3 L1 The inductor value is determined based on the operating frequency, load current, ripple current, and the minimum and maximum input voltage (VIN(min), VIN(max)). L1 Current IPK+ IRIPPLE IO IPK- 1/Fs 0 mA Figure 10. Inductor Current Waveform To keep the circuit in continuous conduction mode (CCM), the maximum ripple current IRIPPLE should be less than twice the minimum load current, or 0.4 Ap-p. Using this value of ripple current, the value of inductor (L1) is calculated using the following: L1 = VOUT x (VIN(max) - VOUT) IRIPPLE x FS x VIN(max) (5) 5V x (42V - 5V) L1 = = 37 H 0.4A x 300 kHz x 42V (6) This procedure provides a guide to select the value of L1. The nearest standard value (47H) will be used. L1 must be rated for the peak current (IPK+) to prevent saturation. During normal loading conditions, the peak current occurs at maximum load current plus maximum ripple. During an overload condition the peak current is limited to 2.1 A nominal (2.5 A maximum). The selected inductor (see Table 1) has a conservative 3.25 Amp saturation current rating. For this manufacturer, the saturation rating is defined as the current necessary for the inductance to reduce by 30%, at 20C. 8.1.4 C3 (CRAMP) With the inductor value selected, the value of C3 (CRAMP) necessary for the emulation ramp circuit is: CRAMP = L x 10-5 (7) Where L is in Henrys With L1 selected for 47 H the recommended value for C3 is 470 pF. 8.1.5 C9, C10 The output capacitors, C9 and C10, smooth the inductor ripple current and provide a source of charge for transient loading conditions. For this design a 10 F ceramic capacitor and a 120 F AL organic capacitor were selected. The ceramic capacitor provides ultra low ESR to reduce the output ripple voltage and noise spikes, while the AL capacitor provides a large bulk capacitance in a small volume for transient loading conditions. An approximation for the output ripple voltage is: ae o 1 VOUT = IL c ESR + / 8 F C S OUT o e (8) Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 15 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com Application Information (continued) 8.1.6 D1 A Schottky type re-circulating diode is required for all LM25575-Q1 applications. Ultra-fast diodes are not recommended and may result in damage to the IC due to reverse recovery current transients. The near ideal reverse recovery characteristics and low forward voltage drop are particularly important diode characteristics for high input voltage and low output voltage applications common to the LM25575-Q1. The reverse recovery characteristic determines how long the current surge lasts each cycle when the buck switch is turned on. The reverse recovery characteristics of Schottky diodes minimize the peak instantaneous power in the buck switch occurring during turn-on each cycle. The resulting switching losses of the buck switch are significantly reduced when using a Schottky diode. The reverse breakdown rating should be selected for the maximum VIN, plus some safety margin. The forward voltage drop has a significant impact on the conversion efficiency, especially for applications with a low output voltage. "Rated" current for diodes vary widely from various manufacturers. The worst case is to assume a short circuit load condition. In this case the diode will carry the output current almost continuously. For the LM25575-Q1 this current can be as high as 2.1 A. Assuming a worst case 1 V drop across the diode, the maximum diode power dissipation can be as high as 2.1 W. For the reference design a 60 V Schottky in a SMC package was selected. 8.1.7 C1, C2 The regulator supply voltage has a large source impedance at the switching frequency. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. When the buck switch turns on, the current into the VIN pin steps to the lower peak of the inductor current waveform, ramps up to the peak value, then drops to zero at turn-off. The average current into VIN during the on-time is the load current. The input capacitance should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating necessary is IRMS > IOUT / 2. Quality ceramic capacitors with a low ESR should be selected for the input filter. To allow for capacitor tolerances and voltage effects, two 1.0 F, 100 V ceramic capacitors will be used. If step input voltage transients are expected near the maximum rating of the LM25575-Q1, a careful evaluation of ringing and possible spikes at the device VIN pin should be completed. An additional damping network or input voltage clamp may be required in these cases. 8.1.8 C8 The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended value of C8 should be no smaller than 0.1 F, and should be a good quality, low ESR, ceramic capacitor. A value of 0.47 F was selected for this design. 8.1.9 C7 The bootstrap capacitor between the BST and the SW pins supplies the gate current to charge the buck switch gate at turn-on. The recommended value of C7 is 0.022 F, and should be a good quality, low ESR, ceramic capacitor. 8.1.10 C4 The capacitor at the SS pin determines the soft-start time, that is the time for the reference voltage and the output voltage, to reach the final regulated value. The time is determined from Equation 9: tss = C4 x 1.225V 10 A (9) For this application, a C4 value of 0.01 F was chosen which corresponds to a soft-start time of 1 ms. 8.1.11 R5, R6 R5 and R6 set the output voltage level, the ratio of these resistors is calculated from Equation 10: R5/R6 = (VOUT / 1.225 V) - 1 16 (10) Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com SNVSB28 - DECEMBER 2017 Application Information (continued) For a 5 V output, the R5 and R6 ratio calculates to 3.082. The resistors should be chosen from standard value resistors, a good starting point is selection in the range of 1.0 k - 10 k. Values of 5.11 k for R5, and 1.65 k for R6 were selected. 8.1.12 R1, R2, C12 A voltage divider can be connected to the SD pin to set a minimum operating voltage VIN(min) for the regulator. If this feature is required, the easiest approach to select the divider resistor values is to select a value for R1 (between 10 k and 100 k recommended) then calculate R2 from Equation 11: (c) R1 R2 = 1.225 x -6 (c) VIN(min) + (5 x 10 x R1) 1.225 (11) Capacitor C12 provides filtering for the divider. The voltage at the SD pin should never exceed 8 V, when using an external set-point divider it may be necessary to clamp the SD pin at high input voltage conditions. The reference design utilizes the full range of the LM25575-Q1 (6 V to 42 V); therefore these components can be omitted. With the SD pin open circuit the LM25575-Q1 responds once the VCC UVLO threshold is satisfied. 8.1.13 R7, C11 A snubber network across the power diode reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and couple spikes and noise to the output. Voltage spikes beyond the rating of the LM25575-Q1 or the re-circulating diode can damage these devices. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are very short. For the current levels typical for the LM25575-Q1 a resistor value between 5 and 20 is adequate. Increasing the value of the snubber capacitor results in more damping but higher losses. Select a minimum value of C11 that provides adequate damping of the SW pin waveform at high load. 8.1.14 R4, C5, C6 These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5. The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of the LM25575-Q1 is as follows: DC Gain(MOD) = Gm(MOD) x RLOAD = 1 x RLOAD (12) The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD,) and output capacitance (COUT). The corner frequency of this pole is as follows: fp(MOD) = 1 / (2 RLOAD COUT) (13) For RLOAD = 5 and COUT = 130 F then fp(MOD) = 245 Hz DC Gain(MOD) = 1 x 5 = 14 dB For the design example of Functional Block Diagram the following modulator gain vs. frequency characteristic was measured as shown in Figure 11. Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 17 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com Application Information (continued) REF LEVEL 0.000 dB 0.0 deg /DIV 10.000 dB 45.000 deg GAIN 0 PHASE 100 1k START 100.000 Hz 10k 100k STOP 100 000.000 Hz Figure 11. Gain and Phase of Modulator RLOAD = 5 Ohms and COUT = 130 F Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a zero at fZ = 1 / (2R4C5). The error amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin. For the design example, a target loop bandwidth (crossover frequency) of 15 kHz was selected. The compensation network zero (fZ) should be selected at least an order of magnitude less than the target crossover frequency. This constrains the product of R4 and C5 for a desired compensation network zero 1 / (2 R4 C5) to be less than 2 kHz. Increasing R4, while proportionally decreasing C5, increases the error amp gain. Conversely, decreasing R4 while proportionally increasing C5, decreases the error amp gain. For the design example C5 was selected for 0.01 F and R4 was selected for 49.9 k. These values configure the compensation network zero at 320 Hz. The error amp gain at frequencies greater than fZ is: R4 and R5, which is approximately 10 (20 dB). REF LEVEL 0.000 dB 0.0 deg /DIV 10.000 dB 45.000 deg PHASE GAIN 0 100 1k START 50.000 Hz 10k STOP 50 000.000 Hz Figure 12. Error Amplifier Gain and Phase The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain. 18 Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com SNVSB28 - DECEMBER 2017 Application Information (continued) REF LEVEL 0.000 dB 0.0 deg /DIV 10.000 dB 45.000 deg GAIN PHASE 0 100 1k START 100.000 Hz 10k 100k STOP 100 000.000 Hz Figure 13. Overall Loop Gain and Phase If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given. Step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response. C6 can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value of C6 must be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of the pole added by C6 is: fp2 = fz x C5 / C6. 8.1.15 BIas Power Dissipation Reduction Buck regulators operating with high input voltage can dissipate an appreciable amount of power for the bias of the IC. The VCC regulator must step-down the input voltage VIN to a nominal VCC level of 7 V. The large voltage drop across the VCC regulator translates into a large power dissipation within the VCC regulator. There are several techniques that can significantly reduce this bias regulator power dissipation. Figure 14 and Figure 15 depict two methods to bias the IC from the output voltage. In each case the internal VCC regulator is used to initially bias the VCC pin. After the output voltage is established, the VCC pin potential is raised above the nominal 7 V regulation level, which effectively disables the internal VCC regulator. The voltage applied to the VCC pin should never exceed 14 V. The VCC voltage should never be larger than the VIN voltage. Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 19 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com Application Information (continued) LM25575-Q1 BST VOUT SW L1 COUT D1 IS GND VCC D2 Copyright (c) 2017, Texas Instruments Incorporated Figure 14. VCC Bias From VOUT For 8 V < VOUT < 14 V LM25575-Q1 BST L1 VOUT SW COUT D1 IS GND D2 VCC Copyright (c) 2017, Texas Instruments Incorporated Figure 15. VCC Bias With Additional Winding on the Output Inductor 20 Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com SNVSB28 - DECEMBER 2017 8.2 Typical Application 8.2.1 Typical Schematic for High Frequency (1 MHz) Application BST 9 V 32 V VIN 0.022 SD 1 3.3 V, 1.5 A 10 SW SYNC CMSH3-40 5.11 k COMP LM25575-Q1 IS 49.9 k 130 3.01 k GND 0.01 OUT FB RAMP 100 p RT SS 3.57 k VCC 0.01 0.1 Copyright (c) 2017, Texas Instruments Incorporated Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 21 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com 9 Layout 9.1 Layout Guidelines 9.1.1 PCB Layout and Thermal Considerations The circuit in Functional Block Diagram serves as both a block diagram of the LM25575-Q1 and a typical application board schematic for the LM25575-Q1. In a buck regulator there are two loops where currents are switched very fast. The first loop starts from the input capacitors, to the regulator VIN pin, to the regulator SW pin, to the inductor then out to the load. The second loop starts from the output capacitor ground, to the regulator PGND pins, to the regulator IS pins, to the diode anode, to the inductor and then out to the load. Minimizing the loop area of these two loops reduces the stray inductance and minimizes noise and possible erratic operation. A ground plane in the PC board is recommended as a means to connect the input filter capacitors to the output filter capacitors and the PGND pins of the regulator. Connect all of the low power ground connections (CSS, RT, CRAMP) directly to the regulator AGND pin. Connect the AGND and PGND pins together through the topside copper area covering the entire underside of the device. Place several vias in this underside copper area to the ground plane. The two highest power dissipating components are the re-circulating diode and the LM25575-Q1 regulator IC. The easiest method to determine the power dissipated within the LM25575-Q1 is to measure the total conversion losses (Pin - Pout) then subtract the power losses in the Schottky diode, output inductor and snubber resistor. An approximation for the Schottky diode loss is P = (1-D) x Iout x Vfwd. An approximation for the output inductor power is P = IOUT2 x R x 1.1, where R is the DC resistance of the inductor and the 1.1 factor is an approximation for the AC losses. If a snubber is used, an approximation for the damping resistor power dissipation is P = VIN2 x Fsw x Csnub, where Fsw is the switching frequency and Csnub is the snubber capacitor. The regulator has an exposed thermal pad to aid power dissipation. Adding several vias under the device to the ground plane will greatly reduce the regulator junction temperature. Selecting a diode with an exposed pad will aid the power dissipation of the diode. The most significant variables that affect the power dissipated by the LM25575-Q1 are the output current, input voltage and operating frequency. The power dissipated while operating near the maximum output current and maximum input voltage can be appreciable. The operating frequency of the LM25575-Q1 evaluation board has been designed for 300 kHz. When operating at 1.5 A output current with a 42 V input the power dissipation of the LM25575-Q1 regulator is approximately 0.9 W. The junction-to-ambient thermal resistance of the LM25575-Q1 will vary with the application. The most significant variables are the area of copper in the PC board, the number of vias under the IC exposed pad and the amount of forced air cooling provided. Referring to the evaluation board artwork, the area under the LM25575-Q1 (component side) is covered with copper and there are 5 connection vias to the solder side ground plane. Additional vias under the IC will have diminishing value as more vias are added. The integrity of the solder connection from the IC exposed pad to the PC board is critical. Excessive voids will greatly diminish the thermal dissipation capacity. The junction-to-ambient thermal resistance of the LM25575-Q1 mounted in the evaluation board varies from 50C/W with no airflow to 28C/W with 900 LFM (Linear Feet per Minute). With a 25C ambient temperature and no airflow, the predicted junction temperature for the LM25575-Q1 will be 25 + (50 x 0.9) = 70C. If the evaluation board is operated at 1.5 A output current, 70 V input voltage and high ambient temperature for a prolonged period of time the thermal shutdown protection within the IC may activate. The IC will turn off allowing the junction to cool, followed by restart with the soft-start capacitor reset to zero. Table 1. 5 V, 1.5 A Demo Board Bill of Materials ITEM 22 PART NUMBER DESCRIPTION VALUE C 1 C3225X7R2A105M CAPACITOR, CER, TDK C 2 C3225X7R2A105M CAPACITOR, CER, TDK C 3 C0805A471K1GAC CAPACITOR, CER, KEMET 470 p, 100 V C 4 C2012X7R2A103K CAPACITOR, CER, TDK 0.01 , 100 V C 5 C2012X7R2A103K CAPACITOR, CER, TDK 0.01 , 100 V C 6 OPEN NOT USED C 7 C2012X7R2A223K CAPACITOR, CER, TDK 0.022 , 100 V C 8 C2012X7R1C474M CAPACITOR, CER, TDK 0.47 , 16 V Submit Documentation Feedback 1 , 100 V 1 , 100 V Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com SNVSB28 - DECEMBER 2017 Layout Guidelines (continued) Table 1. 5 V, 1.5 A Demo Board Bill of Materials (continued) ITEM PART NUMBER DESCRIPTION VALUE C 9 C3225X7R1C106M CAPACITOR, CER, TDK 10 , 16 V C 10 APXE6R3ARA121ME61G CAPACITOR, AL, NIPPON 120 , 6.3 V C 11 C0805C331G1GAC CAPACITOR, CER, KEMET 330 p, 100 V C 12 OPEN NOT USED D 1 CMSH3-60 DIODE, 60V, CENTRAL L 1 DR125-470 INDUCTOR, COOPER R 1 OPEN NOT USED 47 H R 2 OPEN NOT USED R 3 CRCW08052102F RESISTOR 21 k R 4 CRCW08054992F RESISTOR 49.9 k R 5 CRCW08055111F RESISTOR 5.11 k R 6 CRCW08051651F RESISTOR 1.65 k R 7 CRCW2512100J RESISTOR 10, 1 W U 1 LM25575-Q1 REGULATOR, TEXAS INSTRUMENTS 9.2 Layout Example Figure 16. Component Side Figure 17. Solder Side Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 23 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com Layout Example (continued) LM25575-Q1 Figure 18. Silkscreen 24 Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 LM25575-Q1 www.ti.com SNVSB28 - DECEMBER 2017 10 Device and Documentation Support 10.1 Device Support 10.1.1 Developmental Support 10.1.1.1 Custom Design With WEBENCH(R) Tools Click here to create a custom design using the LM25575-Q1 device with the WEBENCH(R) Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: * Run electrical simulations to see important waveforms and circuit performance * Run thermal simulations to understand board thermal performance * Export customized schematic and layout into popular CAD formats * Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 10.4 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 25 LM25575-Q1 SNVSB28 - DECEMBER 2017 www.ti.com 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright (c) 2017, Texas Instruments Incorporated Product Folder Links: LM25575-Q1 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM25575QMH/NOPB ACTIVE HTSSOP PWP 16 92 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L25575 QMH LM25575QMHX/NOPB ACTIVE HTSSOP PWP 16 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L25575 QMH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OTHER QUALIFIED VERSIONS OF LM25575-Q1 : * Catalog: LM25575 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Dec-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM25575QMHX/NOPB Package Package Pins Type Drawing SPQ HTSSOP 2500 PWP 16 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Dec-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM25575QMHX/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE PWP0016A PowerPAD TM HTSSOP - 1.2 mm max height SCALE 2.400 PLASTIC SMALL OUTLINE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 14X 0.65 16 1 2X 4.55 5.1 4.9 NOTE 3 8 9 B 4.5 4.3 16X 0.30 0.19 0.1 C A B (0.15) TYP SEE DETAIL A 4X 0.166 MAX NOTE 5 2X 1.34 MAX NOTE 5 THERMAL PAD 3.3 2.7 17 0.25 GAGE PLANE 1.2 MAX 0.15 0.05 0 -8 0.75 0.50 (1) 3.3 2.7 DETAIL A TYPICAL 4214868/A 02/2017 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may not be present. www.ti.com EXAMPLE BOARD LAYOUT PWP0016A PowerPAD TM HTSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE (3.4) NOTE 9 SOLDER MASK DEFINED PAD (3.3) 16X (1.5) SYMM SEE DETAILS 1 16 16X (0.45) (1.1) TYP 17 SYMM (3.3) (5) NOTE 9 14X (0.65) 8 9 ( 0.2) TYP VIA (1.1) TYP METAL COVERED BY SOLDER MASK (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:10X SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL 0.05 MAX ALL AROUND EXPOSED METAL 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS PADS 1-16 4214868/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. www.ti.com EXAMPLE STENCIL DESIGN PWP0016A PowerPAD TM HTSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE (3.3) BASED ON 0.125 THICK STENCIL 16X (1.5) (R0.05) TYP 1 16 16X (0.45) (3.3) BASED ON 0.125 THICK STENCIL 17 SYMM 14X (0.65) 9 8 SYMM METAL COVERED BY SOLDER MASK (5.8) SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.125 0.15 0.175 3.69 X 3.69 3.3 X 3.3 (SHOWN) 3.01 X 3.01 2.79 X 2.79 4214868/A 02/2017 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. 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