Serializer
Deserializer
DS15BA101 DS15EA101
CML
LVPECL
LVDS
150 Mbps
to
1.5 Gbps
100-ohm Differential Cable
(i.e. CAT5e/6/7, Twinax)
50-ohm Coaxial Cable
(i.e. Belden 9914)
Max Cable Loss ~ 35 dB @ 750 MHz
DS15BA101
www.ti.com
SNLS234J –OCTOBER 2006–REVISED APRIL 2013
DS15BA101 1.5 Gbps Differential Buffer with Adjustable Output Voltage
Check for Samples: DS15BA101
1FEATURES DESCRIPTION
The DS15BA101 is a high-speed differential buffer for
2• Data Rates from DC to 1.5+ Gbps cable driving, level translation, signal buffering, and
• Differential or Single-ended Input signal repeating applications. Its fully differential
• Adjustable Output Amplitude signal path ensures exceptional signal integrity and
noise immunity and it drives both differential and
• Single 3.3V Supply single-ended transmission lines at data rates in
• Industrial -40°C to +85°C Temperature excess of 1.5 Gbps.
• Low Power: 150 mW (typ) at 1.5 Gbps Output voltage amplitude is adjustable via a single
• Space-saving 3 x 3 mm WSON-8 Package external resistor for level translation and cable driving
applications into 50-ohm single-ended and 100-ohm
APPLICATIONS differential mode impedances.
• Cable Extension Applications The DS15BA101 is powered from a single 3.3V
• Level Translation supply and consumes 150 mW (typ) at 1.5 Gbps. It
operates over the full −40°C to +85°C industrial
• Signal Buffering and Repeating temperature range and is available in a space saving
• Security Cameras 3x3 mm WSON-8 package.
Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS15BA101
SNLS234J –OCTOBER 2006–REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
Supply Voltage −0.5V to 3.6V
Input Voltage (all inputs) −0.3V to VCC+0.3V
Output Current 28 mA
Storage Temperature Range −65°C to +150°C
Junction Temperature +150°C
Lead Temperature
(Soldering 4 Sec) +260°C
θJA WSON-8 +90.7°C/W
Package Thermal Resistance θJC WSON-8 +41.2°C/W
ESD Rating (HBM) 5 kV
ESD Rating (MM) 250V
(1) "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be ensured. The
stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values.
The table of "Electrical Characteristics" specifies acceptable device operating conditions.
Recommended Operating Conditions
Supply Voltage (VCC – GND): 3.3V ±5%
Operating Free Air Temperature (TA)
DS15BA101SD −40°C to +85°C
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)
Symbol Parameter Conditions Reference Min Typ Max Units
VICM Input Common Mode Voltage See Note(3) IN+, IN- VCC –
0.8 V
VID/2
VID Differential Input Voltage Swing 100 2000 mVP−P
VOS Output Common Mode Voltage OUT+, OUT- VCC –V
VOUT/2
VOUT Output Voltage Single-ended, 25Ωload 400 mVP-P
RVO = 953Ω1%,
Single-ended, 25Ωload 800 mVP-P
RVO = 487Ω1%,
ICC Supply Current See Note(4) 45 49 mA
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to GND.
(2) Typical values are stated for VCC = +3.3V and TA= +25°C.
(3) Specification is ensured by characterization.
(4) Maximum ICC is measured at VCC = +3.465V and TA= +70°C.
2Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS15BA101
IN+
IN-
GND
RVO
OUT+
OUT-
GND
VCC
1
2
3
4
8
6
5
7
(GND)
DAP
DS15BA101
www.ti.com
SNLS234J –OCTOBER 2006–REVISED APRIL 2013
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1).
Symbol Parameter Conditions Reference Min Typ Max Units
DRMAX Maximum Data Rate See Note(2) IN+, IN- 1.5 2.0 Gbps
tLHT Output Low to High Transition 20% – 80%(3) OUT+, OUT- 120 220 ps
Time
tHLT Output High to Low Transition 120 220 ps
Time
tPLHD Propagation Low to High Delay See Note(2) 0.95 1.10 1.35 ns
tPHLD Propagation High to Low Delay See Note(2) 0.95 1.10 1.35 ns
tTJ Total Jitter 1.5 Gbps 26 psP-P
(1) Typical values are stated for VCC = +3.3V and TA= +25°C.
(2) Specification is ensured by characterization.
(3) Specification is ensured by characterization and verified by test.
CONNECTION DIAGRAM
Figure 1. 8-Pad WSON
See NGQ Package
PIN DESCRIPTIONS
Pin # Name Description
1 IN+ Non-inverting input pin.
2 IN- Inverting input pin.
3 GND Circuit common (ground reference).
4 RVO Output voltage amplitude control. Connect a resistor to VCC to set output voltage.
5 VCC Positive power supply (+3.3V).
6 GND Circuit common (ground reference).
7 OUT- Inverting output pin.
8 OUT+ Non-inverting output pin.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DS15BA101
OUT+
OUT-
DS15BA101
IN+
IN-
50:50:
100: Differential T-Line
LVPECL 100:
OUT+
OUT-
DS15BA101
IN+
IN-
50:50:
VCC
CML3.3V or CML2.5V
100:
100: Differential T-Line
OUT+
OUT-
DS15BA101
IN+
IN-
100:
100: Differential T-Line
LVDS
DS15BA101
SNLS234J –OCTOBER 2006–REVISED APRIL 2013
www.ti.com
DEVICE OPERATION
INPUT INTERFACING
The DS15BA101 accepts either differential or single-ended input. The inputs are self-biased, allowing for simple
AC or DC coupling. DC-coupled inputs must be kept within the specified common-mode range. The IN+ and IN-
pins are self-biased at approximately 2.1V with VCC = 3.3V. The following three figures illustrate typical DC-
coupled interface to common differential drivers.
Figure 2. Typical LVDS Driver DC-Coupled Interface to DS15BA101 Input
Figure 3. Typical CML Driver DC-Coupled Interface to DS15BA101 Input
Figure 4. Typical LVPECL Driver DC-Coupled Interface to DS15BA101 Input
OUTPUT INTERFACING
The DS15BA101 uses current mode outputs. Single-ended output levels are 400 mVP-P into AC-coupled 100Ω
differential cable (with RVO = 953Ω) or into AC-coupled 50Ωcoaxial cable (with RVO = 487Ω). Output level is
controlled by the value of the RVO resistor connected between the RVO and VCC.
The RVO resistor should be placed as close as possible to the RVO pin. In addition, the copper in the plane layers
below the RVO network should be removed to minimize parasitic capacitance. The following figure illustrates
typical DC-coupled interface to common differential receivers and assumes that the receivers have high
impedance inputs. While most receivers have a common mode input range that can accomodate CML signals, it
is recommended to check respective receiver's datasheet prior to implementing the suggested interface
implementation.
4Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS15BA101
DS15BA101
OUT-
IN+
IN-
OUT+
0.1 PF
50:
50:
487:
100:
1 PF1 PF
1 PFDS15EA101
IN+
IN-
50:
1 PF
OUT+
OUT-
CAP+ CAP-
0.1 PF
VCC
VCC
25:
50: Coaxial Cable
RVO
DS15BA101
OUT-
IN+
IN-
OUT+
0.1 PF
50:
50:
953:
100:
1 PF
1 PF
1 PF
1 PFDS15EA101
IN+
IN-
100:
1 PF
OUT+
OUT-
CAP+ CAP-
0.1 PF
VCC
VCC
100: Differential TP Cable
RVO
OUT+
OUT-
CML or
LVPECL or
LVDS
IN+
IN-
50:
50:
VCC
100:
100: Differential T-Line
DS15BA101
DS15BA101
www.ti.com
SNLS234J –OCTOBER 2006–REVISED APRIL 2013
Figure 5. Typical DS15BA101 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
CABLE EXTENDER APPLICATION
The DS15BA101 together with the DS15EA101 form a cable extender chipset optimized for extending serial data
streams from serializer/deserializer (SerDes) pairs and field programmable gate arrays (FPGAs) over 100Ω
differential (i.e. CAT5e/6/7 and twinax) and 50Ωcoaxial cables. Setting correct DS15BA101 output amplitude and
proper cable termination are keys for optimal operation. The following two figures show recommended chipset
configuration for 100Ωdifferential and 50Ωcoaxial cables.
Figure 6. Cable Extender Chipset Connection Diagram for 100ΩDifferential Cables
Figure 7. Cable Extender Chipset Connection Diagram for 50ΩCoaxial Cables
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DS15BA101
DS15BA101
SNLS234J –OCTOBER 2006–REVISED APRIL 2013
www.ti.com
REFERENCE DESIGN
There is a complete reference design (P/N: DriveCable02EVK) available for evaluation of the cable extender
chipset (DS15BA101 and DS15EA101). For more information, visit http://www.ti.com/tool/drivecable02evk.
Typical Performance
Figure 8. 1.5 Gbps Differential DS15BA101 Output Figure 9. 1.5 Gbps Single-ended DS15BA101 Output
RVO = 953Ω, H:100 ps / DIV, V:100 mV / DIV RVO = 487Ω, H:100 ps / DIV, V:100 mV / DIV
Figure 10. 2.0 Gbps Differential DS15BA101 Output Figure 11. 2.0 Gbps Single-ended DS15BA101 Output
RVO = 953Ω, H:100 ps / DIV, V:100 mV / DIV RVO = 487Ω, H:100 ps / DIV, V:100 mV / DIV
6Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS15BA101
DS15BA101
www.ti.com
SNLS234J –OCTOBER 2006–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision I (April 2013) to Revision J Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 6
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DS15BA101
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS15BA101SD/NOPB ACTIVE WSON NGQ 8 1000 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR -40 to 85 BA101
DS15BA101SDE/NOPB ACTIVE WSON NGQ 8 250 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR -40 to 85 BA101
DS15BA101SDX/NOPB ACTIVE WSON NGQ 8 4500 Green (RoHS
& no Sb/Br) SN Level-3-260C-168 HR -40 to 85 BA101
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS15BA101SD/NOPB WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
DS15BA101SDE/NOPB WSON NGQ 8 250 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
DS15BA101SDX/NOPB WSON NGQ 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS15BA101SD/NOPB WSON NGQ 8 1000 210.0 185.0 35.0
DS15BA101SDE/NOPB WSON NGQ 8 250 210.0 185.0 35.0
DS15BA101SDX/NOPB WSON NGQ 8 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
8X 0.3
0.2
2 0.1
8X 0.5
0.3
2X
1.5
1.6 0.1
6X 0.5
0.8
0.7
0.05
0.00
B3.1
2.9 A
3.1
2.9
(0.1) TYP
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
9
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(1.6)
6X (0.5)
(2.8)
8X (0.25)
8X (0.6)
(2)
(R0.05) TYP ( 0.2) VIA
TYP
(0.75)
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
SYMM
1
45
8
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
8X (0.25)
8X (0.6)
6X (0.5)
(1.79)
(1.47)
(2.8)
(R0.05) TYP
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 9:
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
45
8
SYMM
METAL
TYP
9
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